LT1949-1EMS8#TRPBF [Linear]
IC 1.5 A SWITCHING REGULATOR, 1350 kHz SWITCHING FREQ-MAX, PDSO8, PLASTIC, MSOP-8, Switching Regulator or Controller;
| 型号： | LT1949-1EMS8#TRPBF |
| 厂家： | 
Linear |
| 描述： | IC 1.5 A SWITCHING REGULATOR, 1350 kHz SWITCHING FREQ-MAX, PDSO8, PLASTIC, MSOP-8, Switching Regulator or Controller 转换器 稳压器 开关式稳压器或控制器 电源电路 开关式控制器 光电二极管 |
| 文件： | 总8页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Final Electrical Specifications
LT1949-1
1.1MHz, 1A Switch
PWM DC/DC Converter
June 2000
U
DESCRIPTIO
The LT®1949-1 is a fixed frequency step-up DC/DC con-
verter with a 1A, 0.5Ω internal switch. Capable of gener-
ating 10V at 175mA from a 3.3V input, the LT1949-1 is
ideal for generating bias voltages for large screen LCD
panels. Constant frequency 1.1MHz operation results in a
low noise output that is easy to filter and the 30V switch
rating allows output voltage up to 28V using a single
inductor. The high switching frequency allows the use of
ceramic output capacitors. An external compensation pin
gives the user flexibility in optimizing loop compensation,
allowing small, low ESR ceramic capacitors to be used at
the output. The 8-lead MSOP package ensures a low
profile overall solution.
FEATURES
■
■
■
■
■
■
■
■
1A, 0.5Ω, 30V Internal Switch
1.1MHz Fixed Frequency Operation
Operates with VIN as Low as 1.5V
Low-Battery Detector Stays Active in Shutdown
Low VCESAT Switch: 410mV at 800mA
Pin-for-Pin Compatible with the LT1317B
Uses Ceramic Capacitors
Small 8-Lead MSOP Package
U
APPLICATIO S
■
LCD Bias Supplies
The LT1949-1 includes a low-battery detector that stays
alive when the device goes into shutdown. Quiescent
current in shutdown is 50µA, while operating current is
8mA.
■
GPS Receivers
■
Battery Backup
Portable Electronic Equipment
Diagnostic Medical Instrumentation
■
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
TYPICAL APPLICATIO
90
V
IN
3.3V
V
= 10V
L1
OUT
D1
80
70
60
50
40
30
20
4.7µH
C1
3.3µF
CERAMIC
3.6V
V
SW
3V
4.2V
IN
IN
IN
IN
R1
196k
1%
LT1949-1
V
OUT
10V
FB
GND
SHUTDOWN
SHDN
175mA
3pF
V
C
84.5k
50pF
C2
3.3µF
CERAMIC
R2
28k
1%
5
10
50
100
300
C1, C2: TAIYO YUDEN LMK325BJ335MD
D1: MBRM120LT3
L1: SUMIDA CLQ4D10-4R7
1949-1 F01
LOAD CURRENT (mA)
1949-1 F02
Figure 1. 3.3V to 10V/175mA DC/DC Converter
Figure 2. 3.3V to 10V Converter Efficiency
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
1
LT1949-1
W W U W
U W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
VIN, LBO Voltage..................................................... 12V
SW Voltage ............................................... –0.4V to 30V
FB Voltage .................................................... VIN + 0.3V
VC Voltage ................................................................ 2V
LBI Voltage ............................................ 0V ≤ VLBI ≤ 1V
SHDN Voltage ........................................................... 6V
Junction Temperature.......................................... 125°C
Operating Temperature Range (Note 2) ...–40°C to 85°C
Storage Temperature ........................... –65°C to 150°C
Lead Temperature (Soldering, 10sec).................. 300°C
ORDER PART
TOP VIEW
NUMBER
V
1
2
3
4
8 LBO
7 LBI
C
LT1949-1EMS8
FB
SHDN
GND
6 V
IN
5 SW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
MS8 PART MARKING
LTQX
TJMAX = 125°C, θJA = 120°C/W
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 2V, VSHDN = 2V unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
Quiescent Current
●
●
8
50
14
80
mA
µA
Q
V
= 0V
SHDN
V
Feedback Voltage
1.22
1.20
1.24
1.24
1.26
1.26
V
V
FB
●
●
●
●
I
FB Pin Bias Current (Note 3)
Input Voltage Range
24
150
12
nA
V
B
1.7
g
Error Amp Transconductance
Error Amp Voltage Gain
Maximum Duty Cycle
∆I = 5µA
140
280
700
85
480
µmhos
V/V
%
m
A
V
●
80
1
Switch Current Limit (Note 4)
Switching Frequency
V
= 2.5V, Duty Cycle = 30%
1.1
1.1
1.5
A
IN
f
●
0.85
1.35
MHz
OSC
Shutdown Pin Current
V
V
= V
●
●
0.015
–5
0.1
–14
µA
µA
SHDN
SHDN
IN
= 0V
LBI Threshold Voltage
190
180
200
200
210
220
mV
mV
●
●
●
●
LBO Output Low
I
= 10µA
0.15
20
0.25
100
120
V
nA
SINK
LBO Leakage Current
V
V
= 250mV, V
= 5V
LBO
LBI
LBI
LBI Input Bias Current (Note 5)
Low-Battery Detector Gain
Switch Leakage Current
= 150mV
30
nA
1MΩ Pull-Up
2000
0.01
V/V
µA
V
= 5V
●
●
3
SW
Switch V
I
I
= 800mA
= 500mA
410
270
mV
mV
CESAT
SW
SW
400
Reference Line Regulation
SHDN Input Voltage High
SHDN Input Voltage Low
1.8V ≤ V ≤ 12V
0.08
%/V
V
IN
●
●
1.4
6
0.4
V
Note 1: Absolute Maximum Ratings are those values beyond which the life
Note 3: Bias current flows into FB pin.
of a device may be impaired.
Note 4: Switch current limit guaranteed by design and/or correlation to
Note 2: The LT1949-1E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
static tests. Duty cycle affects current limit due to ramp generator.
Note 5: Bias current flows out of LBI pin.
2
LT1949-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Switch Current Limit,
Duty Cycle = 30%
Oscillator Frequency
Switch Current Limit
1.3
1.2
1.1
1.0
0.9
0.8
1.3
1.2
1.1
1.0
0.9
0.8
1.3
1.2
1.1
1.0
0.9
85°C
25°C
–40°C
–50
0
25
50
75
100
0
2
4
6
8
10
12
20
80
–25
0
40
60
DUTY CYCLE (%)
100
INPUT VOLTAGE (V)
TEMPERATURE (°C)
1949-1 G03
1949-1 G01
1949-1 G02
Switch Voltage Drop (VCESAT
)
Feedback Voltage
Quiescent Current, SHDN = 2V
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
1.0
0.8
0.6
0.4
0.2
0
1.25
1.24
1.23
1.22
1.21
1.20
85°C
25°C
–40°C
–50
–25
0
25
50
75
100
0
0.4
0.6
0.8
1.0
1.2
0.2
–50 –25
0
25
50
75
100
TEMPERATURE (°C)
SWITCH CURRENT (A)
TEMPERATURE (°C)
1949-1 G06
1949-1 G04
1949-1 G05
SHDN Pin Current
Quiescent Current, SHDN = 0V
FB Pin Bias Current
60
55
50
45
40
35
30
60
55
50
45
40
35
30
25
20
15
10
2
1
0
–2
–4
–6
1
2
4
0
5
6
–50
–25
0
25
50
75
100
3
–50
–25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
SHDN PIN VOLTAGE (V)
1949-1 G09
1949-1 G07
1949-1 G08
3
LT1949-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Transient Response
VOUT
100mV/DIV
AC COUPLED
IL
500mA/DIV
VIN = 3.3V
VOUT = 10V
20µs/DIV
1949-1 G10
40mA TO 140mA LOAD STEP
CIRCUIT FIGURE 1
U
U
U
PI FU CTIO S
VC (Pin 1): Compensation Pin for Error Amplifier. Con-
nect a series RC network from this pin to ground. Typical
values for compensation are a 30k/330pF combination
when using ceramic output capacitors. Minimize trace
area at VC.
GND (Pin 4): Ground. Connect directly to local ground
plane.
SW (Pin 5): Switch Pin. Connect inductor/diode here.
Minimize trace area at this pin to keep EMI down.
VIN (Pin 6): Supply Pin. Must be bypassed close to the
pin.
FB (Pin 2): Feedback Pin. Reference voltage is 1.24V.
Connect resistor divider tap here. Minimize trace area at
FB. Set VOUT according to: VOUT = 1.24V(1 + R1/R2).
LBI (Pin 7): Low-Battery Detector Input. 200mV refer-
ence. Voltage on LBI must stay between ground and
700mV. Low-battery detector remains active in shutdown
mode.
SHDN (Pin 3): Shutdown. Pull this pin low for shutdown
mode (only the low-battery detector remains active).
Leavethispinfloatingortietoavoltagebetween1.4Vand
6V to enable the device. SHDN pin is logic level and need
only meet the logic specification (1.4V for high, 0.4V for
low).
LBO (Pin 8): Low-Battery Detector Output. Open collec-
tor, can sink 10µA. A 1MΩ pull-up is recommended.
4
LT1949-1
W
BLOCK DIAGRA
LBI
7
1.24V
+
–
+
–
V
LBO
8
C
REFERENCE
g
1
m
FB
2
A4
200mV
ENABLE
ERROR
AMPLIFIER
+
–
SHDN
3
V
OUT
SHUTDOWN
BIAS
A1
COMPARATOR
R1
(EXTERNAL)
SW
5
FB
R2
–
+
FF
S
(EXTERNAL)
DRIVER
RAMP
GENERATOR
Q3
R
Q
+
Σ
A2
COMPARATOR
+
+
–
A = 2
0.06Ω
1.1MHz
OSCILLATOR
4
1949-1 BD
GND
Figure 3. LT1949-1 Block Diagram
U
OPERATIO
The LT1949-1 is a current mode, fixed frequency step-up
DC/DC converter with an internal 1A NPN power transis-
tor. Operation can best be understood by referring to the
Block Diagram.
Layout Hints
The LT1949-1 switches current at high speed, mandating
careful attention to layout for proper performance. You
will not get advertised performance with careless layouts.
Figure 4 shows recommended component placement for
a boost (step-up) converter. Follow this closely in your PC
layout. Note the direct path of the switching loops. Input
capacitor C1 must be placed close (<5mm) to the IC
package. As little as 10mm of wire or PC trace from CIN to
VIN will cause problems such as inability to regulate or
oscillation.
At the beginning of each oscillator cycle, the flip-flop is set
and the switch is turned on. Current in the switch ramps
up until the voltage at A2’s positive input reaches the VC
pin voltage, causing A2’s output to change state and the
switch to be turned off. The signal at A2’s positive input is
a summation of a signal representing switch current and
a ramp generator (introduced to avoid subharmonic oscil-
lations at duty factors greater than 50%). If the load
increases, VOUT (and FB) will drop slightly and the error
amplifier will drive VC to a higher voltage, causing current
in the switch to increase. In this way, the error amplifier
drives the VC pin to the voltage necessary to satisfy the
load. Frequency compensation is provided by an external
series RC network connected between the VC pin and
ground.
The ground terminal of output capacitor C2 should tie
close to Pin 4 of the LT1949-1. Doing this reduces dI/dt in
the ground copper which keeps high frequency spikes to
a minimum. The DC/DC converter ground should tie to the
PC board ground plane at one place only, to avoid intro-
ducing dI/dt in the ground plane.
5
LT1949-1
U
OPERATIO
LBI
LBO
GROUND PLANE
C1
V
IN
1
2
3
4
8
R1
7
6
5
L1
LT1949-1
R2
SHUTDOWN
MULTIPLE
VIAs
C2
GND
V
OUT
1949-1 F04
Figure 4. Recommended Component Placement for Boost
Converter. Note Direct High Current Paths Using Wide PC
Traces. Minimize Trace Area at Pin 1 (VC) and Pin 2 (FB).
Use Multiple Vias to Tie Pin 4 Copper to Ground Plane. Use
Vias at One Location Only to Avoid Introducing Switching
Currents into the Ground Plane
W U U
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APPLICATIO S I FOR ATIO
Low-Battery Detector
Figure 5 details hookup. R1 and R2 need only be low
enough in value so that the bias current of the LBI pin
doesn’t cause large errors. For R2, 49.9k is adequate. The
200mV reference can also be accessed as shown in
Figure 6. The low-battery detector remains active in
shutdown.
TheLT1949-1’slow-batterydetectorisasimplePNPinput
gain stage with an open collector NPN output. The nega-
tive input of the gain stage is tied internally to a 200mV
±5% reference. The positive input is the LBI pin. Arrange-
ment as a low-battery detector is straightforward.
3.3V
200k
R1
V
V
IN
LT1949-1
LBO
IN
2N3906
REF
LBO
LBI
1M
LBI
+
–
LT1949-1
V
TO PROCESSOR
R2
49.9k
200mV
+
GND
10k
10µF
1949-1 F06
200mV
V
– 200mV
4µA
LB
R1 =
INTERNAL
REFERENCE
Figure 6. Accessing 200mV Reference
GND
1949-1 F05
Figure 5. Setting Low-Battery Detector Trip Point
6
LT1949-1
U
TYPICAL APPLICATIO
4 Cell to 5V SEPIC Converter
C2
4.7µF
16V
L1
10µH
D1
V
OUT
V
IN
5V
4V TO 9V
250mA
V
SW
100k
1%
L2
10µH
IN
1M
1M
LT1949-1
C1
C3
4.7µF
FB
GND
SHDN
10µF
16V
6.3V
V
C
33.2k
1%
40.2k
330pF
1949-1 TA02
C1, C2: TAIYO YUDEN EMK316BJ475ML
C3: TAIYO YUDEN JMK316BJ106ML
D1: MOTOROLA MBRM120LT3
L1, L2: SUMIDA CR32-100KC
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.118 ± 0.004*
(3.00 ± 0.102)
8
7
6
5
0.118 ± 0.004**
(3.00 ± 0.102)
0.193 ± 0.006
(4.90 ± 0.15)
1
2
3
4
0.040 ± 0.006
(1.02 ± 0.15)
0.034 ± 0.004
(0.86 ± 0.102)
0.007
(0.18)
0° – 6° TYP
SEATING
PLANE
0.012
(0.30)
REF
0.021 ± 0.006
(0.53 ± 0.015)
0.006 ± 0.004
(0.15 ± 0.102)
MSOP (MS8) 1098
0.0256
(0.65)
BSC
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
7
LT1949-1
U
TYPICAL APPLICATIO
Low Profile Triple Output LCD Bias Generator
D1
D2
D3
D4
23V
5mA
C7
0.1µF
C8
1µF
C9
0.1µF
C4
1µF
L1
4.7µH
V
IN
3.3V
V
SW
IN
C6
1µF
SHUTDOWN
SHDN
LT1949-1
R2
40.2k
8V
200mA
FB
GND
C1
4.7µF
V
C
C2
4.7µF
R1
30.1k
C3
R3
7.5k
330pF
C1, C2, C5: TAIYO YUDEN LMK325BJ475MF
C4, C6, C8: TAIYO YUDEN EMK316BJ105MF
D1 TO D6: BAT-54S, DUAL DIODE
D7: MBRM120LT3
D5
D6
C5
4.7µF
L1: SUMIDA CLQ4D10-4R7
–8V
10mA
1949-1 TA02
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19491i LT/TP 0600 4K • PRINTED IN THE USA
LINEAR TECHNOLOGY CORPORATION 2000
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
8
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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