LT1952IGN-1#TRPBF_技术文档

LT1952/LT1952-1

Single Switch Synchronous

Forward Controller

FEATURES

DESCRIPTION

TheLT^®1952/LT1952-1arecurrentmodePWMcontrollers

optimizedtocontroltheforwardconvertertopology,using

one primary MOSFET. The LT1952/LT1952-1 provide

synchronous rectiﬁer control, resulting in extremely

high efﬁciency. A programmable Volt-Second clamp

provides a safeguard for transformer reset that prevents

saturation. This allows a single MOSFET on the primary

side to reliably run at greater than 50% duty cycle for high

MOSFET, transformer and rectiﬁer utilization. The devices

include soft-start for controlled exit from shutdown and

undervoltage lockout. A precision 107mV current limit

threshold, independent of duty cycle, combines with soft-

starttoprovidehiccupshort-circuitprotection.TheLT1952

is optimized for micropower bootstrap start-up from high

input voltages. The LT1952-1 allows start-up from lower

input voltages. Programmable slope compensation and

leadingedgeblankingallowoptimizationofloopbandwidth

with a wide range of inductors and MOSFETs. Each device

can be programmed over a 100kHz to 500kHz frequency

range and the part can be synchronized to an external

clock. The error ampliﬁer is a true op amp, allowing a wide

range of compensation networks. The LT1952/LT1952-1

are available in a small 16-pin SSOP package.

n

Synchronous Rectiﬁer Control for High Efﬁciency

n

Programmable Volt-Second Clamp

n

Output Power Levels from 25W to 500W

n

Low Current Start-Up

(LT1952: 460μA; V On/Off = 14.25V/8.75V)

IN

(LT1952-1: 400μA; V On/Off = 7.75V/6.5V)

IN

n

True PWM Soft-Start

n

Low Stress Short-Circuit Protection

n

Precision 107mV Current Limit Threshold

n

Adjustable Delay for Synchronous Timing

n

Accurate Shutdown Threshold with Programmable

Hysteresis

n

Programmable Slope Compensation

n

Programmable Leading Edge Blanking

n

Programmable Frequency (100kHz to 500kHz)

n

Synchronizable to an External Clock up to 1.5 • f

OSC

n

Internal 1.23V Reference

2.5V External Reference

Current Mode Control

Small 16-Pin SSOP Package

APPLICATIONS

n

Telecommunications Power Supplies

n

Industrial and Distributed Power

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

n

Isolated and Non Isolated DC/DC Converters

TYPICAL APPLICATION

36V to 72V Input, 12V at 20A Semi-Regulated Bus Converter

12V Bus Converter

_OUTvs V_IN

L1

V

T1

V

IN

PA1494.242

V

12V

20A

PA0905

OUT

SUPPLY FROM BIAS

WINDING OF T1

16

14

12

10

8

10μF

47μF

16V

X5R

s2

V

IN

REF

52.3k

100k

Si7370

s2

PH4840

s2

COMP

Si7450

SS_MAXDC

OUT

OC

V

IN

340k

LT1952/

LT1952-1

I

0.005Ω

T2

SENSE

SD_V

FB

SEC

LTC3900

FG

CG

13k

SYNC

GND

SOUT

SYNC

560Ω

R

220pF

OSC

36

48

54

(V)

60

66

72

42

V

PGND BLANK DELAY

40k 40k

IN

0.1μF

1952 TA01b

178k

1952 TA01

19521fd

1

LT1952/LT1952-1

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

TOP VIEW

V (Note 8) ...............................................–0.3V to 25V

IN

COMP

FB

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

SOUT

SYNC, SS_MAXDC, SD_V , I

, OC ....–0.3V to 6V

SEC SENSE

V

IN

COMP, BLANK, DELAY...............................–0.3V to 3.5V

R

OUT

OSC

FB ................................................................–0.3V to 3V

SYNC

PGND

DELAY

OC

R

..................................................................... –50μA

....................................................................–10mA

OSC

REF

SS_MAXDC

V

REF

Operating Junction Temperature Range

SD_V

SEC

I

SENSE

(Notes 2, 5)............................................–40°C to 125°C

Storage Temperature Range...................–65°C to 150°C

Lead Temperature (Soldering, 10 sec) .................. 300°C

GND

BLANK

GN PACKAGE

16-LEAD PLASTIC SSOP

T

= 125°C, θ = 110°C/W, θ = 40°C/W

JA JC

JMAX

ORDER INFORMATION

LEAD FREE FINISH

LT1952EGN#PBF

LT1952IGN#PBF

LT1952EGN-1#PBF

LT1952IGN-1#PBF

LEAD BASED FINISH

LT1952EGN

TAPE AND REEL

PART MARKING

1952

PACKAGE DESCRIPTION

16-Lead Plastic SSOP

PACKAGE DESCRIPTION

16-Lead Plastic SSOP

TEMPERATURE RANGE

–40°C to 125°C

TEMPERATURE RANGE

–40°C to 125°C

LT1952EGN#TRPBF

LT1952IGN#TRPBF

LT1952EGN-1#TRPBF

LT1952IGN-1#TRPBF

TAPE AND REEL

1952I

19521

1952I1

PART MARKING

1952

LT1952EGN#TR

LT1952IGN

LT1952IGN#TR

1952I

LT1952EGN-1

LT1952EGN-1#TR

LT1952IGN-1#TR

19521

LT1952IGN-1

1952I1

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. COMP = open, FB = 1.4V, R_OSC= 178k, SYNC = 0V, SS_MAXDC = V_REF, V_REF

= 0.1μF, SD_V_SEC= 2V, BLANK = 121k, DELAY = 121k, I_SENSE= 0V, OC = 0V, OUT = 1nF, V_IN= 15V, SOUT = open, unless otherwise speciﬁed.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

PWM CONTROLLER

Operational Input Voltage

l

I(V ) = 0μA

V

OFF

IN

25

6.5

V

mA

μA

V

REF

V

IN

V

IN

V

IN

V

IN

Quiescent Current

I(V ) = 0μA, I = OC = Open

REF SENSE

5.2

460

400

240

1.32

0

l

Start-up Current (LT1952)

Start-up Current (LT1952-1)

Shutdown Current

FB = 0V, SS_MAXDC = 0V (Notes 4, 9)

700

575

350

1.379

SD_V

= 0V

SEC

l

SD_V

Threshold

10V < V < 25V

1.261

8.3

SEC

IN

Current

SD_V

= SD_V

Threshold + 100mV

Threshold – 100mV

μA

SEC (ON)

SEC (OFF)

SEC

10

11.7

μA

SEC

19521fd

2

LT1952/LT1952-1

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. COMP = open, FB = 1.4V, R_OSC= 178k, SYNC = 0V, SS_MAXDC = V_REF, V_REF

= 0.1μF, SD_V_SEC= 2V, BLANK = 121k, DELAY = 121k, I_SENSE= 0V, OC = 0V, OUT = 1nF, V_IN= 15V, SOUT = open, unless otherwise speciﬁed.

PARAMETER

CONDITIONS

MIN

TYP

14.25

8.75

5.5

MAX

15.75

9.25

6.75

8.13

6.82

UNITS

l

V

(LT1952)

V

IN ON

IN OFF

(LT1952)

3.75

IN HYSTERESIS

(LT1952-1)

7.75

6.5

IN ON

(LT1952-1)

IN OFF

(LT1952-1)

0.95

1.25

IN HYSTERESIS

REF

l

Output Voltage

I(V ) = 0μA

2.425

2.5

1

2.575

10

V

mV

REF

Line Regulation

Load Regulation

OSCILLATOR

I(V ) = 0μA, 10V < V < 25V

REF IN

0μA < I(V ) < 2.5mA

1

10

REF

l

Frequency: f

R

= 178k, FB = 1V, SS_MAXDC = 1.84V

= 365k, FB = 1V

165

200

240

kHz

OSC

Minimum Programmable f

Maximum Programmable f

R

OSC

R

OSC

80

440

100

500

120

560

kHz

OSC

= 64.9k, COMP = 2.5V, SD_V

= 2.64V

SEC

SYNC Input Resistance

18

kΩ

V

SYNC Switching Threshold

FB = 1V

1.5

2.2

1.5

SYNC Frequency/f

FB = 1V (Note 7)

1.25

0.05

OSC

f

Line Reg

FB = 1V, R

SS_MAXDC = 1.84V

= 178k; 10V < V < 25V,

0.33

%/V

V

OSC

IN

V

ROSC

R

OSC

Pin voltage

1

ERROR AMPLIFIER

l

FB Reference Voltage

FB Input Bias Current

Open Loop Voltage Gain

Unity Gain Bandwidth

COMP Source Current

COMP Sink Current

10V < V < 25V, V + 0.2V < COMP < V – 0.2

1.201

65

1.226

–75

85

1.250

–200

V

nA

dB

MHz

mA

μA

V

IN

OL

OH

FB = FB Reference Voltage

+ 0.2V < COMP < V – 0.2

V

OL

OH

(Note 6)

3

FB = 1V, COMP = 1.6V

COMP = 1.6V

–4

4

–9

10

COMP Current (Disabled)

FB = V , COMP = 1.6V

18

2.7

0.7

23

28

REF

COMP High Level: V

FB = 1V, I

= –250μA

(COMP)

3.2

0.8

0.15

OH

COMP Active Threshold

FB = 1V, SOUT Duty Cycle > 0 %

= 250μA

V

COMP Low Level: V

CURRENT SENSE

I

0.4

V

OL

(COMP)

I

Maximum Threshold

COMP = 2.5V, FB = 1V

197

98

220

243

mV

SENSE

I

Input Current (Duty Cycle = 0%)

Input Current (Duty Cycle = 80%)

COMP = 2.5V, FB = 1V (Note 4)

–8

–35

μA

SENSE

OC Threshold

COMP = 2.5V, FB = 1V

(OC = 100mV)

107

–50

180

540

1

116

mV

nA

ns

V

OC Input Current

–100

Default Blanking Time

Adjustable Blanking Time

COMP = 2.5V, FB = 1V, R

= 40k (Note 10)

= 120k

BLANK

V

BLANK

19521fd

3

LT1952/LT1952-1

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. COMP = open, FB = 1.4V, R_OSC= 178k, SYNC = 0V, SS_MAXDC = V_REF, V_REF

= 0.1μF, SD_V_SEC= 2V, BLANK = 121k, DELAY = 121k, I_SENSE= 0V, OC = 0V, OUT = 1nF, V_IN= 15V, SOUT = open, unless otherwise speciﬁed.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

SOUT DRIVER

SOUT Clamp Voltage

SOUT Low Level

SOUT High Level

I

= 0μA, COMP = 2.5V, FB = 1V

= 25mA

10.5

12

13.5

0.75

V

(GATE)

0.5

= –25mA, V = 12V, COMP = 2.5V,

10

1

IN

FB = 1V

SOUT Active Pull-Off in Shutdown

V

= 5V, SD_V

= 0V, SOUT = 1V

SEC

mA

IN

SOUT to OUT (Rise) DELAY (t

)

COMP = 2.5V, FB = 1V (Note 10)

= 120k

40

120

ns

DELAY

R

DELAY

V

DELAY

0.9

V

OUT DRIVER

OUT Rise Time

OUT Fall Time

OUT Clamp Voltage

OUT Low Level

FB = 1V, CL = 1nF (Notes 3, 6)

50

30

13

ns

V

I

= 0μA, COMP = 2.5V, FB = 1V

11.5

14.5

(GATE)

I

= 20mA

= 200mA

0.45

1.25

0.75

1.8

V

(GATE)

OUT High Level

I

= –20mA, V = 12V, COMP = 2.5V,

9.9

V

(GATE)

IN

FB = 1V

I

= –200mA, V = 12V, COMP = 2.5V,

9.75

V

(GATE)

IN

FB = 1V

OUT Active Pull-Off in Shutdown

OUT Max Duty Cycle

V

= 5V, SD_V

= 0V, OUT = 1V

SEC

20

83

mA

%

IN

COMP = 2.5V, FB = 1V, R

(f

SD_V

= 10k

DELAY

= 200kHz), V = 10V

OSC

IN

= 1.4V, SS_MAXDC = V

90

SEC

REF

OUT Max Duty Cycle Clamp

COMP = 2.5V, FB = 1V, R

= 10k

DELAY

(f

= 200kHz), V = 10V

OSC

IN

SD_V

= 1.32V, SS_MAXDC = 1.84V

= 2.64V, SS_MAXDC = 1.84V

63.5

25

72

33

80.5

41

%

SEC

SOFT-START

SS_MAXDC Low Level: V

I

= 150μA, OC = 1V

0.2

0.45

0.8

V

OL

(SS_MAXDC)

SS_MAXDC Soft-Start Reset Threshold

SS_MAXDC Active Threshold

Measured on SS_MAXDC

FB = 1V, DC > 0%

V

SS_MAXDC Input Current (Soft-Start Pull-Down: Idis) SS_MAXDC = 1V, SD_V

= 1.4V, OC = 1V

800

μA

SEC

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LT1952EGN/LT1952EGN-1 are guaranteed to meet

performance speciﬁcations from 0°C to 125°C junction temperature.

Speciﬁcations over the –40°C to 125°C operating junction temperature

range are assured by design, characterization and correlation with

statistical process controls. The LT1952IGN/LT1952IGN-1 are guaranteed

over the full –40°C to 125°C operating junction temperature range.

Note 5: Each IC includes over-temperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when over-temperature protection is active.

Continuous operation above the speciﬁed maximum operating junction

temperature may impair device reliability.

Note 6: Guaranteed but not tested.

Note 7: Maximum recommended SYNC frequency = 500kHz.

Note 8: In applications where the V pin is supplied via an external RC

IN

network from a SYSTEM V > 25V, an external zener with clamp voltage

IN

V

< V < 25V should be connected from the V pin to ground.

IN ON(MAX)

Z

I

N

Note 3: Rise and Fall times are measured at 10% and 90% levels.

Note 4: Guaranteed by correlation to static test.

Note 9: V start-up current is measured at V = V – 0.25V and

IN

IN ON

scaled by x 1.18 (to correlate to worst case V start-up current at V

).

IN

IN ON

Note 10: Timing for R = 40k derived from measurement with R = 240k.

19521fd

4

LT1952/LT1952-1

TYPICAL PERFORMANCE CHARACTERISTICS

Switching Frequency

vs Temperature

V_INShutdown Current

vs Temperature

FB Voltage vs Temperature

1.25

1.24

1.23

1.22

1.21

1.20

245

230

215

200

185

170

155

500

450

400

350

300

250

200

150

100

V

= 15V

SEC

IN

SD_V

= 0V

–50

0

25

50

75 100 125

–50

0

25

50

75 100 125

–50

0

25

50

75 100 125

–25

TEMPERATURE (°C)

1952 G01

1952 G02

1952 G03

V_INStart-up Current

vs Temperature

SD_V_SECTurn ON Threshold

vs Temperature

V_INI_Qvs Temperature

600

550

500

450

400

350

300

250

200

6.5

6.0

5.5

5.0

4.5

4.0

3.5

1.42

1.37

1.32

1.27

1.22

SD_V

= 1.4V

OC = OPEN

SEC

LT1952

LT1952-1

–50

0

25

50

75 100 125

–50

0

25

50

75 100 125

–50

0

25

50

75 100 125

–25

TEMPERATURE (°C)

1952 G04

1952 G05

1952 G06

SD_V_SECPin Current

vs Temperature

V_INTurn ON/OFF Voltage

vs Temperature

COMP Active Threshold

vs Temperature

15

10

5

18

16

14

12

10

8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

R

= 0k

ISENSE

PIN CURRENT BEFORE

PART TURN ON

LT1952 V TURN ON VOLTAGE

IN

LT1952 V TURN OFF VOLTAGE

IN

0mA PIN CURRENT AFTER

PART TURN ON

LT1952-1 V ON

LT1952-1 V OFF

IN

0

6

–50

0

25

50

75 100 125

–50

0

25

50

75 100 125

–50

0

25

50

75 100 125

–25

TEMPERATURE (°C)

1952 G07

1952 G08

1952 G09

19521fd

5

LT1952/LT1952-1

TYPICAL PERFORMANCE CHARACTERISTICS

COMP Source Current

vs Temperature

COMP Sink Current

vs Temperature

(Disabled) COMP Pin Current

vs Temperature

12.5

10.0

7.5

12.5

10.0

7.5

50

40

30

20

10

0

FB = 1V

COMP = 1.6V

FB = 1.4V

COMP = 1.6V

FB = V

REF

COMP = 1.6V

CURRENT OUT OF PIN

5.0

–50

0

25

50

75 100 125

–50

0

25

50

75 100 125

–50

0

25

50

75 100 125

–25

TEMPERATURE (°C)

1952 G10

1952 G11

1952 G12

I_SENSEMaximum Threshold

vs COMP

I_SENSEMaximum Threshold

vs Temperature

I_SENSEPin Current (Out of Pin)

vs Duty Cycle

240

230

220

210

200

40

30

20

10

0

240

200

160

120

80

COMP = 2.5V

T

= 25°C

T

= 25°C

ISENSE

A

R

= 0k

R

= 0k

ISENSE

OC THRESHOLD

40

0

–50

0

25

50

75 100 125

–25

0

20 30 40 50 60 70 80 90 100

DUTY CYCLE (%)

0

1.0

1.5

2.0

2.5

3.0

10

0.5

TEMPERATURE (°C)

COMP (V)

1952 G14

1952 G15

1952 G13

I

_SENSEMaximum Threshold

vs Duty Cycle (Programming

Slope Compensation)

OC (Overcurrent) Threshold

vs Temperature

Blank Duration vs Temperature

225

215

205

195

185

175

120

110

100

90

800

600

400

200

0

PRECISION OVERCURRENT THRESHOLD

INDEPENDENT OF DUTY CYCLE

R

= 0W

SLOPE

R

= 120k

BLANK

R

= 470W

R

= 40k

50

BLANK

25

R

SLOPE

= 1k

T

= 25°C

A

COMP = 2.5V

80

0

20 30 40 50 60 70 80 90 100

DUTY CYCLE (%)

–50

0

25

50

75 100 125

–50

0

75 100 125

10

–25

TEMPERATURE (°C)

1952 G16

1952 G17

1952 G18

19521fd

6

LT1952/LT1952-1

TYPICAL PERFORMANCE CHARACTERISTICS

t_DELAY: SOUT Rise to OUT Rise

vs Temperature

t_DELAY: SOUT Rise to OUT Rise

vs R_DELAY

BLANK Duration vs R_BLANK

1000

800

600

400

200

0

200

150

100

50

240

160

80

T

= 25°C

T = 25°C

A

R

= 120k

DELAY

= 40k

50

DELAY

25

0

40 60 80 100 120 140 160

(k)

–50

0

75 100 125

0

80

120

R

DELAY

160

(k)

200

240

20

–25

40

R

TEMPERATURE (°C)

BLANK

1952 G26

1952 G19

1952 G27

OUT Rise/Fall Time

vs OUT Load Capacitance

OUT: Max Duty Cycle CLAMP

vs SD_V_SEC

OUT: Max Duty Cycle vs f_OSC

125

100

75

50

25

0

100

90

80

70

60

50

40

30

20

10

0

T

= 25°C

A

t

r

t

f

80

T

= 25°C

A

T

= 25°C

SS_MAXDC = 1.84V

A

SS_MAXDC = 2.5V

f

= 200kHz

= 10k

OSC

SD_V

= 1.4V

R

SEC

DELAY

70

0

1000

2000

3000

4000

5000

100

200

300

(kHz)

400

500

1.32

1.65

1.98

SD_V

2.31

2.64

OUT LOAD CAPACITANCE (pF)

f

(V)

SEC

OSC

1952 G20

1952 G21

1952 G22

OUT: Max Duty Cycle CLAMP

vs SS_MAXDC

SS_MAXDC Setting

vs f_OSC(for OUT DC = 72%)

SS_MAXDC Reset and Active

Thresholds vs Temperature

90

80

70

60

50

40

30

20

2.32

2.20

2.08

1.96

1.84

1.72

1.60

1.2

1.0

0.8

0.6

0.4

0.2

0

T

f

= 25°C

T

= 25°C

A

= 200kHz

= 10k

SD_V

R

= 1.32V

OSC

SEC

R

= 10k

DELAY

ACTIVE THRESHOLD

SD_V

= 1.32V

SEC

SD_V

= 1.98V

= 2.64V

SEC

RESET THRESHOLD

1.60

1.84

SS_MAXDC (V)

2.08

100

200

300

(kHz)

400

500

–50

0

25

50

75 100 125

–25

f

TEMPERATURE (°C)

OSC

1952 G23

1952 G24

1952 G25

19521fd

7

LT1952/LT1952-1

PIN FUNCTIONS

COMP (Pin 1): Output Pin of the Error Ampliﬁer. The error

ampliﬁer is an op amp, allowing various compensation

networks to be connected between the COMP pin and

FB pin for optimum transient response. The voltage on

this pin corresponds to the peak current of the external

FET. Full operating voltage range is between 0.8V and

GND (Pin 8): Analog Ground.

BLANK (Pin 9): A resistor to ground adjusts the extended

blanking period of the overcurrent and current sense

ampliﬁer outputs during FET turn on—to prevent false

current limit trip. Increasing the resistor value increases

the blanking period.

2.5V corresponding to 0mV to 220mV at the I

pin.

SENSE

I

(Pin 10): The Current Sense Input for the Control

For applications using the 100mV OC pin for overcurrent

detection, typical operating range for the COMP pin is

0.8V to 1.6V. For isolated applications where COMP is

controlled by an opto-coupler, the COMP pin output drive

SENSE

Loop. Connect this pin to the sense resistor in the source

of the external power MOSFET. A resistor in series with

the I

pin programs slope compensation.

SENSE

can be disabled with FB = V , reducing the COMP pin

current to (COMP – 0.7)/40k.

REF

OC (Pin 11): An accurate 107mV threshold, independent

of duty cycle, for overcurrent detection and trigger of

soft-start. Connect this pin directly to the sense resistor

in the source of the external power MOSFET.

FB (Pin 2): Monitors the output voltage via an external

resistor divider and is compared with an internal 1.23V

reference by the error ampliﬁer. FB connected to V

disables error ampliﬁer output.

REF

DELAY (Pin 12): A resistor to ground adjusts the delay

period between SOUT rising edge and OUT rising edge.

Used to maximize efﬁciency in forward converter applica-

tions by adjusting the control timing of secondary side

synchronous rectiﬁer MOSFETs. Increasing the resistor

value increases the delay period.

R

(Pin 3): A resistor to ground programs the operating

OSC

frequency of the IC between 100kHz and 500kHz. Nominal

voltage on the R pin is 1.0V.

OSC

SYNC (Pin 4): Used to Synchronize the Internal Oscillator

to an External Signal. It is directly logic compatible and

can be driven with any signal between 10% and 90% duty

cycle. If unused, the pin can be left open or connected to

ground.

PGND (Pin 13): Power Ground.

OUT (Pin 14): Drives the Gate of an N-channel MOSFET

between 0V and V with a maximum limit of 13V on

IN

OUT pin set by an internal clamp. Active pull-off exists in

shutdown (see electrical speciﬁcation).

SS_MAXDC (Pin 5): External resistor divider from V

REF

sets maximum duty cycle clamp (SS_MAXDC = 1.84V,

V (Pin 15): Input Supply for the Part. It must be closely

IN

SD_V = 1.32V gives 72% duty cycle). Capacitor on

SEC

decoupled to ground. An internal undervoltage lockout

SS_MAXDC pin in combination with external resistor

threshold exists for V at approximately 14.25V on

IN

divider sets soft-start timing.

and 8.75V off for the LT1952. The LT1952-1 has lower

undervoltage lockout thresholds set at 7.75V on and

6.5V off.

V

(Pin6):Theoutputofaninternal2.5Vreferencewhich

REF

supplies control circuitry in the IC. Capable of sourcing up

to 2.5mA drive for external use. Bypass to ground with a

0.1μF ceramic capacitor.

SOUT (Pin 16): Switched Output in Phase with OUT Pin.

Provides sync signal for control of secondary side FETs

inforwardconverterapplicationsrequiringhighlyefﬁcient

synchronous rectiﬁcation. SOUT is actively clamped to

12V. Active pull-off exists in shutdown (see electrical

speciﬁcation).

SD_V

(Pin 7): The SD_V

pin, when pulled below

SEC

its accurate 1.32V threshold, is used to turn off the IC

and reduce current drain from V . The SD_V pin is

IN

SEC

connected to system input voltage through a resistor

divider to deﬁne undervoltage lockout (UVLO) and to

provide a Volt-Second clamp on the OUT pin. A 10μA pin

current hysteresis allows external programming of UVLO

hysteresis.

19521fd

8

LT1952/LT1952-1

TIMING DIAGRAM

t : PROGRAMMABLE SYNCHRONOUS DELAY

DELAY

SOUT

OUT

SS_MAXDC

FAULTS TRIGGERING SOFT-START

< 8.75V

V

IN

OR

SD_V

OR

0.8V (ACTIVE THRESHOLD)

< 1.32V (UVLO)

SEC

0.45V (RESET THRESHOLD)

0.2V

OC > 107mV (OVERCURRENT)

SOFT-START LATCH RESET:

> 14.25V (> 8.75V IF LATCH SET BY OC)

SOFT-START

LATCH SET

V

IN

AND

SD_V

AND

> 1.32V

SEC

OC < 107mV

AND

SS_MAXDC < 0.45V

1952 F01

Figure 1. Timing Diagram

BLOCK DIAGRAM

V

REF

6

SS_MAXDC

5

IN

15

START-UP

INPUT CURRENT (ISTART)

LT1952

= 460μA

ON = 14.25V

OFF = 8.75V

V

ON

IN

V

REF

OFF

I

0.45V

+

–

START

IN

>90%

V

SOFT-START CONTROL

V

+

–

2.5V

LT1952-1

R

S

I

= 400μA

ON = 7.75V

OFF = 6.5V

SOURCE

2.5mA

START

IN

V

Q

V

–

+

p50mA

1.23V

ADAPTIVE

MAXIMUM

DUTY CYCLE

CLAMP

16

SOUT

–

+

12V

I

HYST

10μA SD_V

= 1.32V

SEC

> 1.32V

0μA SD_V

SEC

+

–

(TYPICAL 200kHz)

OSC

ON

DELAY

DRIVER

p1A

SD_V

7

3

S

R

Q

SEC

14

OUT

1.32V

(LINEAR)

R

OSC

(100 TO 500)kHz

SLOPE COMP

8μA 0% DC

RAMP

13 PGND

35μA 80% DC

SYNC

4

13V

BLANK

(VOLTAGE)

ERROR AMPLIFIER

+

–

OVER

CURRENT

1.23V

SENSE

CURRENT

+

–

11

10

OC

0mV TO 220mV

107mV

I

SENSE

2

1

8

9

12

1952 BD

FB

COMP

GND

BLANK

DELAY

Figure 2. Block Diagram

19521fd

9

LT1952/LT1952-1

OPERATION

Introduction

clamped to 12V and provides sync signal timing for

synchronous rectiﬁcation control.

The LT1952/LT1952-1 are current mode synchronous

PWM controllers optimized for control of the simplest

forward converter topology—using only one primary

MOSFET. TheLT1952/LT1952-1areidealfor25Wto500W

power systems where very high efﬁciency and reliability,

low complexity and cost are required in a small space.

Key features of the LT1952/LT1952-1 include an adaptive

maximumdutycycleclampforthesingleprimaryMOSFET.

An additional output signal is included for synchronous

rectiﬁer control. A precision 107mV threshold senses

overcurrent conditions and triggers Soft-Start for low

stress short-circuit protection and control. The key

functions of the LT1952/LT1952-1 are shown in the Block

Diagram in Figure 2.

For SOUT and OUT turn on, a PWM latch is set at the start

of each main oscillator cycle. OUT turn on is delayed from

SOUT turn on by a time t

(Figure 2). t

is pro-

DELAY

grammed using a resistor from the DELAY pin to ground

and is used to set the timing control of the secondary

synchronous rectiﬁers for optimum efﬁciency.

SOUT and OUT turn off at the same time each cycle by

one of three methods:

(1) MOSFET peak current sense at I

SENSE

(2) Adaptive maximum duty cycle clamp reached during

load/line transients

(3) Maximum duty cycle reset of the PWM latch

Part Start-up

During any of the following conditions—low V , low

IN

SD_V

or overcurrent detection at the OC pin—a soft-

In normal operation the SD_V

pin must exceed 1.32V

SEC

start event is latched and both SOUT and OUT turn off

immediately (Figure 1).

and the V pin must exceed 14.25V (7.75V LT1952-1) to

IN

allow the part to turn on. This combination of pin voltages

allows the 2.5V V pin to become active, supplying the

REF

Leading Edge Blanking

LT1952/LT1952-1 control circuitry and providing up to

2.5mA external drive. SD_V threshold can be used for

TopreventMOSFETswitchingnoisecausingprematureturn

off of SOUT or OUT, programmable leading edge blanking

exists. This means both the current sense comparator

and overcurrent comparator outputs are ignored during

MOSFET turn on and for an extended period after the OUT

leading edge (Figure 6). The extended blanking period is

programmable by adjusting a resistor from the BLANK

pin to ground.

SEC

externally programming an undervoltage lockout (UVLO)

threshold on the system input voltage. Hysteresis on

the UVLO threshold can also be programmed since the

SD_V pin draws 11μA just before part turn on and 0μA

SEC

after part turn on.

With the LT1952/LT1952-1 turned on, the V pin can drop

IN

as low as 8.75V (6.5V LT1952-1) before part shutdown

occurs. This V pin hysteresis (5.5V LT1952; 1.25V

IN

Adaptive Maximum Duty Cycle Clamp

(Volt-Second Clamp)

LT1952-1) combined with low 460μA (400μA LT1952-1)

start-up input current allows low power start-up using

a resistor/capacitor network from system V to supply

For forward converter applications using the simplest

topology of a single MOSFET on the primary, a maximum

switchdutycycleclampwhichadaptstotransformerinput

voltageisnecessaryforreliablecontroloftheMOSFET.This

volt-second clamp provides a safeguard for transformer

reset that prevents transformer saturation. Instantaneous

load changes can cause the converter loop to demand

maximum duty cycle. If the maximum duty cycle of the

switch is too great, the transformer reset voltage can

exceedthevoltageratingoftheprimary-sideMOSFETwith

IN

the V pin (Figure 3). The V capacitor value is chosen

IN

to prevent V falling below its turn off threshold before

IN

an auxiliary winding in the converter takes over supply

to the V pin.

IN

Output Drivers

The LT1952/LT1952-1 have two outputs, SOUT and OUT.

The OUT pin provides a 1A peak MOSFET gate drive

clamped to 13V. The SOUT pin has a 50mA peak drive

19521fd

10

LT1952/LT1952-1

OPERATION

catastrophicdamage.Manyconverterssolvethisproblem

by limiting the operational duty cycle of the MOSFET to

50%orless—orbyusingaﬁxed(non-adaptive)maximum

duty cycle clamp with very large voltage rated MOSFETs.

The LT1952/LT1952-1 provide a volt-second clamp to

allow MOSFET duty cycles well above 50%. This gives

greater power utilization for the MOSFET, rectiﬁers and

transformer resulting in less space for a given power

output.Inaddition,thevolt-secondclampallowsareduced

A soft-start event is triggered whenever V is too low,

IN

SD_V

is too low (UVLO), or a 107mV overcurrent

SEC

threshold at OC pin is exceeded. Whenever a soft-start

event is triggered, switching at SOUT and OUT is stopped

immediately.

The SS_MAXDC pin is discharged and only released for

charging when it has fallen below it’s reset threshold

of 0.45V and all faults have been removed. Increasing

voltage on the SS_MAXDC pin above 0.8V will increase

switch maximum duty cycle. A capacitor to ground on

the SS_MAXDC pin in combination with a resistor divider

voltage rating on the MOSFET resulting in lower RDS

ON

for greater efﬁciency. The volt-second clamp deﬁnes a

maximum duty cycle ‘guard rail’ which falls when system

input voltage increases.

from V , deﬁnes the soft-start timing.

REF

Current Mode Topology (I

Pin)

The LT1952/LT1952-1 SD_V

and SS_MAXDC pins

SENSE

SEC

provideacapacitorless,programmablevolt-secondclamp

solution.Somecontrollerswithvolt-secondclampscontrol

switchmaximumdutycyclebyusinganexternalcapacitor

to program maximum switch ON time. Such techniques

have a volt-second clamp inaccuracy directly related to

the error of the external capacitor/pin capacitance and the

error/drift of the internal oscillator. The LT1952/LT1952-

1 use simple resistor ratios to implement a volt-second

clamp without the need for an accurate external capacitor

and with an order of magnitude less dependency on

oscillator error.

The LT1952/LT1952-1 current mode topology eases fre-

quency compensation requirements because the output

inductordoesnotcontributetophasedelayintheregulator

loop. This current mode technique means that the error

ampliﬁer (nonisolated applications) or the optocoupler

(isolated applications) commands current (rather than

voltage)tobedeliveredtotheoutput.Thismakesfrequency

compensation easier and provides faster loop response

to output load transients.

A resistor divider from the application’s output voltage

generatesavoltageattheinvertingFBinputoftheLT1952/

LT1952-1 error ampliﬁer (or to the input of an external

optocoupler) and is compared to an accurate reference

(1.23V for LT1952/LT1952-1). The error ampliﬁer output

An increase of voltage at the SD_V

pin causes the

SEC

maximum duty cycle clamp to decrease. If SD_V

is

SEC

resistively divided down from transformer input voltage,

a volt-second clamp is realised. To adjust the initial

maximum duty cycle clamp, the SS_MAXDC pin voltage

(COMP) deﬁnes the input threshold (I

) of the current

SENSE

sense comparator. COMP voltages between 0.8V (active

threshold) and 2.5V deﬁne a maximum I threshold

is programmed by a resistor divider from the 2.5V V

REF

SENSE

pin to ground. An increase of programmed voltage on

SS_MAXDC pin provides an increase of switch maximum

duty cycle clamp.

from 0mV to 220mV. By connecting I

to a sense

SENSE

resistor in series with the source of an external power

MOSFET, the MOSFET peak current trip point (turn off)

can be controlled by COMP level and hence by the output

voltage. An increase in output load current causing the

output voltage to fall, will cause COMP to rise, increasing

Soft-Start

The LT1952/LT1952-1 provide true PWM soft-start by

using the SS_MAXDC pin to control soft-start timing. The

proportionalrelationshipbetweenSS_MAXDCvoltageand

switch maximum duty cycle clamp allows the SS_MAXDC

pintoslowlyrampoutputvoltagebyrampingthemaximum

switch duty cycle clamp—until switch duty cycle clamp

seamlessly meets the natural duty cycle of the converter.

I

threshold, increasing the current delivered to the

SENSE

output.Forisolatedapplications,theerrorampliﬁerCOMP

output can be disabled to allow the optocoupler to take

control.SettingFB=V disablestheerrorampliﬁerCOMP

REF

output, reducing pin current to (COMP – 0.7)/40k.

19521fd

11

LT1952/LT1952-1

OPERATION

Slope Compensation

latch. The OC pin is connected directly to the source of

the primary side MOSFET to monitor peak current in the

MOSFET (Figure 7). The 107mV threshold is constant

over the entire duty cycle range of the converter because

it is unaffected by the slope compensation added to the

The current mode architecture requires slope compensa-

tion to be added to the current sensing loop to prevent

subharmonic oscillations which can occur for duty cycles

above 50%. Unlike most current mode converters which

have a slope compensation ramp that is ﬁxed internally,

placing a constraint on inductor value and operating

frequency, the LT1952/LT1952-1 have externally adjust-

able slope compensation. Slope compensation can be

I

pin.

SENSE

Synchronizing

A SYNC pin allows the LT1952/LT1952-1 oscillator to be

synchronized to an external clock. The SYNC pin can be

driven from a logic level output, requiring less than 0.8V

for a logic level low and greater than 2.2V for a logic level

high. Duty cycle should run between 10% and 90%. To

avoid loss of slope compensation during synchroniza-

programmed by inserting an external resistor (R

)

SLOPE

in series with the I

pin. The LT1952/LT1952-1 have

SENSE

a linear slope compensation ramp which sources current

out of the I

pin of approximately 8μA at 0% duty

SENSE

cycle to 35μA at 80% duty cycle.

tion, the free running oscillator frequency (f ) should

OSC

Overcurrent Detection and Soft-Start (OC Pin)

be programmed to 80% of the external clock frequency

(f

). TheR

resistorchosenfornon-synchronized

SYNC

SLOPE

An added feature to the LT1952/LT1952-1 is a precise

100mV sense threshold at the OC pin used to detect

overcurrentconditionsintheconverterandsetasoft-start

operation should be increased by 1.25x (= f

/f ).

SYNC OSC

APPLICATIONS INFORMATION

Shutdown and Programming Undervoltage Lockout

The LT1952/LT1952-1 have an accurate 1.32V shutdown

SYSTEM

INPUT (V )

S

R1

R2

SD_V

threshold at the SD_V

pin. This threshold can be

SEC

–

+

OPTIONAL

SHUTDOWN

TRANSISTOR

used in conjunction with a resistor divider to deﬁne the

undervoltage lockout threshold (UVLO) of the system

11μA

1.32V

input voltage (V ) to the power converter (Figure 3). A pin

S

ON OFF

current hysteresis (10μA before part turn on, 0μA after

part turn on) allows UVLO hysteresis to be programmed.

CalculationoftheON/OFFthresholdsforthesupply(SV )

IN

LT1952/LT1952-1

to the power converter can be made as follows:

1952 F03

V

Threshold = 1.32[1 + (R1/R2)]

Figure 3. Programming Undervoltage Lockout (UVLO)

S OFF

S ON

Threshold = SV OFF + (10μA • R1)

IN

Micropower Start-Up: Selection of Start-Up Resistor

and Capacitor for V

A simple open drain transistor can be added to the resistor

divider network at the SD_V pin to control the turn off

of the LT1952/LT1952-1 (Figure 3).

IN

SEC

The LT1952/LT1952-1 use turn-on voltage hysteresis at

the V pin and low start-up current to allow micro-power

IN

start-up (Figure 4). The LT1952/LT1952-1 monitor V pin

The SD_V pin must not be left open since there must

IN

SEC

voltage to allow part turn on at 14.25V (7.75V LT1952-1)

be an external source current >10μA to lift the pin past its

and part turn off at 8.75V (6.5V LT1952-1). Low start-up

1.32V threshold for part turn on.

19521fd

12

LT1952/LT1952-1

APPLICATIONS INFORMATION

possibly exceeding the rating for the V pin. The zener

current (460μA LT1952; 400μA LT1952-1) allows a large

IN

voltage should obey V

< V < 25V.

resistor to be connected between system input supply and

IN ON(MAX)

Z

V . Once the part is turned on, input current increases to

IN

Programming Oscillator Frequency

The oscillator frequency (f ) of the LT1952/LT1952-1 is

drivetheIC(4.5mA)andtheoutputdrivers(I

). Alarge

DRIVE

enough capacitor is chosen at the V pin to prevent V

IN

OSC

fallingbelowitsturnoffthresholdbeforeanauxiliarywinding

programmed using an external resistor (R ) connected

OSC

in the converter takes over supply to V . This technique

IN

between the R

pin and ground. Figure 5 shows typical

resistor values. The LT1952/LT1952-1 free-

runningoscillatorfrequencyisprogrammableintherange

OSC

allowsasimpleresistor/capacitorforstart-upwhichdraws

f

vs R

OSC

low power from the system supply to the converter. The

values for R

and C

are given by:

START

of 100kHz to 500kHz.

R

= (V

– V )/I

IN ON(max) START(MAX)

START(MAX)

S(MIN)

Q(MAX)

Stray capacitance and potential noise pickup on the R

OSC

pin should be minimized by placing the R resistor as

C

V

= (I

+ I ) • t

DRIVE(MAX)

/

START

OSC

START(MIN)

IN HYST(MIN)

close as possible to the R

pin and keeping the area of

OSC

the R

node as small as possible. The ground side of

resistorshouldbereturneddirectlytothe(analog

OSC

Example: (LT1952)

theR

ground) GND pin. R

can be calculated by:

For V

= 36V, V

= 700μA, I

= 5mA, V

= 100μs,

= 15.75V,

OSC

S(MIN)

START(MAX)

DRIVE(MAX)

IN ON(MAX)

I

= 5.5mA,

Q(MAX)

R

= 9.125k [(4100k/f ) – 1]

OSC

= 3.75V

IN HYST(MIN)

and t

500

450

400

350

300

250

200

150

START

R

= (36 – 15.75)/700μA = 28.9k (choose 28.7k)

START

C

= (5.5mA + 5mA) • 100μs/3.75V = 0.28μF

START

(typically choose ≥ 1μF)

Forsysteminputvoltagesexceedingtheabsolutemaximum

rating of the LT1952/LT1952-1 V pin, an external zener

IN

should be connected from the V pin to ground. This

covers the condition where V charges past V

but

IN

IN ON

thepartdoesnotturnonbecauseSD_V <1.32V. Inthis

SEC

100

50 100 150 200 250 300 350 400

condition V will continue to charge towards system V ,

IN

R

(kΩ)

OSC

SYSTEM

1952 F05

INPUT (V )

S

Figure 5. Oscillator Frequency (f_OSC) vs R_OSC

FROM AUXILIARY WINDING

R

START

V

(14.25V ON, 8.75V OFF) LT1952

(7.75V ON, 6.5V OFF) LT1952-1

IN

Programming Leading Edge Blank Time

D1*

For PWM controllers driving external MOSFETs, noise

can be generated at the source of the MOSFET during

gate rise time and some time thereafter. This noise can

–

1.32V

+

potentially exceed the OC and I

pin thresholds of the

SENSE

C

START

LT1952/LT1952-1tocauseprematureturnoffofSOUTand

OUT in addition to false trigger of soft-start. The LT1952/

LT1952-1 provide programmable leading edge blanking

*FOR V > 25V, ZENER D1 RECOMMENDED

S

of the OC and I

comparator outputs to avoid false

SENSE

(V

< V < 25V)

Z

IN ON(MAX)

1952 F04

current sensing during MOSFET switching.

Figure 4. Low Power Start-Up

19521fd

13

LT1952/LT1952-1

APPLICATIONS INFORMATION

Blankingisprovidedin2phases(Figure6):Theﬁrstphase

automatically blanks during gate rise time. Gate rise times

can vary depending on MOSFET type. For this reason the

LT1952/LT1952-1 perform true ‘leading edge blanking’ by

the MOSFET. The current limit for the converter can be

programmed by:

Current limit = (107mV/R )(N /N ) – (1/2)(I )

RIPPLE

S

P

S

where:

R = sense resistor in source of primary MOSFET

automatically blanking OC and I

comparator outputs

SENSE

until OUT rises to within 0.5V of V or reaches its clamp

IN

S

level of 13V. The second phase of blanking starts after

the leading edge of OUT has been completed. This phase

is programmable by the user with a resistor connected

from the BLANK pin to ground. Typical durations for this

I

= p-p ripple current in the output inductor L1

RIPPLE

N = number of transformer secondary turns

S

N = number of transformer primary turns

P

portion of the blanking period are from 45ns at R

BLANK

= 10k to 540ns at R

= 120k. Blanking duration can

BLANK

be approximated as:

Programming Slope Compensation

The LT1952/LT1952-1 use a current mode architecture

to provide fast response to load transients and to ease

frequency compensation requirements. Current mode

switchingregulatorswhichoperatewithdutycyclesabove

50%andhavecontinuousinductorcurrentmustaddslope

compensation to their current sensing loop to prevent

subharmonic oscillations. (For more information on slope

compensation, see Application Note 19.) The LT1952/

LT1952-1haveprogrammableslopecompensationtoallow

a wide range of inductor values, to reduce susceptibility

to PCB generated noise and to optimize loop bandwidth.

The LT1952/LT1952-1 program slope compensation by

Blanking (extended) = [45(R

/10k)]ns

BLANK

(see graph in Typical Performance Characteristics)

(AUTOMATIC)

LEADING

EDGE

(PROGRAMMABLE)

CURRENT

SENSE

DELAY

EXTENDED

BLANKING

OUT

R

BLANK

(MIN)

= 10k

10k < R

b 240k

100ns

BLANK

inserting a resistor R

in series with the I

SLOPE

SENSE

(Figure 7). The LT1952/LT1952-1 generate a current at

the I pin which is linear from 0% duty cycle to the

BLANKING

SENSE

maximum duty cycle of the OUT pin. A simple calculation

0

Xns

of I(I ) • R gives an added ramp to the voltage

X + 45ns

[X + 45(R

/10k)]ns

BLANK

SENSE

SLOPE

1952 F06

at the I

pin for programmable slope compensation.

SENSE

(See both graphs ‘I

Pin Current vs. Duty Cycle’ and

SENSE

Figure 6. Leading Edge Blank Timing

‘I

Maximum Threshold vs Duty Cycle’ in the Typical

SENSE

Performance Characteristics section.)

Programming Current Limit (OC Pin)

CURRENT SLOPE = 35μA • DC

TheLT1952/LT1952-1useaprecise107mVsensethreshold

at the OC pin to detect overcurrent conditions in the

converter and set a soft-start latch. It is independent of

dutycyclebecauseitisnotaffectedbyslopecompensation

LT1952/

LT1952-1

OUT

V

I

= V + (I

• R

)

SLOPE

(ISENSE)

SENSE

S

SENSE

= 8μA + 35DC μA

V

S

DC = DUTY CYCLE

OC

R

SLOPE

FOR SYNC OPERATION

I

SENSE

programmed at the I

pin. The OC pin monitors the

I

= 8μA + (k • 35DC)μA

OSC SYNC

SENSE

SENSE(SYNC)

k = f /f

1952 F07

R

peak current in the primary MOSFET by sensing the

S

voltage across a sense resistor (R ) in the source of

S

Figure 7. Programming Slope Compensation

19521fd

14

LT1952/LT1952-1

APPLICATIONS INFORMATION

Programming Synchronous Rectiﬁer Timing:

SS_MAXDC pin using a resistor divider from V . An

REF

SOUT to OUT delay (‘t ’)

DELAY

increase of voltage at the SS_MAXDC pin causes the

maximum duty cycle clamp to increase.

The LT1952/LT1952-1 have an additional output SOUT

which provides a 50mA peak drive clamped to 12V. In

applications requiring synchronous rectiﬁcation for high

efﬁciency, the LT1952/LT1952-1 SOUT provides a sync

signal for secondary side control of the synchronous

rectiﬁer MOSFETs (Figure 11). Timing delays through the

converter can cause non-optimum control timing for the

synchronous rectiﬁer MOSFETs. The LT1952/LT1952-1

To program the volt-second clamp, the following steps

should be taken:

(1)The maximum operational duty cycle of the converter

should be calculated for the given application.

(2)An initial value for the maximum duty cycle clamp

should be calculated using the equation below with a

ﬁrst pass guess for SS_MAXDC.

provide a programmable delay (t

, Figure 8) between

DELAY

SOUT rising edge and OUT rising edge to optimize timing

control for the synchronous rectiﬁer MOSFETs to achieve

Note: Since maximum operational duty cycle occurs at

minimum system input voltage (UVLO), the voltage at the

maximum efﬁciency gains. A resistor R

connected

DELAY

SD_V

pin = 1.32V.

SEC

from the DELAY pin to ground sets the value of t

.

DELAY

Max Duty Cycle Clamp (OUT pin)

= k • 0.522(SS_MAXDC(DC)/SD_V ) –

Typical values for t

range from 10ns with R

= 160k. (see graph in Typical

=

DELAY

10k to 160ns with R

DELAY

SEC

DELAY

(t

• f

)

DELAY OSC

Performance Characteristics)

where,

SS_MAXDC(DC) = V (R /(R + R )

t

DELAY

REF

B

T

B

LT1952/

LT1952-1

SOUT

OUT

SD_V

= 1.32V at minimum system input voltage

SEC

DELAY

t

= programmed delay between SOUT and OUT

DELAY

1952 F08

R

DELAY

–7

k = 1.11 – 5.5e • (f

)

OSC

(3)Themaximumdutycycleclampcalculatedin(2)should

be programmed to be 10% greater than the maximum

operational duty cycle calculated in (1). Simple adjust-

mentofmaximumdutycyclecanbeachievedbyadjusting

SS_MAXDC.

Figure 8. Programming SOUT to OUT Delay: t_DELAY

Programming Maximum Duty Cycle Clamp

For forward converter applications using the simplest

topology of a single MOSFET on the primary, a maximum

switch duty cycle clamp which adapts to transformer

input voltage is necessary for reliable control of the

MOSFET. Thisvolt-secondclampprovidesasafeguardfor

transformerresetthatpreventstransformersaturation.The

SYSTEM

INPUT VOLTAGE

LT1952/

LT1952-1

R1

ADAPTIVE

SD_V

DUTY CYCLE

SEC

CLAMP INPUT

LT1952/LT1952-1SD_V andSS_MAXDCpinsprovidea

SEC

SS_MAXDC

R2

R *

T

capacitor-less,programmablevolt-secondclampsolution

V

REF

using simple resistor ratios (Figure 9).

1952 F09

R

B

An increase of voltage at the SD_V

pin causes the

MAX DUTY CYCLE

SEC

CLAMP ADJUST INPUT

maximumdutycycleclamptodecrease.DerivingSD_V

SEC

*MINIMUM ALLOWABLE R IS 10k TO

T

GUARANTEE SOFT-START PULL-OFF

from a resistor divider connected to system input voltage

creates the volt-second clamp. The maximum duty cycle

clamp can be adjusted by programming voltage on the

Figure 9. Programming Maximum Duty Cycle Clamp

19521fd

15

LT1952/LT1952-1

APPLICATIONS INFORMATION

Example calculation for (2)

maximum switch duty cycle clamp, determine soft-start

timing (Figure 11).

For R = 35.7k, R = 100k, V = 2.5V,

T

B

REF

R

= 40k, f

= 200kHz and SD_V

= 1.32V,

= 40ns

A soft-start event is triggered for the following faults:

DELAY

OSC

SEC

this gives SS_MAXDC(DC) = 1.84V, t

and k = 1

DELAY

(1) V < 8.75V, or

IN

(2) SD_V

< 1.32V (UVLO), or

SEC

Maximum Duty Cycle Clamp

= 1 • 0.522(1.84/1.32) – (40ns • 200kHz)

= 0.728 – 0.008 = 0.72 (Duty Cycle Clamp = 72%)

(3) OC > 107mV (overcurrent condition)

When a soft-start event is triggered, switching at SOUT

and OUT is stopped immediately. A soft-start latch is set

andSS_MAXDCpinisdischarged.TheSS_MAXDCpincan

only recharge when the soft-start latch has been reset.

Note 1: To achieve the same maximum duty cycle clamp at

100kHz as calculated for 200kHz, the SS_MAXDC voltage

should be reprogrammed by:

Note: A soft-start event caused by (1) or (2) above, also

SS_MAXDC(DC) (100kHz)

= SS_MAXDC(DC) (200kHz) • k (200kHz)/k (100kHz)

= 1.84 • 1.0/1.055 = 1.74V (k = 1.055 for 100kHz)

causes V to be disabled and to fall to ground.

REF

Soft-start latch reset requires all of the following:

Note 2 : To achieve the same maximum duty cycle clamp

while synchronizing to an external clock at the SYNC pin,

the SS_MAXDC voltage should be re-programmed as:

SS_MAXDCC

SSOOFFTT--SSTTAARRTT

EEVVEENNTT TTRRIIGGGGEERREEDD

0..88VV ((AACCTTIIVVEE TTHHRREESSHHOOLLDD))

00..4455VV ((RREESSEETT TTHHRREESSHHOOLLDD))

SS_MAXDC (DC) (fsync)

= SS_MAXDC (DC) (200kHz) • [(fosc/fsync) +

0.09(fosc/200kHz)0.6]

TIMINGG ((AA)):: SSOOFFTT SSTTAARRTTFFAAUULLTTRREEMMOOVVEEDD

BBEEFFOORREE SSSS__MMAAXXDDCC FFAALLLLSS TTOO 00..4455VV

SS_MAXDCC

For SS_MAXDC (DC) (200kHz) = 1.84V for 72%

duty cycle

00..88VV ((AACCTTIIVVEE TTHHRREESSHHOOLLDD))

SS_MAXDC (DC) (fsync = 250kHz) for 72%

duty cycle

0..4455VV ((RREESSEETT TTHHRREESSHHOOLLDD))

0.2V

= 1.84 • [(200kHz/250kHz) + 0.09(1)0.6]

= 1.638V

TIMING (B): SOFTT-

-

SSTTAARRTTFFAAUULLTTRREEMMOOVVEEDD

AFFTTEERR SSSS__MMAAXXDDCC FFAALLLLSS PPAASSTT00..4455VV

1952 F10

Figure 10. Soft-Start Timing

Programming Soft-Start Timing

SS_MAXDC(DC)

The LT1952/LT1952-1 have built-in soft-start capability to

provide low stress controlled start-up from a list of fault

conditions that can occur in the application (see Figure 1

and Figure 10). The LT1952/LT1952-1 provide true PWM

soft-startbyusingtheSS_MAXDCpintocontrolsoft-start

timing.TheproportionalrelationshipbetweenSS_MAXDC

voltage and switch maximum duty cycle clamp allows

the SS_MAXDC pin to slowly ramp output voltage by

ramping the maximum switch duty cycle clamp—until

switchdutycycleclampseamlesslymeetsthenaturalduty

LT1952/

LT1952-1

R

CHARGE

SS_MAXDC

R

T

V

REF

C

SS

C

R

B

SS

1952 F11

SS_MAXDC CHARGING MODEL

SS_MAXDC(DC) = V [R /(R + R )]

REF

B

T

B

R

= [R • R /(R + R )]

T B T B

CHARGE

cycle of the converter. A capacitor C on the SS_MAXDC

SS

Figure 11. Programming Soft-Start Timing

pin and the resistor divider from V

used to program

REF

19521fd

16

LT1952/LT1952-1

APPLICATIONS INFORMATION

(A) V > 14.25* (7.75V LT1952-1), and

Example:

For an overcurrent fault (OC > 100mV), V = 2.5V,

IN

(B) SD_V

> 1.32V, and

SEC

REF

R = 35.7k, R = 100k, C = 0.1μF and assume

T

B

SS

(C) OC < 107mV, and

V

I

= 0.45V,

SS(MIN)

DIS

–4

(D) SS_MAXDC < 0.45V (SS_MAXDC reset threshold)

~ 8e + (2.5 – 0.45)[(1/2 • 100k) – (1/35.7k)]

–4

= 8e + (2.05)(–0.23e ) = 7.5e

*V >8.75V(6.5VLT1952-1)isokforlatchresetifthelatch

IN

was only set by overcurrent condition in (3) above.

SS_MAXDC(DC) = 1.84V

–4

SS_MAXDC (t

= 1.85e–4 s

) = (1e – 7/7.5e ) • (1.84 – 0.45)

FALL

SS_MAXDC Discharge Timing

It can be seen in Figure 10 that two types of discharge

can occur for the SS_MAXDC pin. In timing (A) the fault

that caused the soft-start event has been removed before

SS_MAXDC falls to 0.45V. This means the soft-start

latch will be reset when SS_MAXDC falls to 0.45V and

SS_MAXDCwillbegincharging.Intiming(B),thefaultthat

caused the soft-start event is not removed until some time

after SS_MAXDC has fallen past 0.45V. The SS_MAXDC

pin continues to discharge to 0.2V and remains low until

all faults are removed.

IftheOCfaultisnotremovedbefore185μsthenSS_MAXDC

will continue to fall past 0.45V towards a new V

.

SS(MIN)

The typical V for SS_MAXDC at 150μA is 0.2V.

OL

SS_MAXDC Charge Timing

When all faults are removed and the SS_MAXDC pin

has fallen to its reset threshold of 0.45V or lower, the

SS_MAXDC pin will be released and allowed to charge.

SS_MAXDC will rise until it settles at its programmed DC

voltage—setting the maximum switch duty cycle clamp.

The calculation of charging time for the SS_MAXDC pin

between any two voltage levels can be approximated as

an RC charging waveform using the model shown in

Figure 11.

The time for SS_MAXDC to fall to a given voltage can be

approximated as:

SS_MAXDC (t

) =

FALL

(C /I ) • [SS_MAXDC(DC) – V

]

SS DIS

SS(MIN)

where:

TheabilitytopredictSS_MAXDCrisetimebetweenanytwo

voltages allows prediction of several key timing periods:

I

= net discharge current on C

DIS

SS

C

= capacitor value at SS_MAXDC pin

(1)No Switching Period

SS

(time from SS_MAXDC(DC) to V

+ time from

SS(MIN)

SS_MAXDC(DC) = programmed DC voltage

= minimum SS_MAXDC voltage before

V

to V

)

SS(MIN)

SS(ACTIVE)

V

SS(MIN)

recharge

(2)Converter Output Rise Time

(time from V to V

; V is the

SS(REG) SS(REG)

SS(ACTIVE)

–4

I

~ 8e + (V – V

)[(1/2R ) – (1/R )]

SS(MIN) B T

DIS

REF

level of SS_MAXDC where maximum duty cycle

clamp equals the natural duty cycle of the switch)

For faults arising from (1) and (2),

= 100mV.

V

REF

(3)Time For Maximum Duty Cycle Clamp within X% of

Target Value

For a fault arising from (3),

= 2.5V.

V

REF

The time for SS_MAXDC to charge to a given voltage V

is found by re-arranging:

SS

SS_MAXDC(DC) = V [R /(R + R )]

REF

B

T

B

V

= SS_MAXDC reset threshold = 0.45V

SS(MIN)

(if fault removed before t

)

FALL

19521fd

17

LT1952/LT1952-1

APPLICATIONS INFORMATION

(–t/RC)

V (t) = SS_MAXDC(DC) (1 – e

)

Step 3:

t(V = 0.8V) is calculated from:

SS

to give:

t = RC • (–1) • ln(1 – V /SS_MAXDC(DC))

SS

t = R

• CSS • (–1) • ln(1 – V /SS_MAXDC(DC))

SS

CHARGE

SS

–7

= 2.63e4 • 1e • (–1) • ln(1 – 0.8/1.84)

where:

–3

= 2.63e–3 • (–1) • ln(0.565) = 1.5e

s

V

= SS_MAXDC voltage at time t

SS

From Step 1 and Step 2:

SS_MAXDC(DC) = programmed DC voltage setting

maximum duty cycle clamp =

–3

–4

t

= (1.5 – 0.73)e s = 7.7e

s

CHARGE

V

(R /(R + R )

The total time of no switching for the converter due to a

soft-start event:

REF

B

T

B

R = R

(Figure 11) = R • R /(R + R )

T B T B

CHARGE

–4

= t

+ t

= 1.85e + 7.7e = 9.55e

s

DISCHARGE

CHARGE

C = C (Figure 11)

SS

Example (2) Converter Output Rise Time

Example (1) No Switching Period

The rise time for the converter output to reach regulation

can be closely approximated as the time between the start

Theperiodofnoswitchingfortheconverter,whenasoft-start

event has occurred, depends on how far SS_MAXDC can

fall before recharging occurs and how long a fault exists. It

will be assumed that a fault triggering soft-start is removed

before SS_MAXDC can reach its reset threshold (0.45V).

ofswitching(SS_MAXDC=V

)andthetimewhere

SS(ACTIVE)

converter duty cycle is in regulation (DC(REG)) and no

longercontrolledbySS_MAXDC(SS_MAXDC=V

Converter output rise time can be expressed as:

).

SS(REG)

No Switching Period = t

+ t

CHARGE

DISCHARGE

Output Rise Time = t(V

) – t(V

SS(REG)

)

SS(ACTIVE)

t

= discharge time from SS_MAXDC(DC) to

DISCHARGE

0.45V

Step 1: Determine converter duty cycle DC(REG) for

output in regulation.

t

= charge time from 0.45V to V

SS(ACTIVE)

CHARGE

ThenaturaldutycycleDC(REG)oftheconverterdependson

severalfactors.ForthisexampleitisassumedthatDC(REG)

= 60% for system input voltage near the undervoltage

t

was already calculated earlier as 185μs.

DISCHARGE

is calculated by assuming the following:

CHARGE

lockout threshold (UVLO). This gives SD_V

= 1.32V.

SEC

V

= 2.5V, R = 35.7k, R = 100k, C = 0.1μF and

SS(MIN)

REF

T

B

SS

Also assume that the maximum duty cycle clamp

programmedforthisconditionis72%forSS_MAXDC(DC)

= 0.45V.

t

= t(V = 0.8V) – t(V = 0.45V)

SS SS

CHARGE

= 1.84V, f

= 200kHz and R

= 40k.

OSC

DELAY

Step 1:

SS_MAXDC(DC) = 2.5[100k/(35.7k + 100k)] = 1.84V

= (35.7k • 100k/135.7k) = 26.3k

Step 2: Calculate V

SS(REG)

TocalculatethelevelofSS_MAXDC(V

)thatnolonger

SS(REG)

R

CHARGE

clamps the natural duty cycle of the converter, the equation

formaximumdutycycleclampmustbeused(seeprevious

section ‘Programming Maximum Duty Cycle Clamp’).

Step 2:

t(V = 0.45V) is calculated from,

SS

The point where the maximum duty cycle clamp meets

DC(REG) during soft-start is given by:

t = R

• C • (–1) • ln(1 – V /SS_MAXDC(DC))

SS

CHARGE

SS

–7

4

= 2.63e • 1e • (–1) • ln(1 – 0.45/1.84)

–3

–4

DC(REG) = Max Duty Cycle clamp

= 2.63e • (–1) • ln(0.755) = 7.3e

s

0.6 = k • 0.522(SS_MAXDC(DC)/SD_V ) –

SEC

(t

• f

)

DELAY OSC

19521fd

18

LT1952/LT1952-1

APPLICATIONS INFORMATION

–4

–7

For SD_V = 1.32V, fOSC = 200kHz and R

= 40k

t(1.803) = 2.63e • 1e • (–1) • ln(1 – 1.803/1.84)

SEC

DELAY

–3

–2

= 2.63e • (–1) • ln(0.02) = 1.03e

s

This gives k = 1 and t

= 40ns.

DELAY

HencethetimeforSS_MAXDCtochargefromitsminimum

reset threshold of 0.45V to within 2% of its target value

is given by:

Re-arranging the above equation to solve for SS_MAXDC

= V

SS(REG)

= [0.6 + (t

• f )(SD_V )]/(k • 0.522)

DELAY OSC SEC

t(1.803) – t(0.45) =

= [0.6 + (40ns • 200kHz)(1.32V)]/(1 • 0.522)

= (0.608)(1.32)/0.522 = 1.537V

–2

–4

–3

1.03e – 7.3e = 9.57e

Step 3: Calculate t(V

) – t(V

)

SS(ACTIVE)

Forward Converter Applications

SS(REG)

RecallthetimeforSS_MAXDCtochargetoagivenvoltage

is given by:

The following section covers applications where the

LT1952/LT1952-1 are used in conjunction with other LTC

parts to provide highly efﬁcient power converters using

the single switch forward converter topology.

V

SS

t = R

• C • (–1) • ln(1 – V /SS_MAXDC(DC))

SS SS

CHARGE

(Figure 11 gives the model for SS_MAXDC charging)

For R = 35.7k, R = 100k, R = 26.3k

95% Efﬁcient, 5V, Synchronous Forward Converter

T

B

CHARGE

ThecircuitinFigure14isbasedontheLT1952-1toprovide

the simplest forward power converter circuit—using only

one primary MOSFET. The SOUT pin of the LT1952-1

provides a synchronous control signal for the LTC1698

located on the secondary. The LTC1698 drives secondary

side synchronous rectiﬁer MOSFETs to achieve high

efﬁciency. The LTC1698 also serves as an error ampliﬁer

and optocoupler driver.

For C = 0.1μF, this gives t(V

)

SS

SS(ACTIVE)

4

–7

= t(V

) = 2.63e • 1e • (–1) • ln(1 – 0.8/1.84)

SS(0.8V)

–3

= 2.63e • (–1) • ln(0.565) = 1.5e

s

t(V

) = t(V

) = 26.3k • 0.1μF • –1 •

SS(1.537V)

SS(REG)

–3

ln(1 – 1.66/1.84) = 2.63e • (–1) • ln(0.146)

–3

= 5e

s

The rise time for the converter output

Efﬁciency and transient response are shown in Figures 12

and 13. Peak efﬁciencies of 95% and ultra-fast transient

response are superior to presently available power

modules. Integrated soft-start, overcurrent detection and

short-circuit hiccup mode provide low stress, reliable

protection. In addition, the circuit in Figure 14 is an all-

ceramic capacitor solution providing low output ripple

voltage and improved reliability. The LT1952-based

convertercanbeusedtoreplacepowermoduleconverters

at a much lower cost. The LT1952 solution beneﬁts from

thermalconductionofthesystemboardresultinginhigher

efﬁcienciesandlowerriseincomponenttemperatures.The

7mm height allows dense packaging and the circuit can

easily be adjusted to provide an output voltage from 1.23V

to 26V. Higher currents are achievable by simple scaling

of power components. The LT1952-1-based solution in

Figure 14 is a powerful topology for replacement of a wide

range of power modules.

–3

= t(V

= 3.5e

) – t(V

) = (5 – 1.5)e

SS(ACTIVE)

s

SS(REG)

–3

s

Example (3) Time For Maximum Duty Cycle Clamp to

Reach Within X% of Target Value

A maximum duty cycle clamp of 72% was calculated

previously in the section ‘Programming Maximum

Duty Cycle Clamp’. The programmed value used for

SS_MAXDC(DC) was 1.84V.

ThetimeforSS_MAXDCtochargefromitsminimumvalue

V

to within X% of SS_MAXDC(DC) is given by:

SS(MIN)

t(SS_MAXDC charge time within X% of target)

= t[(1 – (X/100) • SS_MAXDC(DC)] – t(V

)

SS(MIN)

For X = 2 and V

= 0.45V, t(0.98 • 1.84) –

SS(MIN)

t(0.45) = t(1.803) – t(0.45)

From previous calculations, t(0.45) = 7.3e – 4 s.

Using previous values for R , R , and C ,

T

B

SS

19521fd

19

LT1952/LT1952-1

APPLICATIONS INFORMATION

98

96

94

92

90

I

OUT

(5A/DIV)

0A

V

OUT

(200mV/DIV)

88

86

V

= 48V

IN

= 5V

OUT

OSC

f

= 300kHz

1952 F13

20μs/DIV

0

5

10

15

20

25

LOAD CURRENT (A)

Figure 13. Output Voltage Transient Response

(6A to 12A Load Step at 6A/μs)

1952 F12

Figure 12. LT1952-Based Synchronous Forward Converter

Efﬁciency vs Load Current (For Circuit in Figure 14)

+V

IN

36V TO 72V

C

IN

2.2μF

100V

X5R

L1

T1

PA0491

PA1393.152

+V

5V

0UT

20A

475k

C

7

01

16

5

SOUT

22k

SOUT

SD_V

SEC

100μF

Q2

Q3

14

11

10

13

8

X5R

2s

Q1

PH3830

SS_MAXDC

OUT

OC

100k

6

2

V

I

SENSE

REF

1k

LT1952-1

0.015Ω

FB

PGND

GND

18.2k

0.1μF

7V

BIAS

15

3

4

LTC1698

10V

BIAS

1

2

3

4

5

6

16

15

14

13

12

11

R

V

OSC

IN

V

FG

DD

115k

1μF

X5R

SYNC

CG

SYNC

9.53k

SYNC

BLANK DELAY

12

33k

1

PGND

GND

OPTO

V

COMP

AUX

0.1μF

T2

R13

270Ω

I

COMP

SYNC

560Ω

SOUT

9

+I

–I

SNS

1μF

40k

4.75k

220pF

C9, 6.8nF

V

COMP

R14

1.2k

HCPL-M453

10V

8

9

BIAS

V

OVP

FB

6

1

+V

0UT

Q1: PHM15NQ20 PHILIPS

2

3

5

4

R15

38.3k

R16

12.4k

0.1μF

1952 F14

Figure 14. 36V to 72V Input to 5V at 20A Synchronous Forward Converter

19521fd

20

LT1952/LT1952-1

APPLICATIONS INFORMATION

48V to Isolated 12V, 20A (No Opto-Coupler)

‘Bus Converter’

achieves a high 94% at 20A (Figure 15). The solution is

only slightly larger than 1/4 “brick” size and uses only

ceramic capacitors for high reliability.

The wide programmable range and accuracy of the

LT1952/LT1952-1 Volt-Second clamp makes the LT1952/

LT1952-1 an ideal choice for ‘Bus Converter’ applications

where the Volt-Second clamp provides line regulation for

the converter output. The 48V to 12V 20A ‘Bus Converter’

application in Figure16 shows a semi-regulated isolated

output without the need for an optocoupler, optocoupler

driver,referenceorfeedbacknetwork.Some‘BusConverter’

solutions run with a ﬁxed 50% duty cycle resulting in an

output variation of 2-to-1 for applications with a 72V to

36V input range. The LT1952/LT1952-1 use an accurate

wide programmable range Volt-Second clamp to initially

program and then control power supply output voltage

to typically 10% for the same 36V to 72V input range.

Efﬁciency for the LT1952 based bus converter in Figure 16

96.0

95.5

95.0

94.5

94.0

93.5

V

= 48V

IN

OUT

= 12V

93.0

4

6

8

10 12 14 16 18 20

LOAD CURRENT (A)

1952 F15

Figure 15. LT1952-Based Synchronous ‘Bus Converter’

Efﬁciency vs Load Current (For Circuit in Figure 16)

T1

V

U1

PA0815.002

2.4μH

10k

47k

82k

• •

V

OUT

IN

36V TO 72V

12V, 20A

BAS516

0.1μF

BCX55

12V

C

OUT

33μF, 16V

X5R, TDK

3x

Si7370

2x

PH4840

2x

18V

2.2μF, 100V

2x

LTC3900

•

5

6

3

1

FG

CG

+

PH21NQ15

2x

370k

7

10k

GND

CS

13.2k

27k

14

15

8

V

1μF

U1

SD_V

OUT

SEC

4

8

2

7

–

115k

V

CS

3

9

5

CC

R

V

IN

OSC

BAT760

SYNC TIMER

8V

BIAS

BLANK

GND

1μF

C

T

13

12

11

10

16

R

T

0.47μF

0.1μF

SS_MAXDC

PGND

1nF

15k

59k

10k

39k

9mΩ

LT1952 DELAY

OC

1nF

8V

BIAS

6

1

2

V

REF

470Ω

560W

220pF

COMP

FB

I

SENSE

SOUT

L1: PA1494.242 PULSE ENGINEERING

T1: PULSE ENGINEERING

T2: COILCRAFT

• •

T2

Q4470-B

1952 F16

Figure 16. 36V to 72V Input to 12V at 20A No ‘Optocoupler’ Synchronous ‘Bus Converter’

19521fd

21

LT1952/LT1952-1

APPLICATIONS INFORMATION

36V to 72V Input, 3.3V 40A Converter

This allows a signiﬁcant reduction in power component

sizing using the LT1952-based converter.

AnLT1952-basedsynchronousforwardconverterprovides

theidealsolutionforpowersuppliesrequiringhighefﬁciency

atlowoutputvoltagesandhighloadcurrents.The3.3V40A

solution in Figure 18 achieves peak efﬁciencies of 92.5%

(Figure 17) by minimizing power loss due to rectiﬁcation

at the output. Synchronous rectiﬁer control output SOUT,

with programmable delay, optimizes timing control for a

secondarysidesynchronousMOSFETcontroller(LTC3900)

which results in high efﬁciency synchronous rectiﬁcation.

TheLT1952/LT1952-1useaprecisioncurrentlimitthreshold

at the OC pin combined with a soft-start hiccup mode to

provide low stress output short-circuit protection. The

94

93

92

91

90

89

88

V

= 48V

IN

87

86

= 3.3V

OUT

OSC

f

= 300kHz

0

10

20

30

40

50

OUTPUT CURRENT (A)

maximumoutputcurrentwillvaryonly10%overthefullV

IN

1952 F17

range. During short-circuit the average power dissipation

of the circuit will be lower than 15% of maximum rated

power thanks to a soft-start controlled hiccup mode.

Figure 17. LT1952-Based Synchronous Forward Converter

Efﬁciency vs Load Current (For Circuit in Figure 18)

V

U1

PA0912.002

L1

47k

82k

• •

+V

IN

36V TO 72V

V

OUT

3.3V, 40A

BAS516

0.1μF

BCX55

12V

C

OUT

Q2

PH3230

2x

Q3

PH3230

2x

100μF

3x

18V

10k

2.2mF

LTC3900

•

5

6

3

1

FG

CG

+

370k

7

10k

GND

CS

13.2k

27k

14

15

8

V

1mF

U1

Si7846

SD_V

OUT

SEC

4

8

2

7

–

115k

V

CS

3

9

5

CC

R

OSC

V

IN

BAT760

SYNC TIMER

8V

BIAS

BLANK LT1952

SS_MAXDC

GND

PGND

DELAY

OC

1μF

1nF

13

12

11

10

16

15k

0.22μF

0.1μF

59k

10k

33k

39k

10mΩ

1nF

8V

BIAS

6

1

2

V

= 2.5V

R

470Ω

560Ω

220pF

COMP

I

SENSE

SOUT

249k

80.6k

• •

FB = 1.23V

T2

Q4470-B

2.2nF

8V

BIAS

22k

18k

2.2k

V

U1

– 4

5

2

10k

1

L1: PA0713, PULSE ENGINEERING

10k

1μF

3

+

ALL CAPACITORS X7R, CERAMIC, TDK

T2: COILCRAFT

LT1797

270Ω

PS2801

0.1μF

8

4

LT1009

1952 F18

Figure 18. 36V to 72V, 3.3V at 40A Synchronous Forward Converter

19521fd

22

LT1952/LT1952-1

APPLICATIONS INFORMATION

Bus Converter: Optimum Output Voltage Tolerance

(b)Select switch duty cycle for the Bus Converter for a

givenoutputvoltageatV

andcalculateSS_MAXDC

S(MIN)

The Bus Converter applications shown on page 1 and in

Figure 16, provide semi-regulated isolated outputs without

theneedforanoptocoupler,optocouplerdriver,referenceor

feedbacknetwork.TheLT1952/LT1952-1Volt-Secondclamp

adjusts switch duty cycle inversely proportional to input

voltagetoprovideanoutputvoltagethatisregulatedagainst

input line variations. Some bus converters use a switch duty

cycle limit which causes output voltage variation of typically

33% over a 2:1 input voltage range. The LT1952/LT1952-1

typically provide a 10% output variation for the same input

variation.Typicaloutputtoleranceisfurtherimprovedforthe

LT1952 by inserting a resistor from the system input voltage

to the SS_MAXDC pin (Rx in Figure 19).

voltage(SS1)(SeeApplicationsInformation“Program-

ming Maximum Duty Cycle Clamp”)

(c)Calculate R

= [SS1/(2.5 – SS1)] • R

T(1)

B(1)

(2)Calculate Rx:

Rx = ([V

– V

]/[SS1 • (X – 1)]) • R

S(MIN) THEV(1)

S(MAX)

R

= R

S(MAX)

• R /(R

+ R ), X = ideal duty

B(1) T(1)

THEV(1)

cycle (V

B(1)

T(1)

)/actual duty cycle (V

)

S(MAX)

(3)The addition of Rx causes an increase in the original

programmed SS_MAXDC voltage SS1. A new value for

R

shouldbecalculatedtoprovidealowerSS_MAXDC

B(1)

voltage (SS2) to correct for this offset:

TheLT1952/LT1952-1electricalspeciﬁcationsfortheOUT

Max Duty Cycle Clamp show typical switch duty cycle to

move from 72% to 33% for a 2x change of input voltage

(SS_MAXDC pin=1.84V).Sinceoutputvoltageregulation

(a)SS2 = SS1 – [(V – SS1) • R

/Rx]

THEV(1)

S(MIN)

(b)R

= [SS2/(2.5 – SS2)] • R

T(1)

B(2)

(4)The thevinin resistance R

used to calculate Rx

THEV(1)

follows V • Duty Cycle, a switch duty cycle change of

IN

should be re-established for R and R :

T

B

72% to 36% (for a 2x input voltage change) provides

minimal output voltage variation for the LT1952/LT1952-1

bus converter. To achieve this, an SS_MAXDC pin voltage

increase of 1.09x (36/33) would be required at high input

line. A resistor Rx inserted between the SS_MAXDC pin

andsysteminputvoltage(Figure19)increasesSS_MAXDC

voltage as input voltage increases, minimizing output

voltage variation over a 2:1 input voltage change.

(a) R (ﬁnal value) = R

• (R

/R

)

B

B(2)

T(1)

THEV(1) THEV(2)

(b) R (ﬁnal value) = R

• (R

/R

)

T

THEV(1) THEV(2)

where R

= R

• R /(R

+ R

)

THEV(2)

B(2)

T(1)

B(2)

T(1)

Example:

For a Bus Converter running from 36V to 72V input,

= 36V, V = 72V.

V

S(MIN)

S(MAX)

choose R

= 10k, SS_MAXDC = SS1 = 1.84V (for 72%

S(MIN

The following steps determine values for Rx, R and R :

T(1)

T

B

duty cycle at V

) = 36V)

(1)Program switch duty cycle at minimum system input

voltage (V

R

= [1.84V/(2.5V – 1.84V)] • 10k = 28k

= [28k • 10k/(28k + 10k)] = 7.4k

)

B(1)

S(MIN)

(a)R

= 10k (minimum allowed to still guarantee soft-

THEV(1)

T(1)

start pull-down)

SS_MAXDC correction = 36%/33% = 1.09

SYSTEM

INPUT VOLTAGE

Rx = [(72V – 36V)/(1.84 • 0.09)] • 7.4k = 1.6M

SS2 = 1.84 – [(36V – 1.84) • 7.4k/1.6M] = 1.682V

LT1952/

R1

R2

Rx

LT1952-1

VOLT-SECOND

CLAMP INPUT

SD_V

SEC

R

B(2)

= [1.682/(2.5 – 1.682)] • 10k = 20.6k

SS_MAXDC

R

T

R

= [20.6k • 10k/(20.6k + 10k)] = 6.7k

V

THEV(2)

REF

VOLT-SECOND

CLAMP ADJUST INPUT

1952 F19

R

B

R

/R

= 7.4k/6.7k = 1.104

THEV(1) THEV(2)

R (ﬁnal value) = 20.6k • 1.104 = 22.7k (choose 22.6k)

B

Figure 19. Optimal Programming of Maximum Duty

Cycle Clamp for Bus Converter Applications (Adding Rx)

R (ﬁnal value) = 10k • 1.104 = 11k

T

19521fd

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

23

LT1952/LT1952-1

PACKAGE DESCRIPTION

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641 Rev B)

.189 – .196*

(4.801 – 4.978)

.045 p.005

.009

(0.229)

REF

16 15 14 13 12 11 10 9

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 p.0015

.0250 BSC

RECOMMENDED SOLDER PAD LAYOUT

1

2

3

4

5

6

7

8

.015 p .004

(0.38 p 0.10)

× 45°

.0532 – .0688

(1.35 – 1.75)

.004 – .0098

(0.102 – 0.249)

.007 – .0098

(0.178 – 0.249)

0° – 8° TYP

.016 – .050

(0.406 – 1.270)

.0250

(0.635)

BSC

.008 – .012

GN16 (SSOP) 0204

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

RELATED PARTS

PART NUMBER

LT1681/LT3781

LT1698

DESCRIPTION

COMMENTS

High Efﬁciency 2-Switch Forward Control

Synchronous Forward Controllers

Secondary Synchronous Rectiﬁer Controller

Use for Isolated Power Supplies, Contains Voltage Margining, Optocoupler

Driver, Synchronization Circuit with the Primary Side, Error Ampliﬁer

LT1725

LT1950

General Purpose Isolated Flyback Controller

Single Switch Forward Controller

Drives External Power MOSFET, Senses Output Voltage Directly from

Primary Side Switching—No Optoisolator Required, 16-pin SSOP

3V ≤ V ≤ 25V, 25W to 500W, Adaptive Max Duty Cycle Clamp, Programmable

IN

Slope Compensation, Low 100mV Sense Threshold, 16-Pin SSOP

LTC3722-1/LTC3722-2 Dual Mode Phase Modulated Full-Bridge Controllers ZVS Full-Bridge Controllers

LTC3723-1/LTC3723-2 Synchronous Push-Pull PWM Controllers

High Efﬁciency Push-Pull PWM

LTC3803

LTC3806

LTC3900

SOT-23 Flyback Controller

Adjustable Slope Compensation, Internal Soft-Start, 200kHz

Excellent Cross Regulation, High Efﬁciency, Multiple Outputs

Synchronous Flyback Controller

Synchronous Rectiﬁer Driver for

Forward Converters

Use for Isolated Power Supplies, 4.5V ≤ V ≤ 11V, N-channel

IN

Synchronous MOSFET Driver, Programmable Timeout, Reverse Inductor

Current Sense, 16-pin SSOP

19521fd

LT 1108 REV D • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

24

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT1952IGN-1#TRPBF
厂家：	Linear
描述：	LT1952 - Single Switch Synchronous Forward Controller; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C 开关光电二极管
文件：	总24页 (文件大小：225K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT1952IGN-1#TRPBF [Linear]

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