LT1952_15 [Linear]
Single Switch Synchronous Forward Controller;型号: | LT1952_15 |
厂家: | Linear |
描述: | Single Switch Synchronous Forward Controller |
文件: | 总28页 (文件大小:367K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LT1952/LT1952-1
Single Switch Synchronous
Forward Controller
FEATURES
DESCRIPTION
TheLT®1952/LT1952-1arecurrentmodePWMcontrollers
optimizedtocontroltheforwardconvertertopology,using
one primary MOSFET. The LT1952/LT1952-1 provide
synchronous rectifier control, resulting in extremely
high efficiency. A programmable Volt-Second clamp
provides a safeguard for transformer reset that prevents
saturation. This allows a single MOSFET on the primary
side to reliably run at greater than 50% duty cycle for high
MOSFET, transformer and rectifier utilization. The devices
include soft-start for controlled exit from shutdown and
undervoltage lockout. A precision 107mV current limit
threshold, independent of duty cycle, combines with soft-
starttoprovidehiccupshort-circuitprotection.TheLT1952
is optimized for micropower bootstrap start-up from high
input voltages. The LT1952-1 allows start-up from lower
input voltages. Programmable slope compensation and
leadingedgeblankingallowoptimizationofloopbandwidth
with a wide range of inductors and MOSFETs. Each device
can be programmed over a 100kHz to 500kHz frequency
range and the part can be synchronized to an external
clock. The error amplifier is a true op amp, allowing a wide
range of compensation networks. The LT1952/LT1952-1
are available in a small 16-pin SSOP package.
n
Synchronous Rectifier Control for High Efficiency
n
Programmable Volt-Second Clamp
n
Output Power Levels from 25W to 500W
n
Low Current Start-Up
(LT1952: 460µA; V On/Off = 14.25V/8.75V)
IN
(LT1952-1: 400µA; V On/Off = 7.75V/6.5V)
IN
n
True PWM Soft-Start
n
Low Stress Short-Circuit Protection
n
Precision 107mV Current Limit Threshold
n
Adjustable Delay for Synchronous Timing
n
Accurate Shutdown Threshold with Programmable
Hysteresis
n
Programmable Slope Compensation
n
Programmable Leading Edge Blanking
n
Programmable Frequency (100kHz to 500kHz)
n
ꢀ SynchronizableꢀtoꢀanꢀExternalꢀClockꢀupꢀtoꢀ1.5ꢀ•ꢀf
OSC
n
n
n
n
Internal 1.23V Reference
2.5V External Reference
Current Mode Control
Small 16-Pin SSOP Package
APPLICATIONS
n
Telecommunications Power Supplies
n
Industrial and Distributed Power
L, LT, LTC and LTM are registered trademarks and ThinSOT is a trademark of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
n
Isolated and Non Isolated DC/DC Converters
TYPICAL APPLICATION
36V to 72V Input, 12V at 20A Semi-Regulated Bus Converter
12V Bus Converter
VOUT vs VIN
L1
T1
V
IN
PA1494.242
V
12V
20A
PA0905
OUT
SUPPLY FROM BIAS
WINDING OF T1
16
14
12
10
8
10µF
47µF
16V
X5R
×2
V
V
IN
REF
52.3k
100k
Si7370
×2
PH4840
×2
COMP
Si7450
SS_MAXDC
OUT
OC
V
IN
LT1952/
LT1952-1
340k
I
0.005Ω
T2
SENSE
SD_V
FB
SEC
LTC3900
FG
CG
13k
SYNC
GND
SOUT
SYNC
560Ω
R
220pF
OSC
36
48
54
(V)
60
66
72
42
V
IN
PGND BLANK DELAY
40k 40k
0.1µF
0.1µF
1952 TA01b
178k
1952 TA01
19521fe
1
LT1952/LT1952-1
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
V (Note 8) ...............................................–0.3V to 25V
IN
COMP
FB
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SOUT
SYNC, SS_MAXDC, SD_V , I
, OC ....–0.3V to 6V
SEC SENSE
V
IN
COMP, BLANK, DELAY...............................–0.3V to 3.5V
FB ................................................................–0.3V to 3V
R
OUT
OSC
SYNC
PGND
DELAY
OC
R
REF
..................................................................... –50µA
....................................................................–10mA
OSC
SS_MAXDC
V
V
REF
Operating Junction Temperature Range (Notes 2, 5)
E-, I-Grades .......................................–40°C to 125°C
MP-Grade .......................................... –55°C to 125°C
Storage Temperature Range...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
SD_V
SEC
I
SENSE
GND
BLANK
GN PACKAGE
16-LEAD PLASTIC SSOP
T
= 125°C, q = 110°C/W, q = 40°C/W
JA JC
JMAX
ORDER INFORMATION
LEAD FREE FINISH
LT1952EGN#PBF
LT1952IGN#PBF
LT1952MPGN#PBF
LT1952EGN-1#PBF
LT1952IGN-1#PBF
LT1952MPGN-1#PBF
LEAD BASED FINISH
LT1952EGN
TAPE AND REEL
PART MARKING
1952
PACKAGE DESCRIPTION
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
PACKAGE DESCRIPTION
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
LT1952EGN#TRPBF
LT1952IGN#TRPBF
LT1952MPGN#TRPBF
LT1952EGN-1#TRPBF
LT1952IGN-1#TRPBF
LT1952MPGN-1#TRPBF
TAPE AND REEL
1952I
1952
19521
1952I1
19521
PART MARKING
1952
LT1952EGN#TR
LT1952IGN
LT1952IGN#TR
1952I
LT1952MPGN
LT1952MPGN#TR
LT1952EGN-1#TR
LT1952IGN-1#TR
LT1952MPGN-1#TR
1952
LT1952EGN-1
19521
LT1952IGN-1
1952I1
19521
LT1952MPGN-1
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
19521fe
2
LT1952/LT1952-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). COMP = open, FB = 1.4V, ROSC = 178k, SYNC = 0V,
SS_MAXDC = VREF, VREF = 0.1µF, SD_VSEC = 2V, BLANK = 121k, DELAY = 121k, ISENSE = 0V, OC = 0V, OUT = 1nF, VIN = 15V, SOUT = open,
unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLER
Operational Input Voltage
l
I(V ) = 0µA
V
OFF
25
6.5
V
mA
µA
µA
µA
V
REF
IN
V
IN
V
IN
V
IN
V
IN
Quiescent Current
I(V ) = 0µA, I = OC = Open
REF SENSE
5.2
460
400
240
1.32
0
l
l
Start-up Current (LT1952)
Start-up Current (LT1952-1)
Shutdown Current
FB = 0V, SS_MAXDC = 0V (Notes 4, 9)
FB = 0V, SS_MAXDC = 0V (Notes 4, 9)
700
575
350
1.379
SD_V
= 0V
SEC
l
SD_V
SD_V
SD_V
Threshold
10V < V < 25V
1.261
8.3
SEC
IN
Current
Current
SD_V
SD_V
= SD_V
= SD_V
Threshold + 100mV
Threshold – 100mV
µA
µA
V
SEC (ON)
SEC (OFF)
SEC
SEC
SEC
10
11.7
15.75
9.25
SEC
l
l
l
V
V
V
V
(LT1952)
(LT1952)
14.25
8.75
5.5
IN ON
V
IN OFF
(LT1952)
3.75
6.75
V
IN HYSTERESIS
l
l
(LT1952-1)
E-, I-Grades
MP-Grade
7.75
7.75
8.13
8.3
V
V
IN ON
l
l
V
V
V
(LT1952-1)
6.5
6.82
V
V
IN OFF
(LT1952-1)
0.95
1.25
IN HYSTERESIS
REF
l
Output Voltage
I(V ) = 0µA
2.425
2.5
1
2.575
10
V
mV
mV
REF
Line Regulation
Load Regulation
OSCILLATOR
I(V ) = 0µA, 10V < V < 25V
REF IN
0µA < I(V ) < 2.5mA
1
10
REF
l
Frequency: f
R
= 178k, FB = 1V, SS_MAXDC = 1.84V
= 365k, FB = 1V
165
200
240
kHz
OSC
OSC
Minimum Programmable f
Maximum Programmable f
R
OSC
R
OSC
80
440
100
500
120
560
kHz
kHz
OSC
OSC
= 64.9k, COMP = 2.5V, SD_V
= 2.64V
SEC
SYNC Input Resistance
18
kΩ
V
SYNC Switching Threshold
FB = 1V
1.5
2.2
1.5
SYNC Frequency/f
FB = 1V (Note 7)
1.25
0.05
OSC
f
Line Reg
FB = 1V, R
SS_MAXDC = 1.84V
= 178k; 10V < V < 25V,
0.33
%/V
V
OSC
OSC
IN
V
R
OSC
Pin voltage
1
ROSC
ERROR AMPLIFIER
l
FB Reference Voltage
FB Input Bias Current
Open Loop Voltage Gain
Unity Gain Bandwidth
COMP Source Current
COMP Sink Current
10V < V < 25V, V + 0.2V < COMP < V – 0.2
1.201
65
1.226
–75
85
1.250
–200
V
nA
IN
OL
OH
FB = FB Reference Voltage
+ 0.2V < COMP < V – 0.2
V
OL
dB
OH
(Note 6)
3
MHz
mA
mA
µA
FB = 1V, COMP = 1.6V
COMP = 1.6V
–4
4
–9
10
COMP Current (Disabled)
FB = V , COMP = 1.6V
18
2.7
0.7
23
28
REF
COMP High Level: V
FB = 1V, I
= –250µA
3.2
0.8
V
OH
(COMP)
COMP Active Threshold
FB = 1V, SOUT Duty Cycle > 0 %
V
19521fe
3
LT1952/LT1952-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). COMP = open, FB = 1.4V, ROSC = 178k, SYNC = 0V,
SS_MAXDC = VREF, VREF = 0.1µF, SD_VSEC = 2V, BLANK = 121k, DELAY = 121k, ISENSE = 0V, OC = 0V, OUT = 1nF, VIN = 15V, SOUT =
open, unless otherwise specified.
PARAMETER
CONDITIONS
= 250µA
MIN
TYP
MAX
UNITS
COMP Low Level: V
CURRENT SENSE
I
0.15
0.4
V
OL
(COMP)
I
Maximum Threshold
COMP = 2.5V, FB = 1V
197
98
220
243
mV
SENSE
I
I
Input Current (Duty Cycle = 0%)
Input Current (Duty Cycle = 80%)
COMP = 2.5V, FB = 1V (Note 4)
COMP = 2.5V, FB = 1V (Note 4)
–8
–35
µA
µA
SENSE
SENSE
OC Threshold
COMP = 2.5V, FB = 1V
(OC = 100mV)
107
–50
180
540
1
116
mV
nA
ns
ns
V
OC Input Current
–100
Default Blanking Time
Adjustable Blanking Time
COMP = 2.5V, FB = 1V, R
COMP = 2.5V, FB = 1V, R
= 40k (Note 10)
= 120k
BLANK
BLANK
V
BLANK
SOUT DRIVER
SOUT Clamp Voltage
SOUT Low Level
SOUT High Level
I
I
I
= 0µA, COMP = 2.5V, FB = 1V
= 25mA
10.5
12
13.5
0.75
V
V
V
(GATE)
(GATE)
(GATE)
0.5
= –25mA, V = 12V, COMP = 2.5V,
10
1
IN
FB = 1V
SOUT Active Pull-Off in Shutdown
V
= 5V, SD_V
= 0V, SOUT = 1V
SEC
mA
IN
SOUT to OUT (Rise) DELAY (t
)
COMP = 2.5V, FB = 1V (Note 10)
= 120k
40
120
ns
ns
DELAY
R
DELAY
V
0.9
V
DELAY
OUT DRIVER
OUT Rise Time
OUT Fall Time
OUT Clamp Voltage
OUT Low Level
FB = 1V, CL = 1nF (Notes 3, 6)
FB = 1V, CL = 1nF (Notes 3, 6)
50
30
13
ns
ns
V
I
= 0µA, COMP = 2.5V, FB = 1V
11.5
14.5
(GATE)
I
I
= 20mA
= 200mA
0.45
1.25
0.75
1.8
V
V
(GATE)
(GATE)
OUT High Level
I
= –20mA, V = 12V, COMP = 2.5V,
9.9
V
(GATE)
IN
FB = 1V
I
= –200mA, V = 12V, COMP = 2.5V,
9.75
V
(GATE)
IN
FB = 1V
OUT Active Pull-Off in Shutdown
OUT Max Duty Cycle
V
= 5V, SD_V
= 0V, OUT = 1V
SEC
20
83
mA
%
IN
COMP = 2.5V, FB = 1V, R
(f
SD_V
= 10k
DELAY
= 200kHz), V = 10V
OSC
IN
= 1.4V, SS_MAXDC = V
90
SEC
REF
OUT Max Duty Cycle Clamp
COMP = 2.5V, FB = 1V, R
= 10k
DELAY
(f
= 200kHz), V = 10V
OSC
IN
SD_V
SD_V
= 1.32V, SS_MAXDC = 1.84V
= 2.64V, SS_MAXDC = 1.84V
63.5
25
72
33
80.5
41
%
%
SEC
SEC
19521fe
4
LT1952/LT1952-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). COMP = open, FB = 1.4V, ROSC = 178k, SYNC = 0V,
SS_MAXDC = VREF, VREF = 0.1µF, SD_VSEC = 2V, BLANK = 121k, DELAY = 121k, ISENSE = 0V, OC = 0V, OUT = 1nF, VIN = 15V, SOUT =
open, unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SOFT-START
SS_MAXDC Low Level: V
I
= 150µA, OC = 1V
0.2
0.45
0.8
V
V
OL
(SS_MAXDC)
SS_MAXDC Soft-Start Reset Threshold
SS_MAXDC Active Threshold
Measured on SS_MAXDC
FB = 1V, DC > 0%
V
SS_MAXDC Input Current (Soft-Start Pull-Down: Idis) SS_MAXDC = 1V, SD_V
= 1.4V, OC = 1V
800
µA
SEC
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: Rise and Fall times are measured at 10% and 90% levels.
Note 4: Guaranteed by correlation to static test.
Note 5: Each IC includes over-temperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when over-temperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 2: The LT1952/LT1952-1 are tested under pulsed load conditions
such that T ≈ T . The LT1952EGN/LT1952EGN-1 are guaranteed to meet
J
A
performance specifications from 0°C to 125°C junction temperature.
Specifications over the –40°C to 125°C operating junction temperature
range are assured by design, characterization and correlation with
statistical process controls. The LT1952IGN/LT1952IGN-1 are guaranteed
over the –40°C to 125°C operating junction temperature range and the
LT1952MPGN/LT1952MPGN-1 are tested and guaranteed over the full
–55°C to 125°C operating junction temperature range. Note that the
maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
factors.
Note 6: Guaranteed but not tested.
Note 7: Maximum recommended SYNC frequency = 500kHz.
Note 8: In applications where the V pin is supplied via an external RC
IN
network from a SYSTEM V > 25V, an external zener with clamp voltage
IN
V
< V < 25V should be connected from the V pin to ground.
IN ON(MAX)
Z
I
N
Note 9: V start-up current is measured at V = V – 0.25V and
IN
IN
IN ON
scaled by x 1.18 (to correlate to worst case V start-up current at V
).
IN ON
IN
Note 10: Timing for R = 40k derived from measurement with R = 240k.
19521fe
5
LT1952/LT1952-1
TYPICAL PERFORMANCE CHARACTERISTICS
Switching Frequency
vs Temperature
VIN Shutdown Current
vs Temperature
FB Voltage vs Temperature
1.25
1.24
1.23
1.22
1.21
1.20
245
230
215
200
185
170
155
500
450
400
350
300
250
200
150
100
V
= 15V
SEC
IN
SD_V
= 0V
–50
0
25
50
75 100 125
–50
0
25
50
75 100 125
–50
0
25
50
75 100 125
–25
–25
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
1952 G01
1952 G02
1952 G03
VIN Start-up Current
vs Temperature
SD_VSEC Turn ON Threshold
vs Temperature
VIN IQ vs Temperature
600
550
500
450
400
350
300
250
200
6.5
6.0
5.5
5.0
4.5
4.0
3.5
1.42
1.37
1.32
1.27
1.22
SD_V
= 1.4V
OC = OPEN
SEC
LT1952
LT1952-1
–50
0
25
50
75 100 125
–50
0
25
50
75 100 125
–50
0
25
50
75 100 125
–25
–25
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
1952 G04
1952 G05
1952 G06
SD_VSEC Pin Current
vs Temperature
VIN Turn ON/OFF Voltage
vs Temperature
COMP Active Threshold
vs Temperature
15
10
5
18
16
14
12
10
8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
R
= 0k
ISENSE
PIN CURRENT BEFORE
PART TURN ON
LT1952 V TURN ON VOLTAGE
IN
LT1952 V TURN OFF VOLTAGE
IN
0mA PIN CURRENT AFTER
PART TURN ON
LT1952-1 V ON
LT1952-1 V OFF
IN
IN
0
6
–50
0
25
50
75 100 125
–50
0
25
50
75 100 125
–50
0
25
50
75 100 125
–25
–25
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
1952 G07
1952 G08
1952 G09
19521fe
6
LT1952/LT1952-1
TYPICAL PERFORMANCE CHARACTERISTICS
COMP Source Current
vs Temperature
COMP Sink Current
vs Temperature
(Disabled) COMP Pin Current
vs Temperature
12.5
10.0
7.5
12.5
10.0
7.5
50
FB = 1V
COMP = 1.6V
FB = 1.4V
COMP = 1.6V
FB = V
REF
COMP = 1.6V
40
30
20
10
0
CURRENT OUT OF PIN
5.0
5.0
–50
0
25
50
75 100 125
–50
0
25
50
75 100 125
–50
0
25
50
75 100 125
–25
–25
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
1952 G10
1952 G11
1952 G12
ISENSE Maximum Threshold
vs COMP
ISENSE Maximum Threshold
vs Temperature
ISENSE Pin Current (Out of Pin)
vs Duty Cycle
240
230
220
210
200
40
30
20
10
0
240
200
160
120
80
COMP = 2.5V
T
= 25°C
T
= 25°C
ISENSE
A
A
R
= 0k
R
= 0k
ISENSE
OC THRESHOLD
40
0
–50
0
25
50
75 100 125
–25
0
20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
0
1.0
1.5
2.0
2.5
3.0
10
0.5
TEMPERATURE (°C)
COMP (V)
1952 G14
1952 G15
1952 G13
ISENSE Maximum Threshold
vs Duty Cycle (Programming
Slope Compensation)
OC (Overcurrent) Threshold
vs Temperature
Blank Duration vs Temperature
225
215
205
195
185
175
120
110
100
90
800
600
400
200
0
PRECISION OVERCURRENT THRESHOLD
INDEPENDENT OF DUTY CYCLE
R
= 0W
SLOPE
SLOPE
R
BLANK
= 120k
R
= 470W
R
= 40k
50
BLANK
R
SLOPE
= 1k
T
= 25°C
A
COMP = 2.5V
80
0
20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
–50
0
25
50
75 100 125
–50
0
25
75 100 125
10
–25
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
1952 G16
1952 G17
1952 G18
19521fe
7
LT1952/LT1952-1
TYPICAL PERFORMANCE CHARACTERISTICS
tDELAY: SOUT Rise to OUT Rise
vs Temperature
tDELAY: SOUT Rise to OUT Rise
vs RDELAY
BLANK Duration vs RBLANK
1000
800
600
400
200
0
200
150
100
50
240
160
80
T
= 25°C
T = 25°C
A
A
R
= 120k
DELAY
R
= 40k
50
DELAY
25
0
0
0
40 60 80 100 120 140 160
(k)
–50
0
75 100 125
0
80
120
R
DELAY
160
(k)
200
240
20
–25
40
R
TEMPERATURE (°C)
BLANK
1952 G26
1952 G19
1952 G27
OUT Rise/Fall Time
vs OUT Load Capacitance
OUT: Max Duty Cycle CLAMP
vs SD_VSEC
OUT: Max Duty Cycle vs fOSC
125
100
75
50
25
0
100
90
90
80
70
60
50
40
30
20
10
0
T
= 25°C
A
t
r
t
f
80
T
= 25°C
A
T
= 25°C
SS_MAXDC = 1.84V
A
SS_MAXDC = 2.5V
f
= 200kHz
= 10k
OSC
SD_V
= 1.4V
R
SEC
DELAY
70
0
1000
2000
3000
4000
5000
100
200
300
(kHz)
400
500
1.32
1.65
1.98
SD_V
2.31
2.64
OUT LOAD CAPACITANCE (pF)
f
(V)
SEC
OSC
1952 G20
1952 G21
1952 G22
OUT: Max Duty Cycle CLAMP
vs SS_MAXDC
SS_MAXDC Setting
vs fOSC (for OUT DC = 72%)
SS_MAXDC Reset and Active
Thresholds vs Temperature
90
80
70
60
50
40
30
20
2.32
2.20
2.08
1.96
1.84
1.72
1.60
1.2
1.0
0.8
0.6
0.4
0.2
0
T
f
= 25°C
T
= 25°C
A
A
= 200kHz
= 10k
SD_V
R
= 1.32V
OSC
SEC
R
= 10k
DELAY
DELAY
ACTIVE THRESHOLD
SD_V
= 1.32V
SEC
SD_V
SD_V
= 1.98V
= 2.64V
SEC
RESET THRESHOLD
SEC
1.60
1.84
SS_MAXDC (V)
2.08
100
200
300
(kHz)
400
500
–50
0
25
50
75 100 125
–25
f
TEMPERATURE (°C)
OSC
1952 G23
1952 G24
1952 G25
19521fe
8
LT1952/LT1952-1
PIN FUNCTIONS
COMP (Pin 1): Output Pin of the Error Amplifier. The error
amplifier is an op amp, allowing various compensation
networks to be connected between the COMP pin and
FB pin for optimum transient response. The voltage on
this pin corresponds to the peak current of the external
FET. Full operating voltage range is between 0.8V and
GND (Pin 8): Analog Ground.
BLANK (Pin 9): A resistor to ground adjusts the extended
blanking period of the overcurrent and current sense
amplifier outputs during FET turn on—to prevent false
current limit trip. Increasing the resistor value increases
the blanking period.
2.5V corresponding to 0mV to 220mV at the I
pin.
SENSE
I
(Pin 10): The Current Sense Input for the Control
For applications using the 100mV OC pin for overcurrent
detection, typical operating range for the COMP pin is
0.8V to 1.6V. For isolated applications where COMP is
controlled by an opto-coupler, the COMP pin output drive
SENSE
Loop. Connect this pin to the sense resistor in the source
of the external power MOSFET. A resistor in series with
the I
pin programs slope compensation.
SENSE
can be disabled with FB = V , reducing the COMP pin
current to (COMP – 0.7)/40k.
REF
OC (Pin 11): An accurate 107mV threshold, independent
of duty cycle, for overcurrent detection and trigger of
soft-start. Connect this pin directly to the sense resistor
in the source of the external power MOSFET.
FB (Pin 2): Monitors the output voltage via an external
resistor divider and is compared with an internal 1.23V
reference by the error amplifier. FB connected to V
disables error amplifier output.
REF
DELAY (Pin 12): A resistor to ground adjusts the delay
period between SOUT rising edge and OUT rising edge.
Used to maximize efficiency in forward converter applica-
tions by adjusting the control timing of secondary side
synchronous rectifier MOSFETs. Increasing the resistor
value increases the delay period.
R
(Pin 3): A resistor to ground programs the operating
OSC
frequency of the IC between 100kHz and 500kHz. Nominal
voltage on the R pin is 1.0V.
OSC
SYNC (Pin 4): Used to Synchronize the Internal Oscillator
to an External Signal. It is directly logic compatible and
can be driven with any signal between 10% and 90% duty
cycle. If unused, the pin can be left open or connected to
ground.
PGND (Pin 13): Power Ground.
OUT (Pin 14): Drives the Gate of an N-channel MOSFET
between 0V and V with a maximum limit of 13V on
IN
OUT pin set by an internal clamp. Active pull-off exists in
shutdown (see electrical specification).
SS_MAXDC (Pin 5): External resistor divider from V
REF
sets maximum duty cycle clamp (SS_MAXDC = 1.84V,
V (Pin 15): Input Supply for the Part. It must be closely
IN
SD_V = 1.32V gives 72% duty cycle). Capacitor on
SEC
decoupled to ground. An internal undervoltage lockout
SS_MAXDC pin in combination with external resistor
threshold exists for V at approximately 14.25V on
IN
divider sets soft-start timing.
and 8.75V off for the LT1952. The LT1952-1 has lower
undervoltage lockout thresholds set at 7.75V on and
6.5V off.
V
(Pin6):Theoutputofaninternal2.5Vreferencewhich
REF
supplies control circuitry in the IC. Capable of sourcing up
to 2.5mA drive for external use. Bypass to ground with a
0.1µF ceramic capacitor.
SOUT (Pin 16): Switched Output in Phase with OUT Pin.
Provides sync signal for control of secondary side FETs
inforwardconverterapplicationsrequiringhighlyefficient
synchronous rectification. SOUT is actively clamped to
12V. Active pull-off exists in shutdown (see electrical
specification).
SD_V
(Pin 7): The SD_V
pin, when pulled below
SEC
SEC
its accurate 1.32V threshold, is used to turn off the IC
and reduce current drain from V . The SD_V pin is
IN
SEC
connected to system input voltage through a resistor
divider to define undervoltage lockout (UVLO) and to
provide a Volt-Second clamp on the OUT pin. A 10µA pin
current hysteresis allows external programming of UVLO
hysteresis.
19521fe
9
LT1952/LT1952-1
TIMING DIAGRAM
t
: PROGRAMMABLE SYNCHRONOUS DELAY
DELAY
SOUT
OUT
SS_MAXDC
FAULTS TRIGGERING SOFT-START
< 8.75V
V
IN
OR
SD_V
OR
0.8V (ACTIVE THRESHOLD)
< 1.32V (UVLO)
SEC
0.45V (RESET THRESHOLD)
0.2V
OC > 107mV (OVERCURRENT)
SOFT-START LATCH RESET:
> 14.25V (> 8.75V IF LATCH SET BY OC)
SOFT-START
LATCH SET
V
IN
AND
SD_V
AND
> 1.32V
SEC
OC < 107mV
AND
SS_MAXDC < 0.45V
1952 F01
Figure 1. Timing Diagram
BLOCK DIAGRAM
V
V
REF
6
SS_MAXDC
5
IN
15
START-UP
INPUT CURRENT (ISTART)
LT1952
= 460µA
ON = 14.25V
OFF = 8.75V
V
V
ON
IN
IN
V
REF
OFF
I
0.45V
+
–
START
IN
IN
>90%
V
SOFT-START CONTROL
V
+
–
2.5V
LT1952-1
R
S
I
= 400µA
ON = 7.75V
OFF = 6.5V
SOURCE
2.5mA
START
IN
IN
V
Q
V
–
+
±50mA
1.23V
ADAPTIVE
MAXIMUM
DUTY CYCLE
CLAMP
16
SOUT
–
+
12V
I
HYST
10µA SD_V
= 1.32V
SEC
> 1.32V
0µA SD_V
SEC
+
–
(TYPICAL 200kHz)
OSC
ON
DELAY
DRIVER
±1A
SD_V
7
3
S
R
Q
SEC
14
OUT
1.32V
(LINEAR)
R
OSC
(100 TO 500)kHz
SLOPE COMP
8µA 0% DC
RAMP
13 PGND
35µA 80% DC
SYNC
4
13V
BLANK
(VOLTAGE)
ERROR AMPLIFIER
+
–
OVER
CURRENT
1.23V
SENSE
CURRENT
+
+
–
–
11 OC
10
0mV TO 220mV
107mV
I
SENSE
2
1
8
9
12
1952 BD
FB
COMP
GND
BLANK
DELAY
Figure 2. Block Diagram
19521fe
10
LT1952/LT1952-1
OPERATION
Introduction
clamped to 12V and provides sync signal timing for syn-
chronous rectification control.
The LT1952/LT1952-1 are current mode synchronous
PWM controllers optimized for control of the simplest
forward converter topology—using only one primary
MOSFET. TheLT1952/LT1952-1areidealfor25Wto500W
power systems where very high efficiency and reliability,
low complexity and cost are required in a small space.
Key features of the LT1952/LT1952-1 include an adaptive
maximumdutycycleclampforthesingleprimaryMOSFET.
An additional output signal is included for synchronous
rectifier control. A precision 107mV threshold senses
overcurrent conditions and triggers Soft-Start for low
stress short-circuit protection and control. The key
functions of the LT1952/LT1952-1 are shown in the Block
Diagram in Figure 2.
For SOUT and OUT turn on, a PWM latch is set at the start
of each main oscillator cycle. OUT turn on is delayed from
SOUT turn on by a time t
(Figure 2). t
is pro-
DELAY
DELAY
grammed using a resistor from the DELAY pin to ground
and is used to set the timing control of the secondary
synchronous rectifiers for optimum efficiency.
SOUT and OUT turn off at the same time each cycle by
one of three methods:
(1) MOSFET peak current sense at I
pin
SENSE
(2) Adaptive maximum duty cycle clamp reached during
load/line transients
(3) Maximum duty cycle reset of the PWM latch
Part Start-up
During any of the following conditions—low V , low
IN
SD_V
or overcurrent detection at the OC pin—a soft-
In normal operation the SD_V
pin must exceed 1.32V
SEC
SEC
start event is latched and both SOUT and OUT turn off
immediately (Figure 1).
and the V pin must exceed 14.25V (7.75V LT1952-1) to
IN
allow the part to turn on. This combination of pin voltages
allows the 2.5V V pin to become active, supplying the
REF
Leading Edge Blanking
LT1952/LT1952-1 control circuitry and providing up to
2.5mA external drive. SD_V threshold can be used for
TopreventMOSFETswitchingnoisecausingprematureturn
off of SOUT or OUT, programmable leading edge blanking
exists. This means both the current sense comparator
and overcurrent comparator outputs are ignored during
MOSFET turn on and for an extended period after the OUT
leading edge (Figure 6). The extended blanking period is
programmable by adjusting a resistor from the BLANK
pin to ground.
SEC
externally programming an undervoltage lockout (UVLO)
threshold on the system input voltage. Hysteresis on
the UVLO threshold can also be programmed since the
SD_V pin draws 11µA just before part turn on and 0µA
SEC
after part turn on.
With the LT1952/LT1952-1 turned on, the V pin can drop
IN
as low as 8.75V (6.5V LT1952-1) before part shutdown
occurs. This V pin hysteresis (5.5V LT1952; 1.25V
IN
Adaptive Maximum Duty Cycle Clamp
(Volt-Second Clamp)
LT1952-1) combined with low 460µA (400µA LT1952-1)
start-up input current allows low power start-up using
a resistor/capacitor network from system V to supply
For forward converter applications using the simplest
topology of a single MOSFET on the primary, a maximum
switchdutycycleclampwhichadaptstotransformerinput
voltageisnecessaryforreliablecontroloftheMOSFET.This
volt-second clamp provides a safeguard for transformer
reset that prevents transformer saturation. Instantaneous
load changes can cause the converter loop to demand
maximum duty cycle. If the maximum duty cycle of the
switch is too great, the transformer reset voltage can
exceedthevoltageratingoftheprimary-sideMOSFETwith
IN
the V pin (Figure 3). The V capacitor value is chosen
IN
IN
to prevent V falling below its turn off threshold before
IN
an auxiliary winding in the converter takes over supply
to the V pin.
IN
Output Drivers
The LT1952/LT1952-1 have two outputs, SOUT and OUT.
The OUT pin provides a ±1A peak MOSFET gate drive
clamped to 13V. The SOUT pin has a ± 50mA peak drive
19521fe
11
LT1952/LT1952-1
OPERATION
catastrophicdamage.Manyconverterssolvethisproblem
by limiting the operational duty cycle of the MOSFET to
50%orless—orbyusingafixed(non-adaptive)maximum
duty cycle clamp with very large voltage rated MOSFETs.
The LT1952/LT1952-1 provide a volt-second clamp to
allow MOSFET duty cycles well above 50%. This gives
greater power utilization for the MOSFET, rectifiers and
transformer resulting in less space for a given power
output.Inaddition,thevolt-secondclampallowsareduced
A soft-start event is triggered whenever V is too low,
IN
SD_V
is too low (UVLO), or a 107mV overcurrent
SEC
threshold at OC pin is exceeded. Whenever a soft-start
event is triggered, switching at SOUT and OUT is stopped
immediately.
The SS_MAXDC pin is discharged and only released for
charging when it has fallen below it’s reset threshold
of 0.45V and all faults have been removed. Increasing
voltage on the SS_MAXDC pin above 0.8V will increase
switch maximum duty cycle. A capacitor to ground on
the SS_MAXDC pin in combination with a resistor divider
voltage rating on the MOSFET resulting in lower RDS
ON
for greater efficiency. The volt-second clamp defines a
maximum duty cycle ‘guard rail’ which falls when system
input voltage increases.
from V , defines the soft-start timing.
REF
Current Mode Topology (I
Pin)
The LT1952/LT1952-1 SD_V
and SS_MAXDC pins
SENSE
SEC
provideacapacitorless,programmablevolt-secondclamp
solution.Somecontrollerswithvolt-secondclampscontrol
switchmaximumdutycyclebyusinganexternalcapacitor
to program maximum switch ON time. Such techniques
have a volt-second clamp inaccuracy directly related to
the error of the external capacitor/pin capacitance and the
error/drift of the internal oscillator. The LT1952/LT1952-
1 use simple resistor ratios to implement a volt-second
clamp without the need for an accurate external capacitor
and with an order of magnitude less dependency on
oscillator error.
The LT1952/LT1952-1 current mode topology eases fre-
quency compensation requirements because the output
inductordoesnotcontributetophasedelayintheregulator
loop. This current mode technique means that the error
amplifier (nonisolated applications) or the optocoupler
(isolated applications) commands current (rather than
voltage)tobedeliveredtotheoutput.Thismakesfrequency
compensation easier and provides faster loop response
to output load transients.
A resistor divider from the application’s output voltage
generatesavoltageattheinvertingFBinputoftheLT1952/
LT1952-1 error amplifier (or to the input of an external
optocoupler) and is compared to an accurate reference
(1.23V for LT1952/LT1952-1). The error amplifier output
An increase of voltage at the SD_V
pin causes the
SEC
maximum duty cycle clamp to decrease. If SD_V
is
SEC
resistively divided down from transformer input voltage,
a volt-second clamp is realised. To adjust the initial
maximum duty cycle clamp, the SS_MAXDC pin voltage
(COMP) defines the input threshold (I
) of the current
SENSE
sense comparator. COMP voltages between 0.8V (active
threshold) and 2.5V define a maximum I threshold
is programmed by a resistor divider from the 2.5V V
REF
SENSE
pin to ground. An increase of programmed voltage on
SS_MAXDC pin provides an increase of switch maximum
duty cycle clamp.
from 0mV to 220mV. By connecting I
to a sense
SENSE
resistor in series with the source of an external power
MOSFET, the MOSFET peak current trip point (turn off)
can be controlled by COMP level and hence by the output
voltage. An increase in output load current causing the
output voltage to fall, will cause COMP to rise, increasing
Soft-Start
The LT1952/LT1952-1 provide true PWM soft-start by
using the SS_MAXDC pin to control soft-start timing. The
proportionalrelationshipbetweenSS_MAXDCvoltageand
switch maximum duty cycle clamp allows the SS_MAXDC
pintoslowlyrampoutputvoltagebyrampingthemaximum
switch duty cycle clamp—until switch duty cycle clamp
seamlessly meets the natural duty cycle of the converter.
I
threshold, increasing the current delivered to the
SENSE
output.Forisolatedapplications,theerroramplifierCOMP
output can be disabled to allow the optocoupler to take
control.SettingFB=V disablestheerroramplifierCOMP
output, reducing pin current to (COMP – 0.7)/40k.
REF
19521fe
12
LT1952/LT1952-1
OPERATION
Slope Compensation
latch. The OC pin is connected directly to the source of
the primary side MOSFET to monitor peak current in the
MOSFET (Figure 7). The 107mV threshold is constant
over the entire duty cycle range of the converter because
it is unaffected by the slope compensation added to the
The current mode architecture requires slope compensa-
tion to be added to the current sensing loop to prevent
subharmonic oscillations which can occur for duty cycles
above 50%. Unlike most current mode converters which
have a slope compensation ramp that is fixed internally,
placing a constraint on inductor value and operating
frequency, the LT1952/LT1952-1 have externally adjust-
able slope compensation. Slope compensation can be
I
pin.
SENSE
Synchronizing
A SYNC pin allows the LT1952/LT1952-1 oscillator to be
synchronized to an external clock. The SYNC pin can be
driven from a logic level output, requiring less than 0.8V
for a logic level low and greater than 2.2V for a logic level
high. Duty cycle should run between 10% and 90%. To
avoid loss of slope compensation during synchroniza-
programmed by inserting an external resistor (R
)
SLOPE
in series with the I
pin. The LT1952/LT1952-1 have
SENSE
a linear slope compensation ramp which sources current
out of the I
pin of approximately 8µA at 0% duty
SENSE
cycle to 35µA at 80% duty cycle.
tion, the free running oscillator frequency (f ) should
OSC
Overcurrent Detection and Soft-Start (OC Pin)
be programmed to 80% of the external clock frequency
(f
). TheR
resistorchosenfornon-synchronized
SYNC
SLOPE
An added feature to the LT1952/LT1952-1 is a precise
100mV sense threshold at the OC pin used to detect
overcurrentconditionsintheconverterandsetasoft-start
operation should be increased by 1.25x (= f
/f ).
SYNC OSC
APPLICATIONS INFORMATION
Shutdown and Programming Undervoltage Lockout
The LT1952/LT1952-1 have an accurate 1.32V shutdown
SYSTEM
INPUT (V )
S
R1
R2
SD_V
threshold at the SD_V
pin. This threshold can be
SEC
SEC
–
+
OPTIONAL
SHUTDOWN
TRANSISTOR
used in conjunction with a resistor divider to define the
undervoltage lockout threshold (UVLO) of the system
11µA
1.32V
input voltage (V ) to the power converter (Figure 3). A pin
S
ON OFF
current hysteresis (10µA before part turn on, 0µA after
part turn on) allows UVLO hysteresis to be programmed.
CalculationoftheON/OFFthresholdsforthesupply(SV )
IN
LT1952/LT1952-1
to the power converter can be made as follows:
1952 F03
V
V
Threshold = 1.32[1 + (R1/R2)]
Figure 3. Programming Undervoltage Lockout (UVLO)
S OFF
S ON
Threshold = SV ꢀOFFꢀ+ꢀ(10µAꢀ•ꢀR1)
IN
Micropower Start-Up: Selection of Start-Up Resistor
and Capacitor for V
A simple open drain transistorcan be addedtothe resistor
divider network at the SD_V pin to control the turn off
of the LT1952/LT1952-1 (Figure 3).
IN
SEC
The LT1952/LT1952-1 use turn-on voltage hysteresis at
the V pin and low start-up current to allow micro-power
IN
start-up (Figure 4). The LT1952/LT1952-1 monitor V pin
The SD_V pin must not be left open since there must
IN
SEC
voltage to allow part turn on at 14.25V (7.75V LT1952-1)
be an external source current >10µA to lift the pin past its
and part turn off at 8.75V (6.5V LT1952-1). Low start-up
1.32V threshold for part turn on.
19521fe
13
LT1952/LT1952-1
APPLICATIONS INFORMATION
possibly exceeding the rating for the V pin. The zener
current (460µA LT1952; 400µA LT1952-1) allows a large
IN
voltage should obey V
< V < 25V.
resistor to be connected between system input supply and
IN ON(MAX)
Z
V . Once the part is turned on, input current increases to
IN
Programming Oscillator Frequency
The oscillator frequency (f ) of the LT1952/LT1952-1 is
drivetheIC(4.5mA)andtheoutputdrivers(I
). Alarge
DRIVE
enough capacitor is chosen at the V pin to prevent V
IN
IN
OSC
fallingbelowitsturnoffthresholdbeforeanauxiliarywinding
programmed using an external resistor (R ) connected
OSC
in the converter takes over supply to V . This technique
IN
between the R
pin and ground. Figure 5 shows typical
resistor values. The LT1952/LT1952-1 free-
runningoscillatorfrequencyisprogrammableintherange
OSC
allowsasimpleresistor/capacitorforstart-upwhichdraws
f
vs R
OSC
OSC
low power from the system supply to the converter. The
values for R
and C
are given by:
START
START
of 100kHz to 500kHz.
R
= (V
– V )/I
IN ON(max) START(MAX)
START(MAX)
S(MIN)
Q(MAX)
Stray capacitance and potential noise pickup on the R
OSC
pin should be minimized by placing the R resistor as
C
V
= (I
+ I
)ꢀ•ꢀt
/
OSC
START(MIN)
IN HYST(MIN)
DRIVE(MAX)
START
close as possible to the R
pin and keeping the area of
OSC
the R
node as small as possible. The ground side of
resistorshouldbereturneddirectlytothe(analog
OSC
OSC
Example: (LT1952)
theR
ground) GND pin. R
can be calculated by:
For V
= 36V, V
= 700µA, I
= 5mA, V
= 100µs,
= 15.75V,
IN ON(MAX)
OSC
S(MIN)
START(MAX)
DRIVE(MAX)
I
I
= 5.5mA,
Q(MAX)
R
OSC
= 9.125k [(4100k/f ) – 1]
OSC
= 3.75V
IN HYST(MIN)
and t
500
450
400
350
300
250
200
150
START
R
START
= (36 – 15.75)/700µA = 28.9k (choose 28.7k)
C
START
ꢀ=ꢀ(5.5mAꢀ+ꢀ5mA)ꢀ•ꢀ100µs/3.75Vꢀ=ꢀ0.28µFꢀ
(typically choose ≥ 1µF)
Forsysteminputvoltagesexceedingtheabsolutemaximum
rating of the LT1952/LT1952-1 V pin, an external zener
IN
IN
should be connected from the V pin to ground. This
covers the condition where V charges past V
but
IN
IN ON
thepartdoesnotturnonbecauseSD_V <1.32V. Inthis
SEC
100
50 100 150 200 250 300 350 400
condition V will continue to charge towards system V ,
IN
IN
R
OSC
(kΩ)
SYSTEM
1952 F05
INPUT (V )
S
Figure 5. Oscillator Frequency (fOSC) vs ROSC
FROM AUXILIARY WINDING
R
START
V
(14.25V ON, 8.75V OFF) LT1952
(7.75V ON, 6.5V OFF) LT1952-1
IN
Programming Leading Edge Blank Time
D1*
For PWM controllers driving external MOSFETs, noise
can be generated at the source of the MOSFET during
gate rise time and some time thereafter. This noise can
–
1.32V
+
potentially exceed the OC and I
pin thresholds of the
SENSE
C
START
LT1952/LT1952-1tocauseprematureturnoffofSOUTand
OUT in addition to false trigger of soft-start. The LT1952/
LT1952-1 provide programmable leading edge blanking
*FOR V > 25V, ZENER D1 RECOMMENDED
S
of the OC and I
comparator outputs to avoid false
SENSE
(V
< V < 25V)
Z
IN ON(MAX)
1952 F04
current sensing during MOSFET switching.
Figure 4. Low Power Start-Up
19521fe
14
LT1952/LT1952-1
APPLICATIONS INFORMATION
Blankingisprovidedin2phases(Figure6):Thefirstphase
automatically blanks during gate rise time. Gate rise times
can vary depending on MOSFET type. For this reason the
LT1952/LT1952-1 perform true ‘leading edge blanking’ by
the MOSFET. The current limit for the converter can be
programmed by:
Current limit = (107mV/R )(N /N ) – (1/2)(I )
RIPPLE
S
P
S
where:
R = sense resistor in source of primary MOSFET
automatically blanking OC and I
comparator outputs
SENSE
until OUT rises to within 0.5V of V or reaches its clamp
IN
S
level of 13V. The second phase of blanking starts after
the leading edge of OUT has been completed. This phase
is programmable by the user with a resistor connected
from the BLANK pin to ground. Typical durations for this
I
= p-p ripple current in the output inductor L1
RIPPLE
N = number of transformer secondary turns
S
N = number of transformer primary turns
P
portion of the blanking period are from 45ns at R
BLANK
= 10k to 540ns at R
= 120k. Blanking duration can
BLANK
be approximated as:
Programming Slope Compensation
The LT1952/LT1952-1 use a current mode architecture
to provide fast response to load transients and to ease
frequency compensation requirements. Current mode
switchingregulatorswhichoperatewithdutycyclesabove
50%andhavecontinuousinductorcurrentmustaddslope
compensation to their current sensing loop to prevent
subharmonic oscillations. (For more information on slope
compensation, see Application Note 19.) The LT1952/
LT1952-1haveprogrammableslopecompensationtoallow
a wide range of inductor values, to reduce susceptibility
to PCB generated noise and to optimize loop bandwidth.
The LT1952/LT1952-1 program slope compensation by
Blanking (extended) = [45(R
/10k)]ns
BLANK
(see graph in Typical Performance Characteristics)
(AUTOMATIC)
LEADING
EDGE
(PROGRAMMABLE)
CURRENT
SENSE
DELAY
EXTENDED
BLANKING
BLANKING
OUT
R
BLANK
(MIN)
= 10k
10k < R
≤ 240k
100ns
BLANK
inserting a resistor R
in series with the I
pin
SLOPE
SENSE
(Figure 7). The LT1952/LT1952-1 generate a current at
the I pin which is linear from 0% duty cycle to the
BLANKING
SENSE
maximum duty cycle of the OUT pin. A simple calculation
of I(I )ꢀ•ꢀR gives an added ramp to the voltage
0
Xns
X + 45ns
[X + 45(R
/10k)]ns
BLANK
SENSE
at the I
SLOPE
1952 F06
pin for programmable slope compensation.
SENSE
(See both graphs ‘I
Maximum Threshold vs Duty Cycle’ in the Typical
Performance Characteristics section.)
Pin Current vs. Duty Cycle’ and
SENSE
Figure 6. Leading Edge Blank Timing
‘I
SENSE
Programming Current Limit (OC Pin)
CURRENT SLOPE = 35µA • DC
TheLT1952/LT1952-1useaprecise107mVsensethreshold
at the OC pin to detect overcurrent conditions in the
converter and set a soft-start latch. It is independent of
dutycyclebecauseitisnotaffectedbyslopecompensation
LT1952/
LT1952-1
V
I
= V + (I
• R
)
(ISENSE)
SENSE
S
SENSE
SLOPE
= 8µA + 35DC µA
OUT
V
S
DC = DUTY CYCLE
OC
R
SLOPE
FOR SYNC OPERATION
I
SENSE
programmed at the I
pin. The OC pin monitors the
I
= 8µA + (k • 35DC)µA
OSC SYNC
SENSE
SENSE(SYNC)
k = f /f
1952 F07
R
peak current in the primary MOSFET by sensing the
voltage across a sense resistor (R ) in the source of
S
S
Figure 7. Programming Slope Compensation
19521fe
15
LT1952/LT1952-1
APPLICATIONS INFORMATION
Programming Synchronous Rectifier Timing:
SS_MAXDC pin using a resistor divider from V . An
REF
SOUT to OUT delay (‘t
’)
increase of voltage at the SS_MAXDC pin causes the
DELAY
maximum duty cycle clamp to increase.
The LT1952/LT1952-1 have an additional output SOUT
which provides a ± 50mA peak drive clamped to 12V. In
applications requiring synchronous rectification for high
efficiency, the LT1952/LT1952-1 SOUT provides a sync
signal for secondary side control of the synchronous
rectifier MOSFETs (Figure 11). Timing delays through the
converter can cause non-optimum control timing for the
synchronous rectifier MOSFETs. The LT1952/LT1952-1
To program the volt-second clamp, the following steps
should be taken:
(1)The maximum operational duty cycle of the converter
should be calculated for the given application.
(2)An initial value for the maximum duty cycle clamp
should be calculated using the equation below with a
first pass guess for SS_MAXDC.
provide a programmable delay (t
, Figure 8) between
DELAY
SOUT rising edge and OUT rising edge to optimize timing
control for the synchronous rectifier MOSFETs to achieve
Note: Since maximum operational duty cycle occurs at
minimum system input voltage (UVLO), the voltage at the
maximum efficiency gains. A resistor R
connected
DELAY
SD_V
pin = 1.32V.
SEC
from the DELAY pin to ground sets the value of t
.
DELAY
Max Duty Cycle Clamp (OUT pin)
ꢀ =ꢀkꢀ•ꢀ0.522(SS_MAXDC(DC)/SD_V ) –
Typical values for t
range from 10ns with R
= 160k. (see graph in Typical
=
DELAY
10k to 160ns with R
DELAY
SEC
DELAY
(t
ꢀ•ꢀf
)
DELAY OSC
Performance Characteristics)
where,
SS_MAXDC(DC) = V (R /(R + R )
t
DELAY
REF
B
T
B
LT1952/
LT1952-1
SOUT
OUT
SD_V
= 1.32V at minimum system input voltage
SEC
DELAY
t
= programmed delay between SOUT and OUT
DELAY
1952 F08
R
DELAY
–7
k = 1.11 – 5.5e ꢀ•ꢀ(f
)
OSC
(3)Themaximumdutycycleclampcalculatedin(2)should
be programmed to be 10% greater than the maximum
operational duty cycle calculated in (1). Simple adjust-
mentofmaximumdutycyclecanbeachievedbyadjusting
SS_MAXDC.
Figure 8. Programming SOUT to OUT Delay: tDELAY
Programming Maximum Duty Cycle Clamp
For forward converter applications using the simplest
topology of a single MOSFET on the primary, a maximum
switch duty cycle clamp which adapts to transformer
input voltage is necessary for reliable control of the
MOSFET. Thisvolt-secondclampprovidesasafeguardfor
transformerresetthatpreventstransformersaturation.The
SYSTEM
INPUT VOLTAGE
LT1952/
LT1952-1
R1
ADAPTIVE
SD_V
DUTY CYCLE
SEC
CLAMP INPUT
LT1952/LT1952-1SD_V andSS_MAXDCpinsprovidea
SEC
SS_MAXDC
R2
R *
T
capacitor-less,programmablevolt-secondclampsolution
V
REF
using simple resistor ratios (Figure 9).
1952 F09
R
B
An increase of voltage at the SD_V
pin causes the
MAX DUTY CYCLE
SEC
CLAMP ADJUST INPUT
maximumdutycycleclamptodecrease.DerivingSD_V
SEC
*MINIMUM ALLOWABLE R IS 10k TO
T
GUARANTEE SOFT-START PULL-OFF
from a resistor divider connected to system input voltage
creates the volt-second clamp. The maximum duty cycle
clamp can be adjusted by programming voltage on the
Figure 9. Programming Maximum Duty Cycle Clamp
19521fe
16
LT1952/LT1952-1
APPLICATIONS INFORMATION
Example calculation for (2)
maximum switch duty cycle clamp, determine soft-start
timing (Figure 11).
For R = 35.7k, R = 100k, V = 2.5V,
T
B
REF
R
= 40k, f
= 200kHz and SD_V
= 1.32V,
= 40ns
A soft-start event is triggered for the following faults:
DELAY
OSC
SEC
this gives SS_MAXDC(DC) = 1.84V, t
and k = 1
DELAY
(1) V < 8.75V, or
IN
(2) SD_V
< 1.32V (UVLO), or
SEC
Maximum Duty Cycle Clamp
ꢀ =ꢀ1ꢀ•ꢀ0.522(1.84/1.32)ꢀ–ꢀ(40nsꢀ•ꢀ200kHz)
(3) OC > 107mV (overcurrent condition)
= 0.728 – 0.008 = 0.72 (Duty Cycle Clamp = 72%)
When a soft-start event is triggered, switching at SOUT
and OUT is stopped immediately. A soft-start latch is set
andSS_MAXDCpinisdischarged.TheSS_MAXDCpincan
only recharge when the soft-start latch has been reset.
Note 1: To achieve the same maximum duty cycle clamp at
100kHz as calculated for 200kHz, the SS_MAXDC voltage
should be reprogrammed by:
Note: A soft-start event caused by (1) or (2) above, also
SS_MAXDC(DC) (100kHz)
ꢀ =ꢀSS_MAXDC(DC)ꢀ(200kHz)ꢀ•ꢀkꢀ(200kHz)/kꢀ(100kHz)
ꢀ =ꢀ1.84ꢀ•ꢀ1.0/1.055ꢀ=ꢀ1.74Vꢀ(kꢀ=ꢀ1.055ꢀforꢀ100kHz)
causes V to be disabled and to fall to ground.
REF
Soft-start latch reset requires all of the following:
Note 2 : To achieve the same maximum duty cycle clamp
while synchronizing to an external clock at the SYNC pin,
the SS_MAXDC voltage should be re-programmed as:
SS_MAXDC
SOFTT--SSTTAARRTT
EVENT TRIGGERED
0.8V (ACTIVE THRESHOLD)
SS_MAXDC (DC) (fsync)
0.45V (RESET THRESHOLD)
ꢀ =ꢀSS_MAXDCꢀ(DC)ꢀ(200kHz)ꢀ•ꢀ[(fosc/fsync)ꢀ+ꢀ
0.09(fosc/200kHz)0.6]
TIMING (A): SOFTT SSTTAARRTTFFAAUULLTTRREEMMOOVVEEDD
BEFORE SS_MAXDC FAALLLLSS TTOO 00..4455VV
SS_MAXDC
For SS_MAXDC (DC) (200kHz) = 1.84V for 72%
duty cycle
0.8V (ACTIVE THRESHOLD)
SS_MAXDC (DC) (fsync = 250kHz) for 72%
0.45V (RESET THRESHOLD)
0.2V
duty cycle
ꢀ =ꢀ1.84ꢀ•ꢀ[(200kHz/250kHz)ꢀ+ꢀ0.09(1)0.6]ꢀ
TIMING (B): SOFTT--SSTTAARRTTFFAAUULLTTRREEMMOOVVEEDD
AFTTEERR SSSS__MMAAXXDDCC FFAALLLLSS PPAASSTT00..4455VV
1952 F10
= 1.638V
Figure 10. Soft-Start Timing
Programming Soft-Start Timing
SS_MAXDC(DC)
The LT1952/LT1952-1 have built-in soft-start capability to
provide low stress controlled start-up from a list of fault
conditions that can occur in the application (see Figure 1
and Figure 10). The LT1952/LT1952-1 provide true PWM
soft-startbyusingtheSS_MAXDCpintocontrolsoft-start
timing.TheproportionalrelationshipbetweenSS_MAXDC
voltage and switch maximum duty cycle clamp allows
the SS_MAXDC pin to slowly ramp output voltage by
ramping the maximum switch duty cycle clamp—until
switchdutycycleclampseamlesslymeetsthenaturalduty
LT1952/
LT1952/
LT1952-1
LT1952-1
R
CHARGE
SS_MAXDC
SS_MAXDC
R
T
V
REF
C
SS
C
R
B
SS
1952 F11
SS_MAXDC CHARGING MODEL
SS_MAXDC(DC) = V [R /(R + R )]
REF
B
T
B
R
= [R • R /(R + R )]
T B T B
CHARGE
cycle of the converter. A capacitor C on the SS_MAXDC
SS
Figure 11. Programming Soft-Start Timing
pin and the resistor divider from V
used to program
REF
19521fe
17
LT1952/LT1952-1
APPLICATIONS INFORMATION
(A) V > 14.25* (7.75V LT1952-1), and
Example:
For an overcurrent fault (OC > 100mV), V = 2.5V,
IN
(B) SD_V
> 1.32V, and
SEC
REF
R = 35.7k, R = 100k, C = 0.1µF and assume
T
B
SS
(C) OC < 107mV, and
V
I
= 0.45V,
SS(MIN)
DIS
–4
(D) SS_MAXDC < 0.45V (SS_MAXDC reset threshold)
~ 8e ꢀ+ꢀ(2.5ꢀ–ꢀ0.45)[(1/2ꢀ•ꢀ100k)ꢀ–ꢀ(1/35.7k)]
–4
–4
–4
= 8e + (2.05)(–0.23e ) = 7.5e
*V >8.75V(6.5VLT1952-1)isokforlatchresetifthelatch
IN
was only set by overcurrent condition in (3) above.
SS_MAXDC(DC) = 1.84V
–4
SS_MAXDC (t
= 1.85e–4 s
) = (1e – 7/7.5e )ꢀ•ꢀ(1.84ꢀ–ꢀ0.45)
FALL
SS_MAXDC Discharge Timing
It can be seen in Figure 10 that two types of discharge
can occur for the SS_MAXDC pin. In timing (A) the fault
that caused the soft-start event has been removed before
SS_MAXDC falls to 0.45V. This means the soft-start
latch will be reset when SS_MAXDC falls to 0.45V and
SS_MAXDCwillbegincharging.Intiming(B),thefaultthat
caused the soft-start event is not removed until some time
after SS_MAXDC has fallen past 0.45V. The SS_MAXDC
pin continues to discharge to 0.2V and remains low until
all faults are removed.
IftheOCfaultisnotremovedbefore185µsthenSS_MAXDC
will continue to fall past 0.45V towards a new V
.
SS(MIN)
The typical V for SS_MAXDC at 150µA is 0.2V.
OL
SS_MAXDC Charge Timing
When all faults are removed and the SS_MAXDC pin
has fallen to its reset threshold of 0.45V or lower, the
SS_MAXDC pin will be released and allowed to charge.
SS_MAXDC will rise until it settles at its programmed DC
voltage—setting the maximum switch duty cycle clamp.
The calculation of charging time for the SS_MAXDC pin
between any two voltage levels can be approximated as
an RC charging waveform using the model shown in
Figure 11.
The time for SS_MAXDC to fall to a given voltage can be
approximated as:
SS_MAXDC (t
) =
FALL
(C /I )ꢀ•ꢀ[SS_MAXDC(DC)ꢀ–ꢀV
]
SS DIS
SS(MIN)
where:
TheabilitytopredictSS_MAXDCrisetimebetweenanytwo
voltages allows prediction of several key timing periods:
I
= net discharge current on C
DIS
SS
C
SS
= capacitor value at SS_MAXDC pin
(1)No Switching Period
(time from SS_MAXDC(DC) to V
+ time from
SS(MIN)
SS_MAXDC(DC) = programmed DC voltage
V
to V
)
SS(MIN)
SS(ACTIVE)
V
= minimum SS_MAXDC voltage before
SS(MIN)
recharge
(2)Converter Output Rise Time
(time from V to V
; V is the
SS(REG) SS(REG)
level of SS_MAXDC where maximum duty cycle
clamp equals the natural duty cycle of the switch)
SS(ACTIVE)
–4
I
~ 8e + (V – V
)[(1/2R ) – (1/R )]
SS(MIN) B T
DIS
REF
For faults arising from (1) and (2),
= 100mV.
V
REF
(3)Time For Maximum Duty Cycle Clamp within X% of
Target Value
For a fault arising from (3),
= 2.5V.
V
REF
The time for SS_MAXDC to charge to a given voltage V
is found by re-arranging:
SS
SS_MAXDC(DC) = V [R /(R + R )]
REF
B
T
B
V
= SS_MAXDC reset threshold = 0.45V
SS(MIN)
(if fault removed before t
)
FALL
19521fe
18
LT1952/LT1952-1
APPLICATIONS INFORMATION
(–t/RC)
V (t) = SS_MAXDC(DC) (1 – e
)
Step 3:
t(V = 0.8V) is calculated from:
SS
to give:
SS
ꢀ tꢀ=ꢀRCꢀ•ꢀ(–1)ꢀ•ꢀln(1ꢀ–ꢀV /SS_MAXDC(DC))
t = R
ꢀ•ꢀCSSꢀ•ꢀ(–1)ꢀ•ꢀln(1ꢀ–ꢀV /SS_MAXDC(DC))
SS
CHARGE
SS
–7
ꢀ =ꢀ2.63e4ꢀ•ꢀ1e ꢀ•ꢀ(–1)ꢀ•ꢀln(1ꢀ–ꢀ0.8/1.84)
where:
–3
ꢀ =ꢀ2.63e–3ꢀ•ꢀ(–1)ꢀ•ꢀln(0.565)ꢀ=ꢀ1.5e
s
V
SS
= SS_MAXDC voltage at time t
From Step 1 and Step 2:
SS_MAXDC(DC) = programmed DC voltage setting
maximum duty cycle clamp =
–3
–4
t
= (1.5 – 0.73)e s = 7.7e
s
CHARGE
V
REF
(R /(R + R )
The total time of no switching for the converter due to a
soft-start event:
B
T
B
R = R
(Figure 11) = R ꢀ•ꢀR /(R + R )
T B T B
CHARGE
–4
–4
–4
= t
+ t
= 1.85e + 7.7e = 9.55e
s
DISCHARGE
CHARGE
C = C (Figure 11)
SS
Example (2) Converter Output Rise Time
Example (1) No Switching Period
The rise time for the converter output to reach regulation
can be closely approximated as the time between the start
Theperiodofnoswitchingfortheconverter,whenasoft-start
event has occurred, depends on how far SS_MAXDC can
fall before recharging occurs and how long a fault exists. It
will be assumed that a fault triggering soft-start is removed
before SS_MAXDC can reach its reset threshold (0.45V).
ofswitching(SS_MAXDC=V
)andthetimewhere
SS(ACTIVE)
converter duty cycle is in regulation (DC(REG)) and no
longercontrolledbySS_MAXDC(SS_MAXDC=V
Converter output rise time can be expressed as:
).
SS(REG)
No Switching Period = t
+ t
CHARGE
DISCHARGE
Output Rise Time = t(V
) – t(V
)
SS(REG)
SS(ACTIVE)
t
= discharge time from SS_MAXDC(DC) to
DISCHARGE
0.45V
Step 1: Determine converter duty cycle DC(REG) for
output in regulation.
t
= charge time from 0.45V to V
SS(ACTIVE)
CHARGE
ThenaturaldutycycleDC(REG)oftheconverterdependson
severalfactors.ForthisexampleitisassumedthatDC(REG)
= 60% for system input voltage near the undervoltage
t
t
was already calculated earlier as 185µs.
DISCHARGE
is calculated by assuming the following:
CHARGE
lockout threshold (UVLO). This gives SD_V
= 1.32V.
SEC
V
V
= 2.5V, R = 35.7k, R = 100k, C = 0.1µF and
SS(MIN)
REF
T
B
SS
Also assume that the maximum duty cycle clamp
programmedforthisconditionis72%forSS_MAXDC(DC)
= 0.45V.
t
= t(V = 0.8V) – t(V = 0.45V)
SS SS
CHARGE
= 1.84V, f
= 200kHz and R
= 40k.
OSC
DELAY
Step 1:
SS_MAXDC(DC) = 2.5[100k/(35.7k + 100k)] = 1.84V
ꢀ=ꢀ(35.7kꢀ•ꢀ100k/135.7k)ꢀ=ꢀ26.3k
Step 2: Calculate V
SS(REG)
TocalculatethelevelofSS_MAXDC(V
)thatnolonger
SS(REG)
R
CHARGE
clamps the natural duty cycle of the converter, the equation
formaximumdutycycleclampmustbeused(seeprevious
section ‘Programming Maximum Duty Cycle Clamp’).
Step 2:
t(V = 0.45V) is calculated from,
SS
The point where the maximum duty cycle clamp meets
DC(REG) during soft-start is given by:
t = R
ꢀ•ꢀC ꢀ•ꢀ(–1)ꢀ•ꢀln(1ꢀ–ꢀV /SS_MAXDC(DC))
SS
CHARGE
SS
–7
4
= 2.63e ꢀ•ꢀ1e ꢀ•ꢀ(–1)ꢀ•ꢀln(1ꢀ–ꢀ0.45/1.84)ꢀ
–3
–4
DC(REG) = Max Duty Cycle clamp
= 2.63e ꢀ•ꢀ(–1)ꢀ•ꢀln(0.755)ꢀ=ꢀ7.3e
s
ꢀ 0.6ꢀ=ꢀkꢀ•ꢀ0.522(SS_MAXDC(DC)/SD_V ) –
SEC
(t
ꢀ•ꢀf
)
DELAY OSC
19521fe
19
LT1952/LT1952-1
APPLICATIONS INFORMATION
–4
–7
For SD_V = 1.32V, fOSC = 200kHz and R
= 40k
t(1.803) = 2.63e ꢀ•ꢀ1e ꢀ•ꢀ(–1)ꢀ•ꢀln(1ꢀ–ꢀ1.803/1.84)
SEC
DELAY
–3
–2
= 2.63e ꢀ•ꢀ(–1)ꢀ•ꢀln(0.02)ꢀ=ꢀ1.03e
s
This gives k = 1 and t
= 40ns.
DELAY
HencethetimeforSS_MAXDCtochargefromitsminimum
reset threshold of 0.45V to within 2% of its target value
is given by:
Re-arranging the above equation to solve for SS_MAXDC
= V
SS(REG)
= [0.6 + (t
ꢀ•ꢀf )(SD_V )]/(kꢀ•ꢀ0.522)
SEC
DELAY OSC
t(1.803) – t(0.45) =
ꢀ =ꢀ[0.6ꢀ+ꢀ(40nsꢀ•ꢀ200kHz)(1.32V)]/(1ꢀ•ꢀ0.522)
–2
–4
–3
1.03e – 7.3e = 9.57e
= (0.608)(1.32)/0.522 = 1.537V
Step 3: Calculate t(V
) – t(V
)
Forward Converter Applications
SS(REG)
SS(ACTIVE)
RecallthetimeforSS_MAXDCtochargetoagivenvoltage
is given by:
The following section covers applications where the
LT1952/LT1952-1 are used in conjunction with other LTC
parts to provide highly efficient power converters using
the single switch forward converter topology.
V
SS
t = R ꢀ•ꢀC ꢀ•ꢀ(–1)ꢀ•ꢀln(1ꢀ–ꢀV /SS_MAXDC(DC))
CHARGE SS SS
(Figure 11 gives the model for SS_MAXDC charging)
For R = 35.7k, R = 100k, R = 26.3k
95% Efficient, 5V, Synchronous Forward Converter
T
B
CHARGE
ThecircuitinFigure14isbasedontheLT1952-1toprovide
the simplest forward power converter circuit—using only
one primary MOSFET. The SOUT pin of the LT1952-1
provides a synchronous control signal for the LTC1698
located on the secondary. The LTC1698 drives secondary
side synchronous rectifier MOSFETs to achieve high
efficiency. The LTC1698 also serves as an error amplifier
and optocoupler driver.
For C = 0.1µF, this gives t(V
)
SS
SS(ACTIVE)
4
–7
= t(V
) = 2.63e ꢀ•ꢀ1e ꢀ•ꢀ(–1)ꢀ•ꢀln(1ꢀ–ꢀ0.8/1.84)ꢀ
SS(0.8V)
–3
–3
= 2.63e ꢀ•ꢀ(–1)ꢀ•ꢀln(0.565)ꢀ=ꢀ1.5e
s
t(V
) = t(V
)ꢀ=ꢀ26.3kꢀ•ꢀ0.1µFꢀ•ꢀ–1ꢀ•ꢀ
SS(REG)
SS(1.537V)
–3
ln(1 – 1.66/1.84) = 2.63e ꢀ•ꢀ(–1)ꢀ•ꢀln(0.146)ꢀ
–3
= 5e
s
The rise time for the converter output
Efficiency and transient response are shown in Figures 12
and 13. Peak efficiencies of 95% and ultra-fast transient
response are superior to presently available power
modules. Integrated soft-start, overcurrent detection and
short-circuit hiccup mode provide low stress, reliable
protection. In addition, the circuit in Figure 14 is an all-
ceramic capacitor solution providing low output ripple
voltage and improved reliability. The LT1952-based
convertercanbeusedtoreplacepowermoduleconverters
at a much lower cost. The LT1952 solution benefits from
thermalconductionofthesystemboardresultinginhigher
efficienciesandlowerriseincomponenttemperatures.The
7mm height allows dense packaging and the circuit can
easily be adjusted to provide an output voltage from 1.23V
to 26V. Higher currents are achievable by simple scaling
of power components. The LT1952-1-based solution in
Figure 14 is a powerful topology for replacement of a wide
range of power modules.
–3
= t(V
= 3.5e
) – t(V
) = (5 – 1.5)e
s
SS(REG)
–3
SS(ACTIVE)
s
Example (3) Time For Maximum Duty Cycle Clamp to
Reach Within X% of Target Value
A maximum duty cycle clamp of 72% was calculated
previously in the section ‘Programming Maximum
Duty Cycle Clamp’. The programmed value used for
SS_MAXDC(DC) was 1.84V.
ThetimeforSS_MAXDCtochargefromitsminimumvalue
V
to within X% of SS_MAXDC(DC) is given by:
SS(MIN)
t(SS_MAXDC charge time within X% of target)
ꢀ =ꢀt[(1ꢀ–ꢀ(X/100)ꢀ•ꢀSS_MAXDC(DC)]ꢀ–ꢀt(V
)
SS(MIN)
For X = 2 and V
t(0.45) = t(1.803) – t(0.45)
ꢀ=ꢀ0.45V,ꢀt(0.98ꢀ•ꢀ1.84)ꢀ–ꢀ
SS(MIN)
From previous calculations, t(0.45) = 7.3e – 4 s.
Using previous values for R , R , and C ,
T
B
SS
19521fe
20
LT1952/LT1952-1
APPLICATIONS INFORMATION
98
96
94
92
90
I
OUT
(5A/DIV)
0A
V
OUT
(200mV/DIV)
88
86
V
V
= 48V
IN
= 5V
OUT
OSC
f
= 300kHz
1952 F13
20µs/DIV
0
5
10
15
20
25
LOAD CURRENT (A)
Figure 13. Output Voltage Transient Response
(6A to 12A Load Step at 6A/µs)
1952 F12
Figure 12. LT1952-Based Synchronous Forward Converter
Efficiency vs Load Current (For Circuit in Figure 14)
+V
IN
36V TO 72V
C
IN
2.2µF
100V
X5R
L1
T1
PA0491
PA1393.152
+V
5V
0UT
20A
475k
C
7
01
16
5
SOUT
22k
SOUT
SD_V
SEC
100µF
Q2
Q3
14
11
10
13
8
X5R
2×
Q1
PH3830
PH3830
SS_MAXDC
OUT
OC
100k
6
2
V
I
SENSE
REF
1k
LT1952-1
0.015Ω
FB
PGND
GND
18.2k
0.1µF
0.1µF
7V
BIAS
15
3
4
LTC1698
10V
BIAS
1
2
3
4
5
6
16
15
14
13
12
11
R
V
IN
OSC
V
FG
DD
115k
1µF
X5R
SYNC
CG
SYNC
9.53k
SYNC
BLANK DELAY
12
33k
1
PGND
GND
OPTO
V
COMP
AUX
0.1µF
T2
R13
270Ω
I
COMP
SYNC
560Ω
SOUT
9
+I
–I
SNS
SNS
1µF
40k
4.75k
220pF
C9, 6.8nF
V
COMP
R14
1.2k
HCPL-M453
10V
8
9
BIAS
V
OVP
FB
6
1
+V
0UT
Q1: PHM15NQ20 PHILIPS
2
3
5
4
R15
38.3k
R16
12.4k
0.1µF
1952 F14
Figure 14. 36V to 72V Input to 5V at 20A Synchronous Forward Converter
19521fe
21
LT1952/LT1952-1
APPLICATIONS INFORMATION
48V to Isolated 12V, 20A (No Opto-Coupler)
‘Bus Converter’
achieves a high 94% at 20A (Figure 15). The solution is
only slightly larger than 1/4 “brick” size and uses only
ceramic capacitors for high reliability.
The wide programmable range and accuracy of the
LT1952/LT1952-1 Volt-Second clamp makes the LT1952/
LT1952-1 an ideal choice for ‘Bus Converter’ applications
where the Volt-Second clamp provides line regulation for
the converter output. The 48V to 12V 20A ‘Bus Converter’
application in Figure16 shows a semi-regulated isolated
output without the need for an optocoupler, optocoupler
driver,referenceorfeedbacknetwork.Some‘BusConverter’
solutions run with a fixed 50% duty cycle resulting in an
output variation of 2-to-1 for applications with a 72V to
36V input range. The LT1952/LT1952-1 use an accurate
wide programmable range Volt-Second clamp to initially
program and then control power supply output voltage
to typically ±10% for the same 36V to 72V input range.
Efficiency for the LT1952 based bus converter in Figure 16
96.0
95.5
95.0
94.5
94.0
93.5
V
V
= 48V
IN
OUT
= 12V
93.0
4
6
8
10 12 14 16 18 20
LOAD CURRENT (A)
1952 F15
Figure 15. LT1952-Based Synchronous ‘Bus Converter’
Efficiency vs Load Current (For Circuit in Figure 16)
T1
V
U1
PA0815.002
2.4µH
10k
47k
82k
• •
V
V
OUT
IN
36V TO 72V
12V, 20A
BAS516
0.1µF
BCX55
12V
C
OUT
33µF, 16V
X5R, TDK
3x
Si7370
2x
PH4840
2x
18V
2.2µF, 100V
2x
LTC3900
•
5
6
3
1
FG
CG
+
PH21NQ15
2x
370k
7
10k
10k
GND
CS
13.2k
27k
14
15
8
V
1µF
U1
SD_V
OUT
SEC
4
8
2
7
–
115k
V
CS
3
9
5
CC
R
OSC
V
IN
BAT760
SYNC TIMER
8V
BIAS
BLANK
GND
1µF
C
T
13
12
11
10
16
R
T
0.47µF
0.1µF
SS_MAXDC
PGND
1nF
15k
59k
10k
39k
9mΩ
LT1952 DELAY
OC
1nF
8V
BIAS
6
1
2
V
REF
470Ω
560W
220pF
COMP
FB
I
SENSE
SOUT
L1: PA1494.242 PULSE ENGINEERING
T1: PULSE ENGINEERING
T2: COILCRAFT
• •
T2
Q4470-B
1952 F16
Figure 16. 36V to 72V Input to 12V at 20A No ‘Optocoupler’ Synchronous ‘Bus Converter’
19521fe
22
LT1952/LT1952-1
APPLICATIONS INFORMATION
36V to 72V Input, 3.3V 40A Converter
This allows a significant reduction in power component
sizing using the LT1952-based converter.
AnLT1952-basedsynchronousforwardconverterprovides
theidealsolutionforpowersuppliesrequiringhighefficiency
atlowoutputvoltagesandhighloadcurrents.The3.3V40A
solution in Figure 18 achieves peak efficiencies of 92.5%
(Figure 17) by minimizing power loss due to rectification
at the output. Synchronous rectifier control output SOUT,
with programmable delay, optimizes timing control for a
secondarysidesynchronousMOSFETcontroller(LTC3900)
which results in high efficiency synchronous rectification.
TheLT1952/LT1952-1useaprecisioncurrentlimitthreshold
at the OC pin combined with a soft-start hiccup mode to
provide low stress output short-circuit protection. The
94
93
92
91
90
89
88
V
V
= 48V
IN
87
86
= 3.3V
OUT
OSC
f
= 300kHz
0
10
20
30
40
50
OUTPUT CURRENT (A)
maximumoutputcurrentwillvaryonly10%overthefullV
IN
1952 F17
range. During short-circuit the average power dissipation
of the circuit will be lower than 15% of maximum rated
power thanks to a soft-start controlled hiccup mode.
Figure 17. LT1952-Based Synchronous Forward Converter
Efficiency vs Load Current (For Circuit in Figure 18)
V
U1
PA0912.002
L1
47k
82k
• •
+V
IN
36V TO 72V
V
OUT
3.3V, 40A
BAS516
0.1µF
BCX55
12V
C
OUT
Q2
PH3230
2x
Q3
PH3230
2x
100µF
3x
18V
10k
2.2mF
LTC3900
•
5
6
3
1
FG
CG
+
370k
7
10k
10k
GND
CS
13.2k
27k
14
15
8
V
1mF
U1
Si7846
SD_V
SEC
OUT
4
8
2
7
–
115k
V
CS
3
9
5
CC
R
OSC
V
IN
BAT760
SYNC TIMER
8V
BIAS
BLANK LT1952
SS_MAXDC
GND
PGND
DELAY
OC
1µF
1nF
13
12
11
10
16
15k
0.22µF
0.1µF
59k
10k
33k
39k
10mΩ
1nF
8V
BIAS
6
1
2
V
= 2.5V
R
470Ω
560Ω
220pF
COMP
I
SENSE
SOUT
249k
80.6k
• •
FB = 1.23V
T2
Q4470-B
2.2nF
8V
BIAS
22k
18k
2.2k
V
U1
– 4
5
2
10k
1
L1: PA0713, PULSE ENGINEERING
10k
1µF
3
+
ALL CAPACITORS X7R, CERAMIC, TDK
T2: COILCRAFT
LT1797
270Ω
PS2801
0.1µF
8
4
LT1009
1952 F18
Figure 18. 36V to 72V, 3.3V at 40A Synchronous Forward Converter
19521fe
23
LT1952/LT1952-1
APPLICATIONS INFORMATION
Bus Converter: Optimum Output Voltage Tolerance
(b)Select switch duty cycle for the Bus Converter for a
givenoutputvoltageatV andcalculateSS_MAXDC
S(MIN)
The Bus Converter applications shown on page 1 and in
Figure 16, provide semi-regulated isolated outputs without
theneedforanoptocoupler,optocouplerdriver,referenceor
feedbacknetwork.TheLT1952/LT1952-1Volt-Secondclamp
adjusts switch duty cycle inversely proportional to input
voltagetoprovideanoutputvoltagethatisregulatedagainst
input line variations. Some bus converters use a switch duty
cycle limit which causes output voltage variation of typically
±33% over a 2:1 input voltage range. The LT1952/LT1952-1
typically provide a ±10% output variation for the same input
variation.Typicaloutputtoleranceisfurtherimprovedforthe
LT1952 by inserting a resistor from the system input voltage
to the SS_MAXDC pin (Rx in Figure 19).
voltage(SS1)(SeeApplicationsInformation“Program-
ming Maximum Duty Cycle Clamp”)
(c)Calculate R ꢀ=ꢀ[SS1/(2.5ꢀ–ꢀSS1)]ꢀ•ꢀR
B(1)
T(1)
(2)Calculate Rx:
Rx = ([V
– V
]/[SS1ꢀ•ꢀ(Xꢀ–ꢀ1)])ꢀ•ꢀR
S(MIN) THEV(1)
S(MAX)
R
= R ꢀ•ꢀR /(R
S(MAX)
+ R ), X = ideal duty
THEV(1)
cycle (V
B(1)
T(1)
B(1) T(1)
)/actual duty cycle (V
)
S(MAX)
(3)The addition of Rx causes an increase in the original
programmed SS_MAXDC voltage SS1. A new value for
R
shouldbecalculatedtoprovidealowerSS_MAXDC
B(1)
voltage (SS2) to correct for this offset:
TheLT1952/LT1952-1electricalspecificationsfortheOUT
Max Duty Cycle Clamp show typical switch duty cycle to
move from 72% to 33% for a 2x change of input voltage
(SS_MAXDC pin=1.84V).Sinceoutputvoltageregulation
(a)SS2 = SS1 – [(V ꢀ–ꢀSS1)ꢀ•ꢀR
/Rx]
THEV(1)
S(MIN)
(b)R ꢀ=ꢀ[SS2/(2.5ꢀ–ꢀSS2)]ꢀ•ꢀR
B(2)
T(1)
(4)The thevinin resistance R
used to calculate Rx
THEV(1)
follows V ꢀ•ꢀDutyꢀCycle,ꢀaꢀswitchꢀdutyꢀcycleꢀchangeꢀofꢀ
IN
should be re-established for R and R :
T
B
72% to 36% (for a 2x input voltage change) provides
minimal output voltage variation for the LT1952/LT1952-1
bus converter. To achieve this, an SS_MAXDC pin voltage
increase of 1.09x (36/33) would be required at high input
line. A resistor Rx inserted between the SS_MAXDC pin
andsysteminputvoltage(Figure19)increasesSS_MAXDC
voltage as input voltage increases, minimizing output
voltage variation over a 2:1 input voltage change.
(a) R (final value) = R ꢀ•ꢀ(R
/R
)
B
B(2)
THEV(1) THEV(2)
(b) R (final value) = R ꢀ•ꢀ(R
/R
)
T
T(1)
THEV(1) THEV(2)
where R
= R ꢀ•ꢀR /(R
+ R
)
THEV(2)
B(2)
T(1)
B(2)
T(1)
Example:
For a Bus Converter running from 36V to 72V input,
= 36V, V = 72V.
V
S(MIN)
S(MAX)
choose R
= 10k, SS_MAXDC = SS1 = 1.84V (for 72%
S(MIN
The following steps determine values for Rx, R and R :
T(1)
T
B
duty cycle at V
) = 36V)
(1)Program switch duty cycle at minimum system input
voltage (V
R
R
ꢀ=ꢀ[1.84V/(2.5Vꢀ–ꢀ1.84V)]ꢀ•ꢀ10kꢀ=ꢀ28k
ꢀ=ꢀ[28kꢀ•ꢀ10k/(28kꢀ+ꢀ10k)]ꢀ=ꢀ7.4k
)
B(1)
S(MIN)
(a)R
= 10k (minimum allowed to still guarantee soft-
THEV(1)
T(1)
start pull-down)
SS_MAXDC correction = 36%/33% = 1.09
ꢀ Rxꢀ=ꢀ[(72Vꢀ–ꢀ36V)/(1.84ꢀ•ꢀ0.09)]ꢀ•ꢀ7.4kꢀ=ꢀ1.6M
ꢀ SS2ꢀ=ꢀ1.84ꢀ–ꢀ[(36Vꢀ–ꢀ1.84)ꢀ•ꢀ7.4k/1.6M]ꢀ=ꢀ1.682V
SYSTEM
INPUT VOLTAGE
LT1952/
R1
R2
Rx
LT1952-1
VOLT-SECOND
CLAMP INPUT
SD_V
SEC
R
R
R
ꢀ=ꢀ[1.682/(2.5ꢀ–ꢀ1.682)]ꢀ•ꢀ10kꢀ=ꢀ20.6k
B(2)
SS_MAXDC
R
T
ꢀ=ꢀ[20.6kꢀ•ꢀ10k/(20.6kꢀ+ꢀ10k)]ꢀ=ꢀ6.7k
V
THEV(2)
REF
VOLT-SECOND
CLAMP ADJUST INPUT
1952 F19
R
B
/R
= 7.4k/6.7k = 1.104
THEV(1) THEV(2)
R ꢀ(finalꢀvalue)ꢀ=ꢀ20.6kꢀ•ꢀ1.104ꢀ=ꢀ22.7kꢀ(chooseꢀ22.6k)
B
Figure 19. Optimal Programming of Maximum Duty
Cycle Clamp for Bus Converter Applications (Adding Rx)
R ꢀ(finalꢀvalue)ꢀ=ꢀ10kꢀ•ꢀ1.104ꢀ=ꢀ11k
T
19521fe
24
LT1952/LT1952-1
TYPICAL APPLICATIONS
Wide 18V to 72V Input, High Efficiency, 12V at 12A Output, Active Reset Forward Converter Fits in One-Eighth Brick Footprint
+V
+V
V
UL
Q10
PBSS8110
D2
IN
B
L2
L1
+V
R1
OL
BAS516
1.5mH
HR-PQA2050-10
2.2Ω
1
6
7, 8
•
•
•
+V
OUT
+V
IN
D5
C
33µF
X7R
D3
OL
R11
47k
C
IN
PDZ10B
BAS516
+
C
9, 10, 11
FG
SYS
18V TO 72V
2.2µF
220µF 16V
APXE
×3
Q2
HAT2266
Q3
+V
R2
CG
–V
IN
HAT2173
2, 3
+V
IN
T1
R8
R5
G45R2-0405.005
2.2Ω
10Ω
4, 5
V
UL
L3
680µH
D7
1
6
5
4
C25
10nF
Q1
HAT2173
BAS521
R54
4.7Ω
V
BOOST
LTC4440-5
R16
33k
CC
C3
1µF
2
3
D6
BAS521
R18
10k
GND
TG
TS
PE-68386
LTC3900
1
2
3
4
8
C21
220pF
C34
0.22µF
+
•
CS
SYNC
7
6
5
INP
R17
–
CS TIMER
C5
0.22µF
R
CSL
560Ω
Q13
Si2325
R21
10k
0.006Ω
C33
0.1µF
Q9
BCX55
CG
CG
GND
FB
R3 442Ω
•
L53
10µH
C12
470pF
OUT
FB
V
CC
R45 10k
D1 BAS516
C14
1µF
R10
1k
220pF
10µH
D17 BAS516
R13
22k
R14
33k
R19 47.5k
D11
BAS516
OUT
1
2
3
4
5
6
7
8
16
D14
BAS516
V
FB
COMP
FB
SOUT
D9
V
V
UL
UL
PDZ10B
15
14
13
12
11
10
9
V
Q12
BC856T
IN
R26
220Ω
R27
470Ω
C8
R31
10Ω
R15 115k
PS2801-1
LT4430
100pF
1
6
5
4
R
OSC
OUT
+V
OL
V
OPTO
GND COMP
SS FB
CC
C10
C
UL
C16
0.22µF
10V
C17
15nF
LT1952-1
SYNC PGND
2
3
R34
12.1k
100pF
4.7µF
V
C9
100pF
C13 0.47µF
C10 0.1µF
FB
R20 115k
R35
348k
SS_MAXDC DELAY
C23
1µF
R30
1.2k
R38
18.2k
C19
1µF X5R
V
REF
OC
R23 2k
R24 68k
C15
2.2nF 2kV
1952 TA02a
C24
SD_V
GND
I
SENSE
SEC
R22
13.3k
22pF
BLANK
D29
PMEG3002
R28
R32
309k 187k
R2 560k
+V
+V
R2
B
The 12V Output Converter Fits in a One-Eighth “Brick” Footprint and Has a
Very High Efficiency Over 18V to 72V Input Voltage Range
96
95
94
93
92
91
90
89
88
87
86
85
84
24V INPUT
48V INPUT
0
4
6
8
10
12
2
I
(A)
OUT
1952 TA02b
19521fe
25
LT1952/LT1952-1
TYPICAL APPLICATIONS
High Efficiency 36V to 72V Input to 3.3V at 30A Output, Active Reset Forward Converter Fits in One-Eighth Brick Footprint
+V
+V
V
UL
Q10
PBSS8110
D2
IN
B
L2
L1
R1
BAS516
1.5mH
PA1671.650
2.2Ω
1
6
7, 8
•
•
+V
+V
OUT
IN
IN
C
D3
OL
R49
R11
82k
C
IN
100µF
BAS516
2.2Ω
9, 10, 11
2.2µF
×2
V
+
C
R2
SYS
470µF
6.3V
×2
D5
PDZ10B
Q2
HAT2165
Q3
HAT2165
–V
C34
0.22µF
2, 3
R54
4.7Ω
•
R50
2.2Ω
+V
IN
C33
0.1µF
4, 5
R8
2.2Ω
R53
200Ω
T1
PA0861.004
Q13
Si2325
Q1
Si7430
C25
10nF
D17
BAS516
CS
R
CS1
D11
BAS516
R45 10k
0.015Ω
D14 BAS516
V
R27
FB
D6
R13
22k
R14
33k
470Ω
PS2801-1
LT4430
OPTO
B0540W
1
6
5
4
1
16
15
14
V
CC
V
FB
COMP
SOUT
C16
22µF
V
C17
10nF
UL
R26
2
3
R34
220Ω
GND COMP
SS FB
2
4.75k
FB
V
Q12
BC856T
IN
R15 115k
3
R35
82.5k
C23
1µF
R30
1.2k
D10
R
OSC
OUT
R38
18.2k
C19
1µF
BAT760
C
UL
LT1952-1
SYNC
4
5
6
7
8
13
12
11
10
9
4.7µF
PGND
C9
100pF
C15
2.2nF 2kV
1952 TA03a
R20 174k
C24
47pF
SS
SS_MAXDC DELAY
C10 0.1µF
R22 13.3k
V
OC
REF
R23 1.2k
R24 39k
CS
SD_V
GND
I
SENSE
SEC
BLANK
R29 22k
R32
R28
SS
C13
0.47µF
332k 442k
R33
470k
+V +V
R2
B
The High Efficiency of 3.3V Output Converter Allows Tight PCB Layout and
Results in Low Component Temperature Rises
94
93
92
91
90
89
88
0
10
20
(A)
30
I
OUT
1952 TA03b
19521fe
26
LT1952/LT1952-1
(Revision history begins at Rev E)
REV
DATE
DESCRIPTION
MP-grade parts added, changes reflected throughout the data sheet
PAGE NUMBER
E
5/11
1-28
19521fe
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LT1952/LT1952-1
PACKAGE DESCRIPTION
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 ±.0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 ± .004
(0.38 ± 0.10)
× 45°
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
GN16 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC®3900
Synchronous Rectifier N-Channel MOSFET Driver
for Forward Converters
Programmable Timeout and Reverse Inductor Current Protection,
Transformer Synchronization, SSOP-16
LT4430
Secondary-Side Opto-Coupler Driver with Reference Overshoot Control Prevents Output Overshoot During Start-up and Short-
Voltage
Circuit Recovery
LTC3726/LTC3725
LTC3705/LTC3726
LTC3722/LTC2722-2
Isolated Synchronous No Opto Forward Controller
Chip Set
Ideal for Medium Power 24V or 48V Input Applications
2-Switch Synchronous Forward No Opto Isolated
Controller Chip Set
Self-Starting Architecture Eliminates Need for a Bias Voltage on
Primary Side
Synchronous Isolated Full-Bridge Controllers with
Zero Voltage Switching
Ideal for High Power 24V or 48V Input Applications
LTC3723-1/LTC3723-2 Synchronous Push-Pull and Full-Bridge Controllers High Efficiency with On-Chip MOSFET Drivers
LTC3721-1/LTC3721-2 Non-Synchronous Push-Pull and Full-Bridge
Controllers
Minimizes External Components, On-Chip MOSFET Drivers
LT3748
100V No Opto Flyback Controller
5V ≤ V ≤ 100V, Boundary Mode Operation, MSOP-16 with Extra High
IN
Voltage Pin Spacing
LTC3803/LTC3803-3/ Flyback DC/DC Controllers with Fixed 200kHz or
V
and V
Limited Only by External Components, 6-Pin ThinSOT™
IN
OUT
LTC3803-5
300kHz Operating Frequency
Package
19521fe
LT 0511 REV E • PRINTED IN USA
28 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2004
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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