LT1956-5EGN [Linear]
IC 3 A SWITCHING REGULATOR, 570 kHz SWITCHING FREQ-MAX, PDSO16, 0.150 INCH, PLASTIC, SSOP-16, Switching Regulator or Controller;
| 型号： | LT1956-5EGN |
| 厂家： | 
Linear |
| 描述： | IC 3 A SWITCHING REGULATOR, 570 kHz SWITCHING FREQ-MAX, PDSO16, 0.150 INCH, PLASTIC, SSOP-16, Switching Regulator or Controller 开关 光电二极管 |
| 文件： | 总24页 (文件大小：433K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Final Electrical Specifications
LT1956/LT1956-5
High Voltage, 1.5A,
500kHz Step-Down
Switching Regulators
June 2001
U
FEATURES
DESCRIPTIO
■
Wide Input Range: 5.5V to 60V
The LT®1956/LT1956-5 are 500kHz monolithic buck
switching regulators with an input voltage capability up to
60V. Ahighefficiency1.5A, 0.2Ωswitchisincludedonthe
diealongwithallthenecessaryoscillator,controlandlogic
circuitry. The topology is current mode for fast transient
response and good loop stability.
■
1.5A Peak Switch Current
■
Small 16-Pin SSOP Package
Saturating Switch Design: 0.2Ω
■
■
Peak Switch Current Maintained Over
Full Duty Cycle Range
■
Constant 500kHz Switching Frequency
Special design techniques and a new high voltage process
achieve high efficiency over a wide input range. Efficiency
ismaintainedoverawideoutputcurrentrangebyusingthe
output to bias the circuitry and by utilizing a supply boost
capacitor to saturate the power switch. Patented circuitry
maintainspeakswitchcurrentoverthefulldutycyclerange.
Ashutdownpinreducessupplycurrentto25µAandaSYNC
pin allows the device to be externally synchronized from
570kHz to 700kHz with a logic level input.
■
Effective Supply Current: 2.5mA
■
Shutdown Current: 25µA
■
1.2V Feedback Reference (LT1956)
■
5V Fixed Output (LT1956-5)
Easily Synchronizable
■
■
Cycle-by-Cycle Current Limiting
U
APPLICATIO S
■
TheLT1956/LT1956-5areavailableinafused-lead16-pin
SSOP package.
High Voltage, Industrial and Automotive
■
Portable Computers
■
Battery-Powered Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
Battery Chargers
■
Distributed Power Systems
U
TYPICAL APPLICATIO
5V Buck Converter
Efficiency vs Load Current
D2
D1N914
100
90
80
70
60
50
V
= 12V
IN
6
L = 18µH
C2
V
= 5V
OUT
L1*
0.1µF
V
BOOST
IN
5µH
V
5V
1A
OUT
4
2
12V
(TRANSIENTS
TO 60V)
V
LT1956 SW
IN
V
= 3.3V
OUT
C3
2.2µF
50V
15
10
SHDN
BIAS
R1
15.4k
C1
CERAMIC 14
12
+
SYNC
GND
FB
100µF 10V
SOLID
D1
R2
4.99k
V
C
10MQ060N
TANTALUM
1, 8, 9, 16 11
C
C
1nF
0
0.25
0.50
0.75
1.00
1.25
*INCREASE L1 TO 10µH FOR LOAD CURRENTS
ABOVE 0.6A AND TO 18µH ABOVE 1A
1956 TA01
LOAD CURRENT (A)
1956 TA02
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
1
LT1956/LT1956-5
W W
U W
U W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
Input Voltage (VIN) ................................................. 60V
BOOST Pin Above SW ............................................ 35V
BOOST Pin Voltage ................................................. 68V
SYNC, SENSE Voltage (LT1956-5) ........................... 7V
SHDN Voltage ........................................................... 6V
BIAS Pin Voltage .................................................... 48V
FB Pin Voltage/Current (LT1956)................... 3.5V/2mA
Operating Junction Temperature Range
ORDER PART
GND
SW
NC
1
16 GND
NUMBER
2
3
4
5
6
7
8
15
14
13
12
11
10
9
SHDN
SYNC
NC
LT1956EGN
LT1956IGN
LT1956-5EGN
LT1956-5IGN
V
IN
NC
BOOST
NC
FB/SENSE
V
C
BIAS
GND
GN PART MARKING
GND
LT1956EGN/LT1956-5EGN (Note 8).. –40°C to 125°C
LT1956IGN/LT1956-5IGN (Note 8) ... –40°C to 125°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
GN PACKAGE
16-LEAD PLASTIC SSOP
1956
1956I
19565
19565I
TJMAX = 125°C, θJA = 95°C/ W
Consult LTC Marketing for parts specified with wider operating temperature
ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25°C.
V
IN = 15V, VC = 1.5V, SHDN = 1V, Boost o/c, SW o/c, unless otherwise noted.
PARAMETER
CONDITIONS
5.5V ≤ V ≤ 60V
MIN
TYP
MAX
UNITS
Reference Voltage
1.204 1.219 1.234
1.189
V
V
IN
V
+ 0.2 ≤ V ≤ V – 0.2
●
●
1.249
OL
C
OH
SENSE Voltage (LT1956-5)
5.5V ≤ V ≤ 60V
4.94
4.90
5
5.06
5.10
V
V
IN
V
+ 0.2 ≤ V ≤ V – 0.2
OL
C OH
SENSE Pin Resistance
FB Input Bias Current
Error Amp Voltage Gain
9.5
13.8
0.5
19
kΩ
µA
●
●
1.5
(Notes 2, 9)
dl (V ) = ±10µA (Note 9)
200
400
V/V
Error Amp g
1500
1100
2000
3000
3200
µMho
µMho
m
C
V to Switch g
1.7
225
225
0.9
2.1
2
A/V
µA
µA
V
C
m
EA Source Current
EA Sink Current
FB = 1V or V
= 4.1V
●
●
125
100
400
450
SENSE
FB = 1.4V or V
Duty Cycle = 0
SHDN = 1V
= 5.7V
SENSE
V Switching Threshold
C
V High Clamp
C
V
Switch Current Limit
Switch On Resistance
V Open, Boost = V + 5V, FB = 1V or V
C
= 4.1V
●
●
●
1.5
3
A
IN
SENSE
I
= 1.5A, Boost = V + 5V (Note 7)
0.2
0.3
0.4
Ω
Ω
SW
IN
Maximum Switch Duty Cycle
Switch Frequency
FB = 1V or V
= 4.1V
82
75
90
90
%
%
SENSE
V Set to Give DC = 50%
C
460
430
500
540
570
kHz
kHz
●
●
f
f
Line Regulation
5.5V ≤ V ≤ 60V
0.05
0.8
0.15
%/V
V
SW
SW
IN
Shifting Threshold
Df = 10kHz
2
LT1956/LT1956-5
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25°C.
VIN = 15V, VC = 1.5V, SHDN = 1V, Boost o/c, SW o/c, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
4.6
2
MAX
5.5
3
UNITS
Minimum Input Voltage
Minimum Boost Voltage
Boost Current (Note 5)
(Note 3)
●
●
V
V
(Note 4) I ≤ 1.5A
SW
Boost = V + 5V, I = 0.5A
●
●
12
42
25
70
mA
mA
IN
SW
Boost = V + 5V, I = 1.5A
IN
SW
Input Supply Current (I
)
(Note 6) V
= 5V
1.4
2.9
25
2.2
4.2
mA
mA
VIN
BIAS
BIAS
Output Supply Current (I
)
(Note 6) V
= 5V
BIAS
Shutdown Supply Current
SHDN = 0V, V ≤ 60V, SW = 0V, V Open
75
200
µA
µA
IN
C
●
●
Lockout Threshold
V Open
C
2.3
2.38
2.46
V
Shutdown Thresholds (LT1956 Only)
V Open, Shutting Down
V Open, Starting Up
C
●
●
0.15
0.25
0.37
0.45
0.6
0.6
V
V
C
Minimum SYNC Amplitude
SYNC Frequency Range
SYNC Input Resistance
●
1.5
2.2
V
kHz
kΩ
580
700
20
Note 1: Absolute Maximum Ratings are those values beyond which the life
Note 7: Switch on resistance is calculated by dividing V to SW voltage by
the forced current (1.5A). See Typical Performance Characteristics for the
graph of switch voltage at other currents.
Note 8: The LT1956EGN/LT1956-5EGN are guaranteed to meet
performance specifications from 0°C to 125°C junction temperature.
Specifications over the –40°C to 125°C operating junction temperature
range are assured by design, characterization and correlation with
statistical process controls. The LT1956IGN/LT1956-5IGN are guaranteed
and tested over the full –40°C to 125°C operating junction temperature
range.
IN
of a device may be impaired.
Note 2: Gain is measured with a V swing equal to 200mV above the low
C
clamp level to 200mV below the upper clamp level.
Note 3: Minimum input voltage is not measured directly, but is guaranteed
by other tests. It is defined as the voltage where internal bias lines are still
regulated so that the reference voltage and oscillator remain constant.
Actual minimum input voltage to maintain a regulated output will depend
upon output voltage and load current. See Applications Information.
Note 4: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.
Note 9: Transconductance and voltage gain refer to the internal amplifier
exclusive of the voltage divider. To calculate gain and transconductance,
refer to the SENSE pin on fixed voltage parts. Divide values shown by the
Note 5: Boost current is the current flowing into the BOOST pin with the
pin held 5V above input voltage. It flows only during switch on time.
ratio V /1.219.
OUT
Note 6: Input supply current is the quiescent current drawn by the input
pin when the BIAS pin is held at 5V with switching disabled. Bias supply
current is the current drawn by the BIAS pin when the BIAS pin is held at
5V. Total input referred supply current is calculated by summing input
supply current (I ) with a fraction of supply current (I
):
BIAS
VIN
I
= I + (I
)(V /V )
BIAS OUT IN
TOTAL
VIN
With V = 15V, V
= 5V, I = 1.4mA, I
= 2.9mA, I
= 2.4mA.
IN
OUT
VIN
BIAS
TOTAL
3
LT1956/LT1956-5
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Switch Peak Current Limit
FB Pin Voltage and Current
SHDN Pin Bias Current
2.5
2.0
1.5
1.0
1.234
1.229
1.224
1.219
2.0
1.5
250
200
150
100
12
CURRENT REQUIRED TO FORCE SHUTDOWN
(FLOWS OUT OF PIN). AFTER SHUTDOWN,
CURRENT DROPS TO A FEW µA
TYPICAL
VOLTAGE
CURRENT
1.0
0.5
0
GUARANTEED MINIMUM
1.214
1.209
1.204
AT 2.38V STANDBY THRESHOLD
(CURRENT FLOWS OUT OF PIN)
6
0
0
20
40
60
80
100
50
100 125
–50 –25
0
25
75
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
DUTY CYCLE (%)
JUNCTION TEMPERATURE (°C)
1956 G01
1956 G02
1956 G03
Lockout and Shutdown
Thresholds
Shutdown Supply Current
Shutdown Supply Current
300
250
40
35
30
25
20
15
10
5
2.4
2.0
1.6
1.2
0.8
0.4
0
V
= 0V
SHDN
LOCKOUT
V
IN
= 60V
200
150
V
IN
= 15V
100
50
0
START-UP
SHUTDOWN
0
0
0.1
0.2
0.3
0.4
0.5
0
10
20
30
40
50
60
–50
–25
0
25
50
75
100
125
SHUTDOWN VOLTAGE (V)
INPUT VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
1956 G06
1956 G05
1956 G04
Error Amplifier Transconductance
Error Amplifier Transconductance
Frequency Foldback
3000
2500
2000
1500
1000
500
200
150
100
50
625
2500
2000
1500
1000
500
SWITCHING
FREQUENCY
PHASE
GAIN
500
375
250
125
0
V
C
C
OUT
12pF
R
OUT
200k
–3
V
2 • 10
(
)
FB
ERROR AMPLIFIER EQUIVALENT CIRCUIT
= 50Ω
0
FB PIN
CURRENT
R
LOAD
1k
–50
0
100
10k
100k
1M
10M
–25
0
25
50
75
100
125
0
0.2
0.4
0.8
1.0
1.2
–50
0.6
(V)
FREQUENCY (Hz)
JUNCTION TEMPERATURE
V
FB
1956 G08
1956 G07
1956 G09
4
LT1956/LT1956-5
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Minimum Input Voltage with 5V
Output
Switching Frequency
BOOST Pin Current
575
550
525
500
475
450
425
7.5
7.0
6.5
6.0
5.5
5.0
45
40
35
30
25
20
15
10
5
V
= 5V
OUT
L = 18µH
MINIMUM INPUT
VOLTAGE TO START
MINIMUM INPUT
VOLTAGE TO RUN
0
–50
–25
0
25
50
75
100
125
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
LOAD CURRENT (A)
1
0
0.5
1
1.5
JUNCTION TEMPERATURE (°C)
SWITCH CURRENT (A)
1956 G10
1956 G11
1956 G12
VC Pin Shutdown Threshold
Switch Voltage Drop
2.1
1.9
450
400
350
300
250
200
150
100
50
T = 125°C
J
1.7
1.5
1.3
1.1
0.9
T = 25°C
J
T = –40°C
J
0.7
0
0
0.5
1
1.5
50
100 125
–50 –25
0
25
75
SWITCH CURRENT (A)
JUNCTION TEMPERATURE (°C)
1766 G14
1956 G13
5
LT1956/LT1956-5
U
U
U
PI FU CTIO S
VC (Pin 11) The VC pin is the output of the error amplifier
and the input of the peak switch current comparator. It is
normally used for frequency compensation, but can also
serve as a current clamp or control loop override. VC sits
at about 1V for light loads and 2V at maximum load. It can
be driven to ground to shut off the regulator, but if driven
high, current must be limited to 4mA.
GND (Pins 1, 8, 9, 16): The GND pin connections act as
the reference for the regulated output, so load regulation
will suffer if the “ground” end of the load is not at the same
voltage as the GND pins of the IC. This condition will occur
when load current or other currents flow through metal
pathsbetweentheGNDpinsandtheloadground.Keepthe
paths between the GND pins and the load ground short
and use a ground plane when possible.
FB/SENSE (Pin 12): The feedback pin is used to set the
output voltage using an external voltage divider that gen-
erates 1.22V at the pin for the desired output voltage. The
5V fixed output voltage parts have the divider included on
the chip and the FB pin is used as a SENSE pin, connected
directly to the 5V output. Three additional functions are
performed by the FB pin. When the pin voltage drops
below 0.6V, switch current limit is reduced and the exter-
nal SYNC function is disabled. Below 0.8V, switching
frequency is also reduced. See Feedback Pin Functions in
Applications Information for details.
SW (Pin 2): The switch pin is the emitter of the on-chip
power NPN switch. This pin is driven up to the input pin
voltage during switch on time. Inductor current drives the
switch pin negative during switch off time. Negative volt-
age is clamped with the external catch diode. Maximum
negative switch voltage allowed is –0.8V.
NC (Pins 3, 5, 7, 13): No Connection.
VIN (Pin 4): This is the collector of the on-chip power NPN
switch. VIN powers the internal control circuitry when a
voltage on the BIAS pin is not present. High dI/dt edges
occur on this pin during switch turn on and off. Keep the
path short from the VIN pin through the input bypass
capacitor, through the catch diode back to SW. All trace
inductanceonthispathwillcreateavoltagespikeatswitch
off, adding to the VCE voltage across the internal NPN.
SYNC (Pin 14): The SYNC pin is used to synchronize the
internal oscillator to an external signal. It is directly logic
compatible and can be driven with any signal between
10% and 90% duty cycle. The synchronizing range is
equal to initial operating frequency up to 700kHz. See
Synchronizing in Applications Information for details. If
unused, this pin should be tied to ground.
BOOST (Pin 6): The BOOST pin is used to provide a drive
voltage, higher than the input voltage, to the internal
bipolarNPNpowerswitch. Withoutthisaddedvoltage, the
typical switch voltage loss would be about 1.5V. The
additional BOOST voltage allows the switch to saturate
and voltage loss approximates that of a 0.2Ω FET struc-
ture, but with much smaller die area.
SHDN (Pin 15): The SHDN pin is used to turn off the
regulator and to reduce input current to a few microam-
peres. This pin has two thresholds: one at 2.38V to disable
switching and a second at 0.4V to force complete mi-
cropower shutdown. The 2.38V threshold functions as an
accurate undervoltage lockout (UVLO); sometimes used
to prevent the regulator from delivering power until the
input voltage has reached a predetermined level.
BIAS (Pin 10): The BIAS pin is used to improve efficiency
when operating at higher input voltages and light load
current. Connecting this pin to the regulated output volt-
age forces most of the internal circuitry to draw its oper-
ating current from the output voltage rather than the input
supply. This architecture increases efficiency especially
when the input voltage is much higher than the output.
Minimumoutputvoltagesettingforthismodeofoperation
is 3.3V.
If the SHDN pin functions are not required, the pin can
either be left open (to allow an internal bias current to lift
the pin to a default high state) or be forced high to a level
not to exceed 6V.
6
LT1956/LT1956-5
W
BLOCK DIAGRA
The LT1956 is a constant frequency, current mode buck
converter. This means that there is an internal clock and
twofeedbackloopsthatcontrolthedutycycleofthepower
switch. In addition to the normal error amplifier, there is a
current sense amplifier that monitors switch current on a
cycle-by-cycle basis. A switch cycle starts with an oscilla-
tor pulse which sets the RS flip-flop to turn the switch on.
When switch current reaches a level set by the inverting
input of the comparator, the flip-flop is reset and the
switch turns off. Output voltage control is obtained by
using the output of the error amplifier to set the switch
current trip point. This technique means that the error
amplifier commands current to be delivered to the output
rather than voltage. A voltage fed system will have low
phase shift up to the resonant frequency of the inductor
and output capacitor, then an abrupt 180° shift will occur.
The current fed system will have 90° phase shift at a much
lower frequency, but will not have the additional 90° shift
until well beyond the LC resonant frequency. This makes
itmucheasiertofrequencycompensatethefeedbackloop
and also gives much quicker transient response.
Most of the circuitry of the LT1956 operates from an
internal 2.9V bias line. The bias regulator normally draws
power from the regulator input pin, but if the BIAS pin is
connected to an external voltage higher than 3V, bias
powerwillbedrawnfromtheexternalsource(typicallythe
regulated output voltage). This will improve efficiency if
the BIAS pin voltage is lower than regulator input voltage.
High switch efficiency is attained by using the BOOST pin
to provide a voltage to the switch driver which is higher
than the input voltage, allowing switch to be saturated.
This boosted voltage is generated with an external capaci-
tor and diode. Two comparators are connected to the
shutdownpin. Onehasa2.38Vthresholdforundervoltage
lockout and the second has a 0.4V threshold for complete
shutdown.
V
4
IN
R
LIMIT
R
SENSE
–
+
2.9V BIAS
REGULATOR
INTERNAL
CC
BIAS
10
V
CURRENT
COMPARATOR
SLOPE COMP
Σ
SYNC 14
BOOST
6
ANTISLOPE COMP
SHUTDOWN
COMPARATOR
500kHz
OSCILLATOR
–
+
S
Q1
POWER
SWITCH
R
DRIVER
CIRCUITRY
S
FLIP-FLOP
R
0.4V
5.5µA
2
SW
SHDN 15
+
–
FREQUENCY
FOLDBACK
LOCKOUT
COMPARATOR
×1
Q2
FOLDBACK
CURRENT
LIMIT
V
C(MAX)
CLAMP
Q3
ERROR
AMPLIFIER
= 2000µMho
CLAMP
–
+
12
FB
g
m
11
1.22V
2.38V
V
C
GND
1, 8, 9, 16
1956 F01
Figure 1. LT1956 Block Diagram
7
LT1956/LT1956-5
W U U
U
APPLICATIO S I FOR ATIO
FEEDBACK PIN FUNCTIONS
current through the diode and inductor is equal to the
short-circuitcurrentlimitoftheswitch(typically2Aforthe
LT1956, foldingbacktolessthan1A). Minimumswitchon
time limitations would prevent the switcher from attaining
a sufficiently low duty cycle if switching frequency were
maintained at 500kHz, so frequency is reduced by about
5:1 when the feedback pin voltage drops below 0.8V (see
FrequencyFoldbackgraph). Thisdoesnotaffectoperation
with normal load conditions; one simply sees a shift in
switching frequency during start-up as the output voltage
rises.
The feedback (FB) pin on the LT1956 is used to set output
voltage and provide several overload protection features.
The first part of this section deals with selecting resistors
to set output voltage and the remaining part talks about
foldback frequency and current limiting created by the FB
pin. Please read both parts before committing to a final
design. The 5V fixed output voltage part (LT1956-5) has
internaldividerresistorsandtheFBpinisrenamedSENSE,
connected directly to the output.
The suggested value for the output divider resistor (see
Figure 2) from FB to ground (R2) is 5k or less, and a
formula for R1 is shown below. The output voltage error
caused by ignoring the input bias current on the FB pin is
less than 0.25% with R2 = 5k. A table of standard 1%
values is shown in Table 1 for common output voltages.
Please read the following section if divider resistors are
increased above the suggested values.
In addition to lower switching frequency, the LT1956 also
operates at lower switch current limit when the feedback
pin voltage drops below 0.6V. Q2 in Figure 2 performs this
function by clamping the VC pin to a voltage less than its
normal 2.1V upper clamp level. This foldback current limit
greatly reduces power dissipation in the IC, diode and in-
ductor during short-circuit conditions. External synchro-
nization is also disabled to prevent interference with fold-
back operation. Again, it is nearly transparent to the user
under normal load conditions. The only loads that may be
affected are current source loads which maintain full load
current with output voltage less than 50% of final value. In
theseraresituationsthefeedbackpincanbeclampedabove
0.6Vwithanexternaldiodetodefeatfoldbackcurrentlimit.
Caution: clamping the feedback pin means that frequency
shifting will also be defeated, so a combination of high in-
putvoltageanddeadshortedoutputmaycausetheLT1956
to lose control of current limit.
R2 V
−1.22
1.22
(
)
OUT
R1=
Table 1
OUTPUT
VOLTAGE
(V)
R1
% ERROR AT OUTPUT
R2
(NEAREST 1%) DUE TO DISCRETE 1%
(kΩ
)
(k
Ω
)
RESISTOR STEPS
+0.32
3
3.3
5
4.99
4.99
4.99
4.99
4.99
4.99
4.99
4.99
7.32
8.45
15.4
19.6
28.0
35.7
44.2
56.2
–0.43
–0.30
6
+0.20
The internal circuitry which forces reduced switching
frequency also causes current to flow out of the feedback
pin when output voltage is low. The equivalent circuitry is
shown in Figure 2. Q1 is completely off during normal
operation. If the FB pin falls below 0.8V, Q1 begins to
conduct current and reduces frequency at the rate of
approximately 3.5kHz/µA. To ensure adequate frequency
foldback (under worst-case short-circuit conditions), the
external divider Thevinin resistance must be low enough
to pull 115µA out of the FB pin with 0.44V on the pin (RDIV
≤ 3.8k). The net result is that reductions in frequency and
current limit are affected by output voltage divider imped-
ance. Although divider impedance is not critical, caution
should be used if resistors are increased beyond the
suggested values and short-circuit conditions will occur
8
+0.82
10
12
15
–0.52
+0.22
–0.26
More Than Just Voltage Feedback
The feedback pin is used for more than just output voltage
sensing. It also reduces switching frequency and current
limit when output voltage is very low (see the Frequency
Foldback graph in Typical Performance Characteristics).
ThisisdonetocontrolpowerdissipationinboththeICand
in the external diode and inductor during short-circuit
conditions. A shorted output requires the switching regu-
lator to operate at very low duty cycles, and the average
8
LT1956/LT1956-5
W U U
APPLICATIO S I FOR ATIO
U
V
SW
LT1956
TO FREQUENCY
SHIFTING
OUTPUT
5V
1.4V
Q1
ERROR
AMPLIFIER
R1
1.2V
+
–
R4
2k
R3
1k
FB
+
BUFFER
Q2
R2
5k
TO SYNC CIRCUIT
V
C
GND
1956 F02
Figure 2. Frequency and Current Limit Foldback
with high input voltage. High frequency pickup will in-
crease and the protection accorded by frequency and
current foldback will decrease.
V
V
AT I
AT I
= 1A
OUT
OUT
OUT
OUT
20mV/DIV
0.5A/DIV
= 0.1A
CHOOSING THE INDUCTOR
For most applications, the output inductor will fall into the
range of 5µH to 30µH. Lower values are chosen to reduce
physical size of the inductor. Higher values allow more
output current because they reduce peak current seen by
the LT1956 switch, which has a 1.5A limit. Higher values
also reduce output ripple voltage.
INDUCTOR CURRENT
AT I = 1A
OUT
INDUCTOR CURRENT
AT I = 0.1A
OUT
V
V
= 12V
OUT
L = 18µH
1µs/DIV
1956 F03
IN
= 5V
When choosing an inductor you will need to consider
output ripple voltage, maximum load current, peak induc-
tor current and fault current in the inductor. In addition,
other factors such as core and copper losses, allowable
component height, EMI, saturation and cost should also
be considered. The following procedure is suggested as a
way of handling these somewhat complicated and con-
flicting requirements.
Figure 3. LT1956 Ripple Voltage Waveform
frequency impedance of the output capacitor. The follow-
ing equations will help in choosing the required inductor
value to achieve a desirable output ripple voltage level. If
outputripplevoltageisoflessimportance,thesubsequent
suggestions in Peak Inductor and Fault Current and EMI
will additionally help in the selection of the inductor value.
Peak-to-peak output ripple voltage is the sum of a triwave
(created by peak-to-peak ripple current (ILP-P) times ESR)
and a square wave (created by parasitic inductance (ESL)
and ripple current slew rate). Capacitive reactance is
assumed to be small compared to ESR or ESL.
Output Ripple Voltage
Figure 3 shows a typical output ripple voltage waveform
for the LT1956. Ripple voltage is determined by ripple
current (ILP-P) through the inductor and the high
9
LT1956/LT1956-5
W U U
U
APPLICATIO S I FOR ATIO
Peak Inductor Current and Fault Current
dI
dt
VRIPPLE = I
ESR + ESL Σ
) (
(
LP-P)(
)
To ensure that the inductor will not saturate, the peak
inductor current should be calculated knowing the maxi-
mum load current. An appropriate inductor should then
bechosen.Inaddition,adecisionshouldbemadewhether
or not the inductor must withstand continuous fault
conditions.
where:
ESR = equivalent series resistance of the output
capacitor
ESL = equivalent series inductance of the output
capacitor
If maximum load current is 0.5A, for instance, a 0.5A
inductor may not survive a continuous 2A overload condi-
tion. Dead shorts will actually be more gentle on the
inductor because the LT1956 has frequency and current
limit foldback.
dI/dt = slew rate of inductor ripple current = VIN/L
Peak-to-peak ripple current (ILP-P) through the inductor
and into the output capacitor is typically chosen to be
between 20% and 40% of the maximum load current. It is
approximated by:
Peak current can be significantly higher than output cur-
rent, especially with smaller inductors and lighter loads,
so don’t omit this step. Powdered iron cores are forgiving
because they saturate softly, whereas ferrite cores satu-
rate abruptly. Other core materials fall somewhere in
between.Thefollowingformulaassumescontinuousmode
of operation, but errs only slightly on the high side for
discontinuous mode, so it can be used for all conditions.
V
OUT)(
V – V
IN OUT
(
=
)
ILP-P
V
f L
(
IN)( )( )
Example: with VIN = 12V, VOUT = 5V, L = 18µH, ESR = 0.1Ω
and ESL = 10nH, output ripple voltage can be approxi-
mated as follows:
5 12 − 5
( )(
)
V
V – V
IN OUT
I
OUT +(ILP-P
)
(
OUT)(
)
ILP-P
=
= 0.324A
IPEAK
=
= IOUT
12 500 •103 18 •10–6
( )
(
)(
)
2
2 V f L
( )( IN)( )( )
dI
Σ
V
L
12
IN
=
=
= 0.67 •10–6
Table 2
VENDOR/
PART NO.
18 •10−6
dt
VALUE
H)
I
DCR
(Ohms)
HEIGHT
(mm)
DC(MAX)
(Amps)
VRIPPLE = 0.324 0.1 + 10 •10−9 0.67 •10–6
(µ
(
)( )
(
)(
)
Coiltronics
TP3-4R7
CTX5-1P
TP4-100
= 0.0324 + 0.0067 = 0.039VP-P
4.7
5
1.5
2.0
1.5
1.7
1.4
1.5
0.181
0.041
0.146
0.057
0.087
0.097
2.2
4.2
3.0
4.2
4.2
4.2
To reduce output ripple voltage further requires an in-
crease in the inductor value or a reduction in the capacitor
ESR. The latter can effect loop stability since the ESR
forms a useful zero in the overall loop response. Typically
the inductor value is adjusted with the trade-off being a
physically larger inductor with the possibility of increased
component height and cost. Choosing a smaller inductor
with lighter loads may result in discontinuous operation
but the LT1956 is designed to work well in both continu-
ous or discontinuous mode.
10
10
15
20
CTX10-1P
CTX15-1P
CTX20-2P
Sumida
CDRH4D28-4R7
CDRH5D28-100
CDRH6D28-150
CDRH6D28-180
CDRH6D38-220
4.7
10
15
18
22
1.32
1.30
1.40
1.32
1.30
0.072
0.065
0.084
0.095
0.096
3.0
3.0
3.0
3.0
4.0
10
LT1956/LT1956-5
W U U
APPLICATIO S I FOR ATIO
U
EMI
V
V – V
IN OUT
ILP-P
2
(
OUT)(
)
IOUT(MAX)
=
IP –
= IP –
Decide if the design can tolerate an “open” core geometry
like a rod or barrel, which have high magnetic field
radiation, or whether it needs a closed core like a toroid to
prevent EMI problems. This is a tough decision because
the rods or barrels are temptingly cheap and small and
there are no helpful guidelines to calculate when the
magnetic field radiation will be a problem.
2 V f L
( )( IN)( )( )
Continuous Mode
For VOUT = 5V, VIN(MAX) = 8V, L = 10µH:
5 8 – 5
( )(
)
I
OUT(MAX) = 1.5 –
2 8 500 •103 10 •10–6
( )( )
(
)(
)
= 1.5 – 0.19 = 1.31A
Additional Considerations
Note that there is less load current available at the higher
inputvoltagebecauseinductorripplecurrentincreases.At
VIN = 15V and using the same set of conditions:
After making an initial choice, consider additional factors
such as core losses and second sourcing, etc. Use the
experts in Linear Technology’s Applications department if
you feel uncertain about the final choice. They have
experience with a wide range of inductor types and can tell
you about the latest developments in low profile, surface
mounting, etc.
5 15 – 5
( )(
)
I
OUT(MAX) = 1.5 –
2 15 500 •103 10 •10–6
( )( )
(
)(
)
= 1.5 – 0.33 = 1.17A
MAXIMUM OUTPUT LOAD CURRENT
To calculate peak switch current with a given set of
conditions, use:
Maximum load current for a buck converter is limited by
themaximumswitchcurrentrating(IP).Thecurrentrating
fortheLT1956is1.5A. Unlikemostcurrentmodeconvert-
ers, the LT1956 maximum switch current limit does not
fall off at high duty cycles. Most current mode converters
suffer a drop off of peak switch current for duty cycles
above 50%. This is due to the effects of slope compensa-
tion required to prevent subharmonic oscillations in cur-
rent mode converters. (For detailed analysis, see Applica-
tion Note 19.)
V
V – V
IN OUT
ILP-P
2
(
=IOUT +
OUT)(
)
ISW(PEAK) =IOUT
+
2 V f L
( )( IN)( )( )
When a smaller inductor value is chosen to reduce physi-
cal size and/or cost, the inductor ripple current will in-
crease. If load current is less than one half of this ripple
current, the converter enters discontinuous mode. This
involvestheinductorcurrentfallingtozerobeforethenext
switch turn on. The LT1956 is designed to operate well in
either continuous or discontinuous mode. Buck convert-
ers will be in discontinuous mode for output load current
less than:
The LT1956 is able to maintain peak switch current limit
over the full duty cycle range by using patented circuitry to
cancel the effects of slope compensation on peak switch
current without affecting the frequency compensation it
provides.
VOUT
V
IN
VOUT 1–
IOUT
≤
Maximum load current would be equal to maximum
switch current for an infinitely large inductor, but with
finite inductor size, maximum load current is reduced by
one half of peak-to-peak inductor current (ILP-P). The
following formula assumes continuous mode operation,
implying that the term on the right is less than one half of
IP.
2 f L
( )( )( )
Discontinuous Mode
11
LT1956/LT1956-5
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APPLICATIO S I FOR ATIO
OUTPUT CAPACITOR
Output capacitor ripple current (RMS):
The output capacitor is normally chosen by its effective
series resistance (ESR), because this is what determines
output ripple voltage. To get low ESR takes volume, so
physically smaller capacitors have high ESR. The ESR
range for typical LT1956 applications is 0.05Ω to 0.2Ω. A
typical output capacitor is an AVX type TPS, 100µF at 10V,
with a guaranteed ESR less than 0.1Ω. This is a “D” size
surface mount solid tantalum capacitor. TPS capacitors
are specially constructed and tested for low ESR, so they
give the lowest ESR for a given volume. The value in
microfarads is not particularly critical, and values from
22µF to greater than 500µF work well, but you cannot
cheat mother nature on ESR. If you find a tiny 22µF solid
tantalumcapacitor, itwillhavehighESR, andoutputripple
voltage will be terrible. Table 3 shows some typical solid
tantalum surface mount capacitors.
0.29 V
OUT)(
=
V – V
IN OUT
(
)
IRIPPLE(RMS)
L f V
( )( )(
)
IN
Ceramic Capacitors
Higher value, lower cost ceramic capacitors are now
becoming available. They are generally chosen for their
good high frequency operation, small size and very low
ESR (effective series resistance). Their low ESR reduces
outputripplevoltagebutalsoremovesausefulzerointhe
loop frequency response, common to tantalum capaci-
tors. To compensate for this, a resistor RC can be placed
in series with the VC compensation capacitor CC. Care
must be taken however, since this resistor sets the high
frequency gain of the error amplifier, including the gain
at the switching frequency. If the gain of the error
amplifier is high enough at the switching frequency,
output ripple voltage (although smaller for a ceramic
output capacitor) may still affect the proper operation of
the regulator. A filter capacitor CF in parallel with the
RC/CC network is suggested to control possible ripple at
the VC pin. The LT1956 can be stabilized using a 22µF
ceramic output capacitor and VC components values of
CC = 10nF, RC = 2.2k and CF = 1nF.
Table 3. Surface Mount Solid Tantalum Capacitor ESR
and Ripple Current
E CASE SIZE
ESR (MAX,
Ω
)
RIPPLE CURRENT (A)
AVX TPS, Sprague 593D
AVX TAJ
0.1 to 0.3
0.7 to 0.9
0.7 to 1.1
0.4
D CASE SIZE
AVX TPS, Sprague 593D
C CASE SIZE
0.1 to 0.3
0.2 (typ)
0.7 to 1.1
0.5 (typ)
AVX TPS
INPUT CAPACITOR
Many engineers have heard that solid tantalum capacitors
are prone to failure if they undergo high surge currents.
This is historically true, and type TPS capacitors are
speciallytestedforsurgecapability,butsurgeruggedness
is not a critical issue with the output capacitor. Solid
tantalum capacitors fail during very high turn-on surges,
which do not occur at the output of regulators. High
discharge surges, such as when the regulator output is
dead shorted, do not harm the capacitors.
Step-down regulators draw current from the input supply
in pulses. The rise and fall times of these pulses are very
fast. The input capacitor is required to reduce the voltage
ripple this causes at the input of LT1956 and force the
switching current into a tight local loop, thereby minimiz-
ing EMI. The RMS ripple current can be calculated from:
VOUT V – V
(
)
IN
OUT
IRIPPLE(RMS)CIN = IOUT
2
V
IN
Unlike the input capacitor, RMS ripple current in the
output capacitor is normally low enough that ripple cur-
rent rating is not an issue. The current waveform is
triangular with a typical value of 200mARMS. The formula
to calculate this is:
Ceramiccapacitorsareidealforinputbypassing.At500kHz
switching frequency, the energy storage requirement of
the input capacitor suggests that values in the range of
2.2µF to 10µF are suitable for most applications. If opera-
tionisrequiredclosetotheminimuminputrequiredbythe
12
LT1956/LT1956-5
W U U
APPLICATIO S I FOR ATIO
U
short circuited, the feedback amplifier responds to the low
output voltage by raising the control voltage, VC, to its
peak current limit value. Ideally, the output switch would
be turned on, and then turned off as its current exceeded
thevalueindicatedbyVC.However,thereisfiniteresponse
time involved in both the current comparator and turnoff
of the output switch. These result in a minimum on time
output of the LT1956, a larger value may be required. This
is to prevent excessive ripple causing dips below the mini-
mum operating voltage resulting in erratic operation.
Depending on how the LT1956 circuit is powered up you
may need to check for input voltage transients.
The input voltage transients may be caused by input
voltage steps or by connecting the LT1956 converter to an
already powered up source such as a wall adapter. The
sudden application of input voltage will cause a large
surge of current in the input leads that will store energy in
the parasitic inductance of the leads. This energy will
causetheinputvoltagetoswingabovetheDClevelofinput
power source and it may exceed the maximum voltage
rating of input capacitor and LT1956.
tON(MIN). When combined with the large ratio of VIN to
(VF + I • R), the diode forward voltage plus inductor I • R
voltage drop, the potential exists for a loss of control.
Expressed mathematically the requirement to maintain
control is:
VF +I•R
f • tON
where:
≤
V
IN
The easiest way to suppress input voltage transients is to
addasmallaluminumelectrolyticcapacitorinparallelwith
the low ESR input capacitor. The selected capacitor needs
to have the right amount of ESR in order to critically
dampen the resonant circuit formed by the input lead
inductance and the input capacitor. The typical values of
ESRwillfallintherangeof0.5Ωto2Ωandcapacitancewill
fall in the range of 5µF to 50µF.
f = switching frequency
tON = switch on time
VF = diode forward voltage
VIN = Input voltage
I • R = inductor I • R voltage drop
If this condition is not observed, the current will not be
limited at IPK, but will cycle-by-cycle ratchet up to some
higher value. Using the nominal LT1956 clock frequency
of 500KHz, a VIN of 40V and a (VF + I • R) of say 0.7V, the
maximum tON to maintain control would be approximately
35ns, an unacceptably short time.
If tantalum capacitors are used, values in the 22µF to
470µF range are generally needed to minimize ESR and
meet ripple current and surge ratings. Care should be
taken to ensure the ripple and surge ratings are not
exceeded. The AVX TPS and Kemet T495 series are surge
rated. AVX recommends derating capacitor operating
voltage by 2 for high surge applications.
The solution to this dilemma is to slow down the oscillator
when the FB pin voltage is abnormally low thereby indicat-
ing some sort of short-circuit condition. Oscillator fre-
quency is unaffected until FB voltage drops to about 2/3 of
its normal value. Below this point the oscillator frequency
decreasesroughlylinearlydowntoalimitofabout100kHz.
Thisloweroscillatorfrequencyduringshort-circuitcondi-
tions can then maintain control with the effective mini-
mum on time.
SHORT-CIRCUIT CONSIDERATIONS
The LT1956 is a current mode controller. It uses the VC
node voltage as an input to a current comparator which
turns off the output switch on a cycle-by-cycle basis as
this peak current is reached. The internal clamp on the VC
node, nominally 2V, then acts as an output switch peak
current limit. This action becomes the switch current limit
specification. The maximum available output power is
then determined by the switch current limit.
It is recommended that for [VIN/(VOUT + VF)] ratios > 4, a
soft-start circuit should be used to control the output
capacitor charge rate during start-up or during recovery
from an output short circuit, thereby adding additional
control over peak inductor current. See Buck Converter
with Adjustable Soft-Start later in this data sheet.
A potential controllability problem could occur under
short-circuit conditions. If the power supply output is
13
LT1956/LT1956-5
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APPLICATIO S I FOR ATIO
voltage approximately VOUT above VIN to drive the output
stage. However, the output stage discharges the boost
capacitor during the on time of the switch. The output
driver requires at least 3V of headroom throughout this
period to keep the switch fully saturated. If the output
voltageislessthan3V,itisrecommendedthatanalternate
boostsupplyisused. Theboostdiodecanbeconnectedto
the input, although, care must be taken to prevent the 2×
VIN boost voltage from exceeding the BOOST pin absolute
maximum rating. The additional voltage across the switch
driver also increases power loss, reducing efficiency. If
available, an independent supply can be used with a local
bypass capacitor.
CATCH DIODE
HighestefficiencyoperationrequirestheuseofaSchottky
type diode. DC switching losses are minimized due to its
low forward voltage drop, and AC behavior is benign due
to its lack of a significant reverse recovery time. Schottky
diodes are generally available with reverse voltage ratings
of60Vandeven100V,andarepricecompetitivewithother
types.
The use of so-called “ultrafast” recovery diodes is gener-
ally not recommended. When operating in continuous
mode, the reverse recovery time exhibited by “ultrafast”
diodes will result in a slingshot type effect. The power
internalswitchwillrampupVIN currentintothediodeinan
attempt to get it to recover. Then, when the diode has
finallyturnedoff,sometensofnanosecondslater,theVSW
node voltage ramps up at an extremely high dV/dt, per-
haps 5 to even 10V/ns! With real world lead inductances,
the VSW node can easily overshoot the VIN rail. This can
result in poor RFI behavior and if the overshoot is severe
enough, damage the IC itself.
A 0.1µF boost capacitor is recommended for most appli-
cations. Almost any type of film or ceramic capacitor is
suitable, but the ESR should be <1Ω to ensure it can be
fully recharged during the off time of the switch. The
capacitor value is derived from worst-case conditions of
1800ns on time, 42mA boost current and 0.7V discharge
ripple. The boost capacitor value could be reduced under
less demanding conditions, but this will not improve
circuitoperationorefficiency.Underlowinputvoltageand
low load conditions, a higher value capacitor will reduce
discharge ripple and improve start-up operation.
The suggested catch diode (D1) is an International Recti-
fier 10MQ060N Schottky. It is rated at 1.5A average
forward current and 60V reverse voltage. Typical forward
voltage is 0.63V at 1.5A. The diode conducts current only
during switch off time. Peak reverse voltage is equal to
regulatorinputvoltage.Averageforwardcurrentinnormal
operation can be calculated from:
SHUTDOWN FUNCTION AND UNDERVOLTAGE
LOCKOUT
Figure 4 shows how to add undervoltage lockout (UVLO)
to the LT1956. Typically, UVLO is used in situations where
the input supply is current limited, or has a relatively high
source resistance. A switching regulator draws constant
power from the source, so source current increases as
source voltage drops. This looks like a negative resistance
loadtothesourceandcancausethesourcetocurrentlimit
or latch low under low source voltage conditions. UVLO
prevents the regulator from operating at source voltages
where these problems might occur.
ID(AVG) = IOUT (1 – DC)
This formula will not yield values higher than 1.5A with
maximum load current of 1.5A. The only reason to
consider a larger diode is the worst-case condition of a
high input voltage and shorted output. With a shorted
condition, diode current will increase to a typical value of
2A, determined by peak switch current limit. This is safe
forshortperiodsoftime, butitwouldbeprudenttocheck
with the diode manufacturer if continuous operation
under these conditions must be tolerated.
Threshold voltage for lockout is about 2.38V. A 5.5µA bias
currentflowsout ofthepinatthisthreshold. Theinternally
generated current is used to force a default high state on
the shutdown pin if the pin is left open. When low shut-
down current is not an issue, the error due to this current
can be minimized by making RLO 10k or less. If shutdown
BOOST PIN
For most applications, the boost components are a 0.1µF
capacitor and a 1N914 diode. The anode is typically
connected to the regulated output voltage to generate a
14
LT1956/LT1956-5
W U U
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APPLICATIO S I FOR ATIO
R
FB
LT1956
IN
OUTPUT
V
SW
2.38V
+
–
INPUT
STANDBY
R
HI
5.5µA
+
SHDN
+
–
TOTAL
SHUTDOWN
R
C1
LO
0.4V
GND
1956 F04
Figure 4. Undervoltage Lockout
currentisanissue, RLO canberaisedto100k, buttheerror
due to initial bias current and changes with temperature
should be considered.
Example: output voltage is 5V, switching is to stop if input
voltage drops below 12V and should not restart unless
input rises back to 13.5V. ∆V is therefore 1.5V and
VIN = 12V. Let RLO = 25k.
RLO = 10k to 100k 25k suggested
(
)
25k 12 − 2.38 1.5/5 +1 + 1.5
(
)
)
RLO V − 2.38V
[
]
(
)
IN
RHI =
RHI =
2.38V −RLO 5.5µA
(
)
2.38 – 25k 5.5µA
(
VIN = Minimum input voltage
25k 10.41
(
)
=
= 116k
Keep the connections from the resistors to the shutdown
pin short and make sure that interplane or surface capaci-
tance to the switching nodes are minimized. If high
resistor values are used, the shutdown pin should be
bypassed with a 1000pF capacitor to prevent coupling
problems from the switch node. If hysteresis is desired in
the undervoltage lockout point, a resistor RFB can be
added to the output node. Resistor values can be calcu-
lated from:
2.24
RFB = 116k 5/1.5 = 387k
(
)
SYNCHRONIZING
The SYNC input must pass from a logic level low, through
the maximum synchronization threshold with a duty cycle
between 10% and 90%. The input can be driven directly
from a logic level output. The synchronizing range is equal
to initial operating frequency up to 700kHz. This means
that minimum practical sync frequency is equal to the
worst-case high self-oscillating frequency (570kHz), not
the typical operating frequency of 500kHz. Caution should
be used when synchronizing above 662kHz because at
highersyncfrequenciestheamplitudeoftheinternalslope
compensation used to prevent subharmonic switching is
reduced. This type of subharmonic switching only occurs
at input voltages less than twice output voltage. Higher
inductor values will tend to eliminate this problem. See
RLO V − 2.38 ∆V/V
+1 + ∆V
(
)
[
IN
OUT
]
RHI =
2.38 −RLO 5.5µA
(
)
R = R
FB
V
/
∆V
(
)
(
)
HI
OUT
25k suggested for RLO
VIN = Input voltage at which switching stops as input
voltage descends to trip level
∆V = Hysteresis in input voltage level
15
LT1956/LT1956-5
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APPLICATIO S I FOR ATIO
Frequency Compensation section for a discussion of an
entirely different cause of subharmonic switching before
assuming that the cause is insufficient slope compensa-
tion. Application Note 19 has more details on the theory
of slope compensation.
in Figure 5, must be kept as short as possible. This is
implementedinthesuggestedlayoutofFigure6. Shorten-
ingthispathwillalsoreducetheparasitictraceinductance
of approximately 25nH/inch. At switch off, this parasitic
inductance produces a flyback spike across the LT1956
switch. When operating at higher currents and input
voltages, with poor layout, this spike can generate volt-
ages across the LT1956 that may exceed its absolute
maximum rating. A ground plane should always be used
under the switcher circuitry to prevent interplane coupling
and overall noise.
At power-up, when VC is being clamped by the FB pin (see
Figure2,Q2),thesyncfunctionisdisabled.Thisallowsthe
frequency foldback to operate in the shorted output con-
dition. During normal operation, switching frequency is
controlledbytheinternaloscillatoruntiltheFBpinreaches
0.8V, after which the SYNC pin becomes operational. If no
synchronization is required, this pin should be connected
to ground.
LT1956
L1
5V
LAYOUT CONSIDERATIONS
HIGH
FREQUENCY
V
IN
C3
D1
LOAD
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
efficiency, switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted, the high speed switching current path, shown
CIRCULATING
PATH
1956 F05
Figure 5. High Speed Switching Path
CONNECT TO
GROUND PLANE
GND
L1
C1
MINIMIZE LT1956
C3-D1 LOOP
D2
V
OUT
D1
C3
C2
GND
GND
SW
GND
SHDN
SYNC
KELVIN SENSE
V
OUT
V
IN
LT1956
FB
R2
V
C
BOOST
GND
R1
BIAS
GND
C
C
V
IN
KEEP FB AND V COMPONENTS
C
AWAY FROM HIGH FREQUENCY,
HIGH CURRENT COMPONENTS
PLACE FEEDTHROUGH AROUND
GROUND PINS (4 CORNERS) FOR
GOOD THERMAL CONDUCTIVITY
1956 F06
Figure 6. Suggested Layout (Topside Only Shown)
16
LT1956/LT1956-5
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APPLICATIO S I FOR ATIO
U
The VC and FB components should be kept as far away as
possible from the switch and boost nodes. The LT1956
pinout has been designed to aid in this. The ground for
these components should be separated from the switch
current path. Failure to do so will result in poor stability or
subharmonic like oscillation.
currents this spike can be in the order of 10V to 20V or
higher with a poor layout, potentially exceeding the abso-
lute max switch voltage. The path around switch, catch
diode and input capacitor must be kept as short as
possibletoensurereliableoperation.Whenlookingatthis,
a >100MHz oscilloscope must be used, and waveforms
should be observed on the leads of the package. This
switch off spike will also cause the SW node to go below
ground. The LT1956 has special circuitry inside which
mitigates this problem, but negative voltages over 0.8V
lasting longer than 10ns should be avoided. Note that
100MHz oscilloscopes are barely fast enough to see the
details of the falling edge overshoot in Figure 7.
Board layout also has a significant effect on thermal
resistance. Pins 1, 8, 9 and 16, GND, are a continuous
copper plate that runs under the LT1956 die. This is the
bestthermalpathforheatoutofthepackage.Reducingthe
thermal resistance from Pins 1, 8, 9 and 16 onto the board
will reduce die temperature and increase the power capa-
bilityoftheLT1956. Thisisachievedbyprovidingasmuch
copper area as possible around these pins. Adding mul-
tiple solder filled feedthroughs under and around these
four corner pins to the ground plane will also help. Similar
treatment to the catch diode and coil terminations will
reduce any additional heating effects.
A second, much lower frequency ringing is seen during
switch off time if load current is low enough to allow the
inductor current to fall to zero during part of the switch off
time (see Figure 8). Switch and diode capacitance reso-
nate with the inductor to form damped ringing at 1MHz to
10 MHz. This ringing is not harmful to the regulator and it
hasnotbeenshowntocontributesignificantlytoEMI. Any
attempt to damp it with a resistive snubber will degrade
efficiency.
PARASITIC RESONANCE
Resonance or “ringing” may sometimes be seen on the
switch node (see Figure 7). Very high frequency ringing
following switch rise time is caused by switch/diode/input
capacitor lead inductance and diode capacitance. Schot-
tky diodes have very high “Q” junction capacitance that
can ring for many cycles when excited at high frequency.
Iftotalleadlengthfortheinputcapacitor, diodeandswitch
path is 1 inch, the inductance will be approximately 25nH.
At switch off, this will produce a spike across the NPN
output device in addition to the input voltage. At higher
SWITCH NODE
VOLTAGE
10V/DIV
INDUCTOR
CURRENT AT
IOUT = 0.1A
0.2A/DIV
VIN = 25V
VOUT = 5V
L = 15µH
500ns/DIV
1956 F08
SW RISE
SW FALL
Figure 8. Discontinuous Mode Ringing
THERMAL CALCULATIONS
2V/DIV
Power dissipation in the LT1956 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current,andinputquiescentcurrent.Thefollowingformu-
las show how to calculate each of these losses. These
formulas assume continuous mode operation, so they
should not be used for calculating efficiency at light load
currents.
50ns/DIV
1956 F07
Figure 7. Switch Node Resonance
17
LT1956/LT1956-5
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APPLICATIO S I FOR ATIO
Switch loss:
Input Voltage vs Operating Frequency Considerations
2
TheabsolutemaximuminputsupplyvoltagefortheLT1956
is specified at 60V. This is based solely on internal semi-
conductor junction breakdown effects. Due to internal
power dissipation, the actual maximum VIN achievable in
a particular application may be less than this.
RSW IOUT VOUT
(
) (
)
)
PSW
=
+ tEFF(1/2) IOUT
V
f
(
)( IN)( )
V
IN
Boost current loss:
2
VOUT
I
(
/36
OUT
A detailed theoretical basis for estimating internal power
loss is given in the Thermal Calculations section. Note that
AC switching loss is proportional to both operating fre-
quency and output current. The majority of AC switching
loss is also proportional to the square of input voltage. For
example, while the combination of VIN = 25V, VOUT = 5V at
1A and fOSC = 500kHz may be easily achievable, simulta-
neously raising VIN to 60V and fOSC to 700kHz is not
possible. Nevertheless, input voltage transients up to 60V
can usually be accommodated, assuming the resulting
increase in internal dissipation is of insufficient time
duration to raise die temperature significantly.
PBOOST
=
V
IN
Quiescent current loss:
P = V 0.0015 + V 0.003
OUT
(
)
(
)
Q
IN
RSW = Switch resistance (≈0.3) hot
tEFF = Effective switch current/voltage overlap time
= (tr + tf + tIr + tIf)
tr = (VIN/1.2)ns
tf = (VIN/1.7)ns
tIr = tIf = (IOUT/0.05)ns
f = Switch frequency
A second consideration is controllability. A potential limi-
tation occurs with a high step-down ratio of VIN to VOUT
,
Example: with VIN = 12V, VOUT = 5V and IOUT = 1A:
asthisrequiresacorrespondinglynarrowminimumswitch
on time. An approximate expression for this (assuming
continuous mode operation) is given as follows:
0.3 1 2 5
(
)( ) ( )
PSW
=
+ 57•10−9 1/2 1 12 500 •103
(
)
)
( )( )
(
(
)
12
= 0.125 + 0.171= 0.296W
V
OUT + VF
V f
IN( )
Min tON
=
2
5 1/36
( )
(
)
PBOOST
=
= 0.058W
12
where:
VIN = input voltage
VOUT = output voltage
P =12 0.0015 +5 0.003 = 0.033W
(
)
(
)
Q
Total power dissipation is 0.296 + 0.058 + 0.033 = 0.39W.
VF = Schottky diode forward drop
Thermal resistance for the LT1956 package is influenced
by the presence of internal or backside planes. With a full
plane under the GN16 package, thermal resistance will be
about 85°C/W. No plane will increase resistance to about
95°C/W. To calculate die temperature, use the proper
thermalresistancenumberandaddinworst-caseambient
temperature:
fOSC = switching frequency
A potential controllability problem arises if the LT1956 is
called upon to produce an on time shorter than it is able to
produce. Feedback loop action will lower then reduce the
VC control voltage to the point where some sort of cycle-
skipping or odd/even cycle behavior is exhibited.
In summary:
TJ = TA + θJA (PTOT
)
1. Be aware that the simultaneous requirements of high
VIN, high IOUT and high fOSC may not be achievable in
practice due to internal dissipation. The Thermal Calcu-
lationssectionoffersabasistoestimateinternalpower.
With the GN16 package (θJA = 85°C/W), at an ambient
temperature of 85°C,
TJ = 85 + 85(0.39) = 118°C
18
LT1956/LT1956-5
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APPLICATIO S I FOR ATIO
U
In questionable cases a prototype supply should be
Figure 10 shows the overall loop response with a 1nF VC
capacitor and a typical 100µF tantalum output capacitor.
The response is set by the following terms:
built and exercised to verify acceptable operation.
2. The simultaneous requirements of high VIN, low VOUT
and high current can result in an unacceptably short
minimum switch on time. Cycle skipping and/or odd/
even cycle behavior will result although correct output
voltage is usually maintained.
Error amplifier: DC gain is set by gm and RO = 2000µ •
200k = 400. Pole set by CC and RO = 1/(2π • 200k • 1000p)
= 796Hz. Unity gain set by CC and gm = 2000µ/(2π • CC) =
318kHz.
Power stage: DC gain is set by gm and RL (assume 10Ω)
= 2 • 10 = 20. Pole set by COUT and RL = 1/(2π • 100µ• 10)
= 159Hz. Unity gain set by COUT and gm = 2/(2π • 100µ) =
3.18kHz.
FREQUENCY COMPENSATION
Before starting on the theoretical analysis of frequency
response,thefollowingshouldberemembered—theworse
the board layout, the more difficult the circuit will be to
stabilize. This is true of almost all high frequency analog
circuits, read the Layout Considerations section first.
Common layout errors that appear as stability problems
are distant placement of input decoupling capacitor and/
or catch diode, and connecting the VC compensation to a
ground track carrying significant switch current. In addi-
tion, the theoretical analysis considers only first order
non-ideal component behavior. For these reasons, it is
important that a final stability check is made with produc-
tion layout and components.
Tantalumoutputcapacitor:ZerosetbyCOUT andCOUT ESR
= 1/(2π • 100µ • 0.1) = 15.9kHz.
The zero produced by the ESR of the tantalum output
capacitor is very useful in maintaining stability. If better
transient response is required, a zero can be added to the
loop using a resistor (RC) in series with the compensation
capacitor. As the value of RC is increased, transient re-
sponse will generally improve, but two effects limit its
value. First, the combination of output capacitor ESR and
a large RC may stop loop gain rolling off altogether.
Second, if the loop gain is not rolled sufficiently at the
switching frequency, output ripple will perturb the VC pin
enough to cause unstable duty cycle switching similar to
subharmonic oscillation. This may not be apparent at the
output. Small signal analysis will not show this since a
continuous time system is assumed. If needed, an addi-
tional capacitor (CF) can be added to form a pole at
The LT1956 uses current mode control. This alleviates
many of the phase shift problems associated with the
inductor. The basic regulator loop is shown in Figure 9.
The LT1956 can be considered as two gm blocks, the error
amplifier and the power stage.
LT1956
80
60
180
150
120
90
CURRENT MODE
POWER STAGE
V
SW
FB
OUTPUT
ERROR
g
= 2mho
m
AMPLIFIER
GAIN
R1
R2
–
TANTALUM
ESR
40
g
=
m
PHASE
2000µmho
R
L
R
+
O
20
1.22V
200k
+
C1
GND
V
C
0
60
–20
–40
30
R
C
C
F
0
C
C
10
100
1k
10k
100k
1M
1956 F09
FREQUENCY (Hz)
1956 F10
Figure 10. Overall Loop Response
Figure 9. Model for Loop Response
19
LT1956/LT1956-5
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APPLICATIO S I FOR ATIO
typically one fifth the switching frequency (If RC = ~5k,
With the SHDN pin floating, the LT1956 will consume its
quiescentoperatingcurrentof1.5mA. TheVIN pinwillalso
source current to any other components connected to the
input line. If this load is greater than 10mA or the input
could be shorted to ground, a series Schottky diode must
be added, as shown in Figure 11. With these safeguards,
the output can be held at voltages up to the VIN absolute
maximum rating.
CF = ~320pF)
When checking loop stability, the circuit should be oper-
ated over the application’s full voltage, current and tem-
perature range. Any transient loads should be applied and
the output voltage monitored for a well-damped behavior.
CONVERTER WITH BACKUP OUTPUT REGULATOR
In systems with a primary and backup supply, for ex-
ample, a battery powered device with a wall adapter input,
the output of the LT1956 can be held up by the backup
supply with the LT1956 input disconnected. In this condi-
tion, the SW pin will source current into the VIN pin. If the
SHDN pin is held at ground, only the shut down current of
25µAwillbepulledviatheSWpinfromthesecondsupply.
BUCK CONVERTER WITH ADJUSTABLE SOFT-START
Large capacitive loads or high input voltages can cause
high input currents at start-up. Figure 12 shows a circuit
that limits the dv/dt of the output at start-up, controlling
the capacitor charge rate. The buck converter is a typical
configuration with the addition of R3, R4, CSS and Q1.
1N914
0.1µF
18µH
10MQ060N
54k
BOOST
REMOVABLE
INPUT
V
IN
LT1956 SW
5V, 1A
ALTERNATE
SUPPLY
BIAS
R1
15.4k
SHDN
SYNC GND
FB
+
R2
4.99k
100µF
10V
V
C
25k
2.2µF
1nF
10MQ060N
1956 F11
Figure 11. Dual Source Supply with 25µA Reverse Leakage
D2
1N914
C2
0.1µF
L1
18µH
BOOST
BIAS
SW
OUTPUT
5V
1A
INPUT
25V
V
IN
+
+
R1
15.4k
C3
2.2µF
C1
100µF
D1
LT1956
SHDN
SYNC GND
FB
R2
4.99k
V
C
C
SS
C
R3
2k
C
15nF
Q1
1nF
1766 F12
R4
47k
Figure 12. Buck Converter with Adjustable Soft-Start
20
LT1956/LT1956-5
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APPLICATIO S I FOR ATIO
U
As the output starts to rise, Q1 turns on, regulating switch
current via the VC pin to maintain a constant dv/dt at the
output. Output rise time is controlled by the current
through CSS defined by R4 and Q1’s VBE. Once the output
is in regulation, Q1 turns off and the circuit operates
normally. R3 is transient protection for the base of Q1.
would be a simple flyback winding coupled to the buck
converter if C4 were not present. C4 creates a SEPIC
(single-ended primary inductance converter) topology
which improves regulation and reduces ripple current in
L1. Without C4, the voltage swing on L1B compared to
L1A would vary due to relative loading and coupling
losses. C4 provides a low impedance path to maintain an
equal voltage swing in L1B, improving regulation. In a
flybackconverter,duringswitchontime,alltheconverter’s
energyisstoredinL1Aonly, sincenocurrentflowsinL1B.
At switch off, energy is transferred by magnetic coupling
into L1B, powering the –5V rail. C4 pulls L1B positive
duringswitchontime, causingcurrenttoflow, andenergy
to build in L1B and C4. At switch off, the energy stored in
both L1B and C4 supply the –5V rail. This reduces the
current in L1A and changes L1B current waveform from
square to triangular. For details on this circuit, including
maximum output currents, see Design Note 100.
R4 CSS VOUT
( )( )(
)
RiseTime =
VBE
Using the values shown in Figure 10,
47 •103 15•10–9
5
( )
(
)(
)
Rise Time =
= 5ms
0.7
The ramp is linear and rise times in the order of 100ms are
possible. Since the circuit is voltage controlled, the ramp
rate is unaffected by load characteristics and maximum
outputcurrentisunchanged. Variantsofthiscircuitcanbe
used for sequencing multiple regulator outputs.
POSITIVE-TO-NEGATIVE CONVERTER
DUAL OUTPUT SEPIC CONVERTER
The circuit in Figure 14 is a classic positive-to-negative
topology using a grounded inductor. It differs from the
standard approach in the way the IC chip derives its
feedback signal because the LT1956 accepts only positive
feedback signals. The ground pin must be tied to the
The circuit in Figure 13 generates both positive and
negative 5V outputs with a single piece of magnetics. The
two inductors shown are actually just two windings on a
standard Coiltronics inductor. The topology for the 5V
output is a standard buck converter. The –5V topology
D2
1N914
C2
0.1µF
L1A*
V
BOOST
LT1956
IN
18µH
12V
(TRANSIENTS
TO 60V)
V
OUT
V
IN
SW
FB
5V
R1
15.4k
C3
+
C1
100µF
2.2µF
50V
SHDN
SYNC GND
10V TANT
R2
4.99k
V
C
CERAMIC
D1
C
C
1nF
GND
C4
100µF
10V
+
C5
100µF
10V TANT
* L1 IS A SINGLE CORE WITH TWO WINDINGS
COILTRONICS #CTX33-2P
L1B*
D3
†
IF LOAD CAN GO TO ZERO, AN OPTIONAL
TANT
V
OUT
PRELOAD OF 1k TO 5k MAY BE USED TO
IMPROVE LOAD REGULATION
D1, D3: 10MQ060N
–5V†
1956 F13
Figure 13. Dual Output SEPIC Converter
21
LT1956/LT1956-5
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APPLICATIO S I FOR ATIO
D2
Example: with VIN(MIN) = 5.5V, VOUT = 12V, L = 18µH,
VF = 0.63V, IP = 1.5A: IMAX = 0.37A.
FMMD914
C2
0.1µF
L1*
7µH
OUTPUT DIVIDER
BOOST
V
IN
V
V
SW
IN
12V
The resistor connected to VOUT (R2) should be set to
approximately 5k. R1 is calculated from:
R1
LT1956CGN
C3
+
44.2k
2.2µF
FB
C
50V
GND
V
C
R2(VOUT – 1.22)
+
C1
100µF
16V TANT
R1=
D1
C
1.22
10MQO60N
R2
4.99k
R
C
INDUCTOR VALUE
OUTPUT**
–12V, 0.25A
1956 F14
Unlike buck converters, positive-to-negative converters
cannot use large inductor values to reduce output ripple
voltage. At 500kHz, values larger than 22µH make almost
no change in output ripple. The graph in Figure 15 shows
peak-to-peak output ripple voltage for a 12V to –12V
converter versus inductor value. The criteria for choosing
the inductor is therefore typically based on ensuring that
peak switch current rating is not exceeded. This gives the
lowest value of inductance that can be used, but in some
cases (lower output load currents) it may give a value that
creates unnecessarily high output ripple voltage. A com-
promise value is often chosen that reduces output ripple.
As you can see from the graph, large inductors will not
give arbitrarily low ripple, but small inductors can give
high ripple.
* INCREASE L1 TO 10µH OR 18µH FOR HIGHER CURRENT APPLICATIONS.
SEE APPLICATIONS INFORMATION
** MAXIMUM LOAD CURRENT DEPENDS ON MINIMUM INPUT VOLTAGE
AND INDUCTOR SIZE. SEE APPLICATIONS INFORMATION
Figure 14. Positive-to-Negative Converter
regulated negative output. A resistor divider to the FB pin,
then provides the proper feedback voltage for the chip.
Inverting regulators differ from buck regulators in the
basicswitchingnetwork. Currentisdeliveredtotheoutput
as square waves with a peak-to-peak amplitude much
g
reater than load current. This means that maximum load
current will be significantly less than the LT1956’s 1.5A
maximum switch current, even with large inductor val-
ues. The buck converter in comparison, delivers current
to the output as a triangular wave superimposed on a DC
level equal to load current, and load current can approach
1.5A with large inductors. Output ripple voltage for the
positive- to-negative converter will be much higher than
a buck converter. Ripple current in the output capacitor
will also be much higher. The following equation can be
used to calculate maximum load current for the positive-
to-negative converter:
The difficulty in calculating the minimum inductor size
needed is that you must first know whether the switcher
will be in continuous or discontinuous mode at the critical
270
12V TO –12V CONVERTER
OUTPUT CAPACITOR ESR = 0.1Ω
240
210
180
150
120
90
(V )(VOUT
)
I
= 0.25A
LOAD
IN
IP –
(VOUT)(V – 0.3)
IN
2(VOUT + V )(f)(L)
IN
IMAX
=
(VOUT + V – 0.3)(VOUT + V )
IN
F
60
I
= 0.1A
LOAD
30
IP = Maximum rated switch current
VIN = Minimum input voltage
VOUT = Output voltage
0
6
9
12
15
24
18
21
INDUCTOR SIZE (µH)
1956 F15
VF = Catch diode forward voltage
0.3 = Switch voltage drop at 1.5A
Figure 15. Ripple Voltage on Positive-to-Negative Converter
22
LT1956/LT1956-5
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APPLICATIO S I FOR ATIO
U
point where switch current is 1.5A. The first step is to use
the following formula to calculate the load current where
the switcher must use continuous mode. If your load
current is less than this, use the discontinuous mode
formula to calculate minimum inductor needed. If load
current is higher, use the continuous mode formula.
factor in determining output ripple voltage. Ripple shown
on the graph (Figure 15) is with a capacitor ESR of 0.1Ω.
This is reasonable for an AVX type TPS “D” or “E” size
surface mount solid tantalum capacitor, but the final
capacitor chosen must be looked at carefully for ESR
characteristics.
Output current where continuous mode is needed:
Ripple Current in the Input and Output Capacitors
(V )2(IP)2
Positive-to-negativeconvertershavehighripplecurrentin
both the input and output capacitors. For long capacitor
lifetime, the RMS value of this current must be less than
the high frequency ripple current rating of the capacitor.
The following formula will give an approximate value for
RMS ripple current. This formula assumes continuous
mode and large inductor value. Small inductors will give
somewhat higher ripple current, especially in discontinu-
ous mode. The exact formulas are very complex and
appear in Application Note 44, pages 29 and 30. For our
purposes here I have simply added a fudge factor (ff). The
value for ff is about 1.2 for higher load currents and
L ≥15µH. It increases to about 2.0 for smaller inductors at
lower load currents.
IN
ICONT
=
4(V + VOUT)(V + VOUT + V )
IN
IN
F
Minimum inductor discontinuous mode:
2(VOUT)(IOUT
(f)(IP)2
)
LMIN
=
Minimum inductor continuous mode:
(V )(VOUT
IN
)
LMIN
=
(VOUT + V )
F
2(f)(V + VOUT) IP –IOUT 1+
IN
V
IN
For a 12V to –12V converter using the LT1956 with peak
switch current of 1.5A and a catch diode of 0.63V:
VOUT
Capacitor IRMS = (ff)(IOUT
ff = 1.2 to 2.0
)
(12)2(1.5)2
4(12 +12)(12 +12 + 0.63)
V
IN
ICONT
=
= 0.370A
For a load current of 0.25A, this says that discontinuous
mode can be used and the minimum inductor needed is
found from:
Diode Current
Average diodecurrentisequaltoloadcurrent. Peak diode
current will be considerably higher.
2(12)(0.25)
LMIN
=
= 5.3µH
Peak diode current:
(500 •103)(1.5)2
ContinuousMode =
In practice, the inductor should be increased by about
30% over the calculated minimum to handle losses and
variations in value. This suggests a minimum inductor of
7µH for this application, but looking at the ripple voltage
chartshowsthatoutputripplevoltagecouldbereducedby
a factor of two by using a 18µH inductor. There is no rule
of thumb here to make a final decision. If modest ripple is
needed and the larger inductor does the trick, go for it. If
ripple is noncritical use the smaller inductor. If ripple is
extremely critical, a second filter may have to be added in
any case, and the lower value of inductance can be used.
Keep in mind that the output capacitor is the other critical
(V + VOUT
)
(V )(VOUT)
IN
IN
IOUT
+
V
IN
2(L)(f)(V + VOUT)
IN
2(IOUT)(VOUT
(L)(f)
)
DiscontinuousMode =
Keep in mind that during start-up and output overloads,
average diode current may be much higher than with
normalloads.Careshouldbeusedifdiodesratedlessthan
1A are used, especially if continuous overload conditions
must be tolerated.
23
LT1956/LT1956-5
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
0.189 – 0.196*
(4.801 – 4.978)
0.009
(0.229)
REF
16 15 14 13 12 11 10 9
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1
2
3
4
5
6
7
8
0.015 ± 0.004
(0.38 ± 0.10)
× 45°
0.053 – 0.068
(1.351 – 1.727)
0.004 – 0.0098
(0.102 – 0.249)
0.007 – 0.0098
(0.178 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.0250
(0.635)
BSC
0.008 – 0.012
(0.203 – 0.305)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN16 (SSOP) 1098
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PART NUMBER
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DESCRIPTION
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IN
Operation Up to 25V Input, Synchronizable (LT1375)
External Switches, Low Noise, V Up to 36V
IN
600mA, 1.4MHz Step-Down Switching Regulator
Wide Input Range, High Efficiency, Step-Down Switching Regulator
Wide Input Range, High Efficiency, Step-Down Switching Regulator
1.5A, 1.4MHz Step-Down DC/DC Converter
Wide Input Range, High Efficiency, Step-Down Switching Regulator
Low Noise Buck Regulator
3.6V to 25V V , 6-Lead ThinSOTTM
IN
LT1676
7.4V to 60V Input, 100kHz Operation, 700mA Internal Switch
5.5V to 60V Input, 200kHz Operation, 1.5A Internal Switch
High Current, 8-Lead MSOP Package
LT1766
LT1767
LT1776
7.4V to 60V Input, 200kHz Operation, 700mA Internal Switch
LT1777
Operation Up to 48V, Controlled Voltage
and Current Slew Rates
ThinSOT is a trademark of Linear Technology Corporation.
1956i LT/TP 0601 1.5K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2001
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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