LT1952_技术文档

LT1952

Single Switch Synchronous

Forward Controller

U

DESCRIPTIO

FEATURES

■

Synchronous Rectifier Control for High Efficiency

The LT^®1952 is a current mode PWM controller optimized

to control the forward converter topology, using one

primary MOSFET. The LT1952 provides synchronous

rectifier control, resulting in extremely high efficiency. A

programmable Volt-Second clamp provides a safeguard

for transformer reset that prevents saturation. This allows

a single MOSFET on the primary side to reliably run at

greater than 50% duty cycle for high MOSFET, trans-

former and rectifier utilization. The LT1952 includes

soft-start for controlled exit from shutdown, overcurrent

conditions and undervoltage lockout. A precision 100mV

current limit threshold, independent of duty cycle, com-

bineswithsoft-starttoprovidehiccupshortcircuitprotec-

tion. Micropower start-up allows the LT1952 to be effi-

ciently started from high input voltages. Programmable

slope compensation and leading edge blanking allow

optimization of loop bandwidth with a wide range of

inductorsandMOSFETs. TheLT1952canbeprogrammed

over a 100kHz to 500kHz frequency range and the part can

be synchronized to an external clock. The error amplifier

is a true op amp, allowing a wide range of compensation

networks. The LT1952 is available in a small 16-pin SSOP

■

Programmable Volt-Second Clamp

■

Output Power Levels from 25W to 500W

■

Low Current Start-Up

True PWM Soft-Start

■

Low Stress Short Circuit Protection

■

Precision 100mV Current Limit Threshold

■

Adjustable Delay for Synchronous Timing

■

Accurate Shutdown Threshold with Programmable

Hysteresis

■

Programmable Slope Compensation

■

Programmable Leading Edge Blanking

■

Programmable Frequency (100kHz to 500kHz)

■

Synchronizable to an External Clock up to 1.5 • f_OSC

■

Internal 1.23V Reference

■

2.5V External Reference

■

Current Mode Control

■

Small 16-Pin SSOP Package

U

APPLICATIO S

■

Telecommunications Power Supplies

Industrial and Distributed Power

Isolated and Non-Isolated DC/DC Converters

■

package.

■

, LTC and LT are registered trademarks of Linear Technology Corporation.

U

TYPICAL APPLICATIO

36V to 72V Input, 12V at 20A Semi-Regulated Bus Converter

L1

12V Bus Converter

V_OUTvs V_IN

T1

PA0905

V

IN

PA1494.242

V

12V

20A

OUT

SUPPLY FROM BIAS

WINDING OF T1

16

14

12

10

8

10µF

47µF

16V

X5R

×2

V

IN

REF

52.3k

100k

Si7370

×2

PH4840

COMP

×2

Si7450

SS_MAXDC

OUT

OC

V

IN

340k

LT1952

I

0.005Ω

SENSE

SD_V

FB

SEC

LTC3900

FG

CG

13k

T2

SYNC

GND

SOUT

SYNC

560Ω

R

220pF

OSC

36

48

54

(V)

60

66

72

42

PGND BLANK DELAY

40k 40k

V

IN

0.1µF

1952 TA01b

178k

1952 TA01

1952f

1

LT1952

W W U W

U

W

U

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

(Note 1)

ORDER PART

TOP VIEW

V_IN(Note 8) ............................................... –0.3V to 25V

NUMBER

COMP

FB

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

SOUT

SYNC, SS_MAXDC, SD_V_SEC, I_SENSE

,

V

IN

OC, COMP, BLANK, DELAY ......................... –0.3V to 6V

FB ................................................................ –0.3V to 3V

R_OSC...................................................................................... –50µA

LT1952EGN

LT1952IGN

R

OSC

OUT

SYNC

PGND

DELAY

OC

SS_MAXDC

V

_REF.................................................................... –10mA

V

REF

GN PART

MARKING

Operating Junction Temperature Range

SD_V

SEC

I

SENSE

(Notes 2, 5) ....................................... –40°C to 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

GND

BLANK

1952E

1952I

GN PACKAGE

16-LEAD PLASTIC SSOP

T_JMAX= 125°C, θ_JA= 110°C/W, θ_JC= 40°C/W

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. COMP = open, FB = 1.4V, R_OSC= 178k, SYNC = 0V, SS_MAXDC = V_REF, V_REF

= 0.1µF, SD_V_SEC= 2V, BLANK = 40k, DELAY = 40k, I_SENSE= 0V, OC = 0V, OUT = 1nF, V_IN= 15V, SOUT = open, unless otherwise specified.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

PWM CONTROLLER

Operational Input Voltage

I

= 0µA

●

V

25

6.5

V

mA

µA

V

(VREF)

IN OFF

V

Quiescent Current

Startup Current

= 0µA, FB = 0V, I

= OC = Open

SENSE

5.2

460

240

1.32

0

IN

FB = 0V, SS_MAXDC = 0V (Notes 4, 9)

SD_V = 0V

700

350

1.379

Shutdown Current

SEC

SD_V

Threshold

10V < V < 25V

1.261

SEC

IN

Current

SD_V

= SD_V

Threshold + 100mV

Threshold – 100mV

µA

V

SEC (ON)

SEC (OFF)

SEC

9.5

12.75

8.0

11.2

14.25

8.75

5.5

12.9

15.75

9.25

V

●

IN ON

IN OFF

V

3.75

6.75

V

IN HYSTERESIS

REF

Output Voltage

Line Regulation

Load Regulation

OSCILLATOR

I

= 0µA

●

2.425

2.5

1

2.575

10

V

mV

(VREF)

= 0µA, 10V < V < 25V

IN

0µA < I

< 2.5mA

1

10

(VREF)

Frequency: f

R

OSC

= 178k, FB = 1V

●

165

200

240

kHz

OSC

Minimum Programmable f

Maximum Programmable f

R

OSC

R

OSC

= 365k

80

440

100

500

120

560

kHz

OSC

= 64.9k, COMP = 2.5V, SD_V

= 2.64V

OSC

SEC

SYNC Input Resistance

18

kΩ

SYNC Switching Threshold

FB = 1V

1.5

2.2

1.5

V

SYNC Frequency/f

FB = 1V (Note 7)

1.25

0.05

OSC

f

Line Reg

FB = 1V, R

= 178k; 10V < V < 25V,

0.33

%/V

OSC

IN

SS_MAXDC = 1.84V

V

R

OSC

Pin voltage

1

V

ROSC

1952f

2

LT1952

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. COMP = open, FB = 1.4V, R_OSC= 178k, SYNC = 0V, SS_MAXDC = V_REF

,

V_REF= 0.1µF, SD_V_SEC= 2V, BLANK = 40k, DELAY = 40k, I_SENSE= 0V, OC = 0V, OUT = 1nF, V_IN= 15V, SOUT = open, unless otherwise

specified.

PARAMETER

CONDITIONS

MIN

1.201

65

TYP

MAX

UNITS

ERROR AMPLIFIER

FB Reference Voltage

FB Input Bias Current

Open Loop Voltage Gain

Unity Gain Bandwidth

COMP Source Current

COMP Sink Current

COMP Current (Disabled)

10V < V < 25V, V + 0.2V < COMP < V – 0.2

●

1.226

–75

85

1.250

–200

V

nA

dB

MHz

mA

µA

V

IN

OL

OH

FB = FB Reference Voltage

+ 0.2V < COMP < V – 0.2

V

OL

OH

(Note 6)

3

FB = 1V, COMP = 1.6V

COMP = 1.6V

–4

4

–9

10

FB = V , COMP = 1.6V

18

2.7

0.7

23

28

REF

COMP High Level: V

FB = 1V, I

= –250µA

3.2

1.0

0.15

OH

(COMP)

COMP Active Threshold

FB = 1V, SOUT Duty Cycle > 0 %

= 250µA

V

COMP Low Level: V

I

0.4

V

OL

(COMP)

CURRENT SENSE

I

Maximum Threshold

COMP = 2.5V, FB = 1V

197

98

220

243

mV

SENSE

I

Input Current (Duty Cycle = 0%)

Input Current (Duty Cycle = 80%)

COMP = 2.5V, FB = 1V (Note 4)

–8

–35

µA

SENSE

OC Threshold

●

107

–50

180

540

1

116

mV

nA

ns

V

OC Input Current

(OC = 100mV)

–100

Default Blanking Time

Adjustable Blanking Time

COMP = 2.5V, FB = 1V (Note 10)

COMP = 2.5V, FB = 1V, R

= 120k

BLANK

V

BLANK

SOUT DRIVER

SOUT Clamp Voltage

SOUT Low Level

SOUT High Level

I

= 0µA, COMP = 2.5V, FB = 1V

10.5

12

13.5

0.75

V

(GATE)

= 25mA

0.5

= –25mA, V = 12V, COMP = 2.5V,

10

1

IN

FB = 1V

SOUT Active Pull-Off in Shutdown

V

= 5V, SD_V

= 0V, SOUT = 1V

SEC

mA

IN

SOUT to OUT (Rise) DELAY (t

)

COMP = 2.5V, FB = 1V (Note 10)

= 120k

40

120

ns

DELAY

R

DELAY

V

0.9

V

DELAY

OUT DRIVER

OUT Rise Time

OUT Fall Time

OUT Clamp Voltage

OUT Low Level

FB = 1V, CL = 1nF (Notes 3, 6)

50

30

13

ns

V

I

= 0µA, COMP = 2.5V, FB = 1V

11.5

14.5

(GATE)

I

= 20mA

= 200mA

0.45

1.25

0.75

1.8

V

(GATE)

OUT High Level

I

= –20mA, V = 12V, COMP = 2.5V,

9.9

V

(GATE)

IN

FB = 1V

= –200mA, V = 12V, COMP = 2.5V,

I

9.75

V

(GATE)

IN

FB = 1V

OUT Active Pull-Off in Shutdown

V

= 5V, SD_V

= 0V, OUT = 1V

SEC

20

mA

1952f

3

IN

LT1952

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. COMP = open, FB = 1.4V, R_OSC= 178k, SYNC = 0V, SS_MAXDC = V_REF

,

V_REF= 0.1µF, SD_V_SEC= 2V, BLANK = 40k, DELAY = 40k, I_SENSE= 0V, OC = 0V, OUT = 1nF, V_IN= 15V, SOUT = open, unless otherwise

specified.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

OUT Max Duty Cycle

COMP = 2.5V, FB = 1V, R

= 10k

DELAY

(f

OSC

= 200kHz)

SD_V

= 1.4V, SS_MAXDC = V

83

90

%

SEC

REF

OUT Max Duty Cycle Clamp

COMP = 2.5V, FB = 1V, R

= 10k

DELAY

(f

OSC

= 200kHz)

SD_V

= 1.32V, SS_MAXDC = 1.84V

= 2.64V, SS_MAXDC = 1.84V

63.5

25

72

33

80.5

41

%

SEC

SOFT-START

SS_MAXDC Low Level: V

I

= 150µA, OC = 1V

0.2

0.45

0.8

V

OL

(SS_MAXDC)

SS_MAXDC Soft-Start Reset Threshold

SS_MAXDC Active Threshold

Measured on SS_MAXDC

FB = 1V, DC > 0%

V

SS_MAXDC Input Current (Soft-Start Pulldown: Idis)

SS_MAXDC = 1V, SD_V

= 1.4V, OC = 1V

800

µA

SEC

temperature will exceed 125°C when over-temperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

Note 6: Guaranteed but not tested.

Note 7: Maximum recommended SYNC frequency = 500kHz.

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: The LT1952EGN is guaranteed to meet performance specifications

from 0°C to 125°C junction temperature. Specifications over the –40°C to

125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LT1952IGN is guaranteed over the full –40°C to 125°C operating junction

temperature range.

Note 8: In applications where the V pin is supplied via an external RC

IN

network from a SYSTEM V > 25V, an external zener with clamp voltage

IN

V

< V < 25V should be connected from the V pin to ground.

IN ON(MAX)

Z

I

N

Note 3: Rise and Fall times are measured at 10% and 90% levels.

Note 4: Guaranteed by correlation to static test.

Note 9: V start-up current is measured at V = V – 0.25V and

IN

IN ON

scaled by x 1.18 (to correlate to worst case V start-up current at V

).

IN

IN ON

Note 5: This IC includes over-temperature protection that is intended to

protect the device during momentary overload conditions. Junction

Note 10: Timing for R = 40k derived from measurement with R = 240k.

1952f

4

LT1952

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Switching Frequency vs

Temperature

V_INShutdown Current vs

Temperature

FB Voltage vs Temperature

245

230

215

200

185

170

155

500

450

400

350

300

250

200

150

100

1.25

1.24

1.23

1.22

1.21

1.20

V

= 15V

SEC

IN

SD_V

= 0V

–50

0

25

50

75 100 125

–50

0

25

50

75 100 125

–50

0

25

50

75 100 125

–25

TEMPERATURE (°C)

1952 G02

1952 G03

1952 G01

V_INStart-up Current vs

Temperature

SD_V_SECTurn ON Threshold vs

Temperature

V_INI_Qvs Temperature

600

550

500

450

400

350

300

250

200

1.42

1.37

1.32

1.27

1.22

6.5

6.0

5.5

5.0

4.5

4.0

3.5

SD_V

SEC

= 1.4V

OC = OPEN

–50

0

25

50

75 100 125

–50

0

25

50

75 100 125

–25

50

TEMPERATURE (°C)

125

–25

–50

0

25

75 100

–25

TEMPERATURE (°C)

1952 G04

1952 G06

1952 G05

SD_V_SECPin Current vs

Temperature

V_INTurn ON/OFF Voltage vs

Temperature

COMP Active Threshold vs

Temperature

15

10

5

18

16

14

12

10

8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

R

= 0k

ISENSE

PIN CURRENT BEFORE

PART TURN ON

V

TURN ON VOLTAGE

IN

V

TURN OFF VOLTAGE

IN

0µA PIN CURRENT AFTER

PART TURN ON

0

6

–50

0

25

50

75 100 125

–50

0

25

50

75 100 125

–50

0

25

50

75 100 125

–25

TEMPERATURE (°C)

1952 G07

1952 G08

1952 G09

1952f

5

LT1952

U W

TYPICAL PERFOR A CE CHARACTERISTICS

COMP Source Current vs

Temperature

COMP Sink Current vs

Temperature

(Disabled) COMP Pin Current vs

Temperature

12.5

10.0

7.5

50

40

30

20

10

0

12.5

10.0

7.5

FB = 1.4V

COMP = 1.6V

FB = V

REF

COMP = 1.6V

FB = 1V

COMP = 1.6V

CURRENT OUT OF PIN

5.0

–50

0

25

50

75 100 125

–50

0

25

50

75 100 125

50

75 100 125

–25

–50

0

25

–25

TEMPERATURE (°C)

1952 G11

1952 G12

1952 G10

I_SENSEMaximum Threshold vs

COMP

I_SENSEMaximum Threshold vs

Temperature

I_SENSEPin Current (Out of Pin) vs

Duty Cycle

240

230

220

210

200

40

30

20

10

0

240

200

160

120

80

COMP = 2.5V

T = 25°C

A

T

= 25°C

ISENSE

A

R

= 0k

R

= 0k

ISENSE

OC THRESHOLD

40

0

–50

0

25

50

75 100 125

0

20 30 40 50 60 70 80 90 100

10

0

1.0

1.5

2.0

2.5

3.0

–25

0.5

TEMPERATURE (°C)

DUTY CYCLE (%)

COMP (V)

1952 G14

1952 G15

1952 G13

I_SENSEMaximum Threshold vs

Duty Cycle (Programming Slope

Compensation)

OC (Over-Current) Threshold vs

Temperature

Blank Duration vs Temperature

225

215

205

195

185

175

120

110

100

90

800

600

400

200

0

PRECISION OVER-CURRENT THRESHOLD

INDEPENDENT OF DUTY CYCLE

R

= 0Ω

SLOPE

R

= 120k

BLANK

R

= 470Ω

R

= 40k

50

BLANK

25

R

SLOPE

= 1k

T

= 25°C

A

COMP = 2.5V

80

0

20 30 40 50 60 70 80 90 100

DUTY CYCLE (%)

–50

0

25

50

75 100 125

–50

0

75 100 125

10

–25

TEMPERATURE (°C)

1952 G16

1952 G17

1952 G18

1952f

6

LT1952

U W

TYPICAL PERFOR A CE CHARACTERISTICS

t_DELAY: SOUT Rise to OUT Rise vs

Temperature

t_DELAY: SOUT Rise to OUT Rise vs

R_DELAY

BLANK Duration vs R_BLANK

1000

800

600

400

200

0

200

160

120

80

200

150

100

50

T

= 25°C

T

= 25°C

A

R

= 120k

DELAY

40

= 40k

50

DELAY

25

0

40 60 80 100 120 140 160

(k)

0

40 60 80 100 120 140 160

(k)

20

–50

0

75 100 125

–25

R

DELAY

TEMPERATURE (°C)

BLANK

1952 G26

1952 G27

1952 G19

OUT Rise/Fall Time vs OUT Load

Capacitance

OUT: Max Duty Cycle CLAMP vs

SD_V_SEC

OUT: Max Duty Cycle vs f_OSC

125

100

75

50

25

0

100

90

80

70

60

50

40

30

20

10

0

T

= 25°C

A

t

r

t

f

80

T

= 25°C

A

T

= 25°C

SS_MAXDC = 1.84V

A

SS_MAXDC = 2.5V

f

= 200kHz

= 10k

OSC

SD_V

= 1.4V

R

SEC

DELAY

70

0

1000

2000

3000

4000

5000

100

200

300

(kHz)

400

500

1.32

1.65

1.98

SD_V

2.31

2.64

OUT LOAD CAPACITANCE (pF)

f

(V)

OSC

SEC

1952 G20

1952 G21

1952 G22

SS_MAXDC Setting vs f_OSC

(for OUT DC = 72%)

OUT: Max Duty Cycle CLAMP vs

SS_MAXDC

SS_MAXDC Reset and Active

Thresholds vs Temperature

1.2

1.0

0.8

0.6

0.4

0.2

0

90

80

70

60

50

40

30

20

2.32

2.20

2.08

1.96

1.84

1.72

1.60

T

OSC

R

= 25°C

T

= 25°C

A

f

= 200kHz

= 10k

SD_V

R

= 1.32V

SEC

= 10k

DELAY

ACTIVE THRESHOLD

SD_V

= 1.32V

SEC

SD_V

= 1.98V

= 2.64V

SEC

RESET THRESHOLD

SEC

–50

0

25

50

75 100 125

1.60

1.84

SS_MAXDC (V)

2.08

100

200

300

(kHz)

400

500

–25

TEMPERATURE (°C)

f

OSC

1952 G25

1952 G23

1952 G24

1952f

7

LT1952

U

PI FU CTIO S

COMP (Pin 1): Output Pin of the Error Amplifier. The error

amplifier is an op amp, allowing various compensation

networks to be connected between the COMP pin and FB

pin for optimum transient response. The voltage on this

pin corresponds to the peak current of the external FET.

Full operating voltage range is between 0.8V and 2.5V

corresponding to 0mV to 220mV at the I_SENSEpin. For

applications using the 100mV OC pin for over-current

detection,typicaloperatingrangefortheCOMPpinis0.8V

to 1.6V. For isolated applications where COMP is con-

trolled by an opto-coupler, the COMP pin output drive can

bedisabledwithFB=V_REF, reducingtheCOMPpincurrent

to (COMP – 0.7)/40k.

Volt-Second clamp on the OUT pin. A 10µA pin current

hysteresis allows external programming of UVLO

hysteresis.

GND (Pin 8): Analog Ground.

BLANK (Pin 9): A resistor to ground adjusts the extended

blanking period of the over-current and current sense

amplifier outputs during FET turn on — to prevent false

current limit trip. Increasing the resistor value increases

the blanking period.

I

_SENSE(Pin 10): The Current Sense Input for the Control

Loop. Connect this pin to the sense resistor in the source

oftheexternalpowerMOSFET. Aresistorinserieswiththe

I_SENSEpin programs slope compensation.

FB (Pin 2): Monitors the output voltage via an external

resistor divider and is compared with an internal 1.23V

reference by the error amplifier. FB connected to V_REF

disables error amplifier output.

OC (Pin 11): An accurate 100mV threshold, independent

of duty cycle, for over-current detection and trigger of

soft-start. Connect this pin directly to the sense resistor in

the source of the external power MOSFET.

R_OSC(Pin 3): A resistor to ground programs the operating

frequency of the IC between 100kHz and 500kHz. Nominal

voltage on the R_OSCpin is 1.0V.

DELAY (Pin 12): A resistor to ground adjusts the delay

period between SOUT rising edge and OUT rising edge.

Used to maximize efficiency in forward converter applica-

tions by adjusting the control timing of secondary side

synchronous rectifier MOSFETs. Increasing the resistor

value increases the delay period.

SYNC (Pin 4): Used to Synchronize the Internal Oscillator

toanExternalSignal.Itisdirectlylogiccompatibleandcan

be driven with any signal between 10% and 90% duty

cycle. If unused, the pin can be left open or connected to

ground.

PGND (Pin 13): Power Ground.

SS_MAXDC (Pin 5): External resistor divider from V_REF

sets maximum duty cycle clamp (SS_MAXDC = 1.84V,

SD_V_SEC= 1.32V gives 72% duty cycle). Capacitor on

SS_MAXDC pin in combination with external resistor

divider sets soft-start timing.

OUT (Pin 14): Drives the Gate of an N-channel MOSFET

between 0V and V_IN. OUT is actively clamped to 13V.

Active pull-off exists in shutdown (see electrical

specification).

VIN (Pin 15): Input Supply for the Part. It must be closely

decoupled to ground. An internal undervoltage lockout

threshold exists for V_INat approximately 14.25V on and

8.75V off.

V_REF(Pin 6): The output of an internal 2.5V reference

which supplies control circuitry in the IC. Capable of

sourcing up to 2.5mA drive for external use. Bypass to

ground with a 0.1µF ceramic capacitor.

SOUT (Pin 16): Switched Output in Phase with OUT Pin.

Provides sync signal for control of secondary side FETs in

forward converter applications requiring highly efficient

synchronous rectification. SOUT is actively clamped to

12V. Active pull-off exists in shutdown (see electrical

specification).

SD_V_SEC(Pin 7): The SD_V_SECpin, when pulled below its

accurate 1.32V threshold, is used to turn off the IC and

reduce current drain from V_IN.The SD_V_SECpin is con-

nected to system input voltage through a resistor divider

to define undervoltage lockout (UVLO) and to provide a

1952f

8

LT1952

W U

W

TI I G DIAGRA

t : PROGRAMMABLE SYNCHRONOUS DELAY

DELAY

SOUT

OUT

SS_MAXDC

FAULTS TRIGGERING SOFT-START

< 8.75V

V

IN

OR

SD_V

OR

0.8V (ACTIVE THRESHOLD)

< 1.32V (UVLO)

SEC

0.45V (RESET THRESHOLD)

0.2V

OC > 100mV (OVER-CURRENT)

SOFT-START LATCH RESET:

> 14.25V (> 8.75V IF LATCH SET BY OC)

SOFT-START

LATCH SET

V

IN

AND

SD_V

AND

> 1.32V

SEC

OC < 100mV

AND

SS_MAXDC < 0.45V

1952 F01

Figure 1. Timing Diagram

W

BLOCK DIAGRA

V

SS_MAXDC

5

IN

REF

6

15

460µA START-UP

INPUT CURRENT

14.25V ON

8.75V OFF

V

REF

0.45V

+

–

>90%

SOFT-START CONTROL

+

–

2.5V

R

S

SOURCE

2.5mA

Q

–

+

±50mA

1.23V

ADAPTIVE

MAXIMUM

DUTY CYCLE

CLAMP

16

SOUT

–

+

12V

I

HYST

11µA SD_V

= 1.32V

SEC

> 1.32V

0µA SD_V

SEC

+

–

(TYPICAL 200kHz)

OSC

ON

DELAY

DRIVER

±1A

SD_V

R

7

3

S

R

Q

SEC

14

OUT

1.32V

(LINEAR)

OSC

(100 TO 500)kHz

SLOPE COMP

8µA 0% DC

RAMP

13 PGND

35µA 80% DC

SYNC

4

13V

BLANK

(VOLTAGE)

ERROR AMPLIFIER

+

–

1.23V

SENSE

OVER

CURRENT

–

+

–

+

11

10

OC

0mV TO 220mV

100mV

I

SENSE

2

1

8

9

12

1952 BD

FB

COMP

GND

BLANK

DELAY

Figure 2. Block Diagram

1952f

9

LT1952

U

OPERATIO

Introduction

For SOUT and OUT turn on, a PWM latch is set at the start

of each main oscillator cycle. OUT turn on is delayed from

SOUT turn on by a time t_DELAY(Figure 2). t_DELAYis

programmed using a resistor from the DELAY pin to

ground and is used to set the timing control of the

secondary synchronous rectifiers for optimum efficiency.

TheLT1952isacurrentmodesynchronousPWMcontrol-

ler optimized for control of the simplest forward converter

topology — using only one primary MOSFET. The LT1952

is ideal for 25W to 500W power systems where very high

efficiency and reliability, low complexity and cost are

required in a small space. Key features of the LT1952

include an adaptive maximum duty cycle clamp for the

single primary MOSFET. An additional output signal is

included for synchronous rectifier control. A precision

100mV threshold senses over-current conditions and

triggers Soft-Start for low stress short circuit protection

and control. The key functions of the LT1952 are shown in

the Block Diagram in Figure 2.

SOUT and OUT turn off at the same time each cycle by one

of three methods:

(1) MOSFET peak current sense at I_SENSEpin

(2) Adaptive maximum duty cycle clamp reached during

load/line transients

(3) Maximum duty cycle reset of the PWM latch

During any of the following conditions — low V_IN, low

SD_V_SECor over-current detection at the OC pin — a

soft-start event is latched and both SOUT and OUT turn off

immediately (Figure 1).

Part Startup

In normal operation the SD_V_SECpin must exceed 1.32V

and the V_INpin must exceed 14.25V to allow the part to

turn on. This combination of pin voltages allows the 2.5V

V_REFpin to become active, supplying the LT1952 control

circuitryandprovidingupto2.5mAexternaldrive.SD_V_SEC

threshold can be used for externally programming an

undervoltage lockout (UVLO) threshold on the system

input voltage. Hysteresis on the UVLO threshold can also

be programmed since the SD_V_SECpin draws 11µA just

before part turn on and 0µA after part turn on.

Leading Edge Blanking

To prevent MOSFET switching noise causing premature

turn off of SOUT or OUT, programmable leading edge

blanking exists. This means both the current sense com-

parator and over-current comparator outputs are ignored

during MOSFET turn on and for an extended period after

the OUT leading edge (Figure 6). The extended blanking

period is programmable by adjusting a resistor from the

BLANK pin to ground.

With the LT1952 turned on, the V_INpin can drop as low as

8.75V before part shutdown occurs. This V_INpin hyster-

esis (5.5V) combined with low 460µA start-up input

current allows low power start-up using a resistor/capaci-

tor network from system V_INto supply the V_INpin (Figure

3). The V_INcapacitor value is chosen to prevent V_INfalling

below 8.75V before an auxiliary winding in the converter

takes over supply to the V_INpin.

Adaptive Maximum Duty Cycle Clamp

(Volt-Second Clamp)

For forward converter applications using the simplest

topology of a single MOSFET on the primary, a maximum

switchdutycycleclampwhichadaptstotransformerinput

voltage is necessary for reliable control of the MOSFET.

This volt-second clamp provides a safeguard for trans-

former reset that prevents transformer saturation. Instan-

taneous load changes can cause the converter loop to

demand maximum duty cycle. If the maximum duty cycle

oftheswitchistoogreat,thetransformerresetvoltagecan

exceedthevoltageratingoftheprimary-sideMOSFETwith

catastrophicdamage.Manyconverterssolvethisproblem

Output Drivers

TheLT1952hastwooutputs, SOUTandOUT. TheOUTpin

provides a ±1A peak MOSFET gate drive clamped to 13V.

TheSOUTpinhasa±50mApeakdriveclampedto12Vand

provides sync signal timing for synchronous rectification

control.

1952f

10

LT1952

U

OPERATIO

by limiting the operational duty cycle of the MOSFET to

50% or less — or by using a fixed (non-adaptive) maxi-

mum duty cycle clamp with very large voltage rated

MOSFETs. The LT1952 provides a volt-second clamp to

allow MOSFET duty cycles well above 50%. This gives

greater power utilization for the MOSFET, rectifiers and

transformer resulting in less space for a given power

output. In addition, the volt-second clamp allows a re-

duced voltage rating on the MOSFET resulting in lower

RDS_ONfor greater efficiency. The volt-second clamp de-

fines a maximum duty cycle ‘guard rail’ which falls when

system input voltage increases.

A soft-start event is triggered whenever V_INis too low,

SD_V_SECis too low (UVLO), or a 100mV over-current

threshold at OC pin is exceeded. Whenever a soft-start

event is triggered, switching at SOUT and OUT is stopped

immediately.

The SS_MAXDC pin is discharged and only released for

charging when it has fallen below it’s reset threshold of

0.45V and all faults have been removed. Increasing volt-

ageontheSS_MAXDCpinabove0.8Vwillincreaseswitch

maximum duty cycle. A capacitor to ground on the

SS_MAXDC pin in combination with a resistor divider

from V_REF, defines the soft-start timing.

The LT1952 SD_V_SECand SS_MAXDC pins provide a

capacitorless,programmablevolt-secondclampsolution.

Some controllers with volt-second clamps control switch

maximum duty cycle by using an external capacitor to

programmaximumswitchONtime.Suchtechniqueshave

a volt-second clamp inaccuracy directly related to the

error of the external capacitor/pin capacitance and the

error/drift of the internal oscillator. The LT1952 uses

simple resistor ratios to implement a volt-second clamp

without the need for an accurate external capacitor and

with an order of magnitude less dependency on oscillator

error.

Current Mode Topology (I_SENSEPin)

TheLT1952currentmodetopologyeasesfrequencycom-

pensationrequirementsbecausetheoutputinductordoes

not contribute to phase delay in the regulator loop. This

current mode technique means that the error amplifier

(nonisolated applications) or the optocoupler (isolated

applications) commands current (rather than voltage) to

be delivered to the output. This makes frequency compen-

sation easier and provides faster loop response to output

load transients.

A resistor divider from the application’s output voltage

generates a voltage at the inverting FB input of the LT1952

error amplifier (or to the input of an external optocoupler)

and is compared to an accurate reference (1.23V for

LT1952). The error amplifier output (COMP) defines the

input threshold (I_SENSE) of the current sense comparator.

COMP voltages between 0.8V (active threshold) and 2.5V

define a maximum I_SENSEthreshold from 0mV to 220mV.

By connecting I_SENSEto a sense resistor in series with the

source of an external power MOSFET, the MOSFET peak

current trip point (turn off) can be controlled by COMP

level and hence by the output voltage. An increase in

output load current causing the output voltage to fall, will

cause COMP to rise, increasing I_SENSEthreshold, increas-

ing the current delivered to the output. For isolated appli-

cations, the error amplifier COMP output can be disabled

to allow the optocoupler to take control. Setting FB = V_REF

disables the error amplifier COMP output, reducing pin

current to (COMP – 0.7)/40k.

An increase of voltage at the SD_V_SECpin causes the

maximum duty cycle clamp to decrease. If SD_V_SECis

resistively divided down from transformer input voltage, a

volt-second clamp is realised. To adjust the initial maxi-

mum duty cycle clamp, the SS_MAXDC pin voltage is

programmed by a resistor divider from the 2.5V V_REFpin

to ground. An increase of programmed voltage on

SS_MAXDC pin provides an increase of switch maximum

duty cycle clamp.

Soft-Start

The LT1952 provides true PWM soft-start by using the

SS_MAXDC pin to control soft-start timing. The propor-

tionalrelationshipbetweenSS_MAXDCvoltageandswitch

maximum duty cycle clamp allows the SS_MAXDC pin to

slowly ramp output voltage by ramping the maximum

switch duty cycle clamp — until switch duty cycle clamp

seamlessly meets the natural duty cycle of the converter.

1952f

11

LT1952

U

OPERATIO

is connected directly to the source of the primary side

MOSFET to monitor peak current in the MOSFET

(Figure 7). The 100mV threshold is constant over the

entire duty cycle range of the converter because it is

unaffected by the slope compensation added to the

Slope Compensation

The current mode architecture requires slope compensa-

tion to be added to the current sensing loop to prevent

subharmonic oscillations which can occur for duty cycles

above 50%. Unlike most current mode converters which

have a slope compensation ramp that is fixed internally,

placing a constraint on inductor value and operating

frequency, the LT1952 has externally adjustable slope

compensation. Slope compensation can be programmed

byinsertinganexternalresistor(R_SLOPE)inserieswiththe

I_SENSEpin. The LT1952 has a linear slope compensation

ramp which sources current out of the I_SENSEpin of

approximately 8µA at 0% duty cycle to 35µA at 80% duty

cycle.

I_SENSEpin.

Synchronizing

A SYNC pin allows the LT1952 oscillator to be synchro-

nized to an external clock. The SYNC pin can be driven

from a logic level output, requiring less than 0.8V for a

logic level low and greater than 2.2V for a logic level high.

Duty cycle should run between 10% and 90%. To avoid

loss of slope compensation during synchronization, the

free running oscillator frequency (f_OSC) should be pro-

grammed to 80% of the external clock frequency (f_SYNC).

The R_SLOPEresistor chosen for non-synchronized opera-

tion should be increased by 1.25x (= f_SYNC/f_OSC).

Over-Current Detection and Soft-Start (OC Pin)

An added feature to the LT1952 is a precise 100mV sense

threshold at the OC pin used to detect over-current condi-

tions in the converter and set a soft-start latch. The OC pin

U

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APPLICATIO S I FOR ATIO

SYSTEM

Shutdown and Programming Undervoltage Lockout

INPUT (V )

S

The LT1952 has an accurate 1.32V shutdown threshold at

the SD_V_SECpin. This threshold can be used in conjunc-

tion with a resistor divider to define the undervoltage

lockout threshold (UVLO) of the system input voltage (V_S)

to the power converter (Figure 3). A pin current hysteresis

(11µA before part turn on, 0µA after part turn on) allows

UVLO hysteresis to be programmed. Calculation of the

ON/OFF thresholds for the supply (SV_IN) to the power

converter can be made as follows:

R1

R2

SD_V

SEC

–

+

OPTIONAL

SHUTDOWN

TRANSISTOR

11µA

1.32V

ON OFF

LT1952

1952 F03

V_{S OFF}Threshold = 1.32[1 + (R1/R2)]

Figure 3. Programming Undervoltage Lockout (UVLO)

V_{S ON}Threshold = SV_{IN OFF}+ (11µA • R1)

Micropower Start-Up: Selection of Start-Up Resistor

and Capacitor for V_IN

A simple open drain transistor can be added to the resistor

divider network at the SD_V_SECpin to control the turn off

of the LT1952 (Figure 3).

The LT1952 uses turn-on voltage hysteresis at the V_INpin

and low start-up current to allow micro-power start-up

(Figure 4). The LT1952 monitors V_INpin voltage to allow

partturnonat14.25Vandpartturnoffat8.75V. Lowstart-

up current (460µA) allows a large resistor to be connected

1952f

The SD_V_SECpin must not be left open since there must

be an external source current >11µA to lift the pin past its

1.32V threshold for part turn on.

12

LT1952

U

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APPLICATIO S I FOR ATIO

between system input supply and V_IN. Once the part is V_IN,possiblyexceedingtheratingfortheV_INpin.Thezener

turned on, input current increases to drive the IC (4.5mA) voltage should obey V_{IN ON(MAX)}< V_Z< 25V.

and the output drivers (I_DRIVE). A large enough capacitor

Programming Oscillator Frequency

is chosen at the V_INpin to prevent V_INfalling below 8.5V

before an auxiliary winding in the converter takes over

supply to V_IN. This technique allows a simple resistor/

capacitor for start-up which draws low power from the

system supply to the converter. The values for R_STARTand

The oscillator frequency (f_OSC) of the LT1952 is pro-

grammed using an external resistor (R_OSC) connected

between the R_OSCpin and ground. Figure 5 shows typical

f_OSCvs. R_OSCresistor values. The LT1952 free-running

oscillator frequency is programmable in the range of

100kHz to 500kHz.

C

_STARTare given by:

R_START(MAX)= (V_S(MIN)– V_{IN ON(max)})/I_START(MAX)

Stray capacitance and potential noise pickup on the R_OSC

pin should be minimized by placing the R_OSCresistor as

close as possible to the R_OSCpin and keeping the area of

the R_OSCnode as small as possible. The ground side of the

R_OSCresistor should be returned directly to the (analog

ground) GND pin. R_OSCcan be calculated by,

C_START(MIN)= (I_Q(MAX)+ I_DRIVE(MAX)) • t_START

V_{IN HYST(MIN)}

/

Example:

For V_S(MIN)= 36V, V_{IN ON(MAX)}= 15.75V,

I_START(MAX)= 700µA, I_Q(MAX)= 5.5mA,

I_DRIVE(MAX)= 5mA, V_{IN HYST(MIN)}= 3.75V

and t_START= 100µs,

R_OSC= 9.125k [(4100k/f_OSC) – 1]

500

450

400

350

300

250

200

150

R_START= (36 – 15.75)/700µA = 28.9k (choose 28.7k)

C_START= (5.5mA + 5mA) • 100µs/3.75V = 0.28µF

(typically choose ≥ 1µF)

For system input voltages exceeding the absolute maxi-

mumratingoftheLT1952V_INpin,anexternalzenershould

be connected from the V_INpin to ground. This covers the

conditionwhereV_INchargespastV_INON(typically14.25V)

but the part does not turn on because SD_V_SEC< 1.32V. In

this condition V_INwill continue to charge towards system

100

50 100 150 200 250 300 350 400

R

(kΩ)

OSC

SYSTEM

INPUT (V )

1952 F05

S

FROM AUXILIARY WINDING

Figure 5. Oscillator Frequency (f_OSC) vs R_OSC

R

START

V

(14.25V ON, 8.75V OFF)

IN

Programming Leading Edge Blank Time

D1*

–

ForPWMcontrollersdrivingexternalMOSFETs, noisecan

be generated at the source of the MOSFET during gate rise

time and some time thereafter. This noise can potentially

exceed the OC and I_SENSEpin thresholds of the LT1952 to

cause premature turn off of SOUT and OUT in addition to

false trigger of soft-start. The LT1952 provides program-

mable leading edge blanking of the OC and I_SENSEcom-

parator outputs to avoid false current sensing during

MOSFET switching.

1.32V

+

C

START

LT1952

*FOR V > 25V, ZENER D1 RECOMMENDED

S

(V

< V < 25V)

Z

IN ON(MAX)

1952 F04

Figure 4. Low Power Start-Up

1952f

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LT1952

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APPLICATIO S I FOR ATIO

Blankingisprovidedin2phases(Figure6):Thefirstphase

automatically blanks during gate rise time. Gate rise times

can vary depending on MOSFET type. For this reason the

LT1952 performs true ‘leading edge blanking’ by auto-

maticallyblankingOCandI_SENSEcomparatoroutputsuntil

OUT rises to within 0.5V of V_INor reaches its clamp level

of 13V. The second phase of blanking starts after the

leading edge of OUT has been completed. This phase is

programmable by the user with a resistor connected from

theBLANKpintoground.Typicaldurationsforthisportion

of the blanking period are from 45ns at R_BLANK= 10k to

540nsatR_BLANK=120k.Blankingdurationcanbeapproxi-

mated as:

The current limit for the converter can be programmed by,

Current limit = (100mV/R_S)(N_P/N_S) – (1/2)(I_RIPPLE

where,

R_S= sense resistor in source of primary MOSFET

)

I_RIPPLE= p-p ripple current in the output inductor L1

N_S= number of transformer secondary turns

N_P= number of transformer primary turns

Programming Slope Compensation

The LT1952 uses a current mode architecture to provide

fast response to load transients and to ease frequency

compensationrequirements.Currentmodeswitchingregu-

latorswhichoperatewithdutycyclesabove50%andhave

continuous inductor current must add slope compensa-

tion to their current sensing loop to prevent subharmonic

oscillations. (For more information on slope compensa-

tion, see Application Note 19.) The LT1952 has program-

mable slope compensation to allow a wide range of

inductor values, to reduce susceptibility to PCB generated

noise and to optimize loop bandwidth. The LT1952 pro-

grams slope compensation by inserting a resistor R_SLOPE

in series with the I_SENSEpin (Figure 7). The LT1952

generates a current at the I_SENSEpin which is linear from

0% duty cycle to the maximum duty cycle of the OUT pin.

A simple calculation of I(I_SENSE) • R_SLOPEgives an added

ramp to the voltage at the I_SENSEpin for programmable

slopecompensation. (Seebothgraphs‘I_SENSEPinCurrent

vs. Duty Cycle’ and ‘I_SENSEMaximum Threshold vs Duty

Cycle’ in the Typical Performance Characteristics

section.)

Blanking (extended) = [45(R_BLANK/10k)]ns

(see graph in Typical Performance Characteristics)

(AUTOMATIC)

LEADING

EDGE

(PROGRAMMABLE)

CURRENT

SENSE

DELAY

EXTENDED

BLANKING

OUT

R

BLANK

(MIN)

= 10k

10k < R

≤ 240k

100ns

BLANK

BLANKING

0

Xns

X + 45ns

[X + 45(R

/10k)]ns

BLANK

1952 F06

Figure 6. Leading Edge Blank Timing

Programming Current Limit (OC Pin)

CURRENT SLOPE = 35µA • DC

The LT1952 uses a precise 100mV sense threshold at the

OC pin to detect over-current conditions in the converter

and set a soft-start latch. It is independent of duty cycle

because it is not affected by slope compensation pro-

grammed at the I_SENSEpin. The OC pin monitors the peak

current in the primary MOSFET by sensing the voltage

across a sense resistor (R_S) in the source of the MOSFET.

V

= V + (I

• R

)

SLOPE

(ISENSE)

S

SENSE

LT1952

OUT

OC

I

= 8µA + 35DC µA

SENSE

DC = DUTY CYCLE

V

S

R

SLOPE

FOR SYNC OPERATION

I

SENSE

I

= 8µA + (k • 35DC)µA

OSC SYNC

SENSE(SYNC)

k = f /f

1952 F07

R

S

Figure 7. Programming Slope Compensation

1952f

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APPLICATIO S I FOR ATIO

Programming Synchronous Rectifier Timing:

SOUT to OUT delay (‘t_DELAY’)

SS_MAXDC pin using a resistor divider from V_REF. An

increase of voltage at the SS_MAXDC pin causes the

maximum duty cycle clamp to increase.

The LT1952 has an additional output SOUT which pro-

vides a ±50mA peak drive clamped to 12V. In applications

requiringsynchronousrectificationforhighefficiency,the

LT1952 SOUT provides a sync signal for secondary side

control of the synchronous rectifier MOSFETs (Figure11).

Timing delays through the converter can cause non-

optimum control timing for the synchronous rectifier

MOSFETs. The LT1952 provides a programmable delay

(t_DELAY, Figure 8) between SOUT rising edge and OUT

risingedgetooptimizetimingcontrolforthesynchronous

rectifierMOSFETstoachievemaximumefficiencygains. A

resistor R_DELAYconnected from the DELAY pin to ground

sets the value of t_DELAY. Typical values for t_DELAYrange

from10nswithR_DELAY=10kto160nswithR_DELAY=160k.

(see graph in Typical Performance Characteristics)

To program the volt-second clamp, the following steps

should be taken:

(1) The maximum operational duty cycle of the converter

should be calculated for the given application.

(2) An initial value for the maximum duty cycle clamp

should be calculated using the equation below with a

first pass guess for SS_MAXDC.

Note: Since maximum operational duty cycle occurs at

minimum system input voltage (UVLO), the voltage at the

SD_V_SECpin = 1.32V.

Max Duty Cycle Clamp (OUT pin)

= k • 0.522(SS_MAXDC(DC)/SD_V_SEC) –

(t_DELAY• f_OSC

)

t

where,

DELAY

SS_MAXDC(DC) = V_REF(R_B/(R_T+ R_B)

SOUT

LT1952

SD_V_SEC= 1.32V at minimum system input voltage

t_DELAY= programmed delay between SOUT and OUT

DELAY

OUT

1952 F08

R

DELAY

k = 1.11 – 5.5e^–7• (f_OSC

)

(3) The maximum duty cycle clamp calculated in (2)

should be programmed to be 10% greater than the

maximum operational duty cycle calculated in (1). Simple

adjustment of maximum duty cycle can be achieved by

adjusting SS_MAXDC.

Figure 8. Programming SOUT to OUT Delay: t_DELAY

Programming Maximum Duty Cycle Clamp

For forward converter applications using the simplest

topology of a single MOSFET on the primary, a maximum

switchdutycycleclampwhichadaptstotransformerinput

voltage is necessary for reliable control of the MOSFET.

This volt-second clamp provides a safeguard for trans-

former reset that prevents transformer saturation. The

LT1952 SD_V_SECand SS_MAXDC pins provide a capaci-

tor-less, programmable volt-second clamp solution using

simple resistor ratios (Figure 9).

SYSTEM

INPUT VOLTAGE

R1

R2

LT1952

ADAPTIVE

DUTY CYCLE

CLAMP INPUT

SD_V

SEC

SS_MAXDC

R *

T

V

REF

1952 F09

R

B

An increase of voltage at the SD_V_SECpin causes the

maximumdutycycleclamptodecrease.DerivingSD_V_SEC

from a resistor divider connected to system input voltage

creates the volt-second clamp. The maximum duty cycle

clamp can be adjusted by programming voltage on the

MAX DUTY CYCLE

CLAMP ADJUST INPUT

*MINIMUM ALLOWABLE R IS 10k TO

T

GUARANTEE SOFT-START PULL-OFF

Figure 9. Programming Maximum Duty Cycle Clamp

1952f

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LT1952

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APPLICATIO S I FOR ATIO

Example calculation for (2)

A capacitor C_SSon the SS_MAXDC pin and the resistor

divider from V_REFused to program maximum switch duty

cycle clamp, determine soft-start timing (Figure 11).

For R_T= 35.7k, R_B= 100k, V_REF= 2.5V,

R

_DELAY= 40k, f_OSC= 200kHz and SD_V_SEC= 1.32V,

this gives SS_MAXDC(DC) = 1.84V, t_DELAY= 40ns

and k = 1

A soft-start event is triggered for the following faults:

(1) V_IN< 8.75V, or

Maximum Duty Cycle Clamp

= 1 • 0.522(1.84/1.32) – (40ns • 200kHz)

= 0.728 – 0.008 = 0.72 (Duty Cycle Clamp = 72%)

(2) SD_V_SEC< 1.32V (UVLO), or

(3) OC > 100mV (over-current condition)

When a soft-start event is triggered, switching at SOUT

and OUT is stopped immediately. A soft-start latch is set

and SS_MAXDC pin is discharged. The SS_MAXDC pin

canonlyrechargewhenthesoft-startlatchhasbeenreset.

Note 1: To achieve the same maximum duty cycle clamp

at 100kHz as calculated for 200kHz, the SS_MAXDC

voltage should be reprogrammed by,

SS_MAXDC(DC) (100kHz)

= SS_MAXDC(DC) (200kHz) • k (200kHz)/k (100kHz)

= 1.84 • 1.0/1.055 = 1.74V (k = 1.055 for 100kHz)

Note: A soft-start event caused by (1) or (2) above, also

causes V_REFto be disabled and to fall to ground.

The second order effect of t_DELAYshould also be consid-

ered for final adjustment of SS_MAXDC(DC).

SS_MAXDC

Note 2 : To achieve the same maximum duty cycle clamp

while synchronizing to an external clock at the SYNC pin,

the SS_MAXDC voltage should be re-programmed as,

SOFT-START

0.8V (ACTIVE THRESHOLD)

0.45V (RESET THRESHOLD)

EVENT TRIGGERED

TIMING (A): SOFT START FAULT REMOVED

BEFORE SS_MAXDC FALLS TO 0.45V

SS_MAXDC (DC) (fsync)

SS_MAXDC

= SS_MAXDC (DC) (200kHz) • [(fosc/fsync) +

0.09(fosc/200kHz)^0.6

]

For SS_MAXDC (DC) (200kHz) = 1.84V for 72%

duty cycle

0.8V (ACTIVE THRESHOLD)

0.45V (RESET THRESHOLD)

0.2V

TIMING (B): SOFT-START FAULT REMOVED

SS_MAXDC (DC) (fsync = 250kHz) for 72%

duty cycle

1952 F10

AFTER SS_MAXDC FALLS PAST 0.45V

= 1.84 • [(200kHz/250kHz) + 0.09(1)^0.6]

= 1.638V

Figure 10. Soft-Start Timing

SS_MAXDC(DC)

LT1952

Programming Soft-Start Timing

R

CHARGE

SS_MAXDC

TheLT1952hasbuilt-insoft-startcapabilitytoprovidelow

stress controlled startup from a list of fault conditions that

can occur in the application (see Figure 1 and Figure 10).

The LT1952 provides true PWM soft-start by using the

SS_MAXDC pin to control soft-start timing. The propor-

tionalrelationshipbetweenSS_MAXDCvoltageandswitch

maximum duty cycle clamp allows the SS_MAXDC pin to

slowly ramp output voltage by ramping the maximum

switch duty cycle clamp — until switch duty cycle clamp

seamlessly meets the natural duty cycle of the converter.

R

T

V

REF

C

SS

C

R

B

SS

1952 F11

SS_MAXDC CHARGING MODEL

SS_MAXDC(DC) = V [R /(R + R )]

REF

B

T

B

R

= [R • R /(R + R )]

T B T B

CHARGE

Figure 11. Programming Soft-Start Timing

1952f

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Soft-start latch reset requires all of the following:

Example

(A) V_IN> 14.25*, and

For an over-current fault (OC > 100mV), V_REF= 2.5V,

R_T= 35.7k, R_B= 100k, C_SS= 0.1µF and assume

(B) SD_V_SEC> 1.32V, and

V

_SS(MIN)= 0.45V,

I_DIS~ 8e^–4+ (2.5 – 0.45)[(1/2 • 100k) – (1/35.7k)]

= 8e^–4+ (2.05)(–0.23e^–4) = 7.5e^–4

(C) OC < 100mV, and

(D) SS_MAXDC < 0.45V (SS_MAXDC reset threshold)

SS_MAXDC(DC) = 1.84V

*V_IN> 8.75V is ok for latch reset if the latch was only set

by over-current condition in (3) above

SS_MAXDC (t_FALL) = (1e – 7/7.5e^–4) • (1.84 – 0.45)

= 1.85e^–4

s

SS_MAXDC Discharge Timing

IftheOCfaultisnotremovedbefore185µsthenSS_MAXDC

It can be seen in Figure 10 that two types of discharge can

occur for the SS_MAXDC pin. In timing (A) the fault that

caused the soft-start event has been removed before

SS_MAXDC falls to 0.45V. This means the soft-start latch

will be reset when SS_MAXDC falls to 0.45V and

SS_MAXDC will begin charging. In timing (B), the fault

that caused the soft-start event is not removed until some

time after SS_MAXDC has fallen past 0.45V. The

SS_MAXDC pin continues to discharge to 0.2V and re-

mains low until all faults are removed.

will continue to fall past 0.45V towards a new V_SS(MIN)

.

The typical V_OLfor SS_MAXDC at 150µA is 0.2V.

SS_MAXDC Charge Timing

When all faults are removed and the SS_MAXDC pin has

fallen to its reset threshold of 0.45V or lower, the

SS_MAXDC pin will be released and allowed to charge.

SS_MAXDC will rise until it settles at its programmed DC

voltage — setting the maximum switch duty cycle clamp.

The calculation of charging time for the SS_MAXDC pin

between any two voltage levels can be approximated as an

RC charging waveform using the model shown in

Figure 11.

The time for SS_MAXDC to fall to a given voltage can be

approximated as,

SS_MAXDC (t_FALL) =

(C_SS/I_DIS) • [SS_MAXDC(DC) – V_SS(MIN)

]

The ability to predict SS_MAXDC rise time between any

two voltages allows prediction of several key timing

periods:

where,

I_DIS= net discharge current on C_SS

(1) No Switching Period

C_SS= capacitor value at SS_MAXDC pin

(time from SS_MAXDC(DC) to V_SS(MIN)+ time from

SS_MAXDC(DC) = programmed DC voltage

V_SS(MIN)to V_SS(ACTIVE)

)

V_SS(MIN)= minimum SS_MAXDC voltage before

recharge

I_DIS~ 8e^–4+ (V_REF– V_SS(MIN))[(1/2R_B) – (1/R_T)]

(2) Converter Output Rise Time

(time from V_SS(ACTIVE)to V_SS(REG); V_SS(REG)is the

level of SS_MAXDC where maximum duty cycle

clamp equals the natural duty cycle of the switch)

For faults arising from (1) and (2),

V_REF= 100mV.

(3) Time For Maximum Duty Cycle Clamp within X% of

Target Value

For a fault arising from (3),

V_REF= 2.5V.

The time for SS_MAXDC to charge to a given voltage V_SS

is found by re-arranging,

SS_MAXDC(DC) = V_REF[R_B/(R_T+ R_B)]

V_SS(t) = SS_MAXDC(DC) (1 – e^(–t/RC)

)

V_SS(MIN)= SS_MAXDC reset threshold = 0.45V

(if fault removed before t_FALL

)

1952f

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APPLICATIO S I FOR ATIO

Step 3:

to give,

t(V_SS= 0.8V) is calculated from,

t = RC • (–1) • ln(1 – V_SS/SS_MAXDC(DC))

where,

t = R_CHARGE• C_SS• (–1) • ln(1 – V_SS/SS_MAXDC(DC))

= 2.63e⁴• 1e^–7• (–1) • ln(1 – 0.8/1.84)

V

_SS= SS_MAXDC voltage at time t

= 2.63e^–3• (–1) • ln(0.565) = 1.5e^–3

s

SS_MAXDC(DC) = programmed DC voltage setting

maximum duty cycle clamp =

From Step 1 and Step 2

t_CHARGE= (1.5 – 0.73)e^–3s = 7.7e^–4

s

V

_REF(R_B/(R_T+ R_B)

The total time of no switching for the converter due to a

soft-start event

R = R_CHARGE(Figure 11) = R_T• R_B/(R_T+ R_B)

C = C_SS(Figure 11)

= t_DISCHARGE+ t_CHARGE= 1.85e^–4+ 7.7e^–4= 9.55e^–4

s

Example (1) No Switching Period

Example (2) Converter Output Rise Time

The period of no switching for the converter, when a

soft-start event has occurred, depends on how far

SS_MAXDC can fall before recharging occurs and how

long a fault exists. It will be assumed that a fault triggering

soft-start is removed before SS_MAXDC can reach its

reset threshold (0.45V).

The rise time for the converter output to reach regulation

can be closely approximated as the time between the start

of switching (SS_MAXDC = V_SS(ACTIVE)) and the time

where converter duty cycle is in regulation (DC(REG)) and

no longer controlled by SS_MAXDC (SS_MAXDC =

V_SS(REG)). Converteroutputrisetimecanbeexpressedas,

No Switching Period = t_DISCHARGE+ t_CHARGE

Output Rise Time = t(V_SS(REG)) – t(V_SS(ACTIVE)

)

t_DISCHARGE= discharge time from SS_MAXDC(DC) to

0.45V

Step 1: Determine converter duty cycle DC(REG) for

output in regulation

t_CHARGE= charge time from 0.45V to V_SS(ACTIVE)

t_DISCHARGEwas already calculated earlier as 185µs.

t_CHARGEis calculated by assuming the following:

The natural duty cycle DC(REG) of the converter depends

on several factors. For this example it is assumed that

DC(REG) = 60% for system input voltage near the

undervoltage lockout threshold (UVLO). This gives

SD_V_SEC= 1.32V.

V_REF= 2.5V, R_T= 35.7k, R_B= 100k, C_SS= 0.1µF and

V_SS(MIN)= 0.45V.

Also assume that the maximum duty cycle clamp pro-

grammed for this condition is 72% for SS_MAXDC(DC) =

1.84V, f_OSC= 200kHz and R_DELAY= 40k.

t

_CHARGE= t(V_SS= 0.8V) – t(V_SS= 0.45V)

Step 1:

SS_MAXDC(DC) = 2.5[100k/(35.7k + 100k)] = 1.84V

_CHARGE= (35.7k • 100k/135.7k) = 26.3k

Step 2: Calculate V_SS(REG)

R

To calculate the level of SS_MAXDC (V_SS(REG)) that no

longer clamps the natural duty cycle of the converter, the

equation for maximum duty cycle clamp must be used

(seeprevioussection‘ProgrammingMaximumDutyCycle

Clamp’).

Step 2:

t(V_SS= 0.45V) is calculated from,

t = R_CHARGE• C_SS• (–1) • ln(1 – V_SS/SS_MAXDC(DC))

= 2.63e⁴• 1e^–7• (–1) • ln(1 – 0.45/1.84)

The point where the maximum duty cycle clamp meets

DC(REG) during soft-start is given by,

= 2.63e^–3• (–1) • ln(0.755) = 7.3e^–4

s

DC(REG) = Max Duty Cycle clamp

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APPLICATIO S I FOR ATIO

From previous calculations, t(0.45) = 7.3e – 4 s.

0.6 = k • 0.522(SS_MAXDC(DC)/SD_V_SEC) –

(t_DELAY• f_OSC

)

Using previous values for R_T, R_B, and C_SS,

For SD_V_SEC= 1.32V, f_OSC= 200kHz and R_DELAY= 40k

This gives k = 1 and t_DELAY= 40ns.

t(1.803) = 2.63e^–4• 1e^–7• (–1) • ln(1 – 1.803/1.84)

= 2.63e^–3• (–1) • ln(0.02) = 1.03e^–2

s

Hence the time for SS_MAXDC to charge from its mini-

mum reset threshold of 0.45V to within 2% of its target

value is given by,

Re-arranging the above equation to solve for SS_MAXDC

= V_SS(REG)

= [0.6 + (t_DELAY• f_OSC)(SD_V_SEC)]/(k • 0.522)

= [0.6 + (40ns • 200kHz)(1.32V)]/(1 • 0.522)

= (0.608)(1.32)/0.522 = 1.537V

t(1.803) – t(0.45) =

1.03e^–2– 7.3e^–4= 9.57e^–3

Step 3: Calculate t(V_SS(REG)) – t(V_SS(ACTIVE)

)

Forward Converter Applications

RecallthetimeforSS_MAXDCtochargetoagivenvoltage

V_SSis given by,

ThefollowingsectioncoversapplicationswheretheLT1952

is used in conjunction with other LTC parts to provide

highly efficient power converters using the single switch

forward converter topology.

t = R_CHARGE• C_SS• (–1) • ln(1 – V_SS/SS_MAXDC(DC))

(Figure 11 gives the model for SS_MAXDC charging)

For R_T= 35.7k, R_B= 100k, R_CHARGE= 26.3k

95% Efficient, 5V, Synchronous Forward Converter

The circuit in Figure 14 is based on the LT1952 to provide

thesimplestforwardpowerconvertercircuit—usingonly

one primary MOSFET. The SOUT pin of the LT1952 pro-

vides a synchronous control signal for the LTC1698 lo-

cated on the secondary. The LTC1698 drives secondary

side synchronous rectifier MOSFETs to achieve high effi-

ciency. The LTC1698 also serves as an error amplifier and

optocoupler driver.

For C_SS= 0.1µF, this gives t(V_SS(ACTIVE)

= t(V_SS(0.8V)) = 2.63e⁴• 1e^–7• (–1) • ln(1 – 0.8/1.84)

= 2.63e^–3• (–1) • ln(0.565) = 1.5e^–3

)

s

t(V_SS(REG)) = t(V_SS(1.537V)) = 26.3k • 0.1µF • –1 •

ln(1 – 1.66/1.84) = 2.63e^–3• (–1) • ln(0.146)

= 5e^–3s

The rise time for the converter output

Efficiency and transient response are shown in Figures 12

and 13. Peak efficiencies of 95% and ultra-fast transient

response are superior to presently available power mod-

ules. Integrated soft-start, over-current detection and

short circuit hiccup mode provide low stress, reliable

protection. In addition, the circuit in Figure 14 is an all-

ceramic capacitor solution providing low output ripple

voltage and improved reliability. The LT1952-based con-

verter can be used to replace power module converters at

a much lower cost. The LT1952 solution benefits from

thermal conduction of the system board resulting in

higher efficiencies and lower rise in component tempera-

tures. The 7mm height allows dense packaging and the

circuit can easily be adjusted to provide an output voltage

from 1.23V to 26V. Higher currents are achievable by

simple scaling of power components. The LT1952-based

solution in Figure 14 is a powerful topology for replace-

= t(V_SS(REG)) – t(V_SS(ACTIVE)) = (5 – 1.5)e^–3

= 3.5e^–3

s

Example (3) Time For Maximum Duty Cycle Clamp to

Reach Within X% of Target Value

A maximum duty cycle clamp of 72% was calculated

previously in the section ‘Programming Maximum Duty

Cycle Clamp’. The programmed value used for

SS_MAXDC(DC) was 1.84V.

The time for SS_MAXDC to charge from its minimum

value V_SS(MIN)to within X% of SS_MAXDC(DC) is given

by,

t(SS_MAXDC charge time within X% of target)

= t[(1 – (X/100) • SS_MAXDC(DC)] – t(V_SS(MIN)

)

For X = 2 and V_SS(MIN)= 0.45V, t(0.98 • 1.84) –

t(0.45) = t(1.803) – t(0.45)

ment of a wide range of power modules.

1952f

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APPLICATIO S I FOR ATIO

98

96

94

92

90

I

OUT

(5A/DIV)

0A

V

OUT

(200mV/DIV)

88

86

V

= 48V

IN

= 5V

OUT

OSC

f

= 300kHz

1952 F13

0

5

10

15

20

25

20µs/DIV

LOAD CURRENT (A)

1952 F12

Figure 12. LT1952-Based Synchronous Forward Converter

Efficiency vs Load Current (For Circuit in Figure 14)

Figure 13. Output Voltage Transient Response

(6A to 12A Load Step at 6A/µs)

+V

IN

36V TO 72V

C

IN

2.2µF

100V

X5R

L1

T1

PA0491

PA1393.152

+V

5V

0UT

20A

40k

475k

C

7

01

16

5

SOUT

22k

SOUT

SD_V

SEC

100µF

Q2

Q3

14

11

10

13

8

X5R

2×

Q1

PH3830

SS_MAXDC

OUT

OC

100k

6

2

V

REF

I

SENSE

1k

0.015Ω

FB

PGND

GND

LT1952

0.1µF

BAS516

7V

BIAS

15

3

4

LTC1698

10V

1

2

3

4

5

6

16

15

14

13

12

11

R

OSC

V

IN

BIAS

18.2k

SOUT

V

FG

DD

115k

1µF

X5R

SYNC

CG

SYNC

9.53k

SYNC

BLANK DELAY

12

33k

1

PGND

GND

OPTO

V

COMP

AUX

0.1µF

T2

R13

270Ω

I

COMP

SYNC

9

+I

–I

SNS

1µF

40k

4.75k

560Ω

220pF

C9, 6.8nF

V

COMP

R14

1.2k

HCPL-M453

10V

8

9

BIAS

V

FB

OVP

6

1

+V

0UT

Q1: PHM15NQ20 PHILIPS

2

3

5

4

R15

38.3k

R16

12.4k

0.1µF

1952 F14

Figure 14. 36V to 72V Input to 5V at 20A Synchronous Forward Converter

1952f

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APPLICATIO S I FOR ATIO

48V to Isolated 12V, 20A (No Opto-Coupler)

‘Bus Converter’

Thesolutionisonlyslightlylargerthan1/4“brick”sizeand

uses only ceramic capacitors for high reliability.

ThewideprogrammablerangeandaccuracyoftheLT1952

Volt-Second clamp makes the LT1952 an ideal choice for

‘BusConverter’applicationswheretheVolt-Secondclamp

provides line regulation for the converter output. The 48V

to 12V 20A ‘Bus Converter’ application in Figure16 shows

a semi-regulated isolated output without the need for an

optocoupler, optocoupler driver, reference or feedback

network. Some ‘Bus Converter’ solutions run with a fixed

50% duty cycle resulting in an output variation of 2-to-1

forapplicationswitha72Vto36Vinputrange.TheLT1952

uses an accurate wide programmable range Volt-Second

clamp to initially program and then control power supply

output voltage to typically ±10% for the same 36V to 72V

input range. Efficiency for the LT1952-based bus con-

verterinFigure16achievesahigh94%at20A(Figure15).

12V Bus Converter Efficiency

96.0

95.5

95.0

94.5

94.0

93.5

V

= 48V

IN

OUT

= 12V

93.0

4

6

8

10 12 14 16 18 20

LOAD CURRENT (A)

1952 F15

Figure 15. LT1952-Based Synchronous ‘Bus Converter’ Efficiency

vs Load Current (For Circuit in Figure 16)

T1

V

U1

PA0815.002

2.4µH

47k

82k

• •

V

OUT

IN

36V TO 72V

12V, 20A

BAS516

BCX55

12V

0.1µF

C

OUT

33µF, 16V

X5R, TDK

3x

Si7370

2x

PH4840

2x

18V

10k

2.2µF, 100V

2x

LTC3900

•

5

6

3

1

FG

CG

+

PH21NQ15

2x

370k

7

10k

GND

CS

13.2k

27k

14

15

8

V

1µF

U1

SD_V

OUT

SEC

4

8

2

7

–

115k

V

CS

3

9

5

CC

R

V

IN

OSC

BAT760

SYNC TIMER

8V

BIAS

BLANK

GND

1µF

C

T

13

12

11

10

16

R

T

0.47µF

0.1µF

SS_MAXDC

PGND

1nF

15k

59k

10k

39k

9mΩ

LT1952 DELAY

OC

1nF

8V

BIAS

6

1

2

V

REF

470Ω

560Ω

220pF

COMP

FB

I

SENSE

SOUT

L1: PA1494.242 PULSE ENGINEERING

T1: PULSE ENGINEERING

• •

T2

Q4470-B

T2: COILCRAFT

1952 F16

Figure 16. 36V to 72V Input to 12V at 20A No ‘Optocoupler’ Synchronous ‘Bus Converter’

1952f

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APPLICATIO S I FOR ATIO

36V to 72V Input, 3.3V 40A Converter

controlled hiccup mode. This allows a significant reduc-

tion in power component sizing using the LT1952-based

converter.

An LT1952-based synchronous forward converter pro-

vides the ideal solution for power supplies requiring high

efficiency at low output voltages and high load currents.

The 3.3V 40A solution in Figure 18 achieves peak efficien-

cies of 92.5% (Figure 17) by minimizing power loss due to

rectification at the output. Synchronous rectifier control

output SOUT, with programmable delay, optimizes timing

control for a secondary side synchronous MOSFET con-

troller(LTC3900)whichresultsinhighefficiencysynchro-

nous rectification. The LT1952 uses a precision current

limit threshold at the OC pin combined with a soft-start

hiccup mode to provide low stress output short circuit

protection. The maximum output current will vary only

10% over the full V_INrange. During short circuit the

average power dissipation of the circuit will be lower than

15% of maximum rated power thanks to a soft-start

94

93

92

91

90

89

88

V

= 48V

IN

87

86

= 3.3V

OUT

OSC

f

= 300kHz

0

10

20

30

40

50

OUTPUT CURRENT (A)

1952 F17

Figure 17. LT1952-Based Synchronous Forward Converter

Efficiency vs Load Current (For Circuit in Figure 18)

V

U1

PA0912.002

L1

47k

82k

• •

+V

V

OUT

3.3V, 40A

IN

36V TO 72V

BAS516

BCX55

12V

0.1µF

C

OUT

Q2

PH3230

2x

Q3

PH3230

2x

100µF

18V

10k

3x

2.2µF

LTC3900

•

5

6

3

1

FG

CG

+

370k

7

10k

GND

CS

13.2k

27k

14

15

8

V

1µF

U1

Si7846

SD_V

OUT

SEC

4

8

2

7

–

115k

V

CS

3

9

5

CC

R

OSC

V

IN

BAT760

SYNC TIMER

8V

BIAS

BLANK

GND

1µF

1nF

13

12

11

10

16

15k

0.22µF

0.1µF

SS_MAXDC

PGND

59k

10k

33k

39k

10mΩ

LT1952 DELAY

= 2.5V OC

1nF

8V

BIAS

6

1

2

V

R

470Ω

560Ω

220pF

COMP

I

SENSE

SOUT

249k

80.6k

• •

FB = 1.23V

T2

Q4470-B

2.2nF

8V

BIAS

22k

18k

2.2k

V

U1

–

4

3

5

2

10k

1

L1: PA0713, PULSE ENGINEERING

10k

+

ALL CAPACITORS X7R, CERAMIC, TDK

T2: COILCRAFT

LT1797

270Ω

PS8101

1µF

0.1µF

8

4

LT1009

1952 F18

Figure 18. 36V to 72V, 3.3V at 40A Synchronous Forward Converter

1952f

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APPLICATIO S I FOR ATIO

(b) Select switch duty cycle for the Bus Converter for a

given output voltage at V_S(MIN)and calculate

SS_MAXDC voltage (SS1) (See Applications Informa-

tion “Programming Maximum Duty Cycle Clamp”)

Bus Converter: Optimum Output Voltage Tolerance

The Bus Converter applications shown on page 1 and in

Figure 16, provide semi-regulated isolated outputs with-

out the need for an optocoupler, optocoupler driver, refer-

enceorfeedbacknetwork.TheLT1952Volt-Secondclamp

adjusts switch duty cycle inversely proportional to input

voltagetoprovideanoutputvoltagethatisregulatedagainst

input line variations. Some bus converters use a switch

duty cycle limit which causes output voltage variation of

typically±33% over a 2:1 input voltage range. The LT1952

typically provides a ±10% output variation for the same

inputvariation.Typicaloutputtoleranceisfurtherimproved

for the LT1952 by inserting a resistor from the system

input voltage to the SS_MAXDC pin (Rx in Figure 19).

(c) Calculate R_B(1)= [SS1/(2.5 – SS1)] • R_T(1)

(2) Calculate Rx

Rx = ([V_{S(MAX) –}V_S(MIN)]/[SS1 • (X – 1)]) • R_THEV(1)

R_THEV(1)= R_B(1)• R_T(1)/(R_B(1)+ R_T(1)), X = ideal duty

cycle (V_S(MAX))/actual duty cycle (V_S(MAX)

)

(3) The addition of Rx causes an increase in the original

programmed SS_MAXDC voltage SS1. A new value

for R_B(1)should be calculated to provide a lower

SS_MAXDC voltage (SS2) to correct for this offset.

The LT1952 electrical specifications for the OUT Max Duty

Cycle Clamp show typical switch duty cycle to move from

72% to 33% for a 2x change of input voltage

(SS_MAXDC pin=1.84V).Sinceoutputvoltageregulation

follows V_IN• Duty Cycle, a switch duty cycle change of

72% to 36% (for a 2x input voltage change) provides

minimal output voltage variation for the LT1952 bus con-

verter.Toachievethis,anSS_MAXDCpinvoltageincrease

of 1.09x (36/33) would be required at high input line. A

resistor Rx inserted between the SS_MAXDC pin and sys-

tem input voltage (Figure 19) increases SS_MAXDC volt-

age as input voltage increases, minimizing output voltage

variation over a 2:1 input voltage change.

(a) SS2 = SS1 – [(V_S(MIN)– SS1) • R_THEV(1)/Rx]

(b) R_B(2)= [SS2/(2.5 – SS2)] • R_T(1)

(4) The thevinin resistance R_THEV(1)used to calculate Rx

should be re-established for R_Tand R_B.

(a) R_B(final value) = R_B(2)• (R_THEV(1)/R_THEV(2)

(b) R_T(final value) = R_T(1)• (R_THEV(1)/R_THEV(2)

where R_THEV(2)= R_B(2)• R_T(1)/(R_B(2)+ R_T(1)

Example:

)

For a Bus Converter running from 36V to 72V input,

V_S(MIN)= 36V, V_S(MAX)= 72V.

The following steps determine values for Rx, R_Tand R_B

(1) Program switch duty cycle at minimum system input

choose R_T(1)= 10k, SS_MAXDC = SS1 = 1.84V (for 72%

duty cycle at V_S(MIN)= 36V)

voltage (V_S(MIN)

)

R_B(1)= [1.84V/(2.5V – 1.84V)] • 10k = 28k

R_THEV(1)= [28k • 10k/(28k + 10k)] = 7.4k

SS_MAXDC correction = 36%/33% = 1.09

Rx = [(72V – 36V)/(1.84 • 0.09)] • 7.4k = 1.6M

SS2 = 1.84 – [(36V – 1.84) • 7.4k/1.6M] = 1.682V

R_B(2)= [1.682/(2.5 – 1.682)] • 10k = 20.6k

R_THEV(2)= [20.6k • 10k/(20.6k + 10k)] = 6.7k

R_THEV(1)/R_THEV(2)= 7.4k/6.7k = 1.104

R_B(final value) = 20.6k • 1.104 = 22.7k (choose 22.6k)

R_T(final value) = 10k • 1.104 = 11k

(a) R_T(1)= 10k (minimum allowed to still guarantee soft-

start pull-down)

SYSTEM

INPUT VOLTAGE

R1

R2

Rx

LT1952

VOLT-SECOND

CLAMP INPUT

SD_V

SEC

SS_MAXDC

R

T

V

REF

VOLT-SECOND

CLAMP ADJUST INPUT

1952 F19

R

B

Figure 19. Optimal Programming of Maximum Duty Cycle Clamp

for Bus Converter Applications (Adding Rx)

1952f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

23

LT1952

U

PACKAGE DESCRIPTIO

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.189 – .196*

(4.801 – 4.978)

.045 ±.005

.009

(0.229)

REF

16 15 14 13 12 11 10 9

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 ±.0015

.0250 BSC

RECOMMENDED SOLDER PAD LAYOUT

1

2

3

4

5

6

7

8

.015 ± .004

(0.38 ± 0.10)

× 45°

.0532 – .0688

(1.35 – 1.75)

.004 – .0098

(0.102 – 0.249)

.007 – .0098

(0.178 – 0.249)

0° – 8° TYP

.016 – .050

(0.406 – 1.270)

.0250

(0.635)

BSC

.008 – .012

GN16 (SSOP) 0204

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

RELATED PARTS

PART NUMBER

LT1681/LT3781

LT1698

DESCRIPTION

COMMENTS

Synchronous Forward Controllers

Secondary Synchronous Rectifier Controller

High Efficiency 2-Switch Forward Control

Use for Isolated Power Supplies, Contains Voltage Margining, Optocoupler

Driver, Synchronization Circuit with the Primary Side, Error Amplifier

LT1725

LT1950

General Purpose Isolated Flyback Controller

Single Switch Forward Controller

Drives External Power MOSFET, Senses Output Voltage Directly from

Primary Side Switching — No Optoisolator Required, 16-pin SSOP

3V ≤ V ≤ 25V, 25W to 500W, Adaptive Max Duty Cycle Clamp, Programmable

IN

Slope Compensation, Low 100mV Sense Threshold, 16-Pin SSOP

LTC3722-1/LTC3722-2 Dual Mode Phase Modulated Full-Bridge Controllers ZVS Full-Bridge Controllers

LTC3723-1/LTC3723-2 Synchronous Push-Pull PWM Controllers

High Efficiency Push-Pull PWM

LTC3803

LTC3806

LTC3900

SOT-23 Flyback Controller

Adjustable Slope Compensation, Internal Soft-Start, 200kHz

Excellent Cross Regulation, High Efficiency, Multiple Outputs

Synchronous Flyback Controller

Synchronous Rectifier Driver for

Forward Converters

Use for Isolated Power Supplies, 4.5V ≤ V ≤ 11V, N-channel

IN

Synchronous MOSFET Driver, Programmable Timeout, Reverse Inductor

Current Sense, 16-pin SSOP

1952f

LT/TP 0804 1K • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

24

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT1952
厂家：	Linear
描述：	Single Switch Synchronous Forward Controller 单开关同步正向控制器开关控制器
文件：	总24页 (文件大小：253K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT1952 [Linear]

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