LT1994IMS8_技术文档

LT1994

Low Noise, Low Distortion

Fully Differential Input/

Output Ampliﬁer/Driver

U

DESCRIPTIO

FEATURES

TheLT^®1994isahighprecision,verylownoise,lowdistor-

tion, fully differential input/output ampliﬁer optimized for

3V,singlesupplyoperation.TheLT1994’soutputcommon

mode voltage is independent of the input common mode

voltage, and is adjustable by applying a voltage on the

■

Fully Differential Input and Output

■

Wide Supply Range: 2.375V to 12.6V

■

Rail-to-Rail Output Swing

Low Noise: 3nV/√Hz

Low Distortion, 2V , 1MHz: –94dBc

■

P-P

■

Adjustable Output Common Mode Voltage

Unity Gain Stable

V

OCM

pin. A separate internal common mode feedback

pathprovidesaccurateoutputphasebalancingandreduced

even-order harmonics. This makes the LT1994 ideal for

level shifting ground referenced signals for driving dif-

ferential input, single supply ADCs.

Gain-Bandwidth: 70MHz

Slew Rate: 65V/μs

Large Output Current: 85mA

DC Voltage Offset <2mV MAX

Open-Loop Gain: 100V/mV

Low Power Shutdown

The LT1994 output can swing rail-to-rail and is capable

of sourcing and sinking up to 85mA. In addition to the

low distortion characteristics, the LT1994 has a low input

referred voltage noise of 3nV/√Hz. This part maintains

its performance for supply voltages as low as 2.375V. It

draws only 13.3mA of supply current and has a hardware

shutdown feature that reduces current consumption to

225µA.

8-Pin MSOP or 3mm × 3mm DFN Package

U

APPLICATIO S

■

Differential Input A/D Converter Driver

■

Single-Ended to Differential Conversion

■

Differential Ampliﬁcation with Common Mode

The LT1994 is available in an 8-pin MSOP or 8-pin DFN

package.

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Translation

■

Rail-to-Rail Differential Line Driver/Receiver

■

Low Voltage, Low Noise, Differential Signal

Processing

U

TYPICAL APPLICATIO

LT1994 Driving an LTC1403A-1 1MHz

Sine Wave, 8192 Point FFT Plot

A/D Preampliﬁer: Single-Ended Input to Differential Output with Common

Mode Level Shifting

0

–10

F

= 2.8Msps

SAMPLE

IN

= 1.001MHz

499Ω

3V

INPUT = 2V

,

–20

P-P

10µF

SINGLE ENDED

SFDR = 93dB

3V

–30

V

P-P

IN

0.1µF

2V

–40

–50

V

SD0

24.9Ω

DD

+

–60

– +

A

IN

CONV

SCK

–70

V

LT1994

47pF

LTC1403A-1

–

OCM

50.4MHz

–80

0.1µF

+ –

A

IN

–90

V

GND

REF

–100

–110

–120

10µF

V

= 1.5V

OCM

0

0.35

0.70

1.05

1.40

499Ω

1994 TA01

FREQUENCY (MHz)

1994 TA01b

1994fa

1

LT1994

W W U W

ABSOLUTE AXI U RATI GS

(Note 1)

+

–

Total Supply Voltage (V to V )..............................12.6V

Input Voltage (Note 2)............................................... V

Speciﬁed Temperature Range (Note 5) .... –40°C to 85°C

Junction Temperature

MS8.................................................................. 150°C

DFN8................................................................. 125°C

Storage Temperature Range

S

Input Current (Note 2).......................................... 10mA

Input Current (V , SHDN)................................ 10mA

OCM

V

OCM

, SHDN ............................................................. V

S

Output Short-Circuit Duration (Note 3) ............ Indeﬁnite

MS8................................................... –65°C to 150°C

DFN8.................................................. –65°C to 125°C

Operating Temperature Range (Note 4) ... –40°C to 85°C

U

W

U

PACKAGE/ORDER I FOR ATIO

TOP VIEW

–

+

IN

1

2

3

4

8

7

6

5

IN

–

+

IN

1

2

3

4

8 IN

V

SHDN

–

OCM

V

7 SHDN

+

OCM

V

+

–

V

OUT

6 V

+

–

+

–

OUT

5 OUT

MS8 PACKAGE

8-LEAD PLASTIC MSOP

= 150°C, θ = 140°C/W

DD PACKAGE

8-LEAD (3mm × 3mm) PLASTIC DFN

T

JMAX

JA

T

= 125°C, θ = 160°C/W

JA

JMAX

–

UNDERSIDE METAL CONNECTED TO V

ORDER PART NUMBER

DD PART MARKING*

ORDER PART NUMBER

MS8 PART MARKING*

LT1994CDD

LT1994IDD

LBQM

LT1994CMS8

LT1994IMS8

LTBQN

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

*The temperature grade is identiﬁed by a label on the shipping container. Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS ^The

●

+

denotes the speciﬁcations which apply over the full operating

–

temperature range, otherwise speciﬁcations are at T = 25°C. V = 3V, V = 0V, V = V

= V

= mid-supply, V

= OPEN,

A

CM

OCM

ICM

SHDN

OUTCM

is deﬁned as (V – V ).

+

–

R = R = 499Ω, R = 800Ω to a mid-supply voltage (See Figure 1) unless otherwise noted. V is deﬁned (V – V ). V

is deﬁned

I

F

OUT

L

S

+

–

+

–

+

–

+

–

as (V

+ V

)/2. V

is deﬁned as (V + V )/2. V

is deﬁned as (V

– V

). V

OUT

ICM

IN

OUTDIFF

CONDITIONS

V = 2.375V, V

OUT

INDIFF IN IN

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

●

V

Differential Offset Voltage

(Input Referred)

= V /4

2

3

mV

OSDIFF

S

ICM

S

●

V = 3V

V = 5V

S

V = 5V

S

ΔV

/ΔT

OSDIFF

Differential Offset Voltage Drift

(Input Referred)

V = 2.375V, V

= V /4

3

μV/°C

S

V = 3V

V = 5V

S

V = 5V

S

●

I

Input Bias Current

(Note 6)

V = 2.375V, V

= V /4

–45

–18

–3

μA

B

S

V = 3V

V = 5V

S

V = 5V

S

1994fa

2

LT1994

ELECTRICAL CHARACTERISTICS ^The

●

+

denotes the speciﬁcations which apply over the full operating

–

temperature range, otherwise speciﬁcations are at T = 25°C. V = 3V, V = 0V, V = V

= V

= mid-supply, V

= OPEN,

A

CM

OCM

ICM

SHDN

OUTCM

is deﬁned as (V – V ).

+

–

R = R = 499Ω, R = 800Ω to a mid-supply voltage (See Figure 1) unless otherwise noted. V is deﬁned (V – V ). V

is deﬁned

I

F

OUT

L

S

+

–

+

–

+

–

+

–

as (V

+ V

)/2. V

is deﬁned as (V + V )/2. V

is deﬁned as (V

– V

). V

OUT

ICM

IN

OUTDIFF

CONDITIONS

V = 2.375V, V

OUT

INDIFF IN IN

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

●

I

Input Offset Current

(Note 6)

= V /4

0.2

2

3

4

μA

OS

S

ICM

S

●

V = 3V

V = 5V

S

V = 5V

S

R

Input Resistance

Input Capacitance

Common Mode

700

4.5

kΩ

IN

Differential Mode

C

Differential

2

3

pF

IN

e

n

Differential Input Referred Noise Voltage f = 50kHz

Density

nV/√Hz

i

Input Noise Current Density

f = 50kHz

2.5

15

pA/√Hz

nV/√Hz

n

e

Input Referred Common Mode Output

Noise Voltage Density

f = 50kHz, V

Shorted to Ground

nVOCM

OCM

●

V

Input Signal Common Mode Range

V = 3V

S

0

–5

1.75

3.75

V

ICMR

S

(Note 7)

V = 5V

●

CMRRI

Input Common Mode Rejection Ratio

V = 3V, ΔV

= 0.75V

= 2V

55

65

69

45

85

dB

S

ICM

(Note 8)

(Input Referred) ΔV /ΔV

ICM OSDIFF

CMRRIO

(Note 8)

Output Common Mode Rejection Ratio

(Input Referred) ΔV /ΔV

V = 5V, ΔV

S OCM

OCM

OSDIFF

PSRR

(Note 9)

Differential Power Supply Rejection

(ΔV /ΔV

V = 3V to 5V

S

105

70

)

OSDIFF

S

PSRRCM

(Note 9)

Output Common Mode Power Supply

Rejection (ΔV /ΔV

V = 3V to 5V

S

)

OSOCM

S

●

G

Common Mode Gain (∆V

/ΔV

OUTCM

)

V = 2.5V

1

V/V

%

CM

OCM

S

Common Mode Gain Error

V = 2.5V

S

–0.15

1

100 • (G – 1)

CM

BAL

Output Balance (ΔV /ΔV

OUTCM

)

ΔV

= 2V

OUTDIFF

Single-Ended Input

Differential Input

●

–65

–71

–46

–50

dB

●

V

Common Mode Offset Voltage

(V – V

V = 2.375V, V

= V /4

2.5

25

30

40

mV

OSCM

S

ICM

S

)

V = 3V

OUTCM

OCM

S

V = 5V

S

V = 5V

S

ΔV

/ΔT

Common Mode Offset Voltage Drift

V = 2.375V, V

= V /4

5

μV/°C

OSCM

S

ICM

S

V = 3V

S

V = 5V

S

V = 5V

S

–

+

●

V

Output Signal Common Mode Range

(Voltage Range for the V Pin)

V = 3V, 5V

S

V + 1.1

V – 0.8

V

OUTCMR

(Note 7)

OCM

●

R

Input Resistance, V

OCM

30

40

60

kΩ

INVOCM

V

Voltage at the V

V = 5V

2.45

2.5

2.55

V

MID

OCM

S

●

Output Voltage, High, Either Output Pin V = 3V, No Load

(Note 10)

70

90

200

140

175

400

mV

OUT

S

V = 3V, R = 800Ω

S L

V = 3V, R = 100Ω

S

L

●

V = 5V, No Load

150

200

900

325

450

2400

mV

S

V = 5V, R = 800Ω

S

L

V = 5V, R = 100Ω

S

L

1994fa

3

LT1994

ELECTRICAL CHARACTERISTICS ^The

●

+

denotes the speciﬁcations which apply over the full operating

–

temperature range, otherwise speciﬁcations are at T = 25°C. V = 3V, V = 0V, V = V

= V

= mid-supply, V

= OPEN,

A

CM

OCM

ICM

SHDN

OUTCM

is deﬁned as (V – V ).

+

–

R = R = 499Ω, R = 800Ω to a mid-supply voltage (See Figure 1) unless otherwise noted. V is deﬁned (V – V ). V

is deﬁned

I

F

OUT

L

S

+

–

+

–

+

–

+

–

as (V

+ V

)/2. V

is deﬁned as (V + V )/2. V

is deﬁned as (V

– V

). V

OUT

ICM

IN

OUTDIFF

CONDITIONS

V = 3V, No Load

V = 3V, R = 800Ω

V = 3V, R = 100Ω

OUT

INDIFF IN IN

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

●

Output Voltage, Low, Either Output Pin

(Note 10)

30

50

125

70

90

250

mV

S

●

L

S

●

V = 5V, No Load

80

125

900

180

250

2400

mV

S

V = 5V, R = 800Ω

S

L

V = 5V, R = 100Ω

S

L

●

I

Output Short-Circuit Current, Either

Output Pin (Note 11)

V = 2.375V, R = 10Ω

25

30

40

45

35

40

65

85

mA

SC

S

L

V = 3V, R = 10Ω

S

L

V = 5V, R = 10Ω

S

L

V = 5V, V = 0V, R = 10Ω

S

CM

L

+

–

●

SR

Slew Rate

V = 5V, ΔV

= –ΔV = 1V

OUT

50

65

85

V/μS

S

OUT

CM

V = 5V, V = 0V,

S

+

–

ΔV

= –ΔV

= 1.8V

OUT

●

GBW

Gain-Bandwidth Product

TEST

V = 3V, T = 25°C

S CM A

58

70

MHz

S

A

(f

= 1MHz)

V = 5V, V = 0V, T = 25°C

Distortion

V = 3V, R = 800Ω, f = 1MHz,

S

L

IN

+

–

V

– V

= 2V

P-P

OUT

Differential Input

2nd Harmonic

3rd Harmonic

–99

–96

dBc

Single-Ended Input

2nd Harmonic

3rd Harmonic

–94

–108

dBc

t

S

Settling Time

V = 3V, 0.01%, 2V Step

S

120

90

ns

S

V = 3V, 0.1%, 2V Step

A

Large-Signal Voltage Gain

Supply Voltage Range

Supply Current

V = 3V

100

dB

V

VOL

S

●

V

S

2.375

12.6

●

I

S

V = 3V

13.3

13.9

14.8

18.5

19.5

20.5

mA

S

V = 5V

S

V = 5V

S

●

I

Supply Current in Shutdown

V = 3V

0.225

0.375

0.7

0.8

1.75

2.5

mA

SHDN

S

V = 5V

S

V = 5V

S

+

●

V

SHDN Input Logic Low

SHDN Input Logic High

SHDN Pull-Up Resistor

Turn-On Time

V = 3V to 5V

S

V – 2.1

V

IL

+

V = 3V to 5V

S

V – 0.6

IH

R

V = 2.375V to 5V

S

40

55

1

75

kΩ

μs

SHDN

t

V

0.5V to 3V

3V to 0.5V

ON

OFF

SHDN

Turn-Off Time

V

1

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The inputs are protected by a pair of back-to-back diodes. If the

differential input voltage exceeds 1V, the input current should be limited to

less than 10mA.

Note 4: The LT1994C/LT1994I are guaranteed functional over the operating

temperature range –40°C to 85°C.

Note 5: The LT1994C is guaranteed to meet speciﬁed performance from

0°C to 70°C. The LT1994C is designed, characterized, and expected to

meet speciﬁed performance from –40°C to 85°C but is not tested or

QA sampled at these temperatures. The LT1994I is guaranteed to meet

speciﬁed performance from –40°C to 85°C.

Note 3: A heat sink may be required to keep the junction temperature

below the absolute maximum rating when the output is shorted

indeﬁnitely.

Note 6: Input bias current is deﬁned as the average of the input currents

–

+

ﬂowing into Pin 1 and Pin 8 (IN and IN ). Input Offset current is deﬁned

as the difference of the input currents ﬂowing into Pin 8 and Pin 1

+

–

(I = I – I ).

OS

B

1994fa

4

LT1994

ELECTRICAL CHARACTERISTICS

Note 7: Input Common Mode Range is tested using the Test Circuit of

input referred voltage offset. Output CMRR is deﬁned as the ratio of the

change in the voltage at the V

referred voltage offset.

pin to the change in differential input

Figure 1 (R = R ) by applying a single ended 2V , 1kHz signal to V

OCM

F

I

P-P

INP

(V

= 0), and measuring the output distortion (THD) at the common

INM

mode Voltage Range limits listed in the Electrical Characteristics table,

and conﬁrming the output THD is better than –40dB. The voltage range for

the output common mode range (Pin 2) is tested using the Test Circuit of

Figure 1 (R = R ) by applying a 0.5V peak, 1kHz signal to the V

Note 9: Differential Power Supply Rejection (PSRR) is deﬁned as the ratio

of the change in supply voltage to the change in differential input referred

voltage offset. Common Mode Power Supply Rejection (PSRRCM) is

deﬁned as the ratio of the change in supply voltage to the change in the

F

I

OCM

Pin 2 (with V = V

= 0) and measuring the output distortion (THD)

common mode offset, V

– V

.

INP

INM

OUTCM

OCM

at V

with V

biased 0.5V from the V

pin range limits listed

Note 10: Output swings are measured as differences between the output

and the respective power supply rail.

Note 11: Extended operation with the output shorted may cause junction

temperatures to exceed the 150°C limit for the MSOP package (or 125°C

for the DD package) and is not recommended.

OUTCM

OCM

in the Electrical Characteristics Table, and conﬁrming the THD is better

than –40dB.

Note 8: Input CMRR is deﬁned as the ratio of the change in the input

common mode voltage at the pins IN or IN to the change in differential

+

–

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Differential Input Referred

Voltage Offset vs Temperature

Common Mode Voltage Offset vs

Temperature

Input Bias Current and Input

Offset Current vs Temperature

500

250

0

7.5

5.0

2.5

0

–10

–15

–20

–25

–30

1.0

0.5

0

V

= 3V

V

= 3V

S

= 1.5V

OCM

CM

OCM

CM

I , V

= 5V

B

S

FOUR TYPICAL UNITS

I

, V = 3V

S

OS

I

OS

, V = 5V

S

–250

–0.5

–1.0

–500

–750

I , V = 3V

B

S

–2.5

–50

0

25

50

75

100

–50

0

25

50

75

100

–50

0

25

50

75

100

–25

TEMPERATURE (°C)

1994 G01

1994 G02

1994 G03

Frequency Response vs

Supply Voltage

Frequency Response vs

Load Capacitance

Gain Bandwidth vs Temperature

72

71

70

69

68

67

66

2

1

2

1

R

F

= R = 499Ω

I

R

= R = 499Ω

I

F

V

= 2.5V

S

V

= 3V

= 2.5V

V

S

V

=

5V

S

V

= 5V

S

V

= 3V

S

V

= 3V

S

0

V

= 5V

S

–1

–2

–1

–2

5pF FROM EACH

OUTPUT TO GROUND

25pF FROM EACH

OUTPUT TO GROUND

–50

0

25

50

75

100

–25

0.1

1

10

100

0.1

1

10

100

TEMPERATURE (°C)

FREQUENCY (MHz)

1994 G04

1994 G05

1994 G06

1994fa

5

LT1994

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Differential Power Supply

Rejection vs Frequency

Output Impedance vs Frequency

Output Balance vs Frequency

100

10

1

–30

–40

–50

–60

–70

–80

–90

110

100

90

80

70

60

50

40

30

20

10

0

V

= 3V

I

∆V

S

F

OUTCM

R

= R = 499Ω

∆V

OUTDIFF

OSDIFF

+

V

SUPPLY

–

V

SUPPLY

SINGLE ENDED INPUT

DIFFERENTIAL INPUT

V

= 3V

V = 3V

S

0.1

1

10

100

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

FREQUENCY (MHz)

FREQUENCY (Hz)

1995 G08

1995 G09

1994 G07

Input Common Mode Rejection vs

Frequency

Common Mode Output Power

Supply Rejection vs Frequency

Input Noise vs Frequency

100

90

80

70

60

50

40

30

100

10

1

100

60

50

40

30

20

10

0

∆V

V

T

= 3V

= 25°C

∆V

ICM

S

A

S

V

= 3V

S

–

∆V

V

SUPPLY

OSDIFF

OSOCM

V

=

5V

S

+

V

SUPPLY

10

e

n

i

n

V

= 3V

S

1

1M

1k

10k

100k

1M

10M

100M

10

100

1k

10k

100k

0.1

1

10

100

FREQUENCY (Hz)

FREQUENCY (MHz)

1995 G10

1995 G11

1995 G12

Differential Distortion vs Input

Amplitude (Single Ended Input)

Differential Distortion vs Input

Common Mode Level

–60

–70

–40

–50

V

IN

= 3V

V

= 3V

S

F

= 1MHz

= 2V (SINGLE ENDED)

IN

P-P

R

V

= R = 499Ω

F

= 1MHz

I

F

L

I

= 800Ω

R

V

= R = 499Ω

F

L

= MID-SUPPLY

= 800Ω

–60

OCM

= MID-SUPPLY

OCM

–80

2ND, V

= 1.5V

ICM

–70

–

–80

2ND, V = V

CM

–90

2ND

–90

–

3RD, V = V

CM

–100

–110

–100

–110

3RD, V

3

= 1.5V

4

3RD

ICM

1

5

0

0.5

1.5

2.0

2.5

2

1.0

–

+

V (V

IN P-P

)

INPUT COMMON MODE DC BIAS, IN OR IN PINS (V)

1994 G13

1994 G14

1994fa

6

LT1994

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Differential Distortion vs

Frequency

Slew Rate vs Temperature

2V Step Response Settling

68

66

64

62

60

–40

–50

R

= R = 499Ω

I

F

V

= 3V

S

= 2V (SINGLE ENDED)

IN

P-P

F

= 1MHz

I

R

= R = 499Ω

F

L

–60

= 800Ω

V = 3V

S

+0.1%

V

= MID-SUPPLY

OCM

ICM

ERROR

–70

V

OUT

3RD

–80

V

= 5V

S

2ND

–90

–0.1%

ERROR

–100

V

= 3V

S

F

R

= R = 499Ω

I

–110

–50

0

25

50

75

100

–25

100k

1M

FREQUENCY (Hz)

10M

25ns/DIV

TEMPERATURE (°C)

1994 G17

1994 G16

1994 G15

Small Signal Step Response

Large Signal Step Response

Output with Large Input Overdrive

25pF LOAD

V

= 3V

V = 3V

S

F

+

OUT

R

= R = 499Ω

R

= R = 499Ω

I

F

I

–

V

= V

CM

+

OUT

+

OUT

0pF LOAD

V

= 3V

I

= 100mV

S

F

R

= R = 499Ω

V

,

P-P

IN

SINGLE ENDED

–

OUT

–

OUT

–

OUT

V

IN

= 3V SINGLE ENDED

P-P

V

IN

= 10V SINGLE ENDED

P-P

20ns/DIV

100ns/DIV

2µs/DIV

1994 G18

1994 G19

1994 G20

1994fa

7

LT1994

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TYPICAL PERFOR A CE CHARACTERISTICS

Supply Current vs Supply Voltage

Supply Current vs SHDN Voltage

20

15

10

5

16

12

8

16

12

8

+

V

= 5V

V

= 3V

SHDN PIN VOLTAGE = V

S

T

= 85°C

A

T

= –40°C

T

= 85°C

A

T = –40°C

A

T

= –40°C

A

T

= 0°C

A

T

= 0°C

T

= 0°C

A

T

= 25°C

A

T

= 70°C

A

= 25°C

T

= 70°C

A

T

= 25°C

= 70°C

A

4

T

= 85°C

A

4

T

A

0

5.0

7.5

10.0

12.5

0

2

3

5

2.5

1

0

0.5

1.5

2.0

2.5

3.0

1.0

SUPPLY VOLTAGE (V)

SHDN PIN VOLTAGE (V)

1994 G21

1994 G22

1994 G23

SHDN Pin Current vs SHDN

Pin Voltage

Shutdown Supply Current vs

Supply Voltage

1000

750

500

250

0

–10

–20

–30

V

S

= 3V

T

= –40°C

A

T

= 0°C

A

T

= 25°C

A

T

= 25°C

A

T

= 70°C

A

T

= 85°C

A

T

= 85°C

A

T

= –40°C

A

0

2.5

7.5

10.0

12.5

0

0.5

1.5

2.0

2.5

3.0

5.0

1.0

SUPPLY VOLTAGE (V)

SHDN PIN VOLTAGE (V)

1994 G25

1994 G24

1994fa

8

LT1994

U

PI FU CTIO S

+

–

IN , IN (Pins 1, 8): Non-Inverting and Inverting Input

Pins of the Ampliﬁer, respectively. For best performance,

it is highly recommended that stray capacitance be

kept to an absolute minimum by keeping printed circuit

connections as short as possible, and if necessary, strip-

ping back nearby surrounding ground plane away from

these pins.

high quality 1μF and 0.1µF ceramic bypass capacitors be

placed from the positive supply pin (Pin 3) to the negative

supply pin (Pin 6) with minimal routing. Pin 6 should be

directly tied to a low impedance ground plane. For dual

powersupplies,itisrecommendedthathighquality,0.1μF

ceramic capacitors are used to bypass Pin 3 to ground

and Pin 6 to ground. It is also highly recommended that

high quality 1µF and 0.1µF ceramic bypass capacitors be

placed across the power supply pins (Pins 3 and 6) with

minimal routing.

V

OCM

(Pin 2): Output Common Mode Reference Voltage.

OCM

The V

pin is the midpoint of an internal resistive volt-

age divider between the supplies, developing a (default)

mid-supply voltage potential to maximize output signal

swing. V

proximately 40kΩ and can be overdriven by an external

voltage reference. The voltage on V sets the output

common mode voltage level (which is deﬁned as the av-

erage of the voltages on the OUT and OUT pins). V

should be bypassed with a high quality ceramic bypass

capacitor of at least 0.1μF (unless connected directly to

a low impedance, low noise ground plane) to minimize

common mode noise from being converted to differen-

tial noise by impedance mismatches both externally and

internally to the IC.

+

–

OUT , OUT (Pins 4, 5): Output Pins. Each pin can drive

approximately 100Ω to ground with a short circuit current

limit of up to 85mA. Each ampliﬁer output is designed

to drive a load capacitance of 25pF. This basically means

the ampliﬁer can drive 25pF from each output to ground

or 12.5pF differentially. Larger capacitive loads should be

decoupled with at least 25Ω resistors from each output.

has a Thevenin equivalent resistance of ap-

OCM

+

–

OCM

SHDN (Pin 7): When Pin 7 (SHDN) is ﬂoating or when

+

Pin 7 is directly tied to V , the LT1994 is in the normal

operating mode. When Pin 7 is pulled a minimum of 2.1V

+

below V , the LT1994 enters into a low power shutdown

state. Refer to the SHDN pin section under Applications

Information for description of the LT1994 output imped-

ance in the shutdown state.

+

–

V , V (Pins 3, 6): Power Supply Pins. For single supply

applications (Pin 6 grounded) it is recommended that

1994fa

9

LT1994

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APPLICATIO S I FOR ATIO

Functional Description

driveapproximately25pFtoground(12.5pFdifferentially).

Higherloadcapacitancesshouldbedecoupledwithatleast

25Ω of series resistance from each output.

The LT1994 is a small outline, wide band, low noise, and

low distortion fully-differential ampliﬁer with accurate

output phase balancing. The LT1994 is optimized to

drive low voltage, single-supply, differential input ana-

log-to-digital converters (ADCs). The LT1994’s output is

capable of swinging rail-to-rail on supplies as low as 2.5V,

which makes the ampliﬁer ideal for converting ground

Input Pin Protection

The LT1994’s input stage is protected against differential

input voltages that exceed 1V by two pairs of back-to-

back diodes that protect against emitter base breakdown

of the input transistors. In addition, the input pins have

steering diodes to either power supply. If the input pair

is over-driven, the current should be limited to under

10mA to prevent damage to the IC. The LT1994 also has

referenced, single-ended signals into V

referenced

OCM

differential signals in preparation for driving low voltage,

single-supply, differential input ADCs. Unlike traditional

op amps which have a single output, the LT1994 has two

outputs to process signals differentially. This allows for

two times the signal swing in low voltage systems when

comparedtosingle-endedoutputampliﬁers.Thebalanced

differentialnatureoftheampliﬁeralsoprovideseven-order

harmonic distortion cancellation, and less susceptibility

to common mode noise (like power supply noise). The

LT1994 can be used as a single ended input to differential

output ampliﬁer, or as a differential input to differential

output ampliﬁer.

steering diodes to either power supply on the V

, and

OCM

SHDN pins (Pins 2 and 7) and if exposed to voltages that

exceed either supply, they too should be current limited

to under 10mA.

SHDN Pin

If the SHDN pin (Pin 7) is pulled 2.1V below the positive

supply, an internal current is generated that is used to

power down the LT1994. The pin will have the Thevenin

+

equivalent impedance of approximately 55kΩ to V . If

The LT1994’s output common mode voltage, deﬁned as

the average of the two output voltages, is independent

of the input common mode voltage, and is adjusted

by applying a voltage on the V

open, there is an internal resistive voltage divider, which

the pin is left unconnected, an internal pull-up resistor of

120kΩ will keep the part in normal active operation. Care

should be taken to control leakage currents at this pin to

under 1μA to prevent leakage currents from inadvertently

puttingtheLT1994intoshutdown.Inshutdown,allbiasing

pin. If the pin is left

OCM

+

–

develops a potential halfway between the V and V pins.

The V pin will have an equivalent Thevenin equivalent

+

current sources are shut off, and the output pins OUT

OCM

–

and OUT will each appear as open collectors with a non-

resistance of 40kΩ, and a Thevenin equivalent voltage of

half-supply. Whenever this pin is not hard tied to a low

impedance ground plane, it is recommended that a high

linear capacitor in parallel, and steering diodes to either

supply.Becauseofthenon-linearcapacitance,theoutputs

still have the ability to sink and source small amounts of

transient current if exposed to signiﬁcant voltage tran-

quality ceramic cap is used to bypass the V

pin to a

OCM

low impedance ground plane (see Layout Considerations

in this document). The LT1994’s internal common mode

feedback path forces accurate output phase balancing to

reduce even order harmonics, and centers each individual

+

–

sients. The inputs (IN , and IN ) have anti-parallel diodes

that can conduct if voltage transients at the input exceed

1V. The inputs also have steering diodes to either supply.

The turn-on and turn-off time between the shutdown and

active states are on the order of 1μs but depends on the

circuit conﬁguration.

output about the potential set by the V

pin.

OCM

V_OUT⁺+ V_OUT

–

V_OUTCM= V_OCM

=

2

General Ampliﬁer Applications

+

–

The outputs (OUT and OUT ) of the LT1994 are capable

of swinging rail-to-rail. They can source or sink up to

approximately 85mA of current. Each output is rated to

As levels of integration have increased and, correspond-

ingly, system supply voltages decreased, there has been

1994fa

10

LT1994

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APPLICATIO S I FOR ATIO

a need for ADCs to process signals differentially in order

to maintain good signal to noise ratios. These ADCs are

typically supplied from a single supply voltage that can be

as low as 2.5V and will have an optimal common mode

input range near mid-supply. The LT1994 makes interfac-

ing to these ADCs trivial, by providing both single ended

to differential conversion as well as common mode level

shifting.Figure1showsageneralsinglesupplyapplication

where: R is the average of R and R , and R is the

F

F1

F2

I

average of R and R .

I1

I2

β

is deﬁned as the average feedback factor (or gain)

from the outputs to their respective inputs:

AVG

⎛

⎜

⎞

1

R

I1

R +R_F1

I1

I2

β_AVG= •

+

⎟

⎠

2 R +R

⎝

I2

F2

+

with perfectly matched feedback networks from OUT and

Δβ is deﬁned as the difference in feedback factors:

–

OUT . The gain to V

from V

and V is:

INM INP

OUTDIFF

R

I2

R

I1

∆β =

–

R_F

R

I

+

–

R +R_F2R +R_F1

I2

I1

V_OUTDIFF= V_OUT– V_OUT

≈

• V_INP– V

INM

(

)

V

is deﬁned as the average of the two input voltages,

ICM

INP

Note from the above equation that the differential output

and V

(also called the input common mode

INM

+

–

voltage(V

–V

)iscompletelyindependentofinput

voltage):

OUT

and output common mode voltages, or the voltage at the

common mode pin. This makes the LT1994 ideally suited

pre-ampliﬁcation, level shifting, and conversion of single

ended signals to differential output signals in preparation

for driving differential input ADCs.

1

2

V

= • V_INP+ V

(

)

ICM

INM

and V

voltages:

is deﬁned as the difference of the input

INDIFF

Effects of Resistor Pair Mismatch

V

INDIFF

= V_INP– V

INM

Figure 2 shows a circuit diagram that takes into consid-

eration that real world resistors will not perfectly match.

Assuming inﬁnite open loop gain, the differential output

relationship is given by the equation:

When the feedback ratios mismatch (Δβ), common mode

to differential conversion occurs.

Setting the differential input to zero (V

= 0), the de-

INDIFF

gree of common mode to differential conversion is given

R_F

–

V_OUTDIFF= V_OUT⁺– V_OUT

≅

•V

INDIFF

+

R

I

∆β

β_AVG

∆β

β_AVG

•V

ICM

–

•V_OCM,

–

+

–

+

R

V

R

V

R

L

R

V

R

F

V

R

I2

IN

F2

OUT

I

IN

OUT

L

+

V

0.1µF

V

S

R

V

BAL

V

INM

3

4

1

4

1

–

+

–

+

V

OCM

2

8

OCM

2

8

0.1µF

V

LT1994

0.1µF

V

LT1994

OCM

OUTCM

OCM

–

V

–

+

CM

+

0.1µF

5

0.1µF

5

SHDN

6

V

7

V

INP

7

INP

R

BAL

R

0.1µF

V

SHDNB

SHDN

–

R

V

R

L

R

F

V

OUT

I1

F1

OUT

V

I

L

+

V

IN

1994 F02

IN

1994 F01

Figure 1. Test Circuit

Figure 2. Real-World Application

1994fa

11

LT1994

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APPLICATIO S I FOR ATIO

by the equation:

R should be chosen (see Figure 3):

1

–

V_OUTDIFF= V_OUT⁺– V_OUT

≈

R

_INM•R_S

R₁=

R_INM−R_S

∆β

β_AVG

V

_ICM– V_OCM•

(

)

According to Figure 3, the input impedance looking into

V

= 0

INDIFF

thedifferentialamp(R )reﬂectsthesingleendedsource

INM

case, thus:

Ingeneral,thedegreeoffeedbackpairmismatchisasource

ofcommonmodetodifferentialconversionofbothsignals

and noise. Using 1% resistors or better will provide about

28dB of common mode rejection. Using 0.1% resistors

will provide about 48dB of common mode rejection. A low

impedance ground plane should be used as a reference

R

I

R

=

INM

⎛

⎞

1 ⎡ R_F

⎤

⎥

1– •

⎜

⎝

⎟

⎠

⎢

2 R +R_{F ⎦}

⎣ I

R is chosen to balance R || R :

2

1

S

for both the input signal source and the V

pin. A direct

OCM

R₁•R_S

R₁+R_S

short of V

to this ground plane or bypassing the V

OCM

R₂=

with a high quality 0.1µF ceramic capacitor to this ground

plane will further mitigate against common mode signals

from being converted to differential.

Input Common Mode Voltage Range

TheLT1994’sinputcommonmodevoltage(V )isdeﬁned

Input Impedance and Loading Effects

ICM

+

–

as the average of the two input voltages, V , and V

.

IN

The input impedance looking into the V or V

of Figure 1 depends on whether or not the sources V

input

INP

–

+

INP

INM

It extends from V to approximately 1.25V below V . The

input common mode range depends on the circuit con-

and V

INP

is simply:

are fully differential. For balanced input sources

INM

ﬁguration (gain), V

and V (refer to Figure 4). For

CM

OCM

(V = –V ), the input impedance seen at either input

fully differential input applications, where V = –V

,

INP

INM

the common mode input is approximately:

R

INP

= R = R

INM I

+

–

V

IN

+ V

2

⎛ R

I

⎞

⎟

IN

For single ended inputs, because of the signal imbalance

at the input, the input impedance actually increases over

thebalanceddifferentialcase.Theinputimpedancelooking

into either input is:

V

ICM

=

≈ V_OCM

•

+

⎜

⎝R + R_F⎠

I

⎛ R_F

⎝R_F+ R ⎠

⎞

⎟

V_CM

•

⎜

I

R

I

R

INP

= R

=

R

INM

⎛

⎞

1 ⎡ R_F

⎤

⎥

R

S

R

I

R

F

1– •

⎜

⎝

⎟

⎠

⎢

2 R +R_{F ⎦}

⎣ I

V

S

R

1

Inputsignalsourceswithnon-zerooutputimpedancescan

alsocausefeedbackimbalancebetweenthepairoffeedback

networks. For the best performance, it is recommended

that the source’s output impedance be compensated for.

If input impedance matching is required by the source,

–

+

LT1994

R

CHOSEN SO THAT R || R

= R

S

1

2

1

INM

S

–

R

CHOSEN TO BALANCE R || R

1

R

I

R

F

1994 F03

R

2

= R || R

S

1

Figure 3. Optimal Compensation for Signal Source Impedance

1994fa

12

LT1994

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APPLICATIO S I FOR ATIO

–

+

the input common mode voltage, it can be directly tied

R

I

V

IN

R

V

OUT

R

L

F

to the V

pin, but must be capable of driving a 40kΩ

OCM

equivalentresistancethatistiedtoamid-supplypotential.

If an external reference drives the V pin, it should still

be bypassed with a high quality 0.1μF capacitor to a low

impedance ground plane to ﬁlter any thermal noise and

to prevent common mode signals on this pin from being

inadvertently converted to differential signals.

V

S

OCM

V

INM

3

4

1

–

+

V

OCM

2

8

0.1µF

V

LT1994

–

OCM

V

CM

+

5

SHDN

6

V

7

Noise Considerations

INP

V

SHDNB

The LT1994’s input referred voltage noise is on the order

of 3nV/√Hz. Its input referred current noise is on the

order of 2.5pA/√Hz. In addition to the noise generated

by the ampliﬁer, the surrounding feedback resistors also

contribute noise. The output noise generated by both the

ampliﬁer and the feedback components is given by the

equation:

–

R

V

R

L

I

F

OUT

+

V

IN

1994 F04

Figure 4. Circuit for Common Mode Range

With singled ended inputs, there is an input signal com-

ponent to the input common mode voltage. Applying only

V

(setting V

to zero), the input common voltage is

INP

INM

2

approximately:

⎛

⎞

⎡

R_F⎤

R

I ⎦

2

e_ni• 1+

+ 2• I •R

+

(

)

n

F

⎜

⎝

⎟

⎠

⎢

⎥

+

–

⎣

⎛

V

IN

+ V

2

⎛ R

I

⎞

⎟

IN

e_no

=

V

=

≈ V_OCM

•

+

⎜

ICM

2

⎝R + R_F⎠

⎞

I

⎡R_F⎤

2

2• e_nRI

•

+ 2•e_nRF

⎜

⎟

⎠

⎢

⎥

R

⎛ R_F

⎞

⎟

V

INP

2

⎛ R_F

⎝R_F+ R ⎠

⎞

⎟

⎝

⎣ I ⎦

V_CM

•

+

•

⎜

⎝R_F+ R ⎠

I

A plot of this equation and a plot of the noise generated

by the feedback components are shown in Figure 6.

Output Common Mode Voltage Range

The LT1994’s input referred voltage noise contributes the

equivalent noise of a 560Ω resistor. When the feedback

The output common mode voltage is deﬁned as the aver-

age of the two outputs:

2

e

nRF2

nRI2

V_OUT⁺+ V_OUT

–

R

I2

R

F2

V_OUTCM= V_OCM

The V

=

2

i

n–

V /2

S

sets this average by an internal common mode

OCM

3

+

–

feedbackloopwhichinternallyforcesV

=–V

. The

OUT

4

2

1

2

8

e

ncm

–

+

output common mode range extends from approximately

2

V

LT1994

e

no

–

+

OCM

1.1V above V to approximately 0.8V below V . The V

OCM

–

+

5

2

pin sits in the middle of an 80kΩ to 80kΩ voltage divider

i

n+

6

that sets the default mid-supply open circuit potential.

7

–V /2

S

In single supply applications, where the LT1994 is used

to interface to an ADC, the optimal common mode input

range to the ADC is often determined by the ADC’s refer-

ence. If the ADC makes a reference available for setting

2

e

ni

e

nRF1

nRI1

R

I1

R

F1

1994 F05

Figure 5. Noise Analysis

1994fa

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APPLICATIO S I FOR ATIO

Power Dissipation Considerations

network is comprised of resistors whose values are less

than this, the LT1994’s output noise is voltage noise

dominant (See Figure 6):

The LT1994 is housed in either an 8-lead MSOP package

(θ = 140°C/W or an 8-lead DD package (θ = 160°C/

JA

W). The LT1994 combines high speed and large output

current with a small die and small package so there is

a need to be sure the die temperature does not exceed

150°C if housed in the 8-lead MSOP package, and 125°C

if housed in the 8-lead DD package. In the 8-lead MSOP,

⎛

⎝

R_F⎞

R ⎠

I

e_no≈ e • 1+

⎜

⎟

ni

Feedback networks consisting of resistors with values

greater than about 10kΩ will result in output noise which

is ampliﬁer current noise dominant.

–

LT1994 has its V lead fused to the frame so it is possible

tolowerthepackagethermalimpedancebyconnectingthe

–

e_no≈ 2 •I_n•R_F

V pin to a large ground plane or metal trace. Metal trace

and plated through holes can be used to spread the heat

generated by the device to the backside of the PC board.

For example, an 8-lead MSOP on a 3/32" FR-4 board with

Lower resistor values always result in lower noise at the

penalty of increased distortion due to increased loading of

thefeedbacknetworkontheoutput.Higherresistorvalues

will result in higher output noise, but improved distortion

due to less loading on the output.

2

540mm of 2oz. copper on both sides of the PC board tied

–

to the V pin can drop the θ from 140°C/W to 110°C/W

JA

(see Table 1).

100

The underside of the DD package has exposed metal

2

(4mm ) from the lead frame where the die is attached.

TOTAL (AMPLIFIER + FEEDBACK NETWORK)

OUTPUT NOISE

This provides for the direct transfer of heat from the die

junction to the printed circuit board to help control the

maximum operating junction temperature. The dual-in-

line pin arrangement allows for extended metal beyond

the ends of the package on the topside (component side)

of a circuit board. Table 1 summarizes for both the MSOP

and DD packages, the thermal resistance from the die

junction to ambient that can be obtained using various

amounts of topside, and backside metal (2oz. copper).

On multilayer boards, further reductions can be obtained

using additional metal on inner PCB layers connected

through vias beneath the package.

10

FEEDBACK NETWORK

NOISE ALONE

1

0.1

1

10

R

= R (kΩ)

I

F

1994 F06

Figure 6. LT1994 Output Spot Noise vs Spot Noise Contributed by

Feedback Network Alone

In general, the die temperature can be estimated from

Figure 6 shows the noise voltage that will appear differ-

entially between the outputs. The common mode output

noise voltage does not add to this differential noise. For

optimum noise and distortion performance, use a dif-

ferential output conﬁguration.

the ambient temperature T , and the device power dis-

A

sipation P :

D

+

T = T + P • θ

J

A

D

JA

1994fa

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LT1994

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APPLICATIO S I FOR ATIO

The power dissipation in the IC is a function of the supply

voltage, the output voltage, and the load resistance. For

fullydifferentialoutputampliﬁersatagivensupplyvoltage

To operate the device at higher ambient temperature,

–

connect more copper to the V pin to reduce the thermal

resistance of the package as indicated in Table 1. Note that

( V ), and a given differential load (R

), the worst-

LOAD

T

JMAX

for the 8-lead DD package is 125°C (as opposed to

CC

case power dissipation P

occurs at the worst case

150°C for the 8-lead MSOP), and the data for the equation

above should be altered accordingly.

D(MAX)

quiescent current (I

= 20.5mA) and when the load

current is given by the expression:

Q(MAX)

Table 1. LT1994 MSOP and DD Package Thermal Resistivity

LT1994 8-LEAD MSOP PACKAGE

LT1994 8-LEAD DD PACKAGE

V_CC

R_LOAD

I_LOAD

=

Copper Area Copper Area

Thermal

Copper Area

Topside

Thermal

Resistance

(Junction to

Ambient)

Topside

Backside

Resistance

(Junction to

Ambient)

2

(mm )

The worst case power dissipation in the LT1994 at

0

140

135

130

120

110

4

16

160

135

110

95

V_CC

R_LOAD

I_LOAD

=

is:

30

100

540

0

32

2

100

540

64

P_{D MAX}= 2•V_CC• I_LOAD+ I

– I_LOAD•

(

)

Q MAX

(

)

130

70

2

V_CC

R_LOAD

=

+ 2•V_CC•I_Q₍_MAX

)

R_LOAD

Layout Considerations

BecausetheLT1994isahighspeedampliﬁer,itissensitive

to both stray capacitance and stray inductance. Compo-

nents connected to the LT1994 should be connected with

as short and direct connections as possible. A low noise,

low impedance ground plane is critical for the highest

performance. In single supply applications, high quality

surface mount 1μF and 0.1μF ceramic bypass capacitors

with minimum PCB trace should be used directly across

Example: A LT1994 is mounted on a circuit board in a

MSOP-8 package (θ = 140°C/W), and is running off of

JA

5Vsuppliesdrivinganequivalentload(externalloadplus

feedback network) of 75Ω. The worst-case power that

would be dissipated in the device occurs when:

2

V_CC

P_D₍_MAX

5V²

=

+ 2• V_CC•I_Q₍_MAX

=

)

R_LOAD

+

–

the power supplies V to V . In split supply applications,

high quality surface mount 1μF and 0.1μF ceramic bypass

capacitors should be placed across the power supplies

+ 2•5V •17.5MA = 0.54W

75Ω

+

–

V to V , and individual high quality surface mount 0.1μF

bypass caps should be used from each supply to ground

with direct (short) connections.

The maximum ambient temperature the 8-lead MSOP is

allowed to operate under these conditions is:

T = T

– P • θ = 150°C – (0.54W) •

D JA

A

JMAX

(140°C/W) = 75°C

1994fa

15

LT1994

U

W U U

APPLICATIO S I FOR ATIO

Any stray parasitic capacitance to ground at the summing

It is highly recommended that the V

pin be either hard

OCM

+

–

junctions, IN and IN should be kept to an absolute mini-

mum even if it means stripping back the ground plane

away from any trace attached to this node. This becomes

especially true when the feedback resistor network uses

tied to a low impedance ground plane (in split supply

applications) or bypassed to ground with a high quality

0.1μF ceramic capacitor in single supply applications.

This will help prevent thermal noise from the internal

80kΩ-80kΩ voltage divider (25nV/√Hz) and other exter-

nal sources of noise from being converted to differential

noise due to mismatches in the feedback networks. It is

also recommended that the resistive feedback networks

be comprised of 1% resistors (or better) to enhance the

output common mode rejection. This will also prevent

resistor values >500Ω in circuits with R = R . Excessive

F

I

peaking in the frequency response can be mitigated by

adding small amounts of feedback capacitance around RF

(2pF to 5pF). Always keep in mind the differential nature of

theLT1994,andthatitiscriticalthattheoutputimpedances

seen by both outputs (stray or intended) should be as bal-

anced and symmetric as possible. This will help preserve

the natural balance of the LT1994, which minimizes the

generation of even order harmonics, and preserves the

rejection of common mode signals and noise.

V

input referred common mode noise of the common

OCM

mode ampliﬁer path (which cannot be ﬁltered) from being

converted to differential noise, degrading the differential

noise performance.

W

SI PLIFIED SCHE ATIC

+

V

120k

+

V

SHUTDOWN

CIRCUIT

I1

55k

SHDN

C

M1

C

M2

–

+

V

+

V

+

V

Q9

Q11

Q12

+

–

+

–

BIAS

ADJUST

–

+

OUT

ADJUST

Q10

V

Gm

2A

2B

–

+

–

+

V

–

V

+

V

+

–

+

–

V

OUT

V

I2

R1

4k

80k

I3

Q7

Q8

V

OCM

R2

4k

Q1

Q2

Q5 Q6

–

D1 D2

D3 D4

IN

–

OUT

V

Q3

Q4

CM

ADJUST

–

+

V

I4A

I4B

–

+

V

1994 SS01

–

V

1994fa

16

LT1994

U

TYPICAL APPLICATIO S

Differential 1st Order Lowpass Filter

Example: The speciﬁed –3dB frequency is 1MHz Gain = 4

Maximum –3dB frequency (f ) 5MHz

1. Using f = 1000kHz, C11 = 400pF

3dB abs

3dB

Stopband attenuation: –6dB at 2 • f and 14dB at 5 • f

2. Nearest standard 5% value to 400pF is 390pF and C11

= C12 = 390pF

3dB

C11

3. Using f = 1000kHz, C11 = 390pF and Gain = 4, R21

3dB

= R22 = 412Ω and R11 = R12 = 102Ω (nearest 1%

value)

R11

R21

–

V

IN

+

V

0.1µF

Differential 2nd Order Butterworth Lowpass Filter

3

4

1

2

8

+

–

– +

LT1994

V

OUT

Maximum –3dB frequency (f ) 2.5MHz

3dB

0.1µF

Stopband attenuation: –12dB at 2 • f and –28dB at 5 • f

3dB

+ –

5

6

7

R21

+

V

C21

IN

R11

C11

R12

R31

R12

R22

C12

–

V

IN

+

V

0.1µF

1994 TA03

3

4

1

2

8

+

–

– +

V

OUT

Component Calculation:

LT1994

0.1µF

R11 = R12, R21 = R22

+ –

6

5

7

5MHz

f_3dB

f_3dB≤5MHz and Gain ≤

+

V

IN

R32

R22

C22

1. Calculate an absolute value for C11 (C11 ) using a

abs

1994 TA04

speciﬁed –3dB frequency

4•10⁵

f_3dB

Component Calculation:

C11_abs

=

(C11_absin pF and f_3dBin kHz)

R11 = R12, R21 = R22, R31 = R32, C21 = C22,

C11 = 10 • C21, R1 = R11, R2 = R21, R3 = R31,

C2 = C21 and C1 = C11

2. Selectastandard5%capacitorvaluenearesttheabsolute

value for C11

3. Calculate R11 and R21 using the standard 5% C11

value, f and desired gain

3dB

R11 and R21 equations (C11 in pF and f in kHz)

3dB

159.2•10⁶

R21=

C11• f_3dB

R21

Gain

R11=

1994fa

17

LT1994

U

TYPICAL APPLICATIO S

1. Calculate an absolute value for C2 (C2 ) using a

Example: The speciﬁed –3dB frequency is 1MHz Gain = 1

1. Using f = 1000kHz, C2 = 400pF

abs

speciﬁed –3dB frequency

3dB

abs

4•10⁵

f_3dB

2. Nearest standard 5% value to 400pF is 390pF and C21

= C22 = 390pF and C11 = 3900pF

C2_abs

=

(C2_absin pF and f_3dBin kHz)(Note 2)

3. Using f

= 1000kHz, C2 = 390pF and Gain = 1, R1

3dB

2. Selectastandard5%capacitorvaluenearesttheabsolute

value for C2 (C1 = 10 • C2)

= 549Ω, R2 = 549Ω and R3 = 15.4Ω (nearest 1%

values). R11 = R21 = 549Ω, R21 = R22 = 549Ω and

R31 = R32 = 15.4Ω.

3. Calculate R3, R2 and R1 using the standard 5% C2

value, the speciﬁed f

gain (Gn)

and the speciﬁed passband

3dB

Note 1: The equations for R1, R2, R3 are ideal and do

notaccountfortheﬁnitegainbandwidthproduct(GBW)

of the LT1994 (70MHz). The maximum gain is set by

the C1/C2 ratio (which for convenience is set equal to

ten).

2.5MHz

f_3dB

f_3dB≤2.5MHz and Gain ≤8.8 or Gain ≤

R1, R2 and R3 equations (C2 in pF and f in kHz)

Note 2: The calculated value of a capacitor is chosen

to produce input resistors less than 600Ω. If a higher

valueinputresistanceisrequiredthenmultiplyallresis-

tor values and divide all capacitor values by the same

number.

3dB

1.121– 1.131– 0.127 •Gn •10⁸

(

)

(

)

R3=

(Note 1)

Gn +1 •C2• f

1.266 •10¹⁵

(

)

3dB

R2=

R1=

2

R3•C2²• f_3dB

R2

Gn

A Single Ended to Differential Voltage Conversion with Source Impedance Matching and Level Shifting

50Ω

R

= 50Ω

374Ω

402Ω

S

+

V

IN

0.1µF

V

54.9Ω

3

4

1

2

8

–

+

– +

V

OUT

V

+

–

V

+ 0.25V

– 0.25V

V

OCM

OUT

V

LT1994

5

V

OCM

0

0.1µF

OUT

V

IN

+ –

1

0

t

6

7

t

1994 TA05

–1

402Ω

1994fa

18

LT1994

U

PACKAGE DESCRIPTIO

DD Package

8-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1698)

R = 0.115

0.38 0.10

8

TYP

5

0.675 0.05

3.5 0.05

2.15 0.05 (2 SIDES)

1.65 0.05

3.00 0.10

(4 SIDES)

1.65 0.10

(2 SIDES)

PIN 1

TOP MARK

(NOTE 6)

PACKAGE

OUTLINE

(DD8) DFN 1203

4

1

0.25 0.05

0.75 0.05

0.200 REF

0.25 0.05

0.50 BSC

0.50

BSC

2.38 0.05

(2 SIDES)

2.38 0.10

(2 SIDES)

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON TOP AND BOTTOM OF PACKAGE

MS8 Package

8-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1660)

3.00 0.102

(.118 .004)

(NOTE 3)

0.52

(.0205)

REF

0.889 0.127

(.035 .005)

8

7 6 5

3.00 0.102

(.118 .004)

(NOTE 4)

5.23

4.90 0.152

(.193 .006)

3.20 – 3.45

(.206)

DETAIL “A”

0° – 6° TYP

0.254

(.010)

(.126 – .136)

MIN

GAUGE PLANE

0.65

(.0256)

BSC

0.42 0.038

(.0165 .0015)

TYP

1

2

3

4

0.53 0.152

(.021 .006)

1.10

(.043)

MAX

0.86

(.034)

REF

RECOMMENDED SOLDER PAD LAYOUT

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.22 – 0.38

0.127 0.076

NOTE:

(.009 – .015)

(.005 .003)

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

0.65

(.0256)

BSC

TYP

MSOP (MS8) 0204

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

1994fa

InformationfurnishedbyLinearTechnologyCorporationisbelievedtobeaccurateandreliable.However,

no responsibility is assumed for its use. Linear Technology Corporation makes no representation that

the interconnection of its circuits as described herein will not infringe on existing patent rights.

19

LT1994

U

TYPICAL APPLICATIO

RFID Receiver Front-End, 20kHz < –3dB BW < 5MHz

(Baseband Gain = 2)

82pF

0.056µF

140Ω

402Ω

0.1µF

5V

3

1

7

2

8

4

5V

LT1994

I

OUT

BPF

270pF

0.1µF

V

LT5516

+

CC

5

+

RF

6

I

OUT

0.056µF

140Ω

402Ω

–

I

OUT

0°

82pF

–

RF

5V

82pF

270pF

LO INPUT

+

–

0.056µF

LO

+

402Ω

Q

OUT

0°/90°

5V

0.1µF

–

90°

LO

EN

3

1

7

2

8

270pF

4

ENABLE

5V

LT1994

Q

OUT

0.1µF

5

6

0.056µF

140Ω

402Ω

82pF

1994 TA02

RELATED PARTS

PART NUMBER

LT1167

DESCRIPTION

Precision, Instrumentation Amp

COMMENTS

Single Gain Set Resistor: G = 1 to 10,000

LT1806/LT1807

LT1809/LT1810

LT1990

Single/Dual Low Distortion Rail-to-Rail Amp

High Voltage Gain Selectable Differential Amp

Precision Gain Selectable Differential Amp

Fully Differential Input/Output Ampliﬁers

Low Distortion and Noise, Differential In/Out

High Speed Gain Selectable Differential Amp

325MHz, 140V/µs Slew Rate, 3.5nV/√Hz Noise

180MHz, 350V/µs Slew Rate, Shutdown

250V Common Mode, Micropower, Gain = 1, 10

Micropower, Pin Selectable Gain = –13 to 14

Programmable Gain or Fixed Gain (G = 1, 2, 5, 10)

Fixed Gain (G = 2, 4, 10)

LT1991

LTC1992/LTC1992-x

LT1993-2/-4/-10

LT1995

30MHz, 1000V/µs, Pin Selectable Gain = –7 to 8

Pin Selectable Gain = 9 to 117

LT1996

Precision, 100µA, Gain Selectable Differential Amp

LT6600-2.5/-5/-10/-15/-20 Differential Amp and Lowpass, Chebyshev Filter

Filter Cutoff = 2.5MHz, 5MHz, 10MHz, 15MHz or 20MHz

1994fa

LT 0306 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

20

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT1994IMS8
厂家：	Linear
描述：	Low Noise, Low Distortion Fully Differential Input/Output Amplifi er/Driver 低噪声，低失真全差动输入/输出功率放大器器/驱动器驱动器放大器功率放大器
文件：	总20页 (文件大小：289K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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