LT2178A_技术文档

LTC1966

Precision Micropower

∆∑ RMS-to-DC Converter

FeaTures

DescripTion

The LTC^®1966 is a true RMS-to-DC converter that utilizes

an innovative patented DS computational technique. The

internal delta sigma circuitry of the LTC1966 makes it sim-

pler to use, more accurate, lower power and dramatically

more flexible than conventional log antilog RMS-to-DC

converters.

n

Simple to Use, Requires One Capacitor

n

True RMS DC Conversion Using DS Technology

n

High Accuracy:

0.1% Gain Accuracy from 50Hz to 1kHz

0.25% Total Error from 50Hz to 1kHz

High Linearity:

n

0.02% Linearity Allows Simple System Calibration

The LTC1966 accepts single-ended or differential input

signals(forEMI/RFIrejection)andsupportscrestfactorsup

to 4. Common mode input range is rail-to-rail. Differential

n

Low Supply Current:

155µA Typ, 170µA Max

Ultralow Shutdown Current:

0.1µA

Constant Bandwidth:

n

input range is 1V

, and offers unprecedented linearity.

PEAK

Unlike previously available RMS-to-DC converters, the

superiorlinearityoftheLTC1966allowshasslefreesystem

calibration at any input voltage.

n

Independent of Input Voltage

800kHz –3dB, 6kHz 1%

Flexible Supplies:

The LTC1966 also has a rail-to-rail output with a separate

output reference pin providing flexible level shifting. The

LTC1966 operates on a single power supply from 2.7V to

5.5V or dual supplies up to 5.5V. A low power shutdown

mode reduces supply current to 0.5µA.

n

2.7V to 5.5V Single Supply

Up to 5.5V Dual Supply

n

Flexible Inputs:

Differential or Single-Ended

The LTC1966 is insensitive to PC board soldering and

stresses, as well as operating temperature. The LTC1966

is packaged in the space saving MSOP package which is

ideal for portable applications.

Rail-to-Rail Common Mode Voltage Range

Up to 1V

Differential Voltage

PEAK

Flexible Output:

n

Rail-to-Rail Output

Separate Output Reference Pin Allows Level Shifting

Wide Temperature Range:

–55°C to 125°C

applicaTions

n

True RMS Digital Multimeters and Panel Meters

n

Small Size:

True RMS AC + DC Measurements

Space Saving 8-Pin MSOP Package

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

No Latency DS is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners. Protected by U.S. Patents including 6359576, 6362677,

6516291 and 6651036.

Quantum Leap in Linearity Performance

Typical applicaTion

0.2

LTC1966, ∆∑

0

Single Supply RMS-to-DC Converter

2.7V TO 5.5V

–0.2

–0.4

V

DD

OUTPUT

LTC1966

OUT RTN

GND

IN1

IN2

C

DIFFERENTIAL

INPUT

+

–

AVE

V

OUT

1µF

–0.6

CONVENTIONAL

LOG/ANTILOG

1966 TA01

EN

V

SS

0.1µF

OPT. AC

COUPLING

–0.8

60Hz SINEWAVES

–1.0

0

50 100 150 200 250 300 350 400 450 500

V

(mV AC

)

RMS

IN

1966 TA01b

1966fb

1

LTC1966

absoluTe MaxiMuM raTings

pin conFiguraTion

(Note 1)

Supply Voltage

V

to GND............................................. –0.3V to 7V

DD

SS

to V ............................................ –0.3V to 12V

SS

to GND............................................. –7V to 0.3V

TOP VIEW

Input Currents (Note 2)...................................... 10mA

Output Current (Note 3) ..................................... 10mA

ENABLE Voltage ....................... V – 0.3V to V + 12V

GND

IN1

IN2

1

2

3

4

8 ENABLE

7 V

DD

6 OUT RTN

5 V

V

SS

OUT

OUT RTN Voltage............................... V – 0.3V to V

MS8 PACKAGE

8-LEAD PLASTIC MSOP

SS

DD

Operating Temperature Range (Note 4)

T

= 150°C, θ = 220°C/W

JA

JMAX

LTC1966C/LTC1966I ............................–40°C to 85°C

LTC1966H .......................................... –40°C to 125°C

LTC1966MP ....................................... –55°C to 125°C

Specified Temperature Range (Note 5)

LTC1966C/LTC1966I ............................–40°C to 85°C

LTC1966H .......................................... –40°C to 125°C

LTC1966MP ....................................... –55°C to 125°C

Maximum Junction Temperature ......................... 150°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

orDer inForMaTion

LEAD FREE FINISH

LTC1966CMS8#PBF

LTC1966IMS8#PBF

LTC1966HMS8#PBF

LTC1966MPMS8#PBF

TAPE AND REEL

PART MARKING*

PACKAGE DESCRIPTION

8-Lead Plastic MSOP

TEMPERATURE RANGE

LTC1966CMS8#TRPBF

LTC1966IMS8#TRPBF

LTC1966HMS8#TRPBF

LTTG

LTTH

LTTG

0°C to 70°C

–40°C to 85°C

–40°C to 125°C

–55°C to 125°C

LTC1966MPMS8#TRPBF LTTG

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_DD= 5V, V_SS= –5V, V_OUTRTN= 0V, C_AVE= 10µF, V_IN= 200mV_RMS

V_ENABLE= 0.5V unless otherwise noted.

,

SYMBOL PARAMETER

Conversion Accuracy

CONDITIONS

MIN

TYP

MAX

UNITS

G

Conversion Gain Error

Output Offset Voltage

Linearity Error

50Hz to 1kHz Input (Notes 6, 7)

LTC1966C, LTC1966I

0.1

0.3

0.4

0.7

%

ERR

l

LTC1966H, LTC1966MP

V

OOS

(Notes 6, 7)

LTC1966C, LTC1966I

LTC1966H, LTC1966MP

0.1

0.2

0.4

0.6

mV

l

LIN

50mV to 350mV (Notes 7, 8)

0.02

0.15

%

ERR

1966fb

2

LTC1966

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

V_ENABLE= 0.5V unless otherwise noted.

temperature range, otherwise specifications are at T_A= 25°C. V_DD= 5V, V_SS= –5V, V_OUTRTN= 0V, C_AVE= 10µF, V_IN= 200mV_RMS

,

SYMBOL PARAMETER

PSRR Power Supply Rejection

CONDITIONS

MIN

TYP

MAX

UNITS

(Note 9)

LTC1966C, LTC1966I

LTC1966H, LTC1966MP

0.02

0.15

0.20

0.3

%V

l

V

IOS

Input Offset Voltage

(Notes 6, 7, 10)

0.02

0.8

1.0

mV

l

Accuracy vs Crest Factor (CF)

CF = 4

l

60Hz Fundamental, 200mV

(Note 11)

–1

2

mV

RMS

CF = 5

–20

30

RMS

Input Characteristics

l

I

Input Voltage Range

Input Impedance

(Note 14)

V

DD

V

VR

SS

Z

Average, Differential (Note 12)

Average, Common Mode (Note 12)

8

100

MΩ

IN

l

CMRRI

Input Common Mode Rejection

Maximum Input Swing

Minimum RMS Input

(Note 13)

7

200

5

µV/V

V

IMAX

V

IMIN

Accuracy = 1% (Note 14)

1

1.05

mV

l

PSRRI

Power Supply Rejection

V

DD

V

SS

Supply (Note 9)

250

120

600

300

µV/V

Output Characteristics

OVR Output Voltage Range

Output Impedance

l

V

SS

DD

Z

OUT

V

= 0.5V (Note 12)

= 4.5V

75

85

30

95

kΩ

ENABLE

l

CMRRO Output Common Mode Rejection

(Note 13)

16

200

µV/V

V

OMAX

Maximum Differential Output Swing

Accuracy = 2%, DC Input (Note 14)

1.0

0.9

1.05

V

l

PSRRO

Power Supply Rejection

V

Supply (Note 9)

250

50

1000

500

µV/V

DD

SS

Frequency Response

f

1% Additional Error (Note 15)

10% Additional Error (Note 15)

3dB Frequency (Note 15)

C

= 10µF

6

kHz

1P

AVE

20

10P

–3dB

AVE

800

Power Supplies

l

V

Positive Supply Voltage

Negative Supply Voltage

Positive Supply Current

2.7

5.5

0

V

DD

SS

V

(Note 16)

–5.5

I

IN1 = 20mV, IN2 = 0V

IN1 = 200mV, IN2 = 0V

155

158

170

µA

DD

l

Negative Supply Current

IN1 = 20mV, IN2 = 0V

12

20

10

µA

SS

Shutdown Characteristics

l

I

Supply Currents

V

= 4.5V

0.5

µA

DDS

SSS

ENABLE

l

I

–1

–2

–0.1

µA

ENABLE

LTC1966H, LTC1966MP

l

I

ENABLE Pin Current High

V

= 4.5V

–0.3

–0.05

µA

IH

ENABLE

1966fb

3

LTC1966

elecTrical characTerisTics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_DD= 5V, V_SS= –5V, V_OUTRTN= 0V, C_AVE= 10µF, V_IN= 200mV_RMS

V_ENABLE= 0.5V unless otherwise noted.

,

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

I

ENABLE Pin Current Low

V

= 0.5V

–2

–10

–1

–0.1

µA

IL

ENABLE

LTC1966H, LTC1966MP

V

TH

ENABLE Threshold Voltage

V

DD

V

DD

V

DD

= 5V, V = –5V

2.4

2.1

1.3

V

SS

= 5V, V = GND

SS

= 2.7V, V = GND

SS

V

ENABLE Threshold Hysteresis

0.1

V

HYS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 11: High speed automatic testing cannot be performed with 60Hz

inputs. The LTC1966 is 100% tested with DC stimulus. Correlation tests

have shown that the performance limits above can be guaranteed with the

additional testing being performed to verify proper operation of all internal

circuitry.

Note 2: The inputs (IN1, IN2) are protected by shunt diodes to V and

SS

V

. If the inputs are driven beyond the rails, the current should be limited

Note 12: The LTC1966 is a switched capacitor device and the input/

output impedance is an average impedance over many clock cycles. The

input impedance will not necessarily lead to an attenuation of the input

signal measured. Refer to the Applications Information section titled Input

Impedance for more information.

Note 13: The common mode rejection ratios of the LTC1966 are measured

with DC inputs from 50mV to 350mV. The input CMRR is defined as the

DD

to less than 10mA.

Note 3: The LTC1966 output (V ) is high impedance and can be

overdriven, either sinking or sourcing current, to the limits stated.

OUT

Note 4: The LTC1966C/LTC1966I are guaranteed functional over

the operating temperature range of –40°C to 85°C. The LTC1966H/

LTC1966MP are guaranteed functional over the operating temperature

range of –55°C to 125°C.

Note 5: The LTC1966C is guaranteed to meet specified performance from

0°C to 70°C. The LTC1966C is designed, characterized and expected to

meet specified performance from –40°C to 85°C but is not tested nor

QA sampled at these temperatures. The LTC1966I is guaranteed to meet

specified performance from –40°C to 85°C. The LTC1966H is guaranteed

to meet specified performance from –40°C to 125°C. The LTC1966MP is

guaranteed to meet specified performance from –55°C to 125°C.

change in V measured between input levels of V to V + 350mV and

IOS

SS

input levels of V – 350mV to V divided by V – V – 350mV. The

DD

SS

output CMRR is defined as the change in V measured with OUT RTN =

OOS

V

SS

and OUT RTN = V – 350mV divided by V – V – 350mV.

DD DD SS

Note 14: Each input of the LTC1966 can withstand any voltage within

the supply range. These inputs are protected with ESD diodes, so going

beyond the supply voltages can damage the part if the absolute maximum

current ratings are exceeded. Likewise for the output pins. The LTC1966

input and output voltage swings are limited by internal clipping. The

maximum differential input of the LTC1966 (referred to as maximum input

swing) is 1V. This applies to either input polarity, so it can be thought of as

1V. Because the differential input voltage gets processed by the LTC1966

with gain, it is subject to internal clipping. Exceeding the 1V maximum

can, depending on the input crest factor, impact the accuracy of the output

voltage, but does not damage the part. Fortunately, the LTC1966’s ∆∑

topology is relatively tolerant of momentary internal clipping. The input

clipping is tested with a crest factor of 2, while the output clipping is

tested with a DC input.

Note 15: The LTC1966 exploits oversampling and noise shaping to reduce

the quantization noise of internal 1-bit analog-to-digital conversions. At

higher input frequencies, increasingly large portions of this noise are

aliased down to DC. Because the noise is shifted in frequency, it becomes

a low frequency rumble and is only filtered at the expense of increasingly

long settling times. The LTC1966 is inherently wideband, but the output

accuracy is degraded by this aliased noise. These specifications apply with

Note 6: High speed automatic testing cannot be performed with

C

= 10µF. The LTC1966 is 100% tested with C = 22nF. Correlation

AVE

tests have shown that the performance limits above can be guaranteed

with the additional testing being performed to guarantee proper operation

of all the internal circuitry.

Note 7: High speed automatic testing cannot be performed with 60Hz

inputs. The LTC1966 is 100% tested with DC and 10kHz input signals.

Measurements with DC inputs from 50mV to 350mV are used to calculate

the four parameters: G , V , V and linearity error. Correlation tests

ERR OOS IOS

have shown that the performance limits above can be guaranteed with the

additional testing being performed to guarantee proper operation of all

internal circuitry.

Note 8: The LTC1966 is inherently very linear. Unlike older log/antilog

circuits, its behavior is the same with DC and AC inputs, and DC inputs are

used for high speed testing.

Note 9: The power supply rejections of the LTC1966 are measured with DC

inputs from 50mV to 350mV. The change in accuracy from V = 2.7V to

DD

C

AVE

= 10µF and constitute a 3-sigma variation of the output rumble.

V

DD

V

SS

= 5.5V with V = 0V is divided by 2.8V. The change in accuracy from

SS

Note 16: The LTC1966 can operate down to 2.7V single supply but cannot

operate at 2.7V. This additional constraint on V can be expressed

= 0V to V = –5.5V with V = 5.5V is divided by 5.5V.

SS

DD

SS

Note 10: Previous generation RMS-to-DC converters required nonlinear

input stages as well as a nonlinear core. Some parts specify a DC reversal

error, combining the effects of input nonlinearity and input offset voltage.

The LTC1966 behavior is simpler to characterize and the input offset

voltage is the only significant source of DC reversal error.

mathematically as –3 • (V – 2.7V) ≤ V ≤ Ground.

DD

SS

1966fb

4

LTC1966

Typical perForMance characTerisTics

Gain and Offsets

vs Input Common Mode

0.5

0.4

0.5

0.4

0.5

0.4

1.0

V

DD

V

SS

= 5V

= –5V

V

DD

V

SS

= 5V

= GND

V

DD

V

SS

= 2.7V

= GND

0.4

0.8

V

IOS

V

IOS

0.3

0.6

0.2

0.4

V

OOS

GAIN ERROR

0.1

0.2

GAIN ERROR

0

V

OOS

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

–0.2

–0.4

–0.6

–0.8

–1.0

V

OOS

IOS

–5 –4 –3 –2 –1

0

1

2

3

4

5

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

INPUT COMMON MODE (V)

0

0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7

INPUT COMMON MODE (V)

1966 G03

1966 G02

1966 G01

Gain and Offsets

vs Output Common Mode

0.5

0.4

1.0

0.5

0.4

0.5

0.4

0.5

V

DD

V

SS

= 2.7V

= GND

V

DD

V

SS

= 5V

= –5V

V

DD

V

SS

= 5V

= GND

0.8

0.4

V

IOS

0.3

0.6

0.3

V

IOS

0.2

0.4

0.2

V

OOS

GAIN ERROR

V

OOS

0.1

0.2

0.1

0

GAIN ERROR

V

IOS

–0.1

–0.2

–0.3

–0.4

–0.5

–0.2

–0.4

–0.6

–0.8

–1.0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

V

OOS

0

0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7

OUTPUT COMMON MODE (V)

–5 –4 –3 –2 –1

0

1

2

3

4

5

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

OUTPUT COMMON MODE (V)

1966 G04

1966 G06

1966 G05

Gain and Offsets vs Temperature

0.5

0.4

0.5

0.4

1.0

0.5

0.4

0.5

V

DD

V

SS

= 5V

= –5V

V

DD

V

SS

= 2.7V

= GND

V

DD

V

SS

= 5V

= GND

0.4

0.8

0.4

V

IOS

0.3

0.6

0.3

V

IOS

0.2

0.4

0.2

GAIN ERROR

V

OOS

0.1

0.2

0.1

0

V

IOS

GAIN ERROR

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

–0.2

–0.4

–0.6

–0.8

–1.0

–0.1

–0.2

–0.3

–0.4

–0.1

–0.2

–0.3

–0.4

–0.5

V

OOS

–0.5

–60 –40 –20

0

20 40 60 80 100 120 140

TEMPERATURE (°C)

–60 –40

20 40 60 80 100 120 140

TEMPERATURE (°C)

–60 –40 –20

0

20 40 60 80 100 120 140

TEMPERATURE (°C)

1966 G09

1966 G07

1966 G08

1966fb

5

LTC1966

Typical perForMance characTerisTics

Gain and Offsets vs V_SSSupply

Gain and Offsets vs V_DDSupply

Performance vs Crest Factor

0.5

0.4

0.5

0.4

1

201.0

200.8

200.6

200.4

200.2

200.0

199.8

200mV

SCR WAVEFORMS

V

= 5V

V

SS

= GND

RMS

= 10µF

DD

0.4

0.8

C

V

AVE

= 5V

DD

0.3

0.6

O.1%/DIV

V

IOS

V

0.2

0.4

IOS

V

OOS

GAIN ERROR

0.1

0.2

20Hz

60Hz

GAIN ERROR

0

100Hz

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

–0.2

–0.4

–0.6

–0.8

–1.0

V

OOS

3.5 4.0

1.0 1.5 2.0 2.5 3.0

4.5 5.0

–6

–5

–4

–3

(V)

–2

–1

0

2.5

3.0

3.5

4.0

(V)

4.5

5.0

5.5

CREST FACTOR

V

SS

DD

1966 G15

1966 G11

1966 G10

Output Accuracy vs Signal

Amplitude

Performance vs Large Crest Factors

AC Linearity

10

5

230

0.20

0.15

0.10

0.05

0

FUNDAMENTAL

FREQUENCY

AC INPUTS = 60Hz

SINEWAVES

= GND

1% ERROR

60Hz SINEWAVES

C

V

= 1µF

= GND

220

210

AVE

IN2

V

60Hz

IN2

20Hz

0

200

190

180

170

160

250Hz

100Hz

–5

AC INPUT

DD

–1% ERROR

V

= 5V

–0.05

–0.10

–0.15

–0.20

–10

–15

–20

DC INPUT

V

DD

= 5V

200mV

SCR WAVEFORMS

RMS

= 4.7µF

C

V

AVE

= 5V

AC INPUT

= 3V

DD

V

DD

5%/DIV

150

0

0.5

1

1.5

2

2.5

2

3

4

5

6

7

8

1

0

50 100 150 200 250 300 350 400 450 500

(mV AC

V

(V

)

IN1 RMS

CREST FACTOR

V

)

RMS

IN1

1966 G24

1966 G12

1966 G13

Shutdown Currents

vs ENABLE Voltage

Quiescent Supply Currents

vs Supply Voltage

DC Linearity

200

175

150

125

100

75

0.10

0.08

250

200

150

100

50

V

= GND

C

V

= 1µF

SS

V

= 5V

DD

AVE

IN2

= GND

I

DD

0.06

I

DD

0.04

0.02

500

250

0

I

EN

–0.02

–0.04

–0.06

–0.08

–0.10

50

I

SS

0

EFFECT OF OFFSETS

MAY BE POSITIVE

OR NEGATIVE

25

–50

–100

–250

–500

0

I

SS

–25

–500

–300

–100

V

100

(mV)

300

500

0

1

2

5

6

4

6

3

4

0

1

2

3

5

V

SUPPLY VOLTAGE (V)

ENABLE PIN VOLTAGE (V)

DD

IN1

1966 G14

1966 G16

1966 G18

1966fb

6

LTC1966

Typical perForMance characTerisTics

Quiescent Supply Currents

Input Signal Bandwidth

vs Temperature

40

1000

100

10

170

202

200

198

196

0.1%

1%

10%

ERROR ERROR

ERROR

V

= 5V, V = –5V

SS

DD

35

30

25

160

150

= 5V, V = GND

SS

DD

–3dB

140

130

120

110

100

90

V

= 2.7V, V = GND

SS

DD

194

192

20

15

10

190

188

186

184

182

V

= 5V, V = –5V

SS

DD

V

DD

= 2.7V, V = GND

SS

V

= 5V, V = GND

SS

DD

5

0

1%/DIV

= 2.2µF

C

AVE

1

–40 –20

40 60 80 100 120 140

–60

0

20

100

1K

10K

100K

1M

1

10

100

1000

INPUT SIGNAL FREQUENCY (Hz)

TEMPERATURE (°C)

INPUT FREQUENCY (kHz)

1966 G19

1966 G20

1966 G17

Common Mode Rejection Ratio

vs Frequency

Bandwidth to 100kHz

DC Transfer Function Near Zero

110

100

90

80

70

60

50

40

30

20

202

201

30

25

20

15

10

5

0.5%/DIV

AVE

V

= 5V

V

= GND

DD

SS

IN2

THREE REPRESENTITIVE UNITS

C

= 47µF

= –5V

5V INꢀUT CONVERSION

TO DC OUTꢀUT

200

199

198

197

196

0

–5

–10

195

0

30

50 60 70 80 90 100

10 20

40

10

100

1k

10k

100k

1M

0

5

–20 –15 –10 –5

10 15 20

INPUT FREQUENCY (kHz)

FREQUENCY (Hz)

V

(mV DC)

IN1

1966 G23

1966 G21

1966 G22

1966fb

7

LTC1966

pin FuncTions

GND (Pin 1): Ground. A power return pin.

OUT RTN (Pin 6): Output Return. The output voltage is

created relative to this pin. The V and OUT RTN pins

OUT

IN1 (Pin 2): Differential Input. DC coupled (polarity is

irrelevant).

are not balanced and this pin should be tied to a low

impedance, both AC and DC. Although it is typically tied

IN2 (Pin 3): Differential Input. DC coupled (polarity is

irrelevant).

to GND, it can be tied to any arbitrary voltage, V < OUT

SS

RTN < (V – Max Output). Best results are obtained when

DD

OUT RTN = GND.

V

(Pin 4): Negative Voltage Supply. GND to –5.5V.

SS

V

DD

(Pin 7): Positive Voltage Supply. 2.7V to 5.5V.

(Pin 5): Output Voltage. This is high impedance.

OUT

The RMS averaging is accomplished with a single shunt

capacitor from this node to OUT RTN. The transfer func-

tion is given by:

ENABLE (Pin 8): An Active Low Enable Input. LTC1966

is debiased if open circuited or driven to V . For normal

DD

operation, pull to GND, a logic low or even V .

SS



²

V

OUT

– OUT RTN = Average IN2 –IN1

(

)

(

)









1966fb

8

LTC1966

applicaTions inForMaTion

START

NOT

READ

SURE

DO YOU

NEED TRUE RMS-TO-DC

CONVERSION?

FIND SOMEONE WHO DOES

AND GIVE THEM THIS

DATA SHEET

NO

RMS-TO-DC

CONVERSION

YES

CONTACT LTC BY PHONE OR

NO

DO YOU

HAVE ANY LTC1966s

YET?

AT www.linear.com AND

GET SOME NOW

YES

DID

DO YOU WANT TO

KNOW HOW TO USE THE

LTC1966 FIRST?

NO

YES

YOU ALREADY TRY OUT

THE LTC1966?

YES

NO

READ THE TROUBLESHOOTING

NO

DID

GUIDE. IF NECESSARY, CALL

READ THE DESIGN COOKBOOK

YOUR CIRCUIT

WORK?

LTC FOR APPLICATIONS SUPPORT

YES

NOW DOES YOUR

READ THE TROUBLESHOOTING

GUIDE AGAIN OR CALL LTC

FOR APPLICATIONS SUPPORT

YES

RMS CIRCUIT WORK

NO

CONTACT LTC

AND PLACE YOUR ORDER

WELL ENOUGH THAT YOU

ARE READY TO BUY

THE LTC1966?

1966 TA02

1966fb

9

LTC1966

applicaTions inForMaTion

RMS-TO-DC CONVERSION

The last two entries of Table 1 are chopped sine waves as

is commonly created with thyristors such as SCRs and

Triacs. Figure 2a shows a typical circuit and Figure 2b

shows the resulting load voltage, switch voltage and load

currents. The power delivered to the load depends on the

firing angle, as well as any parasitic losses such as switch

ON voltage drop. Real circuit waveforms will also typically

havesignificantringingattheswitchingtransition, depen-

dent on exact circuit parasitics. For the purposes of this

data sheet, SCR waveforms refers to the ideal chopped

sine wave, though the LTC1966 will do faithful RMS-to-DC

conversion with real SCR waveforms as well.

Definition of RMS

RMS amplitude is the consistent, fair and standard way to

measure and compare dynamic signals of all shapes and

sizes. Simply stated, the RMS amplitude is the heating

potential of a dynamic waveform. A 1V

AC waveform

RMS

willgeneratethesameheatinaresistiveloadaswill1VDC.

+

1V DC

R

–

SAME

HEAT

The case shown is for Θ = 90°, which corresponds to 50%

of available power being delivered to the load. As noted in

Table 1, when Θ = 114°, only 25% of the available power

is being delivered to the load and the power drops quickly

as Θ approaches 180°.

1V AC

RMS

1V (AC + DC) RMS

1966 F01

Figure 1

With an average rectification scheme and the typical

calibration to compensate for errors with sine waves, the

RMS level of an input sine wave is properly reported; it

is only with a nonsinusoidal waveform that errors occur.

Because of this calibration, and the output reading in

Mathematically, RMSistherootofthemeanofthesquare:

V_RMS= V²

V

, the term true RMS got coined to denote the use of

RMS

Alternatives to RMS

an actual RMS-to-DC converter as opposed to a calibrated

average rectifier.

Other ways to quantify dynamic waveforms include peak

detection and average rectification. In both cases, an aver-

age (DC) value results, but the value is only accurate at

the one chosen waveform type for which it is calibrated,

typically sine waves. The errors with average rectification

are shown in Table 1. Peak detection is worse in all cases

and is rarely used.

V

I

LOAD

+

–

+

–

V

LOAD

THY

+

AC

MAINS

V

LINE

–

CONTROL

1966 F02a

Figure 2a

Table 1. Errors with Average Rectification vs True RMS

AVERAGE

V

LINE

RECTIFIED

Θ

WAVEFORM

Square Wave

Sine Wave

V

(V)

ERROR*

RMS

V

LOAD

1.000

0.900

0.866

0.637

11%

*Calibrate for 0% Error

–3.8%

V

THY

Triangle Wave

I

LOAD

SCR at 1/2 Power,

Θ = 90°

–29.3%

1966 F02b

Figure 2b

SCR at 1/4 Power,

Θ = 114°

1.000

0.536

–40.4%

1966fb

10

LTC1966

applicaTions inForMaTion

How an RMS-to-DC Converter Works

How the LTC1966 RMS-to-DC Converter Works

Monolithic RMS-to-DC converters use an implicit com-

putation to calculate the RMS value of an input signal.

The fundamental building block is an analog multiply/

divide used as shown in Figure 3. Analysis of this topol-

ogy is easy and starts by identifying the inputs and the

output of the lowpass filter. The input to the LPF is the

calculation from the multiplier/divider; (V_IN)²/V_OUT. The

lowpass filter will take the average of this to create the

output, mathematically:

The LTC1966 uses a completely new topology for RMS-

to-DC conversion, in which a ∆S modulator acts as the

divider,andasimplepolarityswitchisusedasthemultiplier

as shown in Figure 4.

V_IN

D α

V_OUT

∆–∑

REF

V

IN

±±



²



V

V_OUT

(

)

V

LPF

IN

OUT

V_OUT

=

,









Figure 4. Topology of LTC1966

Because V_OUTis DC,





²

The ∆S modulator has a single-bit output whose average

duty cycle (D) will be proportional to the ratio of the input

signaldividedbytheoutput.The∆S isa2ndordermodula-

tor with excellent linearity. The single bit output is used to

selectively buffer or invert the input signal. Again, this is a

circuit with excellent linearity, because it operates at only

two points: 1 gain; the average effective multiplication

over time will be on the straight line between these two

V



²



(

)

IN

V

V_OUT



(

)

IN

=

, so









V_OUT





²

V

(

)

IN



V_OUT

=

, and

V_OUT

V

(

²= V ², or

)

(

)

OUT

IN

points.Thecombinationofthesetwoelementsagaincreates

2

a lowpass filter input signal proportional to (V ) /V

,

V_OUT

=

V

IN

= RMS V

( )

IN

OUT

(

)

IN

which, asshownabove, resultsinRMS-to-DCconversion.

The lowpass filter performs the averaging of the RMS

function and must be a lower corner frequency than the

lowest frequency of interest. For line frequency measure-

ments, this filter is simply too large to implement on-chip,

but the LTC1966 needs only one capacitor on the output

to implement the lowpass filter. The user can select this

capacitor depending on frequency range and settling time

requirements, as will be covered in the Design Cookbook

section to follow.

2

V

IN

(

)

V_OUT

×

÷

V

LPF

IN

OUT

1966 F03

Figure 3. RMS-to-DC Converter with Implicit Computation

Unlike the prior generation RMS-to-DC converters, the

LTC1966 computation does NOT use log/antilog circuits,

whichhaveallthesameproblems,andmore,oflog/antilog

multipliers/dividers, i.e., linearity is poor, the bandwidth

changes with the signal amplitude and the gain drifts with

temperature.

This topology is inherently more stable and linear than

log/antilog implementations primarily because all of the

signalprocessingoccursincircuitswithhighgainopamps

operating closed loop.

1966fb

11

LTC1966

applicaTions inForMaTion

More detail of the LTC1966 inner workings is shown in

the Simplified Schematic towards the end of this data

sheet. Note that the internal scalings are such that the ∆S

But the input nonlinearity will still cause problems in an

RMS-to-DC converter because it will corrupt the accuracy

astheinputsignalshapechanges.AlthoughanRMS-to-DC

converter will convert any input waveform to a DC output,

the accuracy is not necessarily as good for all waveforms

as it is with sine waves. A common way to describe dy-

namic signal wave shapes is crest factor. The crest factor

is the ratio of the peak value relative to the RMS value of

a waveform. A signal with a crest factor of 4, for instance,

has a peak that is four times its RMS value. Because this

peak has energy (proportional to voltage squared) that is

output duty cycle is limited to 0% or 100% only when V

IN

exceeds ± 4 • V

.

OUT

Linearity of an RMS-to-DC Converter

Linearity may seem like an odd property for a device that

implements a function that includes two very nonlinear

processes: squaring and square rooting.

However, anRMS-to-DCconverterhasatransferfunction,

RMS volts in to DC volts out, that should ideally have a

1:1 transfer function. To the extent that the input to output

transfer function does not lie on a straight line, the part

is nonlinear.

2

16 times (4 ) the energy of the RMS value, the peak is

necessarily present for at most 6.25% (1/16) of the time.

The LTC1966 performs very well with crest factors of 4

or less and will respond with reduced accuracy to signals

with higher crest factors. The high performance with crest

factorslessthan4isdirectlyattributabletothehighlinear-

ity throughout the LTC1966.

A more complete look at linearity uses the simple model

shown in Figure 5. Here an ideal RMS core is corrupted by

bothinputcircuitryandoutputcircuitrythathaveimperfect

transfer functions. As noted, input offset is introduced in

the input circuitry, while output offset is introduced in the

output circuitry.

The LTC1966 does not require an input rectifier, as is com-

mon with traditional log/antilog RMS-to-DC converters.

Thus, the LTC1966 has none of the nonlinearities that are

introduced by rectification.

Any nonlinearity that occurs in the output circuity will cor-

rupt the RMS in to DC out transfer function. A nonlinearity

in the input circuitry will typically corrupt that transfer

function far less, simply because with an AC input, the

RMS-to-DC conversion will average the nonlinearity from

a whole range of input values together.

The excellent linearity of the LTC1966 allows calibration to

be highly effective at reducing system errors. See System

Calibration section following the Design Cookbook.

INPUT CIRCUITRY

IDEAL

OUTPUT CIRCUITRY

• V

RMS-TO-DC

• V

INPUT

OUTPUT

IOS

OOS

• INPUT NONLINEARITY

CONVERTER

• OUTPUT NONLINEARITY

1966 F05

Figure 5. Linearity Model of an RMS-to-DC Converter

1966fb

12

LTC1966

applicaTions inForMaTion

DESIGN COOKBOOK

However, if the output is examined on an oscilloscope

with a very low frequency input, the incomplete averag-

ing will be seen, and this ripple will be larger than the

error depicted in Figure 6. Such an output is depicted in

Figure 7. The ripple is at twice the frequency of the input

because of the computation of the square of the input.

The typical values shown, 5% peak ripple with 0.05% DC

The LTC1966 RMS-to-DC converter makes it easy to

implement a rather quirky function. For many applications

all that will be needed is a single capacitor for averaging,

appropriate selection of the I/O connections and power

supply bypassing. Of course, the LTC1966 also requires

power. A wide variety of power supply configurations are

shown in the Typical Applications section towards the end

of this data sheet.

error, occur with C

= 1µF and f

= 10Hz.

AVE

INPUT

IftheapplicationcallsfortheoutputoftheLTC1966tofeed

asamplingorNyquistA/Dconverter(orothercircuitrythat

will not average out this double frequency ripple) a larger

averagingcapacitorcanbeused. Thistrade-offisdepicted

in Figure 8. The peak ripple error can also be reduced by

additional lowpass filtering after the LTC1966, but the

simplest solution is to use a larger averaging capacitor.

Capacitor Value Selection

The RMS or root-mean-squared value of a signal, the root

of the mean of the square, cannot be computed without

someaveragingtoobtainthemeanfunction. TheLTC1966

true RMS-to-DC converter utilizes a single capacitor on

the output to do the low frequency averaging required for

RMS-to-DC conversion. To give an accurate measure of a

dynamic waveform, the averaging must take place over a

sufficiently long interval to average, rather than track, the

lowest frequency signals of interest. For a single averag-

ing capacitor, the accuracy at low frequencies is depicted

in Figure 6.

1

This frequency dependent error is in addition to the static errors that affect all readings and are

therefore easy to trim or calibrate out. The Error Analyses section to follow discusses the effect

of static error terms.

ACTUAL OUTPUT

WITH RIPPLE

IDEAL

OUTPUT

f = 2 × f

INPUT

DC

PEAK

RIPPLE

(5%)

ERROR

(0.05%)

Figure 6 depicts the so-called DC error that results at a

given combination of input frequency and filter capacitor

DC

PEAK

AVERAGE

OF ACTUAL

OUTPUT

1

ERROR =

DC ERROR +

PEAK RIPPLE

(5.05%)

values . It is appropriate for most applications, in which

the output is fed to a circuit with an inherently band lim-

ited frequency response, such as a dual slope/integrating

A/D converter, a ∆S A/D converter or even a mechanical

analog meter.

TIME

1966 F07

Figure 7. Output Ripple Exceeds DC Error

0

–0.2

C = 10µF

C = 4.7µF

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

–1.8

–2.0

C = 2.2µF

C = 0.47µF

C = 0.1µF

C = 1.0µF

C = 0.22µF

1

10

20

50

60

100

INPUT FREQUENCY (Hz)

1966 F06

Figure 6. DC Error vs Input Frequency

1966fb

13

LTC1966

applicaTions inForMaTion

0

–0.2

–0.4

C = 100µF

–0.6

–0.8

C = 2.2µF

C = 1µF

C = 47µF

C = 22µF

C = 10µF

C = 4.7µF

–1.0

–1.2

–1.4

–1.6

–1.8

–2.0

1

10

INPUT FREQUENCY (Hz)

20

50

60

100

1966 F08

Figure 8. Peak Error vs Input Frequency with One Cap Averaging

A 1µF capacitor is a good choice for many applications.

The peak error at 50Hz/60Hz will be <1% and the DC error

will be <0.1% with frequencies of 10Hz or more.

capacitorleakagewillneedtobe>1000timestheLTC1966

output impedance. Accuracy at this level can be hard to

achieve with a ceramic capacitor, particularly with a large

value of capacitance and at high temperature.

Note that both Figure 6 and Figure 8 assume AC-coupled

waveforms with a crest factor less than 2, such as sine

waves or triangle waves. For higher crest factors and/or

Forcriticalapplications,afilmcapacitor,suchasmetalized

polyester, will be a much better choice. Although more

expensive, and larger for a given value, the value stabil-

ity and low leakage make metal film capacitors a trouble

free choice.

AC+DCwaveforms,alargerC willgenerallyberequired.

AVE

See Crest Factor and AC + DC Waveforms.

Capacitor Type Selection

Withanytypeofcapacitor,theselfresonanceofthecapaci-

tor can be an issue with the switched capacitor LTC1966.

If the self resonant frequency of the averaging capacitor

is 1MHz or less, a second smaller capacitor should be

added in parallel to reduce the impedance seen by the

LTC1966outputstageathighfrequencies.Acapacitor100

timessmallerthantheaveragingcapacitorwilltypicallybe

small enough to be a low cost ceramic with a high quality

dielectric such as X7R or NPO/COG.

The LTC1966 can operate with many types of capacitors.

The various types offer a wide array of sizes, tolerances,

parasitics, package styles and costs.

Ceramic chip capacitors offer low cost and small size,

but are not recommended for critical applications. The

value stability over voltage and temperature is poor with

many types of ceramic dielectrics. This will not cause an

RMS-to-DCaccuracyproblemexceptatlowfrequencies,

where it can aggravate the effects discussed in the pre-

vious section. If a ceramic capacitor is used, it may be

necessary to use a much higher nominal value in order

to assure the low frequency accuracy desired.

Input Connections

The LTC1966 input is differential and DC coupled. The

LTC1966 responds to the RMS value of the differential

voltage between Pin 2 and Pin 3, including the DC por-

tion of that difference. However, there is no DC-coupled

path from the inputs to ground. Therefore, at least one of

the two inputs must be connected with a DC return path

to ground.

Anotherparasiticofceramiccapacitorsisleakage,whichis

again dependent on voltage and particularly temperature.

If the leakage is a constant current leak, the I • R drop of

theleakmultipliedbytheoutputimpedanceoftheLTC1966

will create a constant offset of the output voltage. If the

leakisOhmic,theresistordividerformedwiththeLTC1966

output impedance will cause a gain error. For <0.1%

gain accuracy degradation, the parallel impedance of the

Both inputs must be connected to something. If either

input is left floating, a zero volt output will result.

1966fb

14

LTC1966

applicaTions inForMaTion

For single-ended DC-coupled applications, simply con-

nect one of the two inputs (they are interchangeable) to

the signal, and the other to ground. This will work well

for dual supply configurations, but for single supply

configurations it will only work well for unipolar input

signals. The LTC1966 input voltage range is from rail-

on the coupling capacitor connected to the second input

to follow the DC average of the input voltage.

For differential input applications, connect the two inputs

to the differential signal. If AC coupling is desired, one of

thetwoinputscanbeconnectedthroughaseriescapacitor.

In all of these connections, to choose the input coupling

to-rail, and when the input is driven above V or below

DD

capacitor, C , calculate the low frequency coupling time

V

SS

(ground for single supply operation) the gain and

C

constant desired, and divide by the LTC1966 differential

input impedance. Because the LTC1966 input impedance

is about 100 times its output impedance, this capacitor is

typically much smaller than the output averaging capaci-

tor. Its requirements are also much less stringent, and a

ceramic chip capacitor will usually suffice.

offset errors will increase substantially after just a few

hundred millivolts of overdrive. Fortunately, most single

supply circuits measuring a DC-coupled RMS value will

include some reference voltage other than ground, and

thesecondLTC1966inputcanbeconnectedtothatpoint.

Forsingle-endedAC-coupledapplications,Figure9shows

threealternatetopologies.Thefirstone,showninFigure9a

uses a coupling capacitor to one input while the other is

grounded. ThiswillremovetheDCvoltagedifferencefrom

the input to the LTC1966, and it will therefore not be part

of the resulting output voltage. Again, this connection will

work well with dual supply configurations, but in single

supply configurations it will be necessary to raise the volt-

age on the grounded input to assure that the signal at the

Output Connections

TheLTC1966outputisdifferentially,butnotsymmetrically,

generated. That is to say, the RMS value that the LTC1966

computes will be generated on the output (Pin 5) relative

to the output return (Pin 6), but these two pins are not

interchangeable. For most applications, Pin 6 will be tied

to ground (Pin 1), and this will result in the best accuracy.

However, Pin 6 can be tied to any voltage between V

SS

active input stays within the range of V to V . If there

SS

DD

(Pin 4) and V (Pin 7) less the maximum output voltage

DD

is already a suitable voltage reference available, connect

the second input to that point. If not, a midsupply voltage

can be created with two resistors as shown in Figure 9b.

swingdesired.ThislastrestrictionkeepsV itself(Pin5)

OUT

within the range of V to V . If a reference level other

SS

DD

than ground is used, it should be a low impedance, both

Finally, if the input voltage is known to be between V

SS

AC and DC, for proper operation of the LTC1966.

and V , it can be AC-coupled by using the configuration

DD

Use of a voltage in the range of V – 1V to V – 1.3V can

DD

shown in Figure 9c. Whereas the DC return path was

provided through Pin 3 in Figures 9a and 9b, in this case,

the return path is provided on Pin 2, through the input

signal voltages. The switched capacitor action between

the two input pins of the LTC1966 will cause the voltage

lead to errors due to the switch dynamics as the NMOS

transistor is cut off. For this reason, it is recommended

that OUT RTN = 0V if V is ≤3V.

DD

V

DD

V

DD

C

LTC1966

IN1

LTC1966

IN1

IN2

LTC1966

IN1

IN2

2

3

2

3

2

3

IN2

V

IN

V

IN

V

IN

1966 F09

+

V

C

DC

–

V

DD

SS

V

OR GND

SS

R1

100k

R2

100k

(9b)

(9c)

(9a)

Figure 9. Single-Ended AC-Coupled Input Connection Alternatives

1966fb

15

LTC1966

applicaTions inForMaTion

In any configuration, the averaging capacitor should be

connected between Pins 5 and 6. The LTC1966 RMS DC

0

–1

–2

–3

–4

–5

–6

output will be a positive voltage created at V

with respect to OUT RTN (Pin 6).

(Pin 5)

OUT

LTC1966

OPERATES IN THIS RANGE

Power Supply Bypassing

The LTC1966 is a switched capacitor device, and large

transient power supply currents will be drawn as the

switching occurs. For reliable operation, standard power

supply bypassing must be included. For single supply

2.5

3.5

4

4.5

5

5.5

3

V

(V)

operation, a 0.01µF capacitor from V (Pin 7) to GND

DD

1966 F10

(Pin 1) located close to the device will suffice. For dual

Figure 10. V_SSLimits vs V_DD

supplies, add a second 0.01µF capacitor from V (Pin 4)

SS

to GND (Pin 1), located close to the device. If there is a

good quality ground plane available, the capacitors can go

directly to that instead. Power supply bypass capacitors

can, of course, be inexpensive ceramic types.

Up and Running!

If you have followed along this far, you should have the

LTC1966 up and running by now! Don’t forget to enable

thedevicebygroundingPin8, ordrivingitwithalogiclow.

The sampling clock of the LTC1966 operates at approxi-

mately 200kHz, and most operations repeat at a rate of

100kHz. If this internal clock becomes synchronized to a

multiple or submultiple of the input frequency, significant

conversionerrorcouldoccur.Thisisparticularlyimportant

when frequencies exceeding 10kHz can be injected into

the LTC1966 via supply or ground bounce. To minimize

this possibility, capacitive bypassing is recommended on

bothsupplieswithcapacitorsplacedimmediatelyadjacent

to the LTC1966. For best results, the bypass capacitors

should be separately routed from Pin 7 to Pin 1, and from

Pin 4 to Pin 1.

Keep in mind that the LTC1966 output impedance is fairly

high,andthateventhestandard10MΩinputimpedanceof

a digital multimeter (DMM) or a 10× scope probe will load

down the output enough to degrade its typical gain error

of 0.1%. In the end application circuit, either a buffer or

anothercomponentwithanextremelyhighinputimpedance

(such as a dual slope integrating ADC) should be used.

For laboratory evaluation, it may suffice to use a bench

top DMM with the ability to disconnect the 10MΩ shunt.

If you are still having trouble, it may be helpful to skip

ahead a few pages and review the Troubleshooting Guide.

The LTC1966 needs at least 2.7V for its power supply,

more for dual supply configurations. The range of allow-

What About Response Time?

With a large value averaging capacitor, the LTC1966 can

easily perform RMS-to-DC conversion on low frequency

signals. It compares quite favorably in this regard to

prior generation products because nothing about the ∆S

circuitryistemperaturesensitive.SotheRMSresultdoesn’t

get distorted by signal driven thermal fluctuations like a

log/antilog circuit output does.

able negative supply voltages (V ) vs positive supply

SS

voltages (V ) is shown in Figure 10. Mathematically, the

DD

V

constraint is:

SS

–3 • (V – 2.7V) ≤ V ≤ GND

DD

SS

The LTC1966 has internal ESD absorption devices, which

are referenced to the V and V supplies. For effective

DD

SS

in-circuit ESD immunity, the V and V pins must be

DD

SS

However, using large value capacitors results in a slow

response time. Figure 11 shows the rising and falling

step responses with a 1µF averaging capacitor. Although

they both appear at first glance to be standard exponential

connected to a low external impedance. This can be ac-

complished with low impedance power planes or simply

with the recommended 0.01µF decoupling to ground on

each supply.

1966fb

16

LTC1966

applicaTions inForMaTion

120

100

120

C

= 1µF

C

= 1µF

AVE

100

80

60

80

60

40

20

0

40

20

0

0.2

0.4

0.6

0.8

1

0

0.1

0.2

0.3

0.4

0.5

TIME (SEC)

1966 F11b

1966 F11a

Figure 11a. LTC1966 Rising Edge with C_AVE= 1µF

Figure 11b. LTC1966 Falling Edge with C_AVE= 1µF

10

C = 0.1µF

C = 0.22µF C = 0.47µF

C = 1µF

C = 2.2µF

C = 4.7µF

C = 10µF

C = 22µF

C = 47µF

C = 100µF

1

0.1

0.01

0.1

1

SETTLING TIME (SEC)

10

100

1966 F12

Figure 12. LTC1966 Settling Time with One Cap Averaging

decaytypesettling,theyarenot.Thisisduetothenonlinear

nature of an RMS-to-DC calculation. Also note the change

in the time scale between the two; the rising edge is more

than twice as fast to settle to a given accuracy. Again this

decay. For example, when the input amplitude is changed

from 100mV to 110mV (+10%) and back (–10%), the step

responses are essentially the same as a standard expo-

nential rise and decay between those two levels. In such

cases, the time constant of the decay will be in between

that of the rising edge and falling edge cases of Figure 11.

Therefore, the worst case is the falling edge response as

it goes to zero, and it can be used as a design guide.

2

is a necessary consequence of RMS-to-DC calculation.

Although shown with a step change between 0mV and

100mV, the same response shapes will occur with the

LTC1966 for ANY step size. This is in marked contrast

to prior generation log/antilog RMS-to-DC converters,

whose averaging time constants are dependent on the

signal level, resulting in excruciatingly long waits for the

output to go to zero.

Figure 12 shows the settling accuracy vs settling time for

a variety of averaging capacitor values. If the capacitor

value previously selected (based on error requirements)

gives an acceptable settling time, your design is done.

2

To convince oneself of this necessity, consider a pulse train of 50% duty cycle between 0mV

The shape of the rising and falling edges will be dependent

on the total percent change in the step, but for less than

the 100% changes shown in Figure 11, the responses will

be less distorted and more like a standard exponential

and 100mV. At very low frequencies, the LTC1966 will essentially track the input. But as the input

frequency is increased, the average result will converge to the RMS value of the input. If the rise

and fall characteristics were symmetrical, the output would converge to 50mV. In fact though, the

RMS value of a 100mV DC-coupled 50% duty cycle pulse train is 70.71mV, which the asymmetrical

rise and fall characteristics will converge to as the input frequency is increased.

1966fb

17

LTC1966

applicaTions inForMaTion

But with 100µF, the settling time to even 10% is a full 38

seconds, which is a long time to wait. What can be done

about such a design? If the reason for choosing 100µF is

to keep the DC error with a 75mHz input less than 0.1%,

the answer is: not much. The settling time to 1% of 76

seconds is just 5.7 cycles of this extremely low frequency.

Averaging very low frequency signals takes a long time.

A second disadvantage is that the op amp output has

to operate over the same range as the LTC1966 output,

including ground, which in single supply applications is

the negative supply. Although the LTC1966 output will

function fine just millivolts from the rail, most op amp

output stages (and even some input stages) will not.

There are at least two ways to address this. First of all,

the op amp can be operated split supply if a negative

supply is available. Just the op amp would need to do so;

the LTC1966 can remain single supply. A second way to

address this issue is to create a signal reference voltage a

half volt or so above ground. This is most attractive when

the circuitry that follows has a differential input, so that

the tolerance of the signal reference is not a concern. To

do this, tie all three ground symbols shown in Figure 13

to the signal reference, as well as to the differential return

for the circuitry that follows.

However, if the reason for choosing 100µF is to keep the

peak error with a 10Hz input less than 0.05%, there is

another way to achieve that result with a much improved

settling time.

Reducing Ripple with a Post Filter

The output ripple is always much larger than the DC er-

ror, so filtering out the ripple can reduce the peak error

substantially, without the large settling time penalty of

simply increasing the averaging capacitor.

Figure 14 shows an alternative 2nd order post filter, for

a net 3rd order filtering of the LTC1966 RMS calculation.

It also uses the 85kΩ output impedance of the LTC1966

as the first resistor of a 3rd order active RC filter, but this

topology filters without buffering so that the op amp DC

errorcharacteristicsdonotaffecttheoutput. Althoughthe

output impedance of the LTC1966 is increased from 85kΩ

to 285kΩ, this is not an issue with an extremely high input

impedance load, such as a dual slope integrating ADC like

the ICL7106. And it allows a generic op amp to be used,

such as the SOT-23 one shown. Furthermore, it easily

works on a single supply rail by tying the noninverting

input of the op amp to a low noise reference as optionally

shown. This reference will not change the DC voltage at

the circuit output, although it does become the AC ground

for the filter, thus the (relatively) low noise requirement.

Figure 13 shows a basic 2nd order post filter, for a net 3rd

order filtering of the LTC1966 RMS calculation. It uses the

85kΩoutputimpedanceoftheLTC1966asthefirstresistor

of a 3rd order Sallen-Key active RC filter. This topology

featuresabufferedoutput,whichcanbedesirabledepend-

ing on the application. However, there are disadvantages

to this topology, the first of which is that the op amp input

voltage and current errors directly degrade the effective

LTC1966 V . The table inset in Figure 13 shows these

OOS

errors for four of Linear Technology’s op amps.

C1

1µF

R

B

–

+

R1

R2

169k

LT1880

38.3k

5

6

R1

LTC1966

C

C2

0.1µF

AVE

200k

5

1µF

LTC1966

C

C1

0.22µF

C2

0.22µF

AVE

R2

681k

6

1µF

OP AMP

LTC1966 V

LT1494 LT1880 LT1077 LT2050

–

200µV

OOS

OTHER

REF VOLTAGE,

SEE TEXT

V

IOS

3ꢀ5µV

ꢀ3µV

6ꢁ8µV

29ꢁk

1µA

150µV

329µV

6ꢀ9µV

SHORT

1.2mA

60µV

329µV

589µV 230µV

29ꢁk

ꢁ8µA

3µV

2ꢀµV

LT1782

I

• R

B/OS

+

TOTAL OFFSET

VALUE

R

B

SHORT

ꢀ50µA

I

SQ

1966 F13

1066 F14

Figure 14. DC Accurate Post Filter

Figure 13. Buffered Post Filter

1966fb

18

LTC1966

applicaTions inForMaTion

Step Responses with a Post Filter

an issue with input frequency bursts at 50Hz or less, and

even with the overshoot, the settling to a given level of

accuracy improves due to the initial speedup.

Both of the post filters, shown in Figures 13 and 14,

are optimized for additional filtering with clean step

responses. The 85kΩ output impedance of the LTC1966

working into a 1µF capacitor forms a 1st order LPF with

a –3dB frequency of ~1.8Hz. The two filters have 1µF at

the LTC1966 output for easy comparison with a 1µF only

case,andbothhavethesamerelative(Bessel-like)shape.

However, because of the topological differences of pole

placements between the various components within the

two filters, the net effective bandwidth for Figure 13 is

slightly higher (≈1.2 • 1.8 ≈ 2.1Hz) than with 1µF alone,

while the bandwidth for Figure 14 is somewhat lower

(≈0.7 • 1.8 ≈ 1.3Hz) than with 1µF alone. To adjust the

bandwidthofeitherofthem,simplyscaleallthecapacitors

byacommonmultiple,andleavetheresistorsunchanged.

As predicted by Figure 6, the DC error with 1µF is well

under 1mV and is not noticeable at this scale. However, as

predicted by Figure 8, the peak error with the ripple from a

10Hz input is much larger, in this case about 5mV. As can

be clearly seen, the post filters reduce this ripple. Even

the wider bandwidth of Figure 13’s filter is seen to cut the

ripple down substantially (to <1mV) while the settling to

1%happensfaster. WiththenarrowerbandwidthofFigure

14’s filter, the step response is somewhat slower, but the

double frequency output ripple is just 180µV.

Figure16showsthestepresponseofthesamethreecases

with a burst of 60Hz rather than 10Hz. With 60Hz, the ini-

tial portion of the step response is free of the boost seen

in Figure 15 and the two post filter responses have less

than 1% overshoot. The 1µF only case still has noticeable

120Hz ripple, but both filters have removed all detectable

ripple on this scale. This is to be expected; the first order

filter will reduce the ripple about 6:1 for a 6:1 change in

frequency, while the third order filters will reduce the

The step responses of the LTC1966 with 1µF only and with

the two post filters are shown in Figure 15. This is the ris-

ing edge RMS output response to a 10Hz input starting

at t = 0. Although the falling edge response is the worst

case for settling, the rising edge illustrates the ripple that

these post filters are designed to address, so the rising

edge makes for a better intuitive comparison.

3

ripple about 6 :1 or 216:1 for a 6:1 change in frequency.

TheinitialriseoftheLTC1966willhaveenhancedslewrates

with DC and very low frequency inputs due to saturation

effects in the ∆S modulator. This is seen in Figure 15 in

two ways. First, the 1µF only output is seen to rise very

quicklyinthefirst40ms.Thesecondwaythiseffectshows

up is that the post filter outputs have a modest overshoot,

on the order of 3mV to 4mV, or 3% to 4%. This is only

Again, the two filter topologies have the same relative

shape,sothestepresponseandripplefilteringtrade-offsof

the two are the same, with the same performance of each

possible with the other by scaling it accordingly. Figures

17 and 18 show the peak error vs. frequency for a selec-

tion of capacitors for the two different filter topologies.

To keep the clean step response, scale all three capacitors

200mV/

DIV

200mV/

DIV

INPUT

BURST

INPUT

BURST

0

1µF ONLY

FIGURE 13

FIGURE 14

1µF ONLY

FIGURE 13

FIGURE 14

20mV/

DIV

20mV/

DIV

STEP

RESPONSE

STEP

RESPONSE

0

1966 F16

1966 F15

100ms/DIV

Figure 16. Step Responses with 60Hz Burst

Figure 15. Step Responses with 10Hz Burst

1966fb

19

LTC1966

applicaTions inForMaTion

0

–0.2

C = 10µF

–0.4

–0.6

C = 4.7µF

C = 2.2µF

C = 1.0µF

C = 0.47µF

C = 0.22µF

C = 0.1µF

–0.8

–1.0

–1.2

–1.4

–1.6

–1.8

–2.0

1

10

INPUT FREQUENCY (Hz)

100

1966 F17

Figure 17. Peak Error vs Input Frequency with Buffered Post Filter

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

–1.8

–2.0

C = 10µF

C = 4.7µF

C = 2.2µF

C = 1.0µF

C = 0.47µF

C = 0.22µF

C = 0.1µF

1

10

INPUT FREQUENCY (Hz)

100

1966 F18

Figure 18. Peak Error vs Input Frequency with DC Accurate Post Filter

within the filter. Scaling the buffered topology of Figure 13

is simple because the capacitors are in a 10:1:10 ratio.

Scaling the DC accurate topology of Figure 14 can be done

with standard value capacitors; one decade of scaling is

shown in Table 2.

Figures 19 and 20 show the settling time versus settling

accuracy for the buffered and DC accurate post filters,

respectively. The different curves represent different scal-

ingsofthefilters, asindicatedbytheC value. Theseare

AVE

comparable to the curves in Figure 12 (single capacitor

case), with somewhat less settling time for the buffered

post filter, and somewhat more settling time for the DC

accuratepostfilter.Thesedifferencesareduetothechange

in overall bandwidth as mentioned earlier.

Table 2. One Decade of Capacitor Scaling for Figure 14 with EIA

Standard Values

C

C = C =

1 2

AVE

1µF

0.22µF

0.33µF

0.47µF

0.68µF

1µF

1.5µF

2.2µF

3.3µF

4.7µF

6.8µF

The other difference is the settling behavior of the filters

below the 1% level. Unlike the case of a 1st order filter,

any 3rd order filter can have overshoot and ringing. The

filter designs presented here have minimal overshoot

and ringing, but are somewhat sensitive to component

mismatches. Even the 12% tolerance of the LTC1966

output impedance can be enough to cause some ringing.

The dashed lines indicate what can happen when 5%

1.5µF

capacitors and 1% resistors are used.

1966fb

20

LTC1966

applicaTions inForMaTion

10

C = 0.1µF

C = 0.22µF

C = 0.47µF C = 1.0µF

C = 2.2µF

C = 4.7µF

C = 10µF

C = 22µF

C = 47µF

C = 100µF

1

0.1

0.01

0.1

1

SETTLING TIME (SEC)

10

100

1066 F14

Figure 19. Settling Time with Buffered Post Filter

10

C = 0.1µF

C = 0.22µF C = 0.47µF

C = 1.0µF

C = 2.2µF

C = 4.7µF

C = 10µF

C = 22µF

C = 47µF C = 100µF

1

0.1

0.01

0.1

1

SETTLING TIME (SEC)

10

100

1066 F20

Figure 20. Settling Time with DC Accurate Post Filter

Although the settling times for the post filtered configu-

rations shown on Figures 19 and 20 are not that much

different from those with a single capacitor, the point of

using a post filter is that the settling times are far better

for a given level peak error. The filters dramatically reduce

the low frequency averaging ripple with far less impact

on settling time.

at the input frequency and the filter must average out

that lower frequency. So with AC + DC waveforms, the

required value for C_AVEshould be based on half of the

lowest input frequency, using the same design curves

presented in Figures 6, 8, 17 and 18.

Crest factor, which is the peak to RMS ratio of a dynamic

signal, also effects the required C value. With a higher

AVE

crest factor, more of the energy in the signal is concen-

trated into a smaller portion of the waveform, and the

averaging has to ride out the long lull in signal activity.

For busy waveforms, such as a sum of sine waves, ECG

traces or SCR chopped sine waves, the required value for

Crest Factor and AC + DC Waveforms

In the preceding discussion, the waveform was assumed

to be AC-coupled, with a modest crest factor. Both as-

sumptions ease the requirements for the averaging

capacitor. With an AC-coupled sine wave, the calculation

engine squares the input, so the averaging filter that

follows is required to filter twice the input frequency,

making its job easier. But with a sinewave that includes

DC offset, the square of the input has frequency content

C

should be based on the lowest fundamental input

AVE

frequency divided as such:

f

INPUT(MIN)

f_DESIGN

=

3• CF – 2

1966fb

21

LTC1966

applicaTions inForMaTion

using the same design curves presented in Figures 6, 8,

17 and 18. For the worst-case of square top pulse trains,

that are always either zero volts or the peak voltage, base

the selection on the lowest fundamental input frequency

divided by twice as much:

FortheLTC1966,whoseoutputimpedance(Z )is85kΩ,

OUT

this droop works out to –5.22%, so the output would be

reduced to 237mV at the end of the inactive portion of the

input. When the input signal again climbs to 1V

peak/output ratio is 4.22.

, the

PEAK

f

INPUT(MIN)

With C = 10µF, the droop is only –0.548% to 248.6mV

AVE

f_DESIGN

=

and the peak/output ratio is just 4.022, which the LTC1966

6 • CF – 2

has enough margin to handle without error.

The effects of crest factor and DC offsets are cumulative.

For crest factors less than 3.5, the selection of C

as

AVE

So for example, a 10% duty cycle pulse train from 0V

PEAK

previously described should be sufficient to avoid this

droop and modulator saturation effect. But with crest

factors above 3.5, the droop should also be checked for

each design.

to 1V

(CF = √10 = 3.16) repeating at 16.67ms (60Hz)

PEAK

input is effectively only 30Hz due to the DC asymmetry

and is effectively only:

30

f_DESIGN

=

= 3.78Hz

Error Analyses

6 • 3.16 – 2

Once the RMS-to-DC conversion circuit is working, it is

time to take a step back and do an analysis of the accuracy

of that conversion. The LTC1966 specifications include

for the purposes of Figures 6, 8, 17 and 18.

Obviously,theeffectofcrestfactorissomewhatsimplified

above given the factor of 2 difference based on a subjec-

tive description of the waveform type. The results will vary

somewhat based on actual crest factor and waveform

dynamicsandthetypeoffilteringused. Theabovemethod

is conservative for some cases and about right for others.

three basic static error terms, V , V and GAIN. The

OOS IOS

output offset is an error that simply adds to (or subtracts

from) the voltage at the output. The conversion gain of

the LTC1966 is nominally 1.000 V

/V

and the

DCOUT RMSIN

gain error reflects the extent to which this conversion gain

is not perfectly unity. Both of these affect the results in a

fairly obvious way.

The LTC1966 works well with signals whose crest factor is

4orless. Athighercrestfactors, theinternal∆∑modulator

will saturate, and results will vary depending on the exact

frequency, shape and (to a lesser extent) amplitude of the

input waveform. The output voltage could be higher or

lower than the actual RMS of the input signal.

Input offset on the other hand, despite its conceptual

simplicity, effects the output in a nonobvious way. As

its name implies, it is a constant error voltage that adds

directly with the input. And it is the sum of the input and

V

that is RMS converted.

IOS

The∆∑modulatormayalsosaturatewhensignalswithcrest

factors less than 4 are used with insufficient averaging.

This will only occur when the output droops to less than

1/4 of the input voltage peak. For instance, a DC-coupled

pulse train with a crest factor of 4 has a duty cycle of

This means that the effect of V

is warped by the

IOS

nonlinear RMS conversion. With 0.2mV (typ) V , and

IOS

a 200mV

AC input, the RMS calculation will add the

RMS

DC and AC terms in an RMS fashion and the effect is

negligible:

6.25% and a 1V

input is 250mV

. If this input is

PEAK

RMS

50Hz, repeating every 20ms, and C

= 1µF, the output

AVE

2

V

OUT

= √(200mV AC) + (0.2mV DC)

will droop during the inactive 93.75% of the waveform.

This droop is calculated as:

= 200.0001mV

= 200mV + 1/2ppm

INACTIVE TIME







^







_

1– e⁻

V_RMS

2

 2 • Z

• C

AVE

V_MIN

=

OUT





1966fb

22

LTC1966

applicaTions inForMaTion

But with 10× less AC input, the error caused by V is

100× larger:

2

V

OUT

= (√(5mV AC) + (0.8mV DC) ) • 1.003 + 0.2mV

IOS

= 5.279mV

= 5mV + 5.57%

2

V

OUT

= √(20mV AC) + (0.2mV DC)

= 20.001mV

These static error terms are in addition to dynamic error

terms that depend on the input signal. See the Design

Cookbook for a discussion of the DC conversion error

with low frequency AC inputs. The LTC1966 bandwidth

limitations cause additional errors with high frequency

inputs. Another dynamic error is due to crest factor. The

LTC1966 performance versus crest factor is shown in the

Typical Performance Characteristics.

= 20mV + 50ppm

This phenomena, although small, is one source of the

LTC1966’s residual nonlinearity.

On the other hand, if the input is DC-coupled, the input

offset voltage adds directly. With +200mV and a +0.2mV

V

, a 200.2mV output will result, an error of 0.1% or

IOS

1000ppm. With DC inputs, the error caused by V can

IOS

be positive or negative depending if the two have the same Monotonicity and Linearity

or opposing polarity.

The LTC1966, like all implicit RMS-to-DC convertors

The total conversion error with a sine wave input using the (Figure3),hasadivisionwiththeoutputinthedenominator.

typical values of the LTC1966 static errors is computed This works fine most of the time, but when the output is

as follows:

zero or near zero this becomes problematic. The LTC1966

has multiple switched capacitor amplifier stages, and

depending on the different offsets and their polarity, the

DC transfer curve near zero input can take a few different

forms,asshownintheTypicalPerformanceCharacteristics

graph titled DC Transfer Function Near Zero.

2

V

OUT

V

OUT

V

OUT

=(√(500mVAC) +(0.2mVDC) )•1.001+0.1mV

= 500.600mV

= 500mV + 0.120%

2

= (√(50mV AC) + (0.2mV DC) ) • 1.001 + 0.1mV

= 50.150mV

= 50mV + 0.301%

Some units(about1 ofevery 16)will even be wellbehaved

with a transfer function that is the upper half of a unit

rectangular hyperbola with a focal point on the y-axis of

2

= (√(5mV AC) + (0.2mV DC) ) • 1.001 + 0.1mV

= 5.109mV

3

a few millivolts. For AC inputs, these units will have a

monotonictransferfunctionallthewaydowntozeroinput.

= 5mV + 2.18%

The LTC1966 is trimmed for offsets as small as practical,

and the resulting behavior is the best statistical linearity

provided the zero region troubles are avoided.

As can be seen, the gain term dominates with large inputs,

while the offset terms become significant with smaller

inputs. In fact, 5mV is the minimum RMS level needed to

keep the LTC1966 calculation core functioning normally,

so this represents the worst-case of usable input levels.

It is possible, and even easy, to force the zero region to

be well behaved at the price of additional (though predict-

able)V

andsomelinearityerror. Forlargeenoughinput

OOS

Using the worst-case values of the LTC1966 static errors,

the total conversion error is:

signals, this linearity error may be negligible.

3

In general, every LTC1966 will have a DC transfer function that is essentially a unit rectangular

2

V

=(√(500mVAC) +(0.8mVDC) )•1.003+0.2mV

= 501.70mV

hyperbola (the gain is not always exactly unity, but the gain error is small) with an X- and

Y- offset equal to V and V , respectively, until the inputs are small enough that the delta

OUT

IOS

OOS

sigma section gets confused. While some units will be the north half of a north south pair, other

units will have two upper halfs of the conjugate, east west, hyperbolas. The circuit of Figure 23

will assure a continuous transfer function.

= 500mV + 0.340%

2

V

= (√(50mV AC) + (0.8mV DC) ) • 1.003 + 0.2mV

= 50.356mV

= 50mV + 0.713%

1966fb

23

LTC1966

applicaTions inForMaTion

20

15

10

5

To do this, inject current into the output. As shown in

Figure 21, the charge pump output impedance is 170kΩ,

with the computational feedback cutting the closed loop

output impedance to the 85kΩ specification. By injecting

30nAofcurrentintothis170Ω,withzeroinput,a5mVoffset

5mV MIN

LTC1966

ASYMPTOTES

SHIFTED +2.5mV

I

DC

INJECT

CHARGE

PUMP

IN1

IN2

OUTPUT

170kΩ

RMS TO DC

CONVERSION

IDEAL

0

C

AVE

0

5

10

15

20

V

(mV AC)

IN

1966 F22b

Figure 22b. AC Transfer Function with I_INJECT= 30nA

1966 F21

Figure 21. Behavioral Block Diagram of LTC1966

Figure 23 shows an analog implementation of this with

the offset and gain errors corrected; only the slight, but

necessary, degradation in nonlinearity remains. The cir-

cuit works by creating approximately 300mV of bias at

the junction of the 10MΩ resistors when the LTC1966’s

input/output are zero. The 10MΩ resistor to the LTC1966

output therefore feeds in 30nA. The loading of this resis-

tor causes a slight reduction in gain which is corrected,

as is the nominal 2.5mV offset, by the LT1494 op amp.

is created at the output feedback point, which is sufficient

to overcome the 5mV minimum signal level. With large

enough input signals, the computational feedback cuts

the output impedance to 85kΩ so the transfer function

asymptotes will have an output offset of 2.5mV, as shown

in Figure 22. This is the additional, predictable, V

that

OOS

is added, and should be subtracted from the RMS results,

either digitally, or by an analog means.

10MΩ

85kΩ

750k

20

5V

V

DD

5V

10MΩ

1µF

10MΩ

LTC1966

15

IN1

IN2

OUT

+

V

LT1494

OUT

OUTRTN

5mV MIN

–

10

V

GND EN

SS

–5V

84.5k

–5V

1966 F23

100pF

5

ASYMPTOTES

SHIFTED +2.5mV

IDEAL

Figure 23. Monotonic AC Response with Offset

and Gain Corrected

0

–15 –10

–5

0

5

10

15

20

–20

V

IN

(mV DC)

1966 F22a

Figure 22a. DC Transfer Function with I_INJECT= 30nA

1966fb

24

LTC1966

applicaTions inForMaTion

The two 10MΩ resistors not connected to the supply can

be any value as long as they match and the feed voltage

is changed for 30nA injection. The op amp gain is only

1.00845, so the output is dominated by the LTC1966 RMS

results, which keeps errors low. With the values shown,

the resistors can be 2% and only introduce 170ppm of

gain error. The 84.5k resistor is the closest match in the

1% EIA values but if the 2% EIA value of 82k were used

instead, the gain would only be reduced by 248ppm.

or more, I

is usually only specified for maximum and

BIAS

this circuit needs a minimum of 30nA, therefore such an

approach may not always work.

Because the circuit of Figure 23 subtracts the offset cre-

ated by the injected current, the LT1494 output with zero

LTC1966 input will rest at +2.5mV, nominal before offsets,

rather then the 5mV seen in Figure 22.

Output Errors Versus Frequency

ThislowerrorsensitivityisimportantbecausetheLTC1966

output impedance is 85kΩ 11.8%, which can create a

gain error of 0.1%; enough to degrade the overall gain

accuracy somewhat. This gain variation term is increased

with lower value feed resistors, and decreased with higher

value feed resistors.

As mentioned in the Design Cookbook, the LTC1966 per-

formsverywellwithlowfrequencyandverylowfrequency

inputs,providedalargeenoughaveragingcapacitorisused.

However,theLTC1966willhaveadditionaldynamicerrorsas

the input frequency is increased. The LTC1966 is designed

for high accuracy RMS-to-DC conversion of signals into

the audible range. The input sampling amplifiers have a

–3dB frequency of 800kHz or so. However, the switched

capacitor circuitry samples the inputs at a modest 100kHz

nominal. The response versus frequency is depictedinthe

Typical Performance Characteristics titled Input Signal

Bandwidth. Although there is a pattern to the response

versusfrequencythatrepeatseverysamplefrequency,the

errorsarenotoverwhelming.ThisisbecauseLTC1966RMS

calculationisinherentlywideband,operatingproperlywith

minimaloversampling,orevenundersampling,usingsev-

eralproprietarytechniquestoexploitthefactthattheRMS

value of an aliased signal is the same as the RMS value of

the original signal. However, a fundamental feature of the

∆S modulator is that sample estimation noise is shaped

such that minimal noise occurs with input frequencies

much less than the sampling frequency, but such noise

peaks when input frequency reaches half the sampling

frequency.FortunatelytheLTC1966outputaveragingfilter

greatly reduces this error, but the RMS-to-DC topology

frequency shifts the noise to low (baseband) frequencies.

Sowithinputfrequenciesabove5kHzto10kHz, theoutput

will slowly wander around a few percent.

A bigger error caused by the variation of the LTC1966

output impedance is imperfect cancelation of the output

offsetintroducedbytheinjectedcurrent.Theoffsetcorrec-

tion provided by the LT1494 will be based on a consistent

84.5kΩtimestheinjectedcurrent,whiletheLTC1966output

impedancewillvaryenoughthattheoutputoffsetwillhave

a 300µV range about the nominal 2.5mV. If this level of

output offset is not acceptable, either system calibration

orapotentiometerintheLT1494feedbackmaybeneeded.

If the two 10MΩ feed resistors to the LT1494 have signifi-

cant mismatch, cancellation of the 2.5mV offset would be

further impacted, so it is probably worth paying an extra

pennyorsofor1%resistorsoreventhebettertemperature

stability of thin film devices. The 300mV feed voltage is

not particularly critical because it is nominally cancelled,

but the offset errors due to these resistance mismatches

is scaled by that voltage.

Note that the input bias current of the op amp used in

Figure 23 is also nominally cancelled, but it will add or

subtract to the total current injected into the LTC1966

output. With the 1nA I

of the LT1494 this is negligible.

BIAS

While it is possible to eliminate the feed resistors by using

an op amp with a PNP input stage whose I is 30nA

BIAS

1966fb

25

LTC1966

applicaTions inForMaTion

Input Impedance

This resistive divider calculation does give the correct

model of what voltage is seen at the input terminals by a

parallel load averaged over a several clock cycles, which is

what a large shunt capacitor will do—average the current

spikes over several clock cycles.

The LTC1966 true RMS-to-DC converter utilizes a 2.5pF

capacitor to sample the input at a nominal 100kHz sample

frequency. This accounts for the 8MΩ input impedance.

See Figure 24 for the equivalent analog input circuit. Note

however, that the 8MΩ input impedance does not directly

affect the input sampling accuracy. For instance, if a 100k

sourceresistanceisusedtodrivetheLTC1966,thesampling

action of the input stage will drag down the voltage seen

at the input pins with small spikes at every sample clock

edge as the sample capacitor is connected to be charged.

The time constant of this combination is small, 2.5pF •

100kΩ = 250ns, and during the 2.5µs period devoted to

sampling, ten time constants elapse. This allows each

sample to settle to within 46ppm and it is these samples

that are used to compute the RMS value.

Whenhighsourceimpedancesareused,caremustbetaken

to minimize shunt capacitance at the LTC1966 input so as

not to increase the settling time. Shunt capacitance of just

2.5pF will double the input settling time constant and the

error in the above example grows from 46ppm to 0.67%

(6700ppm). A 13pF scope probe will increase the error

to almost 20%. As a consequence, it is important to not

try to filter the input with large input capacitances unless

driven by a low impedance. Keep time constant <<2.5µs.

WhentheLTC1966isdrivenbyopampoutputs,whoselow

DC impedance can be compromised by sharp capacitive

load switching, a small series resistor may be added. A

10kresistorwilleasilysettlewiththe2.5pFinputsampling

capacitor to within 1ppm.

V

DD

I

IN1

R

(TYP)

SW

6k

IN1

V

_IN1− V

C

IN2

EQ

I IN1

=

(

)

AVG

2.5pF

(TYP)

R_EQ

− V

V

DD

V

SS

IN2

IN1

Theseareimportantpointstoconsiderbothduringdesign

anddebug.Duringlabdebug,andevenproductiontesting,

a high value series resistor to any test point is advisable.

I IN2

(

R_EQ= 8MΩ

=

)

I

IN2

R_EQ

R

(TYP)

SW

6k

IN2

C

EQ

2.5pF

(TYP)

1966 F24

V

SS

Output Impedance

Figure 24. LTC1966 Equivalent Analog Input Circuit

The LTC1966 output impedance during operation is simi-

larly due to a switched capacitor action. In this case, 59pF

ofon-chipcapacitanceoperatingat100kHztranslatesinto

170kΩ. The closed loop RMS-to-DC calculation cuts that

in half to the nominal 85kΩ specified.

This is a much higher accuracy than the LTC1966 conver-

sion limits, and far better than the accuracy computed via

the simplistic resistive divider model:

In order to create a DC result, a large averaging capacitor

is required. Capacitive loading and time constants are not

an issue on the output.

R_IN

V = V_SOURCE

IN

R_IN+R_SOURCE

8MΩ

8MΩ + 100kΩ

= V_SOURCE

= V_SOURCE– 1.25%

1966fb

26

LTC1966

applicaTions inForMaTion

However, resistive loading is an issue and the 10MΩ

impedance of a DMM or 10× scope probe will drag the

output down by –0.85% typ.

Use of a guard ring, wherein the LTC1966 output node is

completely surrounded by a low impedance voltage, can

reduce leakage related errors substantially. The ground

ring can be tied to OUTRTN (Pin 6) and should encircle the

output (Pin 5), the averaging capacitor terminal, and the

destination terminal at the ADC, filter op amp, or whatever

else may be next.

During shutdown, the switching action is halted and a

fixed 30k resistor shunts V

is discharged.

to OUT RTN so that C

OUT

AVE

Guard Ringing the Output

Figure 24a shows a sample PCB layout for the circuit of

Figure 13, wherein the guard ring trace encloses R1, R2,

and the terminals of C1, C2, and the op amp input con-

nected to the high impedance LTC1966 Output. For the

circuit of figure 14, the guard ring should enclose R1 and

the terminals of C1 and C2, as well as the terminal at the

ultimate destination.

The LTC1966’s combination of precision and high output

impedance can present challenges that make the use of

a guard ring around the output a good idea for many ap-

plications.

As mentioned above, a 10M resistive loading to ground

will drag down the gain far more than the specificed gain

tolerance. On a printed circuit board, contaminants from

solder flux residue to finger grime can create parasitic

resistances, which may be very high impedance, but can

have deleterious effects on the realized accuracy. As an

Figure 24b shows a sample PCB layout for the circuit of

Figure 23. The summing node of the LT1494 has the same

highimpedanceandhighaccuracyastheLTC1966output,

so here the guard ring encircles both of them. Any leakage

between them is benign because the LT1494 forces them

to the same nominal voltage.

example, if the output (Pin 5) is routed near V (Pin 4)

SS

in a 5V application, a parasitic resistance of 1ꢀ (1,000M)

is enough to introduce a –425µV output offset error, more

than the specified limit of the LTC1966 itself.

LTC1966

MS8

0.1µF

1966 F24b

LT1494

SO8

C

AVE

1µF

LTC1966

MS8

LT1880

SO8

C

AVE

1µF

0.1µF

Figure 24b. PCB Layout of Figure 23 with Guard Ring

1966 F24a

Figure 24a. PCB Layout of Figure 13 with Guard Ring

1966fb

27

LTC1966

applicaTions inForMaTion

Interfacing with an ADC

for are the input impedance, and any input sampling cur-

rents. The input sampling currents drawn by ∆∑ ADCs

often have large spikes of current with short durations

The LTC1966 output impedance and the RMS averaging

ripple need to be considered when using an analog-to-

digitalconverter(ADC)todigitizetheLTC1966RMSresult.

that can confuse some op amps, but with the large C

needed by the LTC1966 these are not an issue.

AVE

The simplest configuration is to connect the LTC1966

directly to the input of a type 7106/7136 ADC as shown

in Figure 25a. These devices are designed specifically for

DVM/DPM use and include display drivers for a 3 1/2 digit

LCD segmented display. Using a dual slope conversion,

theinputissampledoveralongintegrationwindow,which

resultsinrejectionoflinefrequencyripplewhenintegration

timeisanintegernumberoflinecycles.Finally,theseparts

have an input impedance in the ꢀΩ range, with specified

input leakage of 10pA to 20pA. Such a leakage, combined

with the LTC1966 output impedance, results in just 1µV

to 2µV of additional output offset voltage.

The average current is important, as it can create LTC1966

errors; if it is constant it will create an offset, while aver-

age currents that change with the voltage level create gain

errors. Some converters run continuously, others only

sample upon demand, and this will change the results in

ways that need to be understood. The LTC1966 output

impedance has a loose tolerance relative to the usual re-

sistors and the same can be true for the input impedance

of ∆∑ ADC, resulting in gain errors from part-to-part. The

system calibration techniques described in the following

section should be used in applications that demand tight

tolerances.

One example of driving an oversampling ∆∑ ADC is shown

in Figure 25b. In this circuit, the LTC2420 is used with a

LTC1966

OUTPUT

7106 TYPE

IN HI

5

6

31

30

1V V . Since the LTC1966 output voltage range is about

C

REF

AVE

OUT RTN

IN LO

1V, and the LTC2420 has a 12.5% extended input range,

this configuration matches the two ranges with room to

spare. The LTC2420 has an input impedance of 16.6MΩ,

resulting in a gain error of –0.4% to –0.6%. In fact, the

LTC2420 DC input current is not zero at 0V, but rather at

one half its reference, so both an output offset and a gain

error will result. These errors will vary from part to part,

but with a specific LTC1966 and LTC2420 combination,

the errors will be fixed, varying less than 0.05% over

temperature. So a system that has digital calibration can

bequiteaccuratedespitethenominalgainandoffseterror.

With 20 bits of resolution, this part is more accurate than

the LTC1966, but the extra resolution is helpful because

it reduces nonlinearity at the LSB transitions as a digital

gain correction is made. Furthermore, its small size and

ease of use make it attractive.

1966 F25a

Figure 25a. Interfacing to DVM/DPM ADC

LTC1966

LTC2420

2

3

4

1V

V

REF

5

6

OUTPUT

OUT RTN

V

IN

SDO

SERIAL

DATA

C

AVE

GND SCK

CS

1966 F25b

DIGITALLY CORRECT

LOADING ERRORS

Figure 25b. Interfacing to LTC2420

Another type of ADC that has inherent rejection of RMS

averagingrippleisanoversampling∆∑.Withmost,butnot

all, of these devices, it is possible to connect the LTC1966

output directly to the converter input. Issues to look out

1966fb

28

LTC1966

applicaTions inForMaTion

As is shown in Figure 25b, where the LTC2420 is set to

continuously convert by grounding the CS pin. The gain

error will be less if CS is driven at a slower rate, however,

the rate should either be consistent or at a rate low enough

thattheLTC1966anditsoutputcapacitorhavefullysettled

by the beginning of each conversion, so that the loading

errors are consistent.

LTC2420

SO8

LTC1966

MS8

1966 F26b

C

AVE

1µf

Note that in this circuit, the input current of the LTC2420

is being used to assure monotonicity. The LTC2420 Z of

Figure 26b. PCB Layout of Figure 25b with Guard Ring

IN

16.6MΩ is effectively connected to half the reference volt-

age,sowhentheLTC1966haszerosignal,500mV/16.6MΩ

= 30nA is provided.

Figure 10 in Application Note 75, for instance, details a

10-bit ADC with a 35ms conversion time that uses just

29µA of supply current. Such an ADC may also be of use

within a 4mA to 20mA loop.

Alternatively, a 5V V

can be used, but in this case the

REF

LTC1966 output span will only use 20% of the LTC2420’s

input voltage range. Furthermore, if the OUTRTN remains

grounded, the injected current with zero signal will be

150nA, resulting in 5× the offset error and nonlinearity

shown in Figure 22.

Other types of ADCs sample the input signal once and

performaconversiononthatonesample.WiththeseADCs

(Nyquist ADCs), a post filter will be needed in most cases

to reduce the peak error with low input frequencies. The

DC accurate filter of Figure 14 is attractive from an error

standpoint, but it increases the impedance at the ADC

input. In most cases, the buffered post filter of Figure 13

will be more appropriate for use with Nyquist analog-to-

digital converters.

In both of the circuits of Figure 25, a guard ring only has to

encirclethreeterminals,theLTC1966output,thetopofthe

averaging capacitor, and the ADC input. Figure 26 shows

the top copper patterns for example PCB layouts of each.

The low power consumption of the LTC1966 makes it well

suitedforbatterypoweredapplications,anditsslowoutput

(DC) makes it an ideal candidate for a micropower ADC.

SYSTEM CALIBRATION

The LTC1966 static accuracy can be improved with end

system calibration. Traditionally, calibration has been

done at the factory, or at a service depot only, typically

using manually adjusted potentiometers. Increasingly,

systems are being designed for electronic calibration

where the accuracy corrections are implemented in digital

code wherever possible, and with calibration DACs where

necessary. Additionally, many systems are now designed

for self calibration, in which the calibration occurs inside

the machine, automatically without user intervention.

LTC1966

MS8

ICL7106

MQFP

C

AVE

1µf

1966 F26a

Figure 26a. PCB Layout of Figure 25a with Guard Ring

1966fb

29

LTC1966

applicaTions inForMaTion

Whatever calibration scheme is used, the linearity of the

LTC1966 will improve the calibrated accuracy over that

achievablewitholderlog/antilogRMS-to-DCconverters.

Additionally, calibration using DC reference voltages are

essentially as accurate with the LTC1966 as those using

AC reference voltages. Older log/antilog RMS-to-DC

converters required nonlinear input stages (rectifiers)

whose linearity would typically render DC based calibra-

tion unworkable.

and will no doubt be more tempting to correct for. Design-

ers are likewise cautioned against correcting for all of the

nonlinearity.

AC-Only, 1 Point

The dominant error at full-scale will be caused by the

gain error, and by applying a full-scale sine wave input,

this error can be measured and corrected for. Unlike older

log/antilog RMS-to-DC converters, the correction should

be made for zero error at full scale to minimize errors

throughout the dynamic range.

The following are four suggested calibration methods.

Implementations of the suggested adjustments are de-

pendent on the system design, but in many cases, gain

and output offset can be corrected in the digital domain,

and will include the effect of all gains and offsets from the

LTC1966 output through the ADC. Input offset voltage, on

the other hand, will have to be corrected with adjustment

to the actual analog input to the LTC1966.

The best frequency for the calibration signal is roughly ten

times the –0.1% DC error frequency. For 1µF, –0.1% DC

erroroccursat8Hz,so80Hzisagoodcalibrationfrequency,

although anywhere from 60Hz to 100Hz should suffice.

The trade-off here is that on the one hand, the DC error

is input frequency dependent, so a calibration signal

frequency high enough to make the DC error negligible

should be used. On the other hand, as low a frequency as

can be used is best to avoid attenuation of the calibrated

AC signal, either from parasitic RC loading or insufficient

op amp gain. For instance, with a 1kHz calibration signal,

a 1MHz op amp will typically only have 60dB of open loop

gain,soitcouldattenuatethecalibrationsignalafull0.1%.

The methods below assume the unaltered linearity of the

LTC1966, i.e. without the monotonicity fix of Figure 21.

If this is present, the V

shift it introduces should be

OOS

taken out before using either method for which V

is

OOS

not calibrated. Also, the nonlinearity it introduces will

increase the 20mV readings discussed below by 0.78%

but increase the 200mV readings only 78ppm. There

are a variety of ways to deal with these errors, including

possibly ignoring them, but the specifics will depend on

system requirements. Designers are cautioned to avoid

the temptation to digitally take out the hyperbolic transfer

function introduced because if the offsets are not exactly

the nominals assumed, the system will end up right back

where it began with a potential discontinuity with zero

input, either from a divide by zero or from a square root

of a negative number in the calculations to undo the hy-

perobic transfer function. An adaptive algorithm would

most likely be necessary to safely take out more than half

of the introduced nonlinearity.

AC-Only, 2 Point

ThenextmostsignificanterrorforAC-coupledapplications

will be the effect of output offset voltage, noticeable at the

bottom end of the input scale. This too can be calibrated

out if two measurements are made, one with a full-scale

sine wave input and a second with a sine wave input (of

the same frequency) at 10% of full-scale. The trade-off in

selectingthissecondlevelisthatitshouldbesmallenough

that the gain error effect becomes small compared to the

gain error effect at full-scale, while on the other hand,

not using so small an input that the input offset voltage

becomes an issue.

If a 5V reference is used in the connection of Figure 25b,

the V

and nonlinearity created would be even larger,

OOS

1966fb

30

LTC1966

applicaTions inForMaTion

The calculations of the error terms for a 200mV full-scale

case are:

Note: Calculation of and correction for input offset voltage

are the only way in which the two LTC1966 inputs (IN1,

IN2) are distinguishable from each other. The calculation

above assumes the standard definition of offset; that a

positive offset is the case of a positive voltage error inside

the device that must be corrected by applying a like nega-

tive voltage outside. The offset is referred to whichever

pin is driven positive for the +full-scale reading.

Reading at 200mV – Reading at 20mV

Gain =

180mV

Reading at 20mV

Output Offset =

– 20mV

Gain

DC, 2 Point

DC, 3 Point

DCbasedcalibrationispreferableinmanycasesbecausea

DC voltage of known, good accuracy is easier to generate

than such an AC calibration voltage. The only down side

is that the LTC1966 input offset voltage plays a role. It is

therefore suggested that a DC based calibration scheme

check at least two points: full-scale. Applying the –full-

scale input can be done by physically inverting the voltage

or by applying the same +full-scale input to the opposite

LTC1966 input.

One more point is needed with a DC calibration scheme

to determine output offset voltage: +10% of full scale.

The calculation of the input offset is the same as for the

2-point calibration above, while the gain and output offset

are calculated for a 200mV full-scale case as:

Reading at 200mV –Reading at 20mV

Gain =

180mV

Output Offset =

For an otherwise AC-coupled application, only the gain

term may be worth correcting for, but for DC-coupled ap-

plications, the input offset voltage can also be calculated

and corrected for.

Reading at 200mV +Reading at – 200mV – 400mV •Gain

2

The calculations of the error terms for a 200mV full-scale

case are:

Reading at 200mV +Reading at – 200mV

Gain =

400mV

Reading at – 200mV – Reading at 200mV

Input Offset =

2•Gain

1966fb

31

LTC1966

applicaTions inForMaTion

TROUBLESHOOTING GUIDE

4. ꢀain is low by a few percent, along with other screwy

results.

Top Ten LTC1966 Application Mistakes

– Probably tried to use output in a floating, differential

manner.

1. Circuit won’t work–Dead On Arrival–no power drawn.

– Probably forgot to enable the LTC1966 by pulling

Pin 8 low.

Solution: Tie Pin 6 to a low impedance. See Output

Connections in the Design Cookbook.

Solution: Tie Pin 8 to Pin 1.

GROUND PIN 6

2. Circuit won’t work, but draws power. Zero or

very little output, single-ended input application.

– Probably didn’t connect both input pins.

LTC1966

TYPE 7136

ADC

5

6

31

30

Solution: Tie both inputs to something. See Input

Connections in the Design Cookbook.

V

HI

OUT

OUT RTN

LO

1966 TS04

CONNECT PIN 3

2

IN1

5. Offsets perceived to be out of specification because 0V

in ≠ 0V out.

LTC1966

3

– Theoffsetsarenotspecifiedat0Vin.NoRMS-to-DC

converter works well at 0 due to a divide-by-zero

calculation.

IN2

NC

1966 TS02

Solution: Measure V /V

by extrapolating

IOS OOS

readings > 5mV .

DC

3. Screwy results, particularly with respect to linearity

or high crest factors; differential input application.

– Probably AC-coupled both input pins.

6. Linearityperceivedtobeoutofspecificationparticularly

with small input signals.

– This could again be due to using 0V in as one of the

measurement points.

Solution: Make at least one input DC-coupled. See

Input Connections in the Design Cookbook.

Solution:CheckLinearityfrom5mV

to500mV

.

RMS

–

The input offset voltage can cause small AC

linearity errors at low input amplitudes as well. See

Error Analyses section.

DC CONNECT ONE INPUT

Possible Solution: Include a trim for input offset.

2

IN1

LTC1966

3

IN2

1966 TS03

1966fb

32

LTC1966

applicaTions inForMaTion

7. Output is noisy with >10kHz inputs.

10. ꢀain is low by ≅ 1% or more, no other problems.

– This is a fundamental characteristic of this topol-

ogy. The LTC1966 is designed to work very well

with inputs of 1kHz or less. It works okay as high

as 1MHz, but it is limited by aliased ∆S noise.

– Probably due to circuit loading. With a DMM or

a 10× scope probe, Z = 10MΩ. The LTC1966

IN

output is 85kΩ, resulting in –0.85% gain error.

Output impedance is higher with the DC accurate

post filter.

Solution: Bandwidth limit the input or digitally filter

the resulting output.

Solution: Remove the shunt loading or buffer the

output.

8. Large errors occur at crest factors approaching, but

less than 4.

– Loading can also be caused by cheap averaging

capacitors.

– Insufficient averaging.

Solution:IncreaseC .SeeCrestFactorandAC+DC

Solution: Use a high quality metal film capacitor

AVE

Waveforms section for discussion of output droop.

for C

.

AVE

9. Screwy results, errors > spec limits, typically 1% to 5%.

– High impedance (85kΩ) and high accuracy (0.1%)

require clean boards! Flux residue, finger grime, etc.

all wreak havoc at this level.

LOADING DRAGS DOWN GAIN

Solution: Wash the board.

mV

LTC1966

5

6

DCV

V

OUT

Helpful Hint: Sensitivity to leakages can be reduced

significantly through the use of guard traces.

85k

10M

OUT RTN

DMM

IN

200mV

RMS

KEEP BOARD CLEAN

–0.85%

1966 TS10

LTC1966

1966fb

33

LTC1966

Typical applicaTions

5V Supplies, Differential, DC-Coupled

RMS-to-DC Converter

5V Single Supply, Differential, AC-Coupled

RMS-to-DC Converter

5V

V

DD

LTC1966

IN1

IN2 OUT RTN

GND EN

LTC1966

IN1

IN2 OUT RTN

GND EN

DC + AC

INPUTS

PEAK

DIFFERENTIAL)

AC INPUTS

PEAK

DIFFERENTIAL)

V

DC OUTPUT

V

DC OUTPUT

OUT

C

AVE

1µF

(1V

AVE

(1V

1µF

V

SS

C

0.1µF

1966 TA03

1966 TA05

–5V

2.5V Supplies, Single Ended, DC-Coupled

RMS-to-DC Converter with Shutdown

2.7V Single Supply, Single Ended, AC-Coupled

RMS-to-DC Converter with Shutdown

0.1µF

2.5V

2.7V/3V CMOS

2.7V

OFF

X7R

ON

2V

–2.5V

OFF ON

–2V

EN

LTC1966

IN1

IN2 OUT RTN

GND

V

DD

EN

LTC1966

IN1

IN2 OUT RTN

V

DD

AC INPUT

V

DC OUTPUT

DC + AC

INPUT

(1V

OUT

(1V

PEAK

)

C

AVE

V

DC OUTPUT

OUT

1µF

C

AVE

)

PEAK

C

0.1µF

1µF

V

SS

V

GND

SS

1966 TA04

1966 TA06

–2.5V

Battery Powered Single-Ended AC-Coupled

RMS-to-DC Converter

AC INPUT

(1V

PEAK

)

V

DD

C

9V

0.1µF

LTC1966

IN1

IN2 OUT RTN

GND EN

DC

OUTPUT

V

OUT

C

AVE

1µF

0.1µF

X7R

GND

LT1175CS8-5

V

SS

SHDN

OUT

V

SENSE

IN

1966 TA07

1966fb

34

LTC1966

siMpliFieD scheMaTic

V

DD

C12

GND

V

SS

C1

Y1

Y2

C2

2nd ORDER ∆∑ MODULATOR

IN1

IN2

C7

C3

C4

C5

C9

OUTPUT

+

–

C

C11

AVE

A1

A2

–

C8

OUT RTN

1966 SS

C6

C10

CLOSED

DURING

SHUTDOWN

30k

EN

BLEED RESISTOR

FOR C

AVE

TO BIAS CONTROL

1966fb

35

LTC1966

package DescripTion

MS8 Package

8-Lead Plastic MSOP

(Reference LTC DWꢀ # 05-08-1660 Rev F)

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

0.52

(.0205)

REF

8

7 6 5

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

4.90 ± 0.152

(.193 ± .006)

0.889 ± 0.127

(.035 ± .005)

DETAIL “A”

0.254

(.010)

0° – 6° TYP

GAUGE PLANE

5.23

(.206)

MIN

1

2

3

4

3.20 – 3.45

(.126 – .136)

0.53 ± 0.152

(.021 ± .006)

1.10

(.043)

MAX

0.86

(.034)

REF

DETAIL “A”

0.18

(.007)

0.65

(.0256)

BSC

0.42 ± 0.038

(.0165 ± .0015)

SEATING

PLANE

TYP

0.22 – 0.38

0.1016 ± 0.0508

RECOMMENDED SOLDER PAD LAYOUT

(.009 – .015)

(.004 ± .002)

0.65

(.0256)

BSC

TYP

NOTE:

MSOP (MS8) 0307 REV F

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

1966fb

36

LTC1966

revision hisTory ^{(Revision history begins at Rev B)}

REV

DATE

DESCRIPTION

PAGE NUMBER

B

5/11

Revised entire data sheet to add H- and MP- grades

1 to 38

1966fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

37

LTC1966

Typical applicaTion

RMS Noise Measurement

5V

VOLTAGE

NOISE IN

5V

1mV

RMS

DC

NOISE

V

DD

V

=

OUT

1µV

+

LTC1966

IN1

IN2 OUT RTN

GND EN

10k

1/2

LTC6203

V

OUT

100Ω

C

1µF

AVE

–

V

SS

–5V

100k

0.1µF

1966 TA10

–5V

100Ω

1.5µF

BW 1kHz TO 100kHz

INPUT SENSITIVITY = 1µV

TYP

RMS

Single Supply RMS Current Measurement

70A Current Measurement

+

5V

V

LTC1966

IN1

LTC1966

IN1

AC CURRENT

71.2A MAX

V

OUT

DC RMS

AC CURRENT

71.2A MAX

50Hz TO 400Hz

V

T1 10Ω

OUT

4mV /A

V

V = 4mV /A

OUT DC RMS

T1 10Ω

C

OUT

AVE

50Hz TO 400Hz

C

AVE

IN2 OUT RTN

GND EN

1µF

IN2 OUT RTN

GND EN

1µF

V

SS

V

100k

SS

–5V

1966 TA08

T1: CR MAGNETICS CR8348-2500-N

www.crmagnetics.com

0.1µF

1966 TA09

T1: CR MAGNETICS CR8348-2500-N

www.crmagnetics.com

relaTeD parTs

PART NUMBER

LT^®1077

DESCRIPTION

Micropower, Single Supply Precision Op Amp

COMMENTS

48µA I , 60µV V

, 450pA I

OS(MAX) OS(MAX)

SY

LT1175-5

LT1494

Negative, –5V Fixed, Micropower LDO Regulator

1.5µA Max, Precision Rail-to-Rail I/O Op Amp

ꢀeneral Purpose SOT-23 Rail-to-Rail Op Amp

SOT-23 Rail-to-Rail Output Precision Op Amp

Precision, Extended Bandwidth RMS to DC Converter

Precision, Wide Bandwidth RMS to DC Converter

Zero Drift Op Amp in SOT-23

45µA I , Available in SO-8 or SOT-223

Q

375µV V

, 100pA I

OS(MAX) OS(MAX)

LT1782

40µA I , 800µV V

, 2nA I

OS(MAX) OS(MAX)

SY

LT1880

1.2mA I , 150µV V

, 900pA I

OS(MAX) OS(MAX)

SY

LTC1967

LTC1968

LTC2050

LT2178/LT2178A

LTC2402

LTC2420

LTC2422

330µA I , ∆∑ RMS Conversion to 4MHz

SY

2.3mA I , ∆∑ RMS Conversion to 15MHz

SY

750µA I , 3µV V

, 75pA I

OS(MAX) B(MAX)

SY

17µA Max, Single Supply Precision Dual Op Amp

14µA I , 120µV V

, 350pA I

OS(MAX) OS(MAX)

SY

™

200µA I , 4ppm INL, 10ppm TUE

2-Channel, 24-bit, Micropower, No Latency ∆S ADC

SY

200µA I , 8ppm INL, 16ppm TUE

20-bit, Micropower, No Latency ∆S ADC in SO-8

2-Channel, 20-bit, Micropower, No Latency ∆S ADC

SY

Dual Channel Version of LTC2420

1966fb

LT 0511 REV B • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

38

●

 LINEAR TECHNOLOGY CORPORATION 2001

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT2178A
厂家：	Linear
描述：	Precision Micropower RMS-to-DC Converter 精密微功耗RMS至DC转换器转换器
文件：	总38页 (文件大小：369K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT2178A [Linear]

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