LT3023EDD#TRPBF [Linear]
LT3023 - Dual 100mA, Low Dropout, Low Noise, Micropower Regulator; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C;
| 型号： | LT3023EDD#TRPBF |
| 厂家： | 
Linear |
| 描述： | LT3023 - Dual 100mA, Low Dropout, Low Noise, Micropower Regulator; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C PC 光电二极管 输出元件 调节器 |
| 文件： | 总16页 (文件大小：275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3023
Dual 100mA,
Low Dropout, Low Noise,
Micropower Regulator
FEATURES
DESCRIPTION
The LT®3023 is a dual, micropower, low noise, low drop-
out regulator. With an external 0.01μF bypass capacitor,
n
Low Noise: 20μV
(10Hz to 100kHz)
RMS
n
Low Quiescent Current: 20μA/Channel
Wide Input Voltage Range: 1.8V to 20V
Output Current: 100mA/Channel
Very Low Shutdown Current: <0.1μA
Low Dropout Voltage: 300mV at 100mA
Adjustable Output from 1.22V to 20V
Stable with 1μF Output Capacitor
Stable with Aluminum, Tantalum or
Ceramic Capacitors
n
n
n
n
n
n
n
output noise drops to 20μV
over a 10Hz to 100kHz
RMS
bandwidth. Designedforuseinbattery-poweredsystems,
the low 20μA quiescent current per channel makes it an
ideal choice. In shutdown, quiescent current drops to less
than 0.1μA. Shutdown control is independent for each
channel,allowingforflexibilityinpowermanagement.The
device is capable of operating over an input voltage from
1.8V to 20V, and can supply 100mA of output current from
each channel with a dropout voltage of 300mV. Quiescent
current is well controlled in dropout.
n
n
n
n
n
Reverse Battery Protected
No Reverse Current
No Protection Diodes Needed
Overcurrent and Overtemperature Protected
Thermally Enhanced 10-Lead MSOP and DFN
Packages
The LT3023 regulator is stable with output capacitors as
low as 1μF. Small ceramic capacitors can be used without
the series resistance required by other regulators.
Internal protection circuitry includes reverse battery
protection, current limiting, thermal limiting and reverse
current protection. The device is available as an adjust-
able device with a 1.22V reference voltage. The LT3023
regulator is available in the thermally enhanced 10-lead
MSOP and DFN packages.
APPLICATIONS
n
Cellular Phones
n
Pagers
n
Battery-Powered Systems
Frequency Synthesizers
n
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
n
Wireless Modems
TYPICAL APPLICATION
3.3V/2.5V Low Noise Regulators
10Hz to 100kHz Output Noise
3.3V AT100mA
IN
SHDN1
SHDN2
OUT1
20μV
NOISE
V
RMS
IN
3.7V TO
20V
1μF
0.01μF
10μF
422k
249k
BYP1
ADJ1
V
OUT
LT3023
20μV
RMS
100μV/DIV
2.5V AT100mA
OUT2
20μV
NOISE
RMS
0.01μF
10μF
261k
249k
BYP2
ADJ2
3023 TA01b
GND
3023 TA01
3023fa
1
LT3023
ABSOLUTE MAXIMUM RATINGS
(Note 1)
IN Pin Voltage ......................................................... 20V
OUT1, OUT2 Pin Voltage......................................... 20V
Input to Output Differential Voltage......................... 20V
ADJ1, ADJ2 Pin Voltage............................................ 7V
BYP1, BYP2 Pin Voltage ........................................ 0.6V
SHDN1, SHDN2 Pin Voltage ................................... 20V
Output Short-Circut Duration........................... Indefinite
Operating Junction Temperature Range
(Note 2) ............................................. –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
(MSE package only)
PIN CONFIGURATION
TOP VIEW
TOP VIEW
BYP2
ADJ2
GND
1
2
3
4
5
10 OUT2
BYP2
ADJ2
GND
ADJ1
BYP1
1
2
3
4
5
10 OUT2
9
8
7
6
SHDN2
IN
9
8
7
6
SHDN2
IN
SHDN1
OUT1
11
11
ADJ1
BYP1
SHDN1
OUT1
MSE PACKAGE
10-LEAD PLASTIC MSOP
DD PACKAGE
T
= 150°C, θ = 40°C/W, θ = 10°C/W
JMAX
JA JC
10-LEAD (3mm s 3mm) PLASTIC DFN
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
T
= 125°C, θ = 40°C/W, θ = 10°C/W
JMAX
JA JC
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LT3023EDD#PBF
LT3023IDD#PBF
LT3023EMSE#PBF
LT3023IMSE#PBF
LEAD BASED FINISH
LT3023EDD
TAPE AND REEL
LT3023EDD#TRPBF
LT3023IDD#TRPBF
LT3023EMSE#TRPBF
LT3023IMSE#TRPBF
TAPE AND REEL
LT3023EDD#TR
PART MARKING*
LAJA
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead Plastic MSOP
LAJA
LTAHZ
LTAHZ
10-Lead Plastic MSOP
PART MARKING*
LAJA
PACKAGE DESCRIPTION
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead Plastic MSOP
LT3023IDD
LT3023IDD#TR
LAJA
LT3023EMSE
LT3023EMSE#TR
LT3023IMSE#TR
LTAHZ
LT3023IMSE
LTAHZ
10-Lead Plastic MSOP
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
PARAMETER
CONDITIONS
= 100mA
MIN
TYP
MAX
UNITS
l
l
Minimum Input Voltage
(Notes 3, 11)
I
1.8
2.3
V
LOAD
ADJ1, ADJ2 Pin Voltage
(Note 3, 4)
V
= 2V, I
= 1mA
1.205
1.190
1.220
1.220
1.235
1.250
V
V
IN
LOAD
2.3V < V < 20V, 1mA < I
< 100mA
IN
LOAD
3023fa
2
LT3023
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
PARAMETER
CONDITIONS
ΔV = 2V to 20V, I
MIN
TYP
1
MAX
UNITS
l
l
l
l
l
l
Line Regulation (Note 3)
Load Regulation (Note 3)
= 1mA
LOAD
10
mV
IN
V
IN
V
IN
= 2.3V, ΔI
= 2.3V, ΔI
= 1mA to 100mA
= 1mA to 100mA
1
12
25
mV
mV
LOAD
LOAD
Dropout Voltage
I
I
= 1mA
= 1mA
0.10
0.17
0.24
0.30
0.15
0.19
V
V
LOAD
LOAD
V
= V
(Notes 5, 6, 11)
OUT(NOMINAL)
IN
I
I
= 10mA
= 10mA
0.22
0.29
V
V
LOAD
LOAD
I
I
= 50mA
= 50mA
0.28
0.38
V
V
LOAD
LOAD
I
I
= 100mA
= 100mA
0.35
0.45
V
V
LOAD
LOAD
l
l
l
l
l
GND Pin Current (Per Channel)
= V (Notes 5, 7)
I
I
I
I
I
= 0mA
20
55
45
100
400
2
μA
μA
LOAD
LOAD
LOAD
LOAD
LOAD
V
= 1mA
IN
OUT(NOMINAL)
= 10mA
= 50mA
= 100mA
230
1
μA
mA
mA
2.2
4
Output Voltage Noise
C
= 10μF, C
= 0.01μF, I
= 100mA, BW = 10Hz to 100kHz
20
30
μV
RMS
OUT
BYP
LOAD
ADJ1/ADJ2 Pin Bias Current
Shutdown Threshold
(Notes 3, 8)
100
1.4
nA
l
l
V
OUT
V
OUT
= Off to On
= On to Off
0.8
0.65
V
V
0.25
l
l
SHDN1/SHDN2 Pin Current
(Note 9)
V
V
= 0V
= 20V
0
1
0.5
3
μA
μA
SHDN
SHDN
Quiescent Current in Shutdown
Ripple Rejection (Note 3)
V
V
= 6V, V
= 0V (Both SHDN Pins)
0.01
65
0.1
μA
dB
IN
SHDN
= 2.72V (Avg), V
= 50mA
= 0.5V , f = 120Hz,
P-P RIPPLE
55
IN
RIPPLE
I
LOAD
Current Limit
V
V
= 7V, V
= 0V
OUT
200
mA
mA
IN
IN
OUT
l
l
= 2.3V, ΔV
= –5%
110
Input Reverse Leakage Current
V
V
= –20V, V
= 0V
1
mA
μA
IN
OUT
Reverse Output Current (Notes 3,10)
= 1.22V, V < 1.22V
5
10
OUT
IN
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 6: Dropout voltage is the minimum input to output voltage differential
needed to maintain regulation at a specified output current. In dropout, the
output voltage will be equal to: V – V
.
IN
DROPOUT
Note 7: GND pin current is tested with V = 2.44V and a current source
IN
Note 2: The LT3023 is tested and specified under pulse load conditions
load. This means the device is tested while operating in its dropout region
or at the minimum input voltage specification. This is the worst-case GND
pin current. The GND pin current will decrease slightly at higher input
voltages.
Note 8: ADJ1 and ADJ2 pin bias current flows into the pin.
Note 9: SHDN1 and SHDN2 pin current flows into the pin.
Note 10: Reverse output current is tested with the IN pin grounded and the
OUT pin forced to the rated output voltage. This current flows into the OUT
pin and out the GND pin.
Note 11: For the LT3023 dropout voltage will be limited by the minimum
input voltage specification under some output voltage/load conditions.
See the curve of Minimum Input Voltage in the Typical Performance
Characteristics.
such that T ≅ T . The LT3023E is 100% tested at T = 25°C. Performance
J
A
A
at –40°C and 125°C is assured by design, characterization and correlation
with statistical process controls. The LT3023I is guaranteed over the full
–40°C to 125°C operating junction temperature range.
Note 3: The LT3023 is tested and specified for these conditions with the
ADJ1/ADJ2 pin connected to the corresponding OUT1/OUT2 pin.
Note 4: Operating conditions are limited by maximum junction
temperature. The regulated output voltage specification will not apply
for all possible combinations of input voltage and output current. When
operating at maximum input voltage, the output current range must be
limited. When operating at maximum output current, the input voltage
range must be limited.
Note 5: To satisfy requirements for minimum input voltage, the LT3023 is
tested and specified for these conditions with an external resistor divider
(two 250k resistors) for an output voltage of 2.44V. The external resistor
divider will add a 5μA DC load on the output.
3023fa
3
LT3023
TYPICAL PERFORMANCE CHARACTERISTICS
Typical Dropout Voltage
Guaranteed Dropout Voltage
Dropout Voltage
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
= TEST POINTS
T
≤ 125°C
≤ 25°C
J
T
= 125°C
J
I
L
= 100mA
T
J
I
= 50mA
= 10mA
L
T
= 25°C
J
I
L
I
= 1mA
L
0
0
0
40
40
50 60 70 80 90 100
–50 –25
0
25
50
75 100 125
0
10 20 30
50 60 70 80 90 100
0
10 20 30
TEMPERATURE (°C)
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
3023 G03
3023 G01
3023 G02
Quiescent Current
ADJ1 or ADJ2 Pin Voltage
Quiescent Current
40
35
30
25
20
15
10
5
1.240
1.235
1.230
1.225
1.220
1.215
1.210
1.205
1.200
30
25
20
15
10
5
V
= 6V
T
= 25°C
= 250k
IN
L
I = 1mA
L
J
L
R
= 250k
R
I
= 5μA
I
= 5μA
L
L
V
= V
IN
SHDN
V
= V
IN
SHDN
V
= 0V
50
V
= 0V
SHDN
SHDN
0
0
–25
0
25
75
125
–25
0
25
50
75
125
–50
100
–50
100
0
2
4
6
8
10 12 14 16 18 20
INPUT VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
3023 G03
3023 G05
3023 G06
SHDN1 or SHDN2 Pin Threshold
(On-to-Off)
GND Pin Current
GND Pin Current vs ILOAD
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
I
= 1mA
L
T
= 25°C
V
= V
+ 1V
OUT(NOMINAL)
J
IN
*FOR V
= 1.22V
OUT
R
L
= 12.2Ω
L
I
= 100mA*
R
= 24.4Ω
= 50mA*
L
I
L
R
L
= 1.22k
L
R
L
= 122Ω
L
I
= 1mA*
I
= 10mA*
–50 –25
0
25
50
75 100 125
4
40
50 60 70 80 90 100
0
1
2
3
5
6
7
8
9
10
0
10 20 30
TEMPERATURE (°C)
INPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
3023 G09
3023 G07
3023 G08
3023fa
4
LT3023
TYPICAL PERFORMANCE CHARACTERISTICS
SHDN1 or SHDN2 Pin Threshold
(Off-to-On)
SHDN1 or SHDN2 Pin Input
Current
SHDN1 or SHDN2 Pin Input
Current
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
= 20V
SHDN
I
= 100mA
L
I
= 1mA
L
–50
0
25
50
75 100 125
–50
0
25
50
75 100 125
4
–25
–25
0
1
2
3
6
7
8
9
10
5
TEMPERATURE (°C)
TEMPERATURE (°C)
SHDN PIN VOLTAGE (V)
3023 G12
3023 G10
3023 G11
ADJ1 or ADJ2 Pin Bias Current
Current Limit
Current Limit
100
90
80
70
60
50
40
30
20
10
0
350
300
250
200
150
100
50
350
300
250
200
150
100
50
V
T
= 0V
V
V
= 7V
OUT
OUT
J
IN
= 25°C
= 0V
0
0
–50
0
25
50
75 100 125
0
2
3
4
5
6
7
–50
0
25
50
75 100 125
–25
1
–25
TEMPERATURE (°C)
INPUT VOLTAGE (V)
TEMPERATURE (°C)
3023 G13
3023 G14
3023 G15
Reverse Output Current
Reverse Output Current
Input Ripple Rejection
80
70
60
50
40
30
20
10
0
18
15
12
9
100
90
80
70
60
50
40
30
20
10
0
V
V
= 0V
= V
T
V
V
= 25°C
= 0V
IN
OUT
A
IN
= 1.22V
ADJ
= V
OUT
ADJ
CURRENT FLOWS
INTO OUTPUT PIN
C
= 10μF
OUT
6
I
V
C
= 100mA
3
L
C
OUT
= 1μF
= 2.3V + 50mV
RIPPLE
RMS
IN
= 0
BYP
0
50
TEMPERATURE (°C)
100 125
0.01
0.1
1
10
100
1000
4
–50 –25
0
25
75
0
1
2
3
5
6
7
8
9
10
FREQUENCY (kHz)
OUTPUT VOLTAGE (V)
3023 G18
3023 G17
3023 G16
3023fa
5
LT3023
TYPICAL PERFORMANCE CHARACTERISTICS
Input Ripple Rejection
Input Ripple Rejection
Channel-to-Channel Isolation
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
C
= 0.01μF
BYP
V
OUT1
20mV/DIV
C
= 1000pF
BYP
C
= 100pF
BYP
V
OUT2
20mV/DIV
V
= V
+
OUT (NOMINAL)
IN
1V + 0.5V RIPPLE
P-P
3023 G21a
I
V
C
= 100mA
L
50μs/DIV
AT f = 120Hz
= 2.3V + 50mV
RIPPLE
RMS
IN
I
= 50mA
–25
C
C
, C
= 10μF
L
OUT1 OUT2
= 10μF
OUT
, C
= 0.01μF
BYP1 BYP2
ΔI = 10mA to 100mA
0
25
50
75
125
–50
100
0.01
0.1
1
10
100
1000
L1
L2
IN
ΔI = 10mA to 100mA
V
FREQUENCY (kHz)
TEMPERATURE (°C)
= 6V, V
= V
= 5V
OUT1
OUT2
3023 G19
3023 G20
Channel-to-Channel Isolation
Minimum Input Voltage
Load Regulation
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
2.5
2.0
1.5
1.0
0.5
0
100
90
80
70
60
50
40
30
20
10
0
I
= 100mA PER CHANNEL
LOAD
I
= 100mA
L
I
= 50mA
L
Δ
= 1mA TO 100mA
IL
0.01
0.1
1
10
100
1000
50
125
–50 –25
0
25
50
75 100 125
–50
0
25
75 100
–25
FREQUENCY (kHz)
TEMPERATURE (°C)
TEMPERATURE (°C)
3023 G21b
3023 G23
3023 G22
RMS Output Noise vs
Bypass Capacitor
Output Noise Spectral Density
Output Noise Spectral Density
10
1
10
1
160
140
120
100
80
C
I
= 10μF
C
L
= 10μF
C
C
L
= 10μF
= 0
OUT
L
OUT
OUT
BYP
= 100mA
I
= 100mA
f = 10Hz TO 100kHz
I
= 100mA
V
SET FOR 5V
OUT
C
= 1000pF
BYP
V
SET FOR 5V
OUT
V
SET FOR 5V
OUT
C
= 100pF
BYP
V
=V
ADJ
OUT
V
=V
OUT
ADJ
60
0.1
0.01
0.1
0.01
C
= 0.01μF
BYP
40
V
=V
ADJ
OUT
20
0
0.01
0.1
1
10
100
10
100
1k
10k
0.01
0.1
1
10
100
C
(pF)
FREQUENCY (kHz)
FREQUENCY (kHz)
BYP
3023 G26
3023 G25
3023 G24
3023fa
6
LT3023
TYPICAL PERFORMANCE CHARACTERISTICS
RMS Output Noise vs
Load Current (10Hz to 100kHz)
10Hz to 100kHz Output Noise
CBYP = 0
10Hz to 100kHz Output Noise
CBYP = 100pF
160
140
120
100
80
C
= 10μF
OUT
C
= 0μF
BYP
BYP
C
= 0.01μF
V
SET FOR 5V
OUT
V
V
OUT
OUT
100μV/DIV
100μV/DIV
V
=V
ADJ
OUT
60
40
3023 G29
3023 G28
V
SET FOR 5V
OUT
1ms/DIV
1ms/DIV
20
C
I
= 10μF
C
L
= 10μF
OUT
L
OUT
OUT
V
=V
ADJ
OUT
10
= 100mA
I
= 100mA
0
0.01
V
SET FOR 5V OUT
V SET FOR 5V OUT
OUT
0.1
1
100
LOAD CURRENT (mA)
3023 G27
10Hz to 100kHz Output Noise
CBYP = 1000pF
10Hz to 100kHz Output Noise
CBYP = 0.01μF
V
V
OUT
100μV/DIV
OUT
100μV/DIV
3023 G30
3023 G31
1ms/DIV
1ms/DIV
C
L
V
= 10μF
C
= 10μF
OUT
OUT
I
= 100mA
I = 100mA
L
SET FOR 5V OUT
V
SET FOR 5V OUT
OUT
OUT
Transient Response
CBYP = 0
Transient Response
CBYP = 0.01μF
0.2
0.1
0.04
0.02
0
0
–0.1
–0.2
–0.02
–0.04
V
C
C
V
= 6V
IN
IN
V
C
C
V
= 6V
IN
IN
= 10μF
= 10μF
= 10μF
OUT
OUT
= 10μF
OUT
OUT
SET FOR 5V OUT
SET FOR 5V OUT
100
50
0
100
50
0
800
TIME (μs)
80
0
400
1200
1600
2000
0
20 40 60
100 120 140 160 180 200
TIME (μs)
3023 G32
3023 G33
3023fa
7
LT3023
PIN FUNCTIONS
GND (Pin 3): Ground.
SHDN1/SHDN2(Pins7/9):Shutdown.TheSHDN1/SHDN2
pins are used to put the corresponding channel of the
LT3023 regulator into a low power shutdown state. The
output will be off when the pin is pulled low. The SHDN1/
SHDN2 pins can be driven either by 5V logic or open-col-
lector logic with pull-up resistors. The pull-up resistors
are required to supply the pull-up current of the open-
collector gates, normally several microamperes, and the
SHDN1/SHDN2 pin current, typically 1μA. If unused, the
ADJ1/ADJ2 (Pins 4/2): Adjust Pin. These are the inputs to
the error amplifiers. These pins are internally clamped to
7V. They have a bias current of 30nA which flows into the
pin(seecurveofADJ1/ADJ2PinBiasCurrentvsTempera-
ture in the Typical Performance Characteristics section).
The ADJ1 and ADJ2 pin voltage is 1.22V referenced to
ground and the output voltage range is 1.22V to 20V.
BYP1/BYP2 (Pins 5/1): Bypass. The BYP1/BYP2 pins are
used to bypass the reference of the LT3023 regulator to
achieve low noise performance from the regulator. The
pin must be connected to V . The device will not function
IN
if the SHDN1/SHDN2 pins are not connected.
IN (Pin 8): Input. Power is supplied to the device through
the IN pin. A bypass capacitor is required on this pin if
the device is more than six inches away from the main
input filter capacitor. In general, the output impedance of
a battery rises with frequency, so it is advisable to include
a bypass capacitor in battery-powered circuits. A bypass
capacitor in the range of 1μF to 10μF is sufficient. The
LT3023 regulator is designed to withstand reverse volt-
ages on the IN pin with respect to ground and the OUT
pin. In the case of a reverse input, which can happen if
a battery is plugged in backwards, the device will act as
if there is a diode in series with its input. There will be
no reverse current flow into the regulator and no reverse
voltage will appear at the load. The device will protect both
itself and the load.
BYP1/BYP2pinsareclampedinternallyto 0.6V(oneV )
BE
from ground. A small capacitor from the corresponding
output to this pin will bypass the reference to lower the
output voltage noise. A maximum value of 0.01μF can
be used for reducing output voltage noise to a typical
20μV
over a 10Hz to 100kHz bandwidth. If not used,
RMS
this pin must be left unconnected.
OUT1/OUT2(Pins6/10):Output.Theoutputssupplypower
totheloads.Aminimumoutputcapacitorof1μFisrequired
to prevent oscillations. Larger output capacitors will be
required for applications with large transient loads to limit
peak voltage transients. See the Applications Information
section for more information on output capacitance and
reverse output characteristics.
Exposed Pad (Pin 11): Ground. This pin must be soldered
to the PCB and electrically connected to ground.
3023fa
8
LT3023
APPLICATIONS INFORMATION
The LT3023 is a dual 100mA low dropout regulator with
micropower quiescent current and shutdown. The device
is capable of supplying 100mA per channel at a dropout
voltage of 300mV. Output voltage noise can be lowered
IN OUT1/OUT2
LT3023
V
OUT
⎛
⎞
⎟
R2
R1
+
V
= 1.22V 1+
+ I
(
R2
)(
)
OUT
ADJ
V
⎜
IN
⎝
⎠
R2
R1
V
= 1.22V
ADJ
ADJ1/ADJ2
GND
I
= 30nA AT 25°C
ADJ
to 20μV
over a 10Hz to 100kHz bandwidth with the
RMS
OUTPUT RANGE = 1.22V TO 20V
addition of a 0.01μF reference bypass capacitor. Addition-
ally, the reference bypass capacitor will improve transient
response of the regulator, lowering the settling time for
transient load conditions. The low operating quiescent
current (20μA per channel) drops to less than 1μA in
shutdown. In addition to the low quiescent current, the
LT3023 regulator incorporates several protection features
which make it ideal for use in battery-powered systems.
The device is protected against both reverse input and
reverse output voltages. In battery backup applications
where the output can be held up by a backup battery when
the input is pulled to ground, the LT3023 acts like it has a
diodeinserieswithitsoutputandpreventsreversecurrent
flow. Additionally, in dual supply applications where the
regulator load isreturned to a negative supply, the output
can be pulled below ground by as much as 20V and still
allow the device to start and operate.
3023 F01
Figure 1. Adjustable Operation
The device is tested and specified with the ADJ1/ADJ2
pin tied to the corresponding OUT1/OUT2 pin for an out-
put voltage of 1.22V. Specifications for output voltages
greater than 1.22V will be proportional to the ratio of the
desired output voltage to 1.22V: V /1.22V. For example,
load regulation for an output current change of 1mA to
OUT
100mA is –1mV typical at V
load regulation is:
= 1.22V. At V
= 12V,
OUT
OUT
(12V/1.22V)(–1mV) = –9.8mV
Bypass Capacitance and Low Noise Performance
The LT3023 regulator may be used with the addition of a
bypass capacitor from V
to the corresponding BYP1/
OUT
BYP2 pin to lower output voltage noise. A good quality
low leakage capacitor is recommended. This capacitor
will bypass the reference of the regulator, providing a
low frequency noise pole. The noise pole provided by this
bypass capacitor will lower the output voltage noise to
Adjustable Operation
The LT3023 has an output voltage range of 1.22V to 20V.
The output voltage is set by the ratio of two external resis-
tors as shown in Figure 1. The device servos the output
to maintain the corresponding ADJ1/ADJ2 pin voltage
at 1.22V referenced to ground. The current in R1 is then
equal to 1.22V/R1 and the current in R2 is the current in
R1 plus the ADJ1/ADJ2 pin bias current. The ADJ1/ADJ2
pin bias current, 30nA at 25°C, flows through R2 into the
ADJ1/ADJ2 pin. The output voltage can be calculated us-
ing the formula in Figure 1. The value of R1 should be no
greater than 250k to minimize errors in the output voltage
caused by the ADJ1/ADJ2 pin bias current. Note that in
shutdowntheoutputisturnedoffandthedividercurrentwill
bezero. CurvesofADJ1/ADJ2PinVoltagevsTemperature
and ADJ1/ADJ2 Pin Bias Current vs Temperature appear
in the Typical Performance Characteristics.
as low as 20μV
with the addition of a 0.01μF bypass
RMS
capacitor. Using a bypass capacitor has the added benefit
ofimprovingtransientresponse.Withnobypasscapacitor
and a 10μF output capacitor, a 10mA to 100mA load step
will settle to within 1% of its final value in less than 100μs.
With the addition of a 0.01μF bypass capacitor, the output
will stay within 1% for a 10mA to 100mA load step (see
Transient Reponse in Typical Performance Characteristics
section). However, regulator start-up time is proportional
to the size of the bypass capacitor, slowing to 15ms with
a 0.01μF bypass capacitor and 10μF output capacitor.
3023fa
9
LT3023
APPLICATIONS INFORMATION
Output Capacitance and Transient Response
and temperature coefficients as shown in Figures 3 and 4.
When used with a 5V regulator, a 16V 10μF Y5V capacitor
can exhibit an effective value as low as 1μF to 2μF for the
DC bias voltage applied and over the operating tempera-
ture range. The X5R and X7R dielectrics result in more
stable characteristics and are more suitable for use as the
output capacitor. The X7R type has better stability across
temperature, while the X5R is less expensive and is avail-
able in higher values. Care still must be exercised when
using X5R and X7R capacitors; the X5R and X7R codes
only specify operating temperature range and maximum
capacitancechangeovertemperature.Capacitancechange
due to DC bias with X5R and X7R capacitors is better than
Y5VandZ5Ucapacitors,butcanstillbesignificantenough
to drop capacitor values below appropriate levels. Capaci-
tor DC bias characteristics tend to improve as component
The LT3023 regulator is designed to be stable with a
wide range of output capacitors. The ESR of the out-
put capacitor affects stability, most notably with small
capacitors. A minimum output capacitor of 1μF with an
ESR of 3Ω or less is recommended to prevent oscilla-
tions. The LT3023 is a micropower device and output
transientresponsewillbeafunctionofoutputcapacitance.
Larger values of output capacitance decrease the peak
deviations and provide improved transient response for
larger load current changes. Bypass capacitors, used to
decouple individual components powered by the LT3023,
will increase the effective output capacitor value. With
larger capacitors used to bypass the reference (for low
noise operation), larger values of output capacitors are
needed. For 100pF of bypass capacitance, 2.2μF of output
capacitorisrecommended.Witha330pFbypasscapacitor
or larger, a 3.3μF output capacitor is recommended. The
shaded region of Figure 2 defines the region over which
the LT3023 regulator is stable. The minimum ESR needed
isdefinedbytheamountofbypasscapacitanceused,while
the maximum ESR is 3Ω.
20
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
0
X5R
–20
–40
Extra consideration must be given to the use of ceramic
capacitors. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior across
temperature and applied voltage. The most common
dielectrics used are specified with EIA temperature char-
acteristic codes of Z5U, Y5V, X5R and X7R. The Z5U and
Y5V dielectrics are good for providing high capacitances
in a small package, but they tend to have strong voltage
–60
Y5V
–80
–100
0
8
12 14
2
4
6
10
16
DC BIAS VOLTAGE (V)
3023 F03
Figure 3. Ceramic Capacitor DC Bias Characteristics
40
20
4.0
3.5
3.0
X5R
0
–20
STABLE REGION
2.5
2.0
–40
Y5V
C
= 0
1.5
1.0
0.5
0
BYP
C
= 100pF
BYP
–60
C
= 330pF
BYP
C
> 3300pF
BYP
–80
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
–100
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
1
3
6
9 10
8
2
4
5
7
OUTPUT CAPACITANCE (μF)
3023 F02
3023 F04
Figure 2. Stability
Figure 4. Ceramic Capacitor Temperature Characteristics
3023fa
10
LT3023
APPLICATIONS INFORMATION
casesizeincreases, butexpectedcapacitanceatoperating
Characteristics section. Power dissipation will be equal
to the sum of the two components listed above. Power
dissipationfrombothchannelsmustbeconsideredduring
thermal analysis.
voltage should be verified.
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress,
similar to the way a piezoelectric accelerometer or micro-
phone works. For a ceramic capacitor the stress can be
induced by vibrations in the system or thermal transients.
The resulting voltages produced can cause appreciable
amounts of noise, especially when a ceramic capacitor is
used for noise bypassing. A ceramic capacitor produced
Figure 5’s trace in response to light tapping from a pencil.
Similar vibration induced behavior can masquerade as
The LT3023 regulator has internal thermal limiting de-
signed to protect the device during overload conditions.
For continuous normal conditions, the maximum junction
temperature rating of 125°C must not be exceeded. It is
important to give careful consideration to all sources of
thermal resistance from junction to ambient. Additional
heat sources mounted nearby must also be considered.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes can also be used to spread the heat gener-
ated by power devices.
C
C
LOAD
= 10μF
= 0.01μF
= 100mA
OUT
BYP
I
The following tables list thermal resistance for several
different board sizes and copper areas. All measurements
were taken in still air on 3/32" FR-4 board with one ounce
copper.
V
OUT
500μV/DIV
Table 1. MSE Package, 10-Lead MSOP
COPPER AREA
THERMAL RESISTANCE
3023 F05
TOPSIDE*
BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
100ms/DIV
2
2
2
2
2
2
2
2
2
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
40°C/W
45°C/W
50°C/W
62°C/W
Figure 5. Noise Resulting from Tapping on a Ceramic Capacitor
2
1000mm
2
increased output voltage noise.
225mm
2
100mm
Thermal Considerations
*Device is mounted on topside.
The power handling capability of the device will be limited
by the maximum rated junction temperature (125°C). The
power dissipated by the device will be made up of two
components (for each channel):
Table 2. DD Package, 10-Lead DFN
COPPER AREA
THERMAL RESISTANCE
TOPSIDE*
BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
2
2
2
2
2
2
2
2
2
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
40°C/W
45°C/W
50°C/W
62°C/W
1. Output current multiplied by the input/output voltage
differential: (I )(V – V ), and
2
1000mm
2
OUT
IN
OUT
225mm
100mm
2
2. GND pin current multiplied by the input voltage:
(I )(V ).
*Device is mounted on topside.
GND
IN
The thermal resistance juncton-to-case (θ ), measured
JC
The ground pin current can be found by examining the
GND Pin Current curves in the Typical Performance
at the Exposed Pad on the back of the die is 10°C/W.
3023fa
11
LT3023
APPLICATIONS INFORMATION
Calculating Junction Temperature
limiting and thermal limiting, the devices are protected
against reverse input voltages, reverse output voltages
and reverse voltages from output to input.
Example: Given an output voltage on the first channel of
3.3V, an output voltage of 2.5V on the second channel, an
input voltage range of 4V to 6V, output current ranges of
0mAto100mAforthefirstchanneland0mAto50mAforthe
second channel, with a maximum ambient temperature of
50°C, what will the maximum junction temperature be?
Current limit protection and thermal overload protection
areintendedtoprotectthedeviceagainstcurrentoverload
conditionsattheoutputofthedevice.Fornormaloperation,
the junction temperature should not exceed 125°C.
The power dissipated by each channel of the device will
be equal to:
The input of the device will withstand reverse voltages
of 20V. Current flow into the device will be limited to less
than 1mA (typically less than 100μA) and no negative
voltage will appear at the output. The device will protect
both itself and the load. This provides protection against
batteries which can be plugged in backward.
I
(V
– V ) + I (V
)
OUT(MAX) IN(MAX)
OUT
GND IN(MAX)
where (for the first channel):
I
= 100mA
= 6V
OUT
OUT(MAX)
V
The output of the LT3023 can be pulled below ground
withoutdamagingthedevice.Iftheinputisleftopencircuit
or grounded, the output can be pulled below ground by
20V. The output will act like an open circuit; no current will
flow out of the pin. If the input is powered by a voltage
source, the output will source the short-circuit current of
the device and will protect itself by thermal limiting. In
this case, grounding the SHDN1/SHDN2 pins will turn off
the device and stop the output from sourcing the short-
circuit current.
IN(MAX)
I
at (I
= 100mA, V = 6V) = 2mA
GND
IN
so:
P1 = 100mA(6V – 3.3V) + 2mA(6V) = 0.28W
and (for the second channel):
I
= 50mA
= 6V
OUT IN
OUT(MAX)
V
IN(MAX)
I
at (I
= 50mA, V = 6V) = 1mA
GND
so:
The ADJ1 and ADJ2 pins can be pulled above or below
ground by as much as 7V without damaging the device.
If the input is left open circuit or grounded, the ADJ1 and
ADJ2 pins will act like an open circuit when pulled below
ground and like a large resistor (typically 100k) in series
with a diode when pulled above ground.
P2 = 50mA(6V – 2.5V) + 1mA(6V) = 0.18W
The thermal resistance will be in the range of 40°C/W to
60°C/W depending on the copper area. So the junction
temperature rise above ambient will be approximately
equal to:
InsituationswheretheADJ1andADJ2pinsareconnected
to a resistor divider that would pull the pins above their 7V
clamp voltage if the output is pulled high, the ADJ1/ADJ2
pin input current must be limited to less than 5mA. For
example, a resistor divider is used to provide a regulated
1.5V output from the 1.22V reference when the output
is forced to 20V. The top resistor of the resistor divider
must be chosen to limit the current into the ADJ pin to
less than 5mA when the ADJ1/ADJ2 pin is at 7V. The 13V
difference between output and ADJ1/ADJ2 pin divided by
the 5mA maximum current into the ADJ1/ADJ2 pin yields
a minimum top resistor value of 2.6k.
(0.28W + 018W)(60°C/W) = 27.8°C
The maximum junction temperature will then be equal to
the maximum junction temperature rise above ambient
plus the maximum ambient temperature or:
T
= 50°C + 27.8°C = 77.8°C
JMAX
Protection Features
The LT3023 regulator incorporates several protection
features which makes it ideal for use in battery-powered
circuits. In addition to the normal protection features
associated with monolithic regulators, such as current
3023fa
12
LT3023
APPLICATIONS INFORMATION
100
90
80
760
60
50
40
30
20
10
0
In circuits where a backup battery is required, several
different input/output conditions can occur. The output
voltage may be held up while the input is either pulled
to ground, pulled to some intermediate voltage or is left
open circuit. Current flow back into the output will follow
the curve shown in Figure 6.
T
V
V
= 25°C
= 0V
A
IN
= V
OUT
ADJ
CURRENT FLOWS
INTO OUTPUT PIN
When the IN pin of the LT3023 is forced below the OUT1
or OUT2 pins or the OUT1/OUT2 pins are pulled above the
IN pin, input current will typically drop to less than 2μA.
This can happen if the input of the device is connected
to a discharged (low voltage) battery and the output is
held up by either a backup battery or a second regulator
circuit. The state of the SHDN1/SHDN2 pins will have no
effect on the reverse output current when the output is
pulled above the input.
4
0
1
2
3
5
6
7
8
9
10
OUTPUT VOLTAGE (V)
3023 F06
Figure 6. Reverse Output Current
TYPICAL APPLICATIONS
Noise Bypassing Slows Startup, Allows Outputs to Track
V
SHDN1/SHDN2
1V/DIV
V
OUT1
1V/DIV
V
OUT2
1V/DIV
V
IN
3.7V TO 20V
3.3V
IN
OUT1
AT 100mA
0.01μF
0.01μF
10μF
422k
1μF
3023 TA02b
BYP1
ADJ1
2ms/DIV
249k
LT3023
Startup Time
OFF ON
2.5V
AT 100mA
SHDN1
SHDN2
OUT2
100
10μF
261k
BYP2
ADJ2
GND
10
1
249k
3023 TA02a
0.1
10
100
1000
10000
C
(pF)
BYP
3023 TA02c
3023fa
13
LT3023
PACKAGE DESCRIPTION
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
R = 0.115
TYP
6
0.38 0.10
10
0.675 0.05
3.50 0.05
2.15 0.05 (2 SIDES)
1.65 0.05
3.00 0.10
(4 SIDES)
1.65 0.10
(2 SIDES)
PIN 1
PACKAGE
OUTLINE
TOP MARK
(SEE NOTE 6)
(DD) DFN 1103
5
1
0.25 0.05
0.50 BSC
0.75 0.05
0.200 REF
0.25 0.05
0.50
BSC
2.38 0.10
(2 SIDES)
2.38 0.05
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3023fa
14
LT3023
PACKAGE DESCRIPTION
MSE Package
10-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1664 Rev B)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.06 0.102
2.794 0.102
(.110 .004)
0.889 0.127
(.035 .005)
(.081 .004)
1
1.83 0.102
(.072 .004)
5.23
(.206)
MIN
2.083 0.102 3.20 – 3.45
(.082 .004) (.126 – .136)
10
0.50
(.0197)
BSC
0.305 0.038
(.0120 .0015)
TYP
3.00 0.102
(.118 .004)
(NOTE 3)
0.497 0.076
(.0196 .003)
REF
10 9
8
7 6
RECOMMENDED SOLDER PAD LAYOUT
3.00 0.102
(.118 .004)
(NOTE 4)
4.90 0.152
(.193 .006)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
1
2
3
4 5
GAUGE PLANE
0.53 0.152
(.021 .006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 0.0508
(.004 .002)
0.50
(.0197)
BSC
MSOP (MSE) 0307 REV B
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3023fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LT3023
TYPICAL APPLICATION
Startup Sequencing
Turn-On Waveforms
V
SHDN1
1V/DIV
V
IN
3.7V TO 20V
3.3V
AT
V
IN
OUT1
OUT1
1V/DIV
100mA
0.01μF
0.01μF
10μF
LT3023
V
OUT2
1μF
1V/DIV
BYP1
ADJ1
422k
249k
35.7k
28k
3023 TA03b
2.5V
AT
100mA
2ms/DIV
OFF ON
SHDN1
SHDN2
OUT2
10μF
Turn-Off Waveforms
261k
249k
BYP2
ADJ2
GND
0.47μF
V
SHDN1
1V/DIV
3023 TA03a
V
OUT1
1V/DIV
V
OUT2
1V/DIV
3023 TA03c
2ms/DIV
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1129
700mA, Micropower, LDO
500mA, Micropower Negative LDO
3A, Negative LDO
V : 4.2V to 30V, V
= 3.75V, I = 50μA, I = 16μA, DD, SOT-223, S8,TO220,
IN
OUT(MIN) Q SD
TSSOP20 Packages
LT1175
Guaranteed Voltage Tolerance and Line/Load Regulation, V : –20V to –4.3V,
IN
V
= –3.8V, I = 45μA, I = 10μA, DD,SOT-223, S8 Packages
OUT(MIN)
Q SD
LT1185
Accurate Programmable Current Limit, Remote Sense, V : –35V to –4.2V, V
IN OUT(MIN)
= –2.40V, I = 2.5mA, I <1μA, TO220-5 Package
Q
SD
LT1761
100mA, Low Noise Micropower, LDO
150mA, Low Noise Micropower, LDO
500mA, Low Noise Micropower, LDO
Low Noise < 20μV
OUT(MIN) =
Stable with 1μF Ceramic Capacitors, V : 1.8V to 20V,
RMS, IN
V
1.22V, I = 20μA, I <1μA, ThinSOT Package
Q SD
LT1762
Low Noise < 20μV
MS8 Package
V : 1.8V to 20V, V
= 1.22V, I = 25μA, I <1μA,
Q SD
RMS, IN
OUT(MIN)
LT1763
Low Noise < 20μV
S8 Package
V : 1.8V to 20V, V
= 1.22V, I = 30μA, I <1μA,
Q SD
RMS, IN
OUT(MIN)
LT1764/LT1764A
LTC1844
LT1962
3A, Low Noise, Fast Transient Response, LDO
150mA, Very Low Drop-Out LDO
Low Noise < 40μV
OUT(MIN)
"A" Version Stable with Ceramic Capacitors, V : 2.7V to 20V,
RMS, IN
Q
V
= 1.21V, I = 1mA, I <1μA, DD, TO220 Packages
SD
Low Noise < 30μV
OUT(MIN)
, Stable with 1μF Ceramic Capacitors, V : 1.6V to 6.5V,
IN
RMS
V
= 1.25V, I = 40μA, I <1μA, ThinSOT Package
Q SD
300mA, Low Noise Micropower, LDO
Low Noise < 20μV
MS8 Package
V : 1.8V to 20V, V = 1.22V, I = 30μA, I <1μA,
OUT(MIN) Q SD
RMS, IN
LT1963/LT1963A
LT1964
1.5A, Low Noise, Fast Transient Response, LDO Low Noise < 40μV
"A" Version Stable with Ceramic Capacitors, V : 2.1V to 20V,
RMS, IN
Q
V
= 1.21V, I = 1mA, I <1μA, DD, TO220, SOT-223, S8 Packages
OUT(MIN)
SD
200mA, Low Noise Micropower, Negative LDO
Low Noise < 30μV
OUT(MIN)
Stable with Ceramic Capacitors, V : –0.9V to –20V,
RMS, IN
V
= –1.21V, I = 30μA, I = 3μA, ThinSOT Package
Q
SD
LTC3407
Dual 600mA. 1.5MHz Synchronous Step Down V : 2.5V to 5.5V, V
= 0.6 V, I = 40μA, I <1μA, MSE Package
OUT(MIN) Q SD
IN
DC/DC Converter
3023fa
LT 0208 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
© LINEAR TECHNOLOGY CORPORATION 2003
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号：
LT3023IDD#PBF
LT3023 - Dual 100mA, Low Dropout, Low Noise, Micropower Regulator; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
Linear
LT3023IMSE
LT3023 - Dual 100mA, Low Dropout, Low Noise, Micropower Regulator; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C
Linear
LT3024EDE#PBF
LT3024 - Dual 100mA/500mA Low Dropout, Low Noise, Micropower Regulator; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C
Linear
LT3024EDE#TR
LT3024 - Dual 100mA/500mA Low Dropout, Low Noise, Micropower Regulator; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C
Linear
LT3024EDE#TRPBF
LT3024 - Dual 100mA/500mA Low Dropout, Low Noise, Micropower Regulator; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C
Linear
©2020 ICPDF网 联系我们和版权申明