LT3024EFE#PBF [Linear]
暂无描述;
| 型号： | LT3024EFE#PBF |
| 厂家： | 
Linear |
| 描述： | 暂无描述 稳压器 |
| 文件： | 总16页 (文件大小：486K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3024
Dual 100mA/500mA
Low Dropout, Low Noise,
Micropower Regulator
U
FEATURES
DESCRIPTIO
The LT®3024 is a dual, micropower, low noise, low drop-
out regulator. With an external 0.01µF bypass capacitor,
output noise drops to 20µVRMS over a 10Hz to 100kHz
bandwidth. Designedforuseinbattery-poweredsystems,
the low 30µA quiescent current per output makes it an
ideal choice. In shutdown, quiescent current drops to less
than 0.1µA. Shutdown control is independent for each
output, allowing for flexibility in power management. The
device is capable of operating over an input voltage range
of 1.8V to 20V. The device can supply 100mA of output
current from Output 2 with a dropout voltage of 300mV.
Output 1 can supply 500mA of output current with a
dropout voltage of 300mV. Quiescent current is well
controlled in dropout.
■
Low Noise: 20µVRMS (10Hz to 100kHz)
■
Low Quiescent Current: 30µA/Output
■
Wide Input Voltage Range: 1.8V to 20V
■
Output Current: 100mA/500mA
■
Very Low Shutdown Current: <0.1µA
■
■
■
■
Low Dropout Voltage: 300mV at 100mA/500mA
Adjustable Outputs from 1.22V to 20V
Stable with 1µF/3.3µF Output Capacitor
Stable with Aluminum, Tantalum or
Ceramic Capacitors
■
■
■
■
■
Reverse-Battery Protected
No Reverse Current
No Protection Diodes Needed
Overcurrent and Overtemperature Protected
Thermally Enhanced 16-Lead TSSOP and 12-Lead
(4mm × 3mm) DFN Packages
The LT3024 regulator is stable with output capacitors as
low as 1µF for the 100mA output and 3.3µF for the 500mA
output. Small ceramic capacitors can be used without the
series resistance required by other regulators.
U
APPLICATIO S
Internal protection circuitry includes reverse-battery pro-
tection, current limiting, thermal limiting and reverse
current protection. The device is available as an adjustable
device with a 1.22V reference voltage. The LT3024 regu-
latorisavailableinthethermallyenhanced16-leadTSSOP
and 12-lead, low profile (4mm × 3mm × 0.75mm) DFN
packages.
■
Cellular Phones
■
Pagers
■
Battery-Powered Systems
■
Frequency Synthesizers
■
Wireless Modems
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
TYPICAL APPLICATIO
3.3V/2.5V Low Noise Regulators
10Hz to 100kHz Output Noise
3.3V AT 500mA
20µV NOISE
IN
OUT1
RMS
V
IN
SHDN1
SHDN2
0.01µF
10µF
10µF
422k
249k
3.7V TO
20V
1µF
BYP1
ADJ1
V
OUT
100µV/DIV
20µV
RMS
LT3024
2.5V AT 100mA
20µV NOISE
OUT2
RMS
0.01µF
261k
BYP2
ADJ2
3024 TA01b
GND
249k
3024 TA01a
3024f
1
LT3024
ABSOLUTE AXI U RATI GS
W W
U W
(Note 1)
IN Pin Voltage........................................................ ±20V
OUT1, OUT2 Pin Voltage ....................................... ±20V
Input-to-Output Differential Voltage....................... ±20V
ADJ1, ADJ2 Pin Voltage ......................................... ±7V
BYP1, BYP2 Pin Voltage ....................................... ±0.6V
SHDN1, SHDN2 Pin Voltage ................................. ±20V
Output Short-Circut Duration.......................... Indefinite
Operating Junction Temperature Range
(Note 2) ............................................ –40°C to 125°C
Storage Temperature Range
FE Package ....................................... –65°C to 150°C
DE Package ...................................... –65°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
U W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART
NUMBER
ORDER PART
TOP VIEW
NUMBER
GND
BYP1
OUT1
OUT1
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
ADJ1
SHDN1
IN
BYP1
OUT1
OUT1
GND
1
2
3
4
5
6
12 ADJ1
11 SHDN1
10 IN
LT3024EFE
LT3024EDE
17
13
IN
9
8
7
IN
OUT2
BYP2
GND
SHDN2
ADJ2
GND
OUT2
BYP2
SHDN2
ADJ2
FE PART
MARKING
DE PART
MARKING
DE12 PACKAGE
12-LEAD (4mm × 3mm) PLASTIC DFN
FE PACKAGE
16-LEAD PLASTIC TSSOP
3024EFE
3024
TJMAX = 150°C, θJA = 40°C/ W, θJC = 10°C/ W
TJMAX = 150°C, θJA = 38°C/ W, θJC = 8°C/ W
EXPOSED PAD (PIN 13) IS GND
MUST BE SOLDERED TO PCB
EXPOSED PAD (PIN 17) IS GND
MUST BE SOLDERED TO PCB
Consult factory for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Minimum Input Voltage
(Notes 3, 11)
Output 2, I
Output 1, I
= 100mA
= 500mA
●
●
1.8
1.8
2.3
2.3
V
V
LOAD
LOAD
ADJ1, ADJ2 Pin Voltage
(Notes 3, 4)
V
= 2V, I
= 1mA
IN
1.205
1.190
1.190
1.220
1.220
1.220
1.235
1.250
1.250
V
V
V
IN
LOAD
Output 2, 2.3V < V < 20V, 1mA < I
Output 1, 2.3V < V < 20V, 1mA < I
< 100mA
< 500mA
●
●
LOAD
LOAD
IN
Line Regulation (Note 3)
Load Regulation (Note 3)
∆V = 2V to 20V, I
= 1mA
●
●
●
1
1
10
mV
IN
LOAD
Output 2, V = 2.3V, ∆I
= 1mA to 100mA
= 1mA to 100mA
12
25
mV
mV
IN
LOAD
LOAD
V
= 2.3V, ∆I
IN
Output 1, V = 2.3V, ∆I
= 1mA to 500mA
= 1mA to 500mA
1
12
25
mV
mV
IN
LOAD
LOAD
V
= 2.3V, ∆I
IN
3024f
2
LT3024
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Dropout Voltage
(Output 2)
I
I
= 1mA
= 1mA
0.10
0.15
0.19
V
V
LOAD
LOAD
●
●
●
●
●
●
●
●
V
= V
IN
OUT(NOMINAL)
I
I
= 10mA
= 10mA
0.17
0.24
0.30
0.13
0.17
0.20
0.30
0.22
0.29
V
V
LOAD
LOAD
(Notes 5, 6, 11)
I
I
= 50mA
= 50mA
0.31
0.40
V
V
LOAD
LOAD
I
I
= 100mA
= 100mA
0.35
0.45
V
V
LOAD
LOAD
Dropout Voltage
(Output 1)
I
I
= 10mA
= 10mA
0.19
0.25
V
V
LOAD
LOAD
V
= V
IN
OUT(NOMINAL)
I
I
= 50mA
= 50mA
0.22
0.32
V
V
LOAD
LOAD
(Notes 5, 6, 11)
I
I
= 100mA
= 100mA
0.34
0.44
V
V
LOAD
LOAD
I
I
= 500mA
= 500mA
0.35
0.45
V
V
LOAD
LOAD
GND Pin Current
(Output 2)
I
I
I
I
I
= 0mA
●
●
●
●
●
20
55
230
1
2.2
45
90
400
2
µA
µA
LOAD
LOAD
LOAD
LOAD
LOAD
= 1mA
V
= V
= 10mA
= 50mA
= 100mA
µA
IN
OUT(NOMINAL)
(Notes 5, 7)
mA
mA
4
GND Pin Current
(Output 1)
I
I
I
I
I
I
= 0mA
●
●
●
●
●
●
30
65
1.1
2
75
120
1.6
3
µA
µA
mA
mA
mA
mA
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
= 1mA
V
= V
= 50mA
= 100mA
= 250mA
= 500mA
IN
OUT(NOMINAL)
(Notes 5, 7)
5
8
11
16
Output Voltage Noise
C
= 10µF, C
= 0.01µF, I
= Full Current,
20
µV
RMS
OUT
BYP
LOAD
BW = 10Hz to 100kHz
ADJ Pin Bias Current
Shutdown Threshold
ADJ1, ADJ2 (Notes 3, 8)
30
100
1.4
nA
V
V
= Off to On
= On to Off
●
●
0.80
0.65
V
V
OUT
OUT
0.25
55
SHDN1/SHDN2 Pin Current
(Note 9)
V
V
, V
= 0V
= 20V
●
●
0
1
0.5
3.0
µA
µA
SHDN1 SHDN2
, V
SHDN1 SHDN2
Quiescent Current in Shutdown
Ripple Rejection
V
V
= 6V, V
= 0V, V = 0V
SHDN2
0.01
65
0.1
µA
IN
SHDN1
= 2.72V (Avg), V
= Full Current
= 0.5V , f = 120Hz,
P-P RIPPLE
dB
IN
RIPPLE
I
LOAD
Current Limit
Output 2, V = 7V, V
= 0V
OUT
200
700
mA
mA
IN
OUT
= 2.3V, ∆V
V
= –0.1V
●
110
520
IN
Output 1, V = 7V, V
= 0V
mA
mA
IN
OUT
= 2.3V, ∆V
V
= –0.1V
●
●
IN
OUT
Input Reverse Leakage Current
V
V
= –20V, V
= 0V
1
mA
IN
OUT
Reverse Output Current
(Notes 3,10)
= 1.22V, V < 1.22V
5
10
µA
OUT
IN
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
T = 25°C. Performance at –40°C and 125°C is assured by design,
characterization and correlation with statistical process controls.
A
Note 2: The LT3024 regulator is tested and specified under pulse load
Note 3: The LT3024 is tested and specified for these conditions with the
ADJ1/ADJ2 pin connected to the corresponding OUT1/OUT2 pin.
conditions such that T ≈ T . The LT3024 is 100% production tested at
J
A
3024f
3
LT3024
ELECTRICAL CHARACTERISTICS
Note 4: Operating conditions are limited by maximum junction
temperature. The regulated output voltage specification will not apply for
all possible combinations of input voltage and output current. When
operating at maximum input voltage, the output current range must be
limited. When operating at maximum output current, the input voltage
range must be limited.
or at the minimum input voltage specification. This is the worst-case GND
pin current. The GND pin current will decrease slightly at higher input
voltages. Total GND pin current is equal to the sum of GND pin currents
from Output 1 and Output 2.
Note 8: ADJ1 and ADJ2 pin bias current flows into the pin.
Note 9: SHDN1 and SHDN2 pin current flows into the pin.
Note 5: To satisfy requirements for minimum input voltage, the LT3024 is
tested and specified for these conditions with an external resistor divider
(two 250k resistors) for an output voltage of 2.44V. The external resistor
divider will add a 5µA DC load on the output.
Note 6: Dropout voltage is the minimum input to output voltage differential
needed to maintain regulation at a specified output current. In dropout, the
Note 10: Reverse output current is tested with the IN pin grounded and the
OUT pin forced to the rated output voltage. This current flows into the OUT
pin and out the GND pin.
Note 11: For the LT3024 dropout voltage will be limited by the minimum
input voltage specification under some output voltage/load conditions. See
the curve of Minimum Input Voltage in the Typical Performance
Characteristics.
output voltage will be equal to: V – V
.
IN
DROPOUT
Note 7: GND pin current is tested with V = 2.44V and a current source
IN
load. This means the device is tested while operating in its dropout region
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Output 2
Typical Dropout Voltage
Output 2
Guaranteed Dropout Voltage
Output 2 Dropout Voltage
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
= TEST POINTS
T
≤ 125°C
≤ 25°C
J
T = 125°C
J
I
= 100mA
L
T
J
I
= 50mA
= 10mA
L
T = 25°C
J
I
L
I
= 1mA
L
0
–50
0
0
0
25
50
75 100 125
–25
40
40
50 60 70 80 90 100
0
10 20 30
50 60 70 80 90 100
0
10 20 30
TEMPERATURE (°C)
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
3024 G03
3024 G01
3024 G02
Output 1
Typical Dropout Voltage
Output 1
Guaranteed Dropout Voltage
Output 1 Dropout Voltage
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
= TEST POINTS
I
= 500mA
L
I
= 250mA
T = 125°C
L
J
T
≤ 125°C
≤ 25°C
J
I
= 100mA
L
I
= 50mA
L
T
J
T = 25°C
J
I
= 1mA
L
I
L
= 10mA
0
–50
0
0
0
25
50
75 100 125
–25
200
200
250 300 350 400 450 500
0
50 100 150
250 300 350 400 450 500
0
50 100 150
TEMPERATURE (°C)
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
3024 G06
3024 G04
3024 G05
3024f
4
LT3024
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Quiescent Current (Per Output)
ADJ1 or ADJ2 Pin Voltage
Quiescent Current (Per Output)
40
35
30
25
20
15
10
5
1.240
1.235
1.230
1.225
1.220
1.215
1.210
1.205
1.200
50
45
40
35
30
25
20
15
10
5
T = 25°C
L
I = 1mA
L
J
R
= 250k
V
= V
IN
SHDN
V
= V
IN
SHDN
V
= 6V
= 250k, I = 5µA
L
IN
L
R
V
SHDN
= 0V
0
0
–25
0
25
50
75
125
–25
0
25
50
75
125
2
4
6
10 12 14
18
20
–50
100
–50
100
0
8
16
TEMPERATURE (°C)
TEMPERATURE (°C)
INPUT VOLTAGE (V)
3024 G07
3024 G08
3024 G09
Output 2
GND Pin Current vs ILOAD
Output 1 GND Pin Current
Output 2 GND Pin Current
1200
1000
800
600
400
200
0
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
V
IN
= V
+ 1V
OUT(NOMINAL)
T = 25°C
J
*FOR V
= 1.22V
OUT
R
L
= 24.4Ω
L
R
L
= 12.2Ω
L
I
= 50mA*
I
= 100mA*
T = 25°C
J
V
= V
IN
SHDN
OUT
*FOR V
= 1.22V
R
L
= 24.4Ω
L
I
= 50mA*
R
L
= 122Ω
L
I
= 10mA*
= 1.22k
L
R
L
= 1.22k
L
R
L
= 122Ω
L
R
I
I
= 1mA*
I
= 10mA*
= 1mA*
L
4
40
4
0
1
2
3
5
6
7
8
9
10
0
10 20 30
50 60 70 80 90 100
0
1
2
3
5
6
7
8
9
10
INPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
INPUT VOLTAGE (V)
3024 G10
3024 G11
3024 G12
Output 1
GND Pin Current vs ILOAD
SHDN1 or SHDN2 Pin Threshold
(On-to-Off)
Output 1 GND Pin Current
12
10
8
12
10
8
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
IN
= V
+ 1V
I
= 1mA
T = 25°C
OUT(NOMINAL)
L
J
V
= V
IN
SHDN
OUT
*FOR V
= 1.22V
R
L
= 2.44Ω
L
I
= 500mA*
R
L
= 4.07Ω
L
6
6
I
= 300mA*
4
4
R
L
= 12.2Ω
L
I
= 100mA*
2
2
0
0
4
0
50 100 150 200
300 350 400 450 500
0
1
2
3
5
6
7
8
9
10
250
–50
0
25
50
75
125
–25
100
TEMPERATURE (°C)
INPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
3024 G13
3024 G14
3024 G15
3024f
5
LT3024
TYPICAL PERFOR A CE CHARACTERISTICS
U W
SHDN1 or SHDN2 Pin Threshold
(Off-to-On)
SHDN1 or SHDN2 Pin Input
Current
SHDN1 or SHDN2 Pin Input
Current
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
SHDN
= 20V
I
L
= FULL
I
L
= 1mA
–50
0
25
50
75 100 125
0
1
2
3
4
6
7
8
9
10
–50
–25
0
25
50
75 100 125
–25
5
TEMPERATURE (°C)
TEMPERATURE (°C)
SHDN PIN VOLTAGE (V)
3024 G16
3024 G17
3024 G18
ADJ1 or ADJ2 Pin Bias Current
Output 2 Current Limit
Output 2 Current Limit
100
90
80
70
60
50
40
30
20
10
0
350
300
250
200
150
100
50
350
300
250
200
150
100
50
V
V
= 7V
OUT
V
= 0V
IN
OUT
J
= 0V
T = 25°C
0
0
–50
0
25
50
75 100 125
0
2
3
4
5
6
7
–50
–25
0
25
50
75 100 125
–25
1
TEMPERATURE (°C)
INPUT VOLTAGE (V)
TEMPERATURE (°C)
3024 G19
3024 G20
3024 G21
Reverse Output Current
Output 1 Current Limit
Output 1 Current Limit
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.2
1.0
0.8
0.6
0.4
0.2
0
100
90
80
70
60
50
40
30
20
10
0
V
= 0V
V = 7
IN
OUT
T
V
V
= 25°C
OUT
A
V
= 0V
= 0V
IN
OUT
= V
ADJ
CURRENT FLOWS
INTO OUTPUT PIN
0
2
3
4
5
6
7
1
4
0
1
2
3
5
6
7
8
9
10
–50
0
25
50
75 100 125
–25
INPUT VOLTAGE (V)
TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
3024 G22
3024 G24
3024 G23
3024f
6
LT3024
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Output 2
Input Ripple Rejection
Output 2
Input Ripple Rejection
Reverse Output Current
80
70
60
50
40
30
20
10
0
18
15
12
9
80
70
60
50
40
30
20
10
0
V
V
= 0V
OUT
IN
= V
= 1.22V
ADJ
C
= 0.01µF
BYP
C
= 1000pF
BYP
C
= 100pF
BYP
C
= 10µF
OUT
6
C
= 1µF
OUT
I
V
C
= 100mA
I
V
C
= 100mA
3
L
L
IN
OUT
= 2.3V + 50mV
RIPPLE
10
= 2.3V + 50mV
RIPPLE
RMS
IN
BYP
RMS
= 0
= 10µF
0
50
TEMPERATURE (°C)
100 125
0.01
0.1
1
100
1000
–50 –25
0
25
75
0.01
0.1
1
10
100
1000
FREQUENCY (kHz)
FREQUENCY (kHz)
3024 G26
3024 G27
3024 G25
Output 2
Input Ripple Rejection
Output 1
Input Ripple Rejection
Output 1
Input Ripple Rejection
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
C
= 0.01µF
BYP
C
= 10µF
OUT
C
= 1000pF
BYP
C
= 100pF
BYP
I
= 500mA
V
= V
+
I
L
IN
= 500mA
= V
L
V
IN
OUT (NOMINAL)
C
= 4.7µF
= V +
OUT
1V + 0.5V RIPPLE
P-P
V
+
IN
OUT(NOMINAL)
OUT(NOMINAL)
1V + 50mV
C
RIPPLE
1k
AT f = 120Hz
1V + 50mV
RMS
RIPPLE
RMS
= 10µF
I
= 50mA
C
BYP
= 0
OUT
L
10
100
10k
100k
1M
10
100
1k
10k
100k
1M
–25
0
25
50
75
125
–50
100
FREQUENCY (Hz)
FREQUENCY (Hz)
TEMPERATURE (°C)
3024 G30
3024 G29
3024 G28
Output 1 Ripple Rejection
Output 2 Minimum Input Voltage
Output 1 Minimum Input Voltage
2.5
2.0
1.5
1.0
0.5
0
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
68
66
64
62
60
58
56
54
52
V
OUT
= 1.22V
V
OUT
= 1.22V
I
L
= 500mA
I
L
= 100mA
I
= 1mA
L
I
L
= 50mA
V
= V
+
IN
OUT (NOMINAL)
1V + 0.5V RIPPLE
P-P
AT f = 120Hz
I
= 500mA
L
–50
0
25
50
75 100 125
–25
–25
0
25
50
75
125
–50
0
25
50
75
125
–50
100
100
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3024 G33
3024 G31
3024 G32
3024f
7
LT3024
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Channel-to-Channel Isolation
Channel-to-Channel Isolation
Output 2 Load Regulation
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
100
90
CHANNEL 2
80
V
OUT1
20mV/DIV
70
CHANNEL 1
60
50
V
OUT2
20mV/DIV
40
30
20
10
0
GIVEN CHANNEL IS TESTED
WITH 50mVRMS SIGNAL ON
OPPOSING CHANNEL, BOTH
CHANNELS DELIVERING FULL
CURRENT
C
OUT1 = 22µF
COUT2 = 10µF
BYP1 = CBYP2 = 0.01µF
50µs/DIV
3024 G50
∆
= 1mA TO 100mA
IL
C
∆IL1 = 50mA TO 500mA
∆IL2 = 10mA TO 100mA
–50 –25
0
25
50
75 100 125
10
100
1k
10k
100k
1M
TEMPERATURE (°C)
FREQUENCY (Hz)
V
IN = 6V, VOUT1 = VOUT2 = 5V
3024 G34
3024 G35
Output 1 Load Regulation
Output Noise Spectral Density
Output Noise Spectral Density
10
1
10
1
5
0
C
L
= 10µF
OUT
C
C
L
= 10µF
∆I = 1mA TO 500mA
L
OUT
BYP
I
= FULL LOAD
= 0
I
= FULL LOAD
V
OUT
SET FOR 5V
C
BYP
= 1000pF
V
OUT
SET FOR 5V
C
BYP
= 100pF
V
OUT
=V
ADJ
V
OUT
=V
ADJ
0.1
0.01
0.1
0.01
–5
C
BYP
= 0.01pF
–10
–50
–25
0
25
50
75
125
0.01
0.1
1
10
100
100
0.01
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
TEMPERATURE (°C)
3023 G38
3024 G37
3024 G36
Output 2
RMS Output Noise vs Load
Current (10Hz to 100kHz)
Output 1
RMS Output Noise vs Load
Current (10Hz to 100kHz)
RMS Output Noise
vs Bypass Capacitor
160
140
120
100
80
140
120
100
80
160
140
120
100
80
C = 10µF
OUT
C
I
BW
= 10µF
V
= 5V
OUT
L
C
= 10µF
OUT
OUT
C
= 0µF
= FULL LOAD
BYP
BYP
C
= 0
BYP
BYP
C
= 0.01µF
f
= 10Hz TO 100kHz
C
= 0.01µF
CHANNEL 2
V
SET FOR 5V
OUT
V
OUT
SET FOR 5V
CHANNEL 1
= 1.22V
V
OUT
60
V
=V
ADJ
OUT
60
60
CHANNEL 2
V
OUT
= V
ADJ
40
40
40
CHANNEL 1
V
SET FOR 5V
V
SET FOR 5V
= V
OUT
OUT
V
20
20
20
V
=V
ADJ
OUT
10
OUT
ADJ
0
0.01
0
0
0.01
0.1
1
100
10
100
1000
10000
0.1
1
10
100
1000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
C
(pF)
BYP
3024 G40
3024 G39
3024 G41
3024f
8
LT3024
U W
TYPICAL PERFOR A CE CHARACTERISTICS
10Hz to 100kHz Output Noise
CBYP = 0pF
10Hz to 100kHz Output Noise
CBYP = 100pF
10Hz to 100kHz Output Noise
CBYP = 1000pF
VOUT
100µV/DIV
VOUT
100µV/DIV
VOUT
100µV/DIV
COUT = 10µF
1ms/DIV
3024 G42
COUT = 10µF
1ms/DIV
3024 G43
COUT = 10µF
1ms/DIV
3024 G44
IL = 100mA
IL = 100mA
IL = 100mA
VOUT SET FOR 5V
VOUT SET FOR 5V
VOUT SET FOR 5V
10Hz to 100kHz Output Noise
CBYP = 0.01µF
Output 2 Transient Response
CBYP = 0.01µF
Output 2 Transient Response
CBYP = 0pF
V
C
C
= 6V, V
SET FOR 5V
OUT
V
C
C
= 6V, V
SET FOR 5V
OUT
IN
IN
IN
IN
0.2
0.1
0.04
0.02
0
= 10µF
= 10µF
= 10µF
= 10µF
OUT
OUT
0
VOUT
100µV/DIV
–0.1
–0.2
–0.02
–0.04
100
50
0
100
50
0
C
OUT = 10µF
1ms/DIV
3024 G45
IL = 100mA
VOUT SET FOR 5V
800
TIME (µs)
80
100 120 140 160 180 200
TIME (µs)
0
400
1200
1600
2000
0
20 40 60
3024 G46
3024 G47
Output 1 Transient Response
CBYP = 0pF
Output 1 Transient Response
CBYP = 0.01µF
V
C
C
= 6V, V
SET FOR 5V
OUT
V
C
C
= 6V, V
SET FOR 5V
OUT
IN
IN
IN
IN
0.4
0.2
0
0.10
0.05
0
= 10µF
= 10µF
= 10µF
= 10µF
OUT
OUT
–0.2
–0.4
–0.05
–0.10
600
400
200
0
600
400
200
0
400
TIME (µs)
40
0
200
600
800
1000
0
10 20 30
50 60 70 80 90 100
TIME (µs)
3024 G48
3024 G49
3024f
9
LT3024
U
U
U
(DFN Package)/(TSSOP Package)
PI FU CTIO S
GND (Pins 4, 13)/(Pins 1, 5, 8, 9, 16, 17): Ground. The
Exposed Pad must be soldered to PCB ground for opti-
mum thermal performance.
SHDN1/SHDN2 (Pins 11/8)/(Pins 14/11): Shutdown. The
SHDN1/SHDN2 pins are used to put the corresponding
outputoftheLT3024regulatorintoalowpowershutdown
state. The output will be off when the pin is pulled low. The
SHDN1/SHDN2 pins can be driven either by 5V logic or
open-collector logic with pull-up resistors. The pull-up
resistors are required to supply the pull-up current of the
open-collector gates, normally several microamperes,
and the SHDN1/SHDN2 pin current, typically 1µA. If
unused, the pin must be connected to VIN. The device will
not function if the SHDN1/SHDN2 pins are not connected.
ADJ1/ADJ2 (Pins 12/7)/(Pins 15/10): Adjust Pin. These
are the input to the error amplifiers. These pins are
internally clamped to ±7V. They have a bias current of
30nAwhichflowsintothepin(seecurveofADJ1/ADJ2Pin
Bias Current vs Temperature in the Typical Performance
Characteristics section). The ADJ1 and ADJ2 pin voltage
is 1.22V referenced to ground and the output voltage
range is 1.22V to 20V.
IN (Pins 9, 10)/(Pins 12, 13): Input. Power is supplied to
the device through the IN pin. A bypass capacitor is
required on this pin if the device is more than six inches
away from the main input filter capacitor. In general, the
output impedance of a battery rises with frequency, so it
is advisable to include a bypass capacitor in battery-
poweredcircuits. Abypasscapacitorintherangeof1µFto
10µF is sufficient. The LT3024 regulator is designed to
withstand reverse voltages on the IN pin with respect to
ground and the OUT pin. In the case of a reverse input,
which can happen if a battery is plugged in backwards, the
device will act as if there is a diode in series with its input.
There will be no reverse current flow into the regulator and
no reverse voltage will appear at the load. The device will
protect both itself and the load.
BYP1/BYP2(Pins1/6)/(Pins2/7):Bypass.TheBYP1/BYP2
pins are used to bypass the reference of the LT3024
regulator to achieve low noise performance from the
regulator. The BYP1/BYP2 pins are clamped internally to
±0.6V (one VBE) from ground. A small capacitor from the
corresponding output to this pin will bypass the reference
to lower the output voltage noise. A maximum value of
0.01µF can be used for reducing output voltage noise to a
typical 20µVRMS over a 10Hz to 100kHz bandwidth. If not
used, this pin must be left unconnected.
OUT1/OUT2 (Pins 2, 3/5)/(Pins 3, 4/6): Output. The
outputs supply power to the loads. A minimum output
capacitor of 1µF is required to prevent oscillations on
Output 2; Output 1 requires a minimum of 3.3µF. Larger
output capacitors will be required for applications with
large transient loads to limit peak voltage transients. See
theApplicationsInformationsectionformoreinformation
on output capacitance and reverse output characteristics.
W U U
U
APPLICATIO S I FOR ATIO
The LT3024 is a dual 100mA/500mA low dropout regula-
torwithmicropowerquiescentcurrentandshutdown. The
device is capable of supplying 100mA from Output 2 at a
dropout voltage of 300mV. Output 1 delivers 500mA at a
dropout voltage of 300mV. The two regulators have com-
mon VIN and GND pins and are thermally coupled, how-
ever, the two outputs of the LT3024 operate indepen-
dently. They can be shut down independently and a fault
condition on one output will not affect the other output
electrically.Outputvoltagenoisecanbeloweredto20µVRMS
over a 10Hz to 100kHz bandwidth with the addition of a
0.01µFreferencebypasscapacitor. Additionally, therefer-
ence bypass capacitor will improve transient response of
the regulator, lowering the settling time for transient load
conditions.Thelowoperatingquiescentcurrent(30µAper
output) drops to less than 1µA in shutdown. In addition to
3024f
10
LT3024
W U U
APPLICATIO S I FOR ATIO
U
the low quiescent current, the LT3024 regulator incorpo-
rates several protection features which make it ideal for
use in battery-powered systems. The device is protected
against both reverse input and reverse output voltages. In
battery backup applications where the output can be held
up by a backup battery when the input is pulled to ground,
the LT3024 acts like it has a diode in series with its output
and prevents reverse current flow. Additionally, in dual
supplyapplicationswheretheregulatorloadisreturnedto
a negative supply, the output can be pulled below ground
by as much as 20V and still allow the device to start and
operate.
to 1.22V: VOUT/1.22V. For example, load regulation on
Output 2 for an output current change of 1mA to 100mA
is –1mV typical at VOUT = 1.22V. At VOUT = 12V, load
regulation is:
(12V/1.22V)(–1mV) = –9.8mV
Bypass Capacitance and Low Noise Performance
The LT3024 regulator may be used with the addition of a
bypass capacitor from VOUT to the corresponding BYP pin
to lower output voltage noise. A good quality low leakage
capacitor is recommended. This capacitor will bypass the
referenceoftheregulator,providingalowfrequencynoise
pole. The noise pole provided by this bypass capacitor will
lower the output voltage noise to as low as 20µVRMS with
the addition of a 0.01µF bypass capacitor. Using a bypass
capacitor has the added benefit of improving transient
response. With no bypass capacitor and a 10µF output
capacitor, a 10mA to 100mA load step on Output 2 will
settletowithin1%ofitsfinalvalueinlessthan100µs.With
the addition of a 0.01µF bypass capacitor, the output will
staywithin1%forthesameloadstep.Bothoutputsexhibit
this improvement in transient response (see Transient
Reponse in Typical Performance Characteristics section).
However, regulator start-up time is inversely proportional
to the size of the bypass capacitor, slowing to 15ms with
a 0.01µF bypass capacitor and 10µF output capacitor.
Adjustable Operation
The LT3024 has an output voltage range of 1.22V to 20V.
The output voltage is set by the ratio of two external resis-
tors as shown in Figure 1. The device servos the output to
maintain the corresponding ADJ pin voltage at 1.22V ref-
erenced to ground. The current in R1 is then equal to
1.22V/R1andthecurrentinR2isthecurrentinR1plusthe
ADJ pin bias current. The ADJ pin bias current, 30nA at
25°C, flows through R2 into the ADJ pin. The output volt-
age can be calculated using the formula in Figure 1. The
value of R1 should be no greater than 250k to minimize
errors in the output voltage caused by the ADJ pin bias
current. Note that in shutdown the output is turned off and
the divider current will be zero. Curves of ADJ Pin Voltage
vs Temperature and ADJ Pin Bias Current vs Temperature
appear in the Typical Performance Characteristics.
Output Capacitance and Transient Response
TheLT3024regulatorisdesignedtobestablewithawide
rangeofoutputcapacitors. TheESRoftheoutputcapaci-
tor affects stability, most notably with small capacitors.
A minimum output capacitor of 1µF with an ESR of 3Ω or
lessisrecommendedforOutput2topreventoscillations.
A minimum output capacitor of 3.3µF with an ESR of 3Ω
or less is recommended for Output 1. The LT3024 is a
micropower device and output transient response will be
a function of output capacitance. Larger values of output
capacitance decrease the peak deviations and provide
improved transient response for larger load current
changes. Bypass capacitors, used to decouple individual
components powered by the LT3024, will increase the
effective output capacitor value. With larger capacitors
The device is tested and specified with the ADJ pin tied to
thecorrespondingOUTpinforanoutputvoltageof1.22V.
Specifications for output voltages greater than 1.22V will
be proportional to the ratio of the desired output voltage
IN OUT1/OUT2
LT3024
V
OUT
R2
R1
V
= 1.22V 1+
= 1.22V
+ I
(
R2
+
)(
)
OUT
ADJ
V
IN
R2
V
ADJ
ADJ1/ADJ2
GND
I
= 30nA AT 25°C
ADJ
R1
OUTPUT RANGE = 1.22V TO 20V
3024 F01
Figure 1. Adjustable Operation
3024f
11
LT3024
W U U
U
APPLICATIO S I FOR ATIO
Extra consideration must be given to the use of ceramic
capacitors. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior across
temperature and applied voltage. The most common
dielectrics used are Z5U, Y5V, X5R and X7R. The Z5U and
Y5V dielectrics are good for providing high capacitances
in a small package, but exhibit strong voltage and tem-
perature coefficients as shown in Figures 4 and 5. When
used with a 5V regulator, a 10µF Y5V capacitor can exhibit
an effective value as low as 1µF to 2µF over the operating
temperature range. The X5R and X7R dielectrics result in
more stable characteristics and are more suitable for use
as the output capacitor. The X7R type has better stability
across temperature, while the X5R is less expensive and
is available in higher values.
used to bypass the reference (for low noise operation),
larger values of output capacitors are needed. For 100pF
of bypass capacitance on Output 2, 2.2µF of output
capacitor is recommended. With a 330pF bypass capaci-
tor or larger on this output, a 3.3µF output capacitor is
recommended. For Output 1, 4.7µF of output capacitor is
recommended for 100pF of bypass capacitance. With
1000pForlargerbypasscapacitoronthisoutput, a6.8µF
output capacitor is recommended. The shaded region of
Figures2and3definetheregionsoverwhichtheLT3024
regulator is stable. The minimum ESR needed is defined
by the amount of bypass capacitance used, while the
maximum ESR is 3Ω.
4.0
3.5
4.0
3.5
3.0
3.0
STABLE REGION
2.5
STABLE REGION
2.5
2.0
2.0
C
BYP
= 0
C
= 0
1.5
1.0
0.5
0
1.5
1.0
0.5
0
BYP
C
= 100pF
C
BYP
= 100pF
BYP
C
BYP
= 330pF
C
= 330pF
BYP
C
BYP
≥ 1000pF
C
> 3300pF
BYP
1
3
6
9 10
1
3
6 9 10
7 8
2
4
5
7 8
2
4
5
OUTPUT CAPACITANCE (µF)
OUTPUT CAPACITANCE (µF)
3024 F02
3024 F03
Figure 2. Output 2 Stability
Figure 3. Output 1 Stability
40
20
20
0
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
X5R
X5R
0
–20
–40
–60
–80
–100
–20
–40
–60
–80
–100
Y5V
Y5V
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
50
TEMPERATURE (°C)
100 125
0
8
12 14
–50 –25
0
25
75
2
4
6
10
16
DC BIAS VOLTAGE (V)
3024 F04
3024 F05
Figure 5. Ceramic Capacitor Temperature Characteristics
Figure 4. Ceramic Capacitor DC Bias Characteristics
3024f
12
LT3024
W U U
APPLICATIO S I FOR ATIO
U
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress,
similar to the way a piezoelectric accelerometer or
microphone works. For a ceramic capacitor the stress
can be induced by vibrations in the system or thermal
transients. The resulting voltages produced can cause
appreciable amounts of noise, especially when a ceramic
capacitor is used for noise bypassing. A ceramic capaci-
tor produced Figure 6’s trace in response to light tapping
from a pencil. Similar vibration induced behavior can
masquerade as increased output voltage noise.
For continuous normal conditions, the maximum junction
temperature rating of 125°C must not be exceeded. It is
important to give careful consideration to all sources of
thermal resistance from junction to ambient. Additional
heat sources mounted nearby must also be considered.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes can also be used to spread the heat gener-
ated by power devices.
The following tables list thermal resistance for several
different board sizes and copper areas. All measurements
were taken in still air on 3/32" FR-4 board with one ounce
copper.
COUT = 10µF
C
BYP = 0.01µF
ILOAD = 100mA
Table 1. FE Package, 16-Lead TSSOP
COPPER AREA
THERMAL RESISTANCE
TOPSIDE*
2500mm2
1000mm2
225mm2
BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
VOUT
500µV/DIV
2500mm2
2500mm2
2500mm2
2500mm2
2500mm2
2500mm2
2500mm2
2500mm2
38°C/W
43°C/W
48°C/W
60°C/W
100mm2
*Device is mounted on topside.
100ms/DIV
3024 F05
Table 2. UE Package, 12-Lead DFN
COPPER AREA
Figure 6. Noise Resulting from Tapping on a Ceramic Capacitor
THERMAL RESISTANCE
TOPSIDE*
2500mm2
1000mm2
225mm2
BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
2500mm2
2500mm2
2500mm2
2500mm2
2500mm2
2500mm2
2500mm2
2500mm2
40°C/W
45°C/W
50°C/W
62°C/W
Thermal Considerations
The power handling capability of the device will be limited
by the maximum rated junction temperature (125°C). The
power dissipated by the device will be made up of two
components for each output:
100mm2
*Device is mounted on topside.
1. Output current multiplied by the input/output voltage
differential: (IOUT)(VIN – VOUT), and
The thermal resistance junction-to-case (θJC), measured
at the Exposed Pad on the back of the die is 10°C/W for the
DFN package and 8°C/W for the TSSOP package.
2. GND pin current multiplied by the input voltage:
(IGND)(VIN).
Calculating Junction Temperature
The ground pin current can be found by examining the
GND Pin Current curves in the Typical Performance Char-
acteristics section. Power dissipation will be equal to the
sum of the two components listed above.
Example: Given Output 1 set for an output voltage of 3.3V,
Output 2 set for an output voltage of 2.5V, an input voltage
range of 3.8V to 5V, an output current range of 0mA to
500mA for Output 1, an output current range of 0mA to
100mA for Output 2 and a maximum ambient temperature
of 50°C, what will the maximum junction temperature be?
The LT3024 regulator has internal thermal limiting de-
signed to protect the device during overload conditions.
3024f
13
LT3024
U
W U U
APPLICATIONS INFORMATION
The power dissipated by each output will be equal to:
Current limit protection and thermal overload protection
areintendedtoprotectthedeviceagainstcurrentoverload
conditions at the output of the device. For normal opera-
tion, the junction temperature should not exceed 125°C.
I
OUT(MAX)(VIN(MAX) – VOUT) + IGND(VIN(MAX))
Where for Output 1:
IOUT(MAX) = 500mA
The input of the device will withstand reverse voltages of
20V.Currentflowintothedevicewillbelimitedtolessthan
1mA (typically less than 100µA) and no negative voltage
will appear at the output. The device will protect both itself
and the load. This provides protection against batteries
which can be plugged in backward.
V
IN(MAX) = 5V
IGND at (IOUT = 500mA, VIN = 5V) = 9mA
For Output 2:
I
OUT(MAX) = 100mA
VIN(MAX) = 5V
The output of the LT3024 can be pulled below ground
withoutdamagingthedevice.Iftheinputisleftopencircuit
or grounded, the output can be pulled below ground by
20V. The output will act like an open circuit; no current will
flow out of the pin. If the input is powered by a voltage
source, the output will source the short-circuit current of
the device and will protect itself by thermal limiting. In this
case, grounding the SHDN1/SHDN2 pins will turn off the
device and stop the output from sourcing the short-circuit
current.
IGND at (IOUT = 100mA, VIN = 5V) = 2mA
So for Output 1:
P = 500mA (5V – 3.3V) + 9mA (5V) = 0.90W
For Output 2:
P = 100mA (5V – 2.5V) + 2mA (5V) = 0.26W
The thermal resistance will be in the range of 35°C/W to
55°C/W depending on the copper area. So the junction
temperature rise above ambient will be approximately
equal to:
The ADJ pins can be pulled above or below ground by as
muchas7Vwithoutdamagingthedevice.Iftheinputisleft
opencircuitorgrounded, theADJpinswillactlikeanopen
circuit when pulled below ground and like a large resistor
(typically 100k) in series with a diode when pulled above
ground.
(0.90W + 0.26W) 50°C/W = 57.8°C
The maximum junction temperature will then be equal to
the maximum junction temperature rise above ambient
plus the maximum ambient temperature or:
TJMAX = 50°C + 57.8°C = 107.8°C
In situations where the ADJ pins are connected to a
resistor divider that would pull the pins above their 7V
clampvoltageiftheoutputispulledhigh, theADJpininput
current must be limited to less than 5mA. For example, a
resistor divider is used to provide a regulated 1.5V output
fromthe1.22Vreferencewhentheoutputisforcedto20V.
The top resistor of the resistor divider must be chosen to
limitthecurrentintotheADJpintolessthan5mAwhenthe
ADJ pin is at 7V. The 13V difference between output and
ADJpindividedbythe5mAmaximumcurrentintotheADJ
pin yields a minimum top resistor value of 2.6k.
Protection Features
The LT3024 regulator incorporates several protection
features which make it ideal for use in battery-powered
circuits. In addition to the normal protection features
associated with monolithic regulators, such as current
limiting and thermal limiting, the device is protected
against reverse input voltages, reverse output voltages
and reverse voltages from output to input. The two regu-
lators have common VIN and GND pins and are thermally
coupled, however, the two outputs of the LT3024 operate
independently. They can be shut down independently and
a fault condition on one output will not affect the other
output electrically.
3024f
14
LT3024
U
W U U
APPLICATIONS INFORMATION
100
90
80
760
60
50
40
30
20
10
0
In circuits where a backup battery is required, several
different input/output conditions can occur. The output
voltage may be held up while the input is either pulled to
ground, pulledtosomeintermediatevoltageorisleftopen
circuit. Current flow back into the output will follow the
curve shown in Figure 7.
T
V
V
= 25°C
A
= 0V
IN
OUT
= V
ADJ
CURRENT FLOWS
INTO OUTPUT PIN
When the IN pin of the LT3024 is forced below either OUT
pinoreitherOUTpinispulledabovetheINpin,inputcurrent
for the corresponding regulator will typically drop to less
than 2µA. This can happen if the input of the device is
connectedtoadischarged(lowvoltage)batteryandtheout-
put is held up by either a backup battery or a second regu-
lator circuit. The state of the SHDN1/SHDN2 pin will have
no effect on the reverse output current when the output is
pulled above the input.
4
0
1
2
3
5
6
7
8
9
10
OUTPUT VOLTAGE (V)
3024 F07
Figure 7. Reverse Output Current
U
PACKAGE DESCRIPTIO
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BB
4.90 – 5.10*
(.193 – .201)
3.58
(.141)
3.58
(.141)
16 1514 13 12 1110
9
6.60 ±0.10
4.50 ±0.10
2.94
(.116)
SEE NOTE 4
2.94
(.116)
6.40
BSC
0.45 ±0.05
1.05 ±0.10
0.65 BSC
5
7
8
1
2
3
4
6
RECOMMENDED SOLDER PAD LAYOUT
1.10
(.0433)
MAX
4.30 – 4.50*
(.169 – .177)
0° – 8°
0.65
(.0256)
BSC
0.45 – 0.75
0.09 – 0.20
0.05 – 0.15
(.018 – .030)
(.0036 – .0079)
(.002 – .006)
0.195 – 0.30
(.0077 – .0118)
FE16 (BB) TSSOP 0203
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
3024f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LT3024
U
PACKAGE DESCRIPTIO
DE/UE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695)
0.38 ± 0.10
4.00 ±0.10
(2 SIDES)
R = 0.115
TYP
7
12
R = 0.20
TYP
0.65 ±0.05
3.50 ±0.05
2.20 ±0.05 (2 SIDES)
1.70 ±0.05
3.00 ±0.10 1.70 ± 0.10
(2 SIDES)
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
PIN 1
NOTCH
PACKAGE
OUTLINE
(UE12/DE12) DFN 0603
6
0.25 ± 0.05
1
0.75 ±0.05
0.200 REF
0.25 ± 0.05
0.50
BSC
0.50
BSC
3.30 ±0.10
(2 SIDES)
3.30 ±0.05
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1129
700mA, Micropower, LDO
V : 4.2V to 30V, V
= 3.75V, I = 50µA, I < 16µA,
IN
OUT(MIN) Q SD
DD, SOT-223, S8,TO220, TSSOP20 Packages
Guaranteed Voltage Tolerance and Line/Load Regulation
V : –20V to –4.3V, V = –3.8V, I = 45µA, I < 10µA,
LT1175
500mA, Micropower Negative LDO
IN
OUT(MIN)
Q
SD
DD,SOT-223, S8 Packages
Accurate Programmable Current Limit, Remote Sense
V : –35V to –4.2V, V = –2.40V, I = 2.5mA, I < 1µA, TO220-5 Package
LT1185
LT1761
LT1762
LT1763
3A, Negative LDO
IN
OUT(MIN)
Q
SD
100mA, Low Noise Micropower, LDO
150mA, Low Noise Micropower, LDO
500mA, Low Noise Micropower, LDO
Low Noise < 20µV
IN
Stable with 1µF Ceramic Capacitors,
OUT(MIN)
RMS,
V : 1.8V to 20V, V
= 1.22V, I = 20µA, I < 1µA, ThinSOT Package
Q SD
Low Noise < 20µV
V : 1.8V to 20V, V
RMS,
OUT(MIN)
RMS,
= 1.22V, I = 25µA, I < 1µA, MS8 Package
IN
Q
SD
Low Noise < 20µV
V : 1.8V to 20V, V
= 1.22V, I = 30µA, I < 1µA, S8 Package
IN
OUT(MIN)
Q
SD
LT1764/LT1764A 3A, Low Noise, Fast Transient Response, LDO
Low Noise < 40µV
IN
"A" Version Stable with Ceramic Capacitors,
OUT(MIN)
RMS,
V : 2.7V to 20V, V
= 1.21V, I = 1mA, I < 1µA, DD, TO220 Packages
Q SD
LTC1844
LT1962
150mA, Very Low Drop-Out LDO
Low Noise < 30µV
IN
, Stable with 1µF Ceramic Capacitors,
RMS
V : 1.6V to 6.5V, V
= 1.25V, I = 40µA, I < 1µA, ThinSOT Package
Q SD
OUT(MIN)
OUT(MIN)
300mA, Low Noise Micropower, LDO
Low Noise < 20µV
IN
RMS,
V : 1.8V to 20V, V
= 1.22V, I = 30µA, I < 1µA, MS8 Package
Q SD
LT1963/LT1963A 1.5A, Low Noise, Fast Transient Response, LDO
Low Noise < 40µV
IN
DD, TO220, SOT-223, S8 Packages
"A" Version Stable with Ceramic Capacitors,
OUT(MIN)
RMS,
V : 2.1V to 20V, V
= 1.21V, I = 1mA, I < 1µA,
Q SD
LT1964
LT3023
LTC3407
200mA, Low Noise Micropower, Negative LDO
Dual 100mA, Low Noise, Micropower LDO
Low Noise < 30µV Stable with Ceramic Capacitors,
RMS,
V : –0.9V to –20V, V
= –1.21V, I = 30µA, I < 3µA, ThinSOT Package
Q SD
IN
OUT(MIN)
Low Noise < 20µV
IN
Stable with 1µF Ceramic Capacitors,
OUT(MIN)
RMS,
V : 1.8V to 20V, V
= 1.22V, I = 40µA, I < 1µA, MS10E, DFN Packages
Q SD
Dual 600mA. 1.5MHz Synchronous Step Down
DC/DC Converter
V : 2.5V to 5.5V, V
IN
= 0.6 V, I = 40µA, I < 1µA, MS10E Package
OUT(MIN) Q SD
3024f
LT/TP 0104 1K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2004
相关型号：
LT3024EFE#TRPBF
LT3024 - Dual 100mA/500mA Low Dropout, Low Noise, Micropower Regulator; Package: TSSOP; Pins: 16; Temperature Range: -40°C to 85°C
Linear
LT3024IDE#PBF
LT3024 - Dual 100mA/500mA Low Dropout, Low Noise, Micropower Regulator; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C
Linear
LT3024IDE#TR
LT3024 - Dual 100mA/500mA Low Dropout, Low Noise, Micropower Regulator; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C
Linear
LT3024IDE#TRPBF
LT3024 - Dual 100mA/500mA Low Dropout, Low Noise, Micropower Regulator; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C
Linear
©2020 ICPDF网 联系我们和版权申明