LT3029EDETR_技术文档

LT3029

Dual 500mA/500mA

Low Dropout, Low Noise,

Micropower Linear Regulator

DESCRIPTION

FEATURES

The LT^®3029 is a dual, micropower, low noise, low drop-

out linear regulator. The device operates either with a

common input supply or independent input supplies for

each channel, over an input voltage range of 1.8V to 20V.

Each output supplies up to 500mA of output current with

a typical dropout voltage of 300mV. Quiescent current is

well controlled in dropout. With an external 10nF bypass

n

Output Current: 500mA per Channel

n

Low Dropout Voltage: 300mV

n

Low Noise: 20μV

(10Hz to 100kHz)

RMS

n

Low Quiescent Current: 55μA per Channel

Wide Input Voltage Range: 1.8V to 20V (Common or

Independent Input Supply)

n

Adjustable Output: 1.215V Reference Voltage

Very Low Quiescent Current in Shutdown: <1μA per

Channel

Stable with 3.3μF Minimum Output Capacitor

Stable with Ceramic, Tantalum or Aluminum

Electrolytic Capacitors

Reverse-Battery and Reverse Output-to-Input

Protection

Current Limit with Foldback and Thermal Shutdown

Tracking/Sequencing Capability: Compatible with

LTC292X Power Supply Tracking ICs

Thermally Enhanced 16-Lead MSOP and 16-Lead

(4mm × 3mm) DFN Packages

capacitor, output noise is only 20μV

over a 10Hz to

RMS

100kHz bandwidth. Designed for use in battery-powered

systems,thelow55μAquiescentcurrentperchannelmakes

it an ideal choice. In shutdown, quiescent current drops to

less than 1μA. Shutdown control is independent for each

channel, allowing for ﬂexible power management.

n

TheLT3029optimizesstabilityandtransientresponsewith

low ESR ceramic output capacitors, requiring a minimum

of only 3.3μF. The regulator does not require the addition

of ESR, as is common with other regulators.

n

Internal circuitry provides reverse-battery protection,

reverse-current protection, current limiting with foldback

and thermal shutdown. The device is available as an

adjustable output voltage device with a 1.215V reference

voltage. The LT3029 is offered in the thermally enhanced

16-lead MSOP and 16-lead, low proﬁle (4mm × 3mm ×

0.75mm) DFN packages.

APPLICATIONS

n

General Purpose Linear Regulator

n

Battery-Powered Systems

n

Microprocessor Core/Logic Supplies

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

n

Post Regulator for Switching Supplies

n

Tracking/Sequencing Power Supplies

Dropout Voltage vs Load Current

TYPICAL APPLICATION

400

T

= 25°C

2.5V_INto 1.5V/1.8V Application

J

350

300

250

200

150

100

50

V

IN

2.5V

V

OUT1

IN1

OUT1

LT3029

1.8V

10nF

500mA

113k

1%

3.3μF

BYP1

ADJ1

IN2

237k

1%

SHDN1

V

OUT2

1.5V

SHDN2 OUT2

500mA

10nF

54.9k

1%

BYP2

ADJ2

0

237k

1%

GND

0

50 100 150 200 250 300 350 400 450 500

OUTPUT CURRENT (mA)

3029 TA01b

3029 TA01

3029f

1

LT3029

ABSOLUTE MAXIMUM RATINGS ^{(Note 1)}

IN1, IN2 Pin Voltage................................................ 22V

OUT1, OUT2 Pin Voltage......................................... 22V

Input-to-Output Differential Voltage........................ 22V

ADJ1, ADJ2 Pin Voltage............................................ 9V

BYP1, BYP2 Pin Voltage ........................................ 0.6V

SHDN1 , SHDN2 Pin Voltage.................................. 22V

Output Short-Circuit Duration .......................... Indeﬁnite

Operating Junction Temperature (Notes 2, 12)

LT3029E............................................. –40°C to 125°C

LT3029I.............................................. –40°C to 125°C

LT3029H ............................................ –40°C to 150°C

LT3029MP.......................................... –55°C to 125°C

Storage Temperature Range................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

(MSOP Only)..................................................... 300°C

PIN CONFIGURATION

TOP VIEW

BYP1

NC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

ADJ1

SHDN1

IN1

BYP1

NC

OUT1

GND

OUT2

BYP2

1

2

3

4

5

6

7

8

16 ADJ1

15 SHDN1

14 IN1

OUT1

GND

17

GND

13 IN1

IN1

17

GND

12 IN2

IN2

11 IN2

10 SHDN2

OUT2

BYP2

IN2

9

ADJ2

SHDN2

ADJ2

MSE PACKAGE

16-LEAD PLASTIC MSOP

DE PACKAGE

T

= 125°C (LT3029E/LT3029I, LT3029MP), θ = 37°C/W, θ : 5°C/W TO 10°C/W

JA JC

JMAX

16-LEAD (4mm s 3mm) PLASTIC DFN

T

= 150°C (LT3029H), θ = 37°C/W, θ : 5°C/W TO 10°C/W

JA JC

JMAX

T

= 125°C, θ = 38°C/W, θ = 4.3°C/W

EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB GND

JMAX

JA

JC

EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB GND

ORDER INFORMATION

LEAD FREE FINISH

LT3029EDE#PBF

LT3029IDE#PBF

LT3029EMSE#PBF

LT3029IMSE#PBF

LT3029HMSE#PBF

LT3029MPMSE#PBF

LEAD BASED FINISH

LT3029EDE

TAPE AND REEL

PART MARKING*

3029

PACKAGE DESCRIPTION

16-Lead (4mm × 3mm) Plastic DFN

16-Lead Plastic MSOP

TEMPERATURE RANGE

–40°C to 125°C

–40°C to 150°C

–55°C to 125°C

TEMPERATURE RANGE

–40°C to 125°C

–40°C to 150°C

–55°C to 125°C

LT3029EDE#TRPBF

LT3029IDE#TRPBF

LT3029EMSE#TRPBF

LT3029IMSE#TRPBF

LT3029HMSE#TRPBF

LT3029MPMSE#TRPBF

TAPE AND REEL

3029

16-Lead Plastic MSOP

3029

16-Lead Plastic MSOP

3029

16-Lead Plastic MSOP

PART MARKING*

3029

PACKAGE DESCRIPTION

16-Lead (4mm × 3mm) Plastic DFN

16-Lead Plastic MSOP

LT3029EDE#TR

LT3029IDE

LT3029IDE#TR

3029

LT3029EMSE

LT3029EMSE#TR

LT3029IMSE#TR

3029

LT3029IMSE

3029

16-Lead Plastic MSOP

LT3029HMSE

LT3029HMSE#TR

LT3029MPMSE#TR

3029

16-Lead Plastic MSOP

LT3029MPMSE

3029

16-Lead Plastic MSOP

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

3029f

2

LT3029

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. (Note 2)

PARAMETER

CONDITIONS

= 500mA

MIN

TYP

MAX

UNITS

l

Minimum Input Voltage (Notes 3, 11)

ADJ1, ADJ2 Pin Voltage (Notes 3, 4, 9)

I

1.8

2.3

V

LOAD

V

= 2V, I

= 1mA

1.203

1.191

1.173

1.215

1.227

1.239

V

IN

LOAD

l

2.3V < V < 20V, 1mA < I

< 500mA (E, I, MP)

< 500mA (H)

IN

LOAD

2.3V < V < 20V, 1mA < I

IN

l

Line Regulation (Note 3)

Load Regulation (Note 3)

ΔV = 2V to 20V, I

= 1mA

LOAD

0.5

2.5

5

mV

IN

V

IN

V

IN

V

IN

= 2.3V, ΔI

= 1mA to 500mA

= 1mA to 500mA (E, I, MP)

= 1mA to 500mA (H)

6

15

32

mV

LOAD

l

Dropout Voltage

I

= 10mA

0.11

0.16

0.2

0.18

0.25

V

LOAD

l

V

= V

OUT(NOMINAL)

IN

(Notes 5, 6, 11)

I

= 50mA

0.22

0.31

V

LOAD

I

= 100mA

0.25

0.34

V

LOAD

I

= 500mA

0.3

0.36

0.46

V

LOAD

l

GND Pin Current (per Channel)

I

= 0mA

55

90

1.1

2

4.3

10

150

250

2

μA

mA

LOAD

V

= V

= 1mA

IN

OUT(NOMINAL)

(Notes 5, 7)

= 50mA

= 100mA

= 250mA

= 500mA

3.5

8

16

Output Voltage Noise

C

= 10μF, C

= 10nF, I

= 500mA,

20

μV

RMS

OUT

BYP

LOAD

BW = 10Hz to 100kHz

ADJ1/ADJ2 Pin Bias Current

Shutdown Threshold

ADJ1, ADJ2 (Notes 3, 8)

30

100

1.1

nA

l

V

= Off to On

= On to Off

0.45

0.40

V

OUT

0.20

l

SHDN1/SHDN2 Pin Current (Note 10)

V

, V

= 0V

= 20V

0

0.6

0.5

3

μA

SHDN1 SHDN2

, V

SHDN1 SHDN2

Quiescent Current in Shutdown (per Channel)

Ripple Rejection

V

= 6V, V

= 0V, V = 0V

SHDN2

0.01

67

0.1

μA

dB

IN

SHDN1

V

= 2.715V (Avg), V

= 0.5V ,

P-P

55

IN

RIPPLE

f

= 120Hz, I

= 500mA

RIPPLE

LOAD

Current Limit (Note 9)

V

= 7V, V

= 0V

1.5

A

IN

OUT

l

= 2.3V, ΔV

= –0.1V

= 0V

520

mA

OUT

Input Reverse Leakage Current

Reverse Output Current

V

= –20V, V

1

mA

μA

IN

OUT

= 1.215V, V = 0V

0.5

10

OUT

IN

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 3: The LT3029 is tested and speciﬁed for these conditions with the

ADJ1/ADJ2 pin connected to the corresponding OUT1/OUT2 pin.

Note 4: Maximum junction temperature limits operating conditions. The

regulated output voltage speciﬁcation does not apply for all possible

combinations of input voltage and output current. When operating at

maximum input voltage, limit the output current range. When operating at

maximum output current, limit the input voltage range.

Note 2: The LT3029 is tested and speciﬁed under pulse load conditions

such that T ≈ T . The LT3029E is 100% tested at T = 25°C. Performance

J

A

of the LT3029E over the full –40°C to 125°C operating junction

temperature range is assured by design, characterization and correlation

with statistical process controls. The LT3029I is guaranteed over the full

–40°C to 125°C operating junction temperature range. The LT3029MP is

100% tested and guaranteed over the –55°C to 125°C operating junction

temperature range. The LT3029H is tested at 150°C operating junction

temperature. High junction temperatures degrade operating lifetimes.

Operating lifetime is derated at junction temperatures greater than 125°C.

Note 5: To satisfy minimum input voltage requirements, the LT3029 is

tested and speciﬁed for these conditions with an external resistor divider

(two 243k resistors) for an output voltage of 2.437V. The external resistor

divider adds 5μA of DC load on the output.

Note 6: Dropout voltage is the minimum input to output voltage differential

needed to maintain regulation at a speciﬁed output current. In dropout, the

output voltage equals: V – V

.

IN

DROPOUT

3029f

3

LT3029

ELECTRICAL CHARACTERISTICS

Note 7: GND pin current is tested with V = 2.437V and a current source

Note 10: SHDN1/SHDN2 pin current ﬂows into the pin.

IN

load. This means the device is tested while operating in its dropout region

or at the minimum input voltage speciﬁcation. This is the worst-case

GND pin current. The GND pin current decreases slightly at higher input

voltages. Total GND pin current equals the sum of output 1 and output 2

GND pin currents.

Note 8: ADJ1/ADJ2 pin bias current ﬂows into the pin.

Note 9: The LT3029 contains current limit foldback circuitry. See the

Note 11: The LT3029 minimum input voltage speciﬁcation limits dropout

voltage under some output voltage/load conditions. See the curve of

Minimum Input Voltage in the Typical Performance Characteristics.

Note 12: The LT3029 includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature exceeds the maximum operating junction temperature when

overtemperature protection is active. Continuous operation above the

speciﬁed maximum operating junction temperature may impair device

reliability.

Typical Performance Characteristics for current limit as a function of the

V

– V

differential voltage.

IN

OUT

TYPICAL PERFORMANCE CHARACTERISTICS ^T_J^{= 25°C, unless otherwise noted.}

Typical Dropout Voltage

Guaranteed Dropout Voltage

500

450

400

350

300

250

200

150

100

50

500

450

400

350

300

250

200

150

100

50

= TEST POINTS

T

= 150°C

J

T

= 150°C

J

T

= 125°C

J

T

= 25°C

J

T

= 25°C

J

T

= –55°C

J

0

200

0

50 100 150

250 300 350 400 450 500

200

250 300 350 400 450 500

0

50 100 150

OUTPUT CURRENT (mA)

3029 G02

3029 G01

Dropout Voltage vs Temperature

Quiescent Current (per Channel)

500

450

400

350

300

250

200

150

100

50

150

125

100

75

V

= 6V

= 243k, I = 5μA

L

IN

L

R

I

= 500mA

L

I

= 250mA

= 100mA

L

I

L

V

= V

IN

SHDN

I

= 10mA

L

50

25

I

= 50mA

L

I

= 1mA

L

0

25

–75 –50 –25

0

50 75 100 125 150 175

25

–75 –50 –25

0

50 75 100 125 150 175

TEMPERATURE (°C)

3029 G03

3029 G04

3029f

4

LT3029

T_J= 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

ADJ1 or ADJ2 Pin Voltage

Quiescent Current (per Channel)

1.239

1.233

1.227

1.221

1.215

1.209

1.203

1.197

1.191

160

140

120

100

80

I

= 1mA

T

= 25°C

= 243k

OUT

L

J

L

R

V

= 1.215V

V

= V

IN

SHDN

60

40

20

V

= 0V

SHDN

0

25

–75 –50 –25

0

50 75 100 125 150 175

8

0

2

4

6

10 12 14 16 18 20

TEMPERATURE (°C)

INPUT VOLTAGE (V)

3029 G05

3029 G06

GND Pin Current (per Channel)

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

16

14

12

10

8

T

= 25°C

OUT

T

= 25°C

OUT

J

FOR V

= 1.215V

FOR V

= 1.215V

R

= 24.3Ω, I = 50mA

L

R

= 2.43Ω, I = 500mA

L

6

= 4.05Ω, I = 300mA

L

4

R

= 121.5Ω, I = 10mA

L

R

= 12.15Ω, I = 100mA

L

2

= 1.215kΩ, I = 1mA

L

0

4

0

1

2

3

5

6

7

8

9

10

4

0

1

2

3

5

6

7

8

9

10

INPUT VOLTAGE (V)

3029 G07

3029 G08

SHDN1 or SHDN2 Pin Threshold

(On-to-Off)

GND Pin Current vs I_LOAD

16

14

12

10

8

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

T

= 25°C

I

= 1mA

J

L

V

= V

+ 1V

IN

OUT(NOMINAL)

6

4

2

0

200

250 300 350 400 450 500

0

50 100 150

25

–75 –50 –25

0

50 75 100 125 150 175

OUTPUT CURRENT (mA)

TEMPERATURE (°C)

3029 G09

3029 G10

3029f

5

LT3029

T_J= 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

SHDN1 or SHDN2 Pin Threshold

(Off-to-On)

SHDN1 or SHDN2 Pin

Input Current

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

T

= 25°C

J

I

= 500mA

L

I

= 1mA

L

25

0

2

4

6

8

12 14 16 18 20

–75 –50 –25

0

50 75 100 125 150 175

10

TEMPERATURE (°C)

SHDN PIN VOLTAGE (V)

3029 G11

3029 G12

SHDN1 or SHDN2 Pin

Input Current

ADJ1 or ADJ2 Pin Bias Current

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

150

135

120

105

90

V

= 20V

SHDN

75

60

45

30

15

0

25

–75 –50 –25

0

50 75 100 125 150 175

25

–75 –50 –25

0

50 75 100 125 150 175

TEMPERATURE (°C)

3029 G14

3029 G13

Current Limit

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

V

= 0V

V

= 7V

OUT

IN

OUT

= 0V

T

= 25°C

J

T

= –55°C

J

T

= 125°C

J

T

= 150°C

J

25

8

–75 –50 –25

0

50 75 100 125 150 175

0

2

4

6

10 12 14 16 18 20

INPUT VOLTAGE (V)

TEMPERATURE (°C)

3029 G15

3029 G16

3029f

6

LT3029

T_J= 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

Reverse Current

Input Ripple Rejection

100

90

300

270

240

210

180

150

120

90

T

I

V

C

= 25°C

J

L

V

= 0V

ADJ

IN

= 500mA

= V

= 1.215V

OUT

= V

+1V + 50mV

RIPPLE

IN

BYP

OUT(NOMINAL)

RMS

80

= 0

C

= 10μF

OUT

70

I

ADJ

60

50

40

30

20

10

0

C

= 3.3μF

1M

OUT

60

30

I

OUT

0

10

100

1k

10k 100k

10M

25

–75 –50 –25

0

50 75 100 125 150 175

FREQUENCY (Hz)

TEMPERATURE (°C)

3029 G18

I

FLOWS INTO ADJ PIN TO GND PIN

FLOWS INTO OUT PIN TO IN PIN

ADJ

OUT

3029 G17

Input Ripple Rejection

100

90

100

90

80

70

60

50

40

30

20

10

0

V

IN

= V + 1.5V + 0.5V RIPPLE

OUT(NOMINAL) P-P

f = 120Hz

C

= 0.01μF

I

L

= 500mA

BYP

80

70

60

50

C

= 1000pF

BYP

40

30

20

10

0

C

= 100pF

BYP

T

= 25°C

= 500mA

= V

J

I

L

V

C

+1V + 50mV

RIPPLE

RMS

IN

OUT(NOMINAL)

= 10μF

OUT

10

100

1k

10k 100k

1M

10M

25

–75 –50 –25

0

50 75 100 125 150 175

FREQUENCY (Hz)

TEMPERATURE (°C)

3029 G19

3029 G20

Channel-to-Channel Isolation

Minimum Input Voltage

100

90

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

T

= 25°C

J

V

= 1.215V

OUT

80

I

= 500mA

L

70

60

50

I

= 1mA

L

40

30

20

10

0

10

100

1k

10k 100k

1M

10M

25

–75 –50 –25

0

50 75 100 125 150 175

FREQUENCY (Hz)

TEMPERATURE (°C)

GIVEN CHANNEL IS TESTED WITH 50mV

SIGNAL ON OPPOSING CHANNEL, BOTH

CHANNELS DELIVERING FULL CURRENT

3029 G21

RMS

3029 G22

3029f

7

LT3029

T_J= 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

Channel-to-Channel Isolation

Load Regulation

0

–2

V

OUT1

–4

50mV/DIV

–6

–8

V

OUT2

–10

–12

–14

–16

–18

–20

50mV/DIV

3029 G23

50μs/DIV

C

= 10μF

BYP2

ΔI = 50mA TO 500mA

ΔI = 1mA TO 500mA

L

OUT1

OUT2

BYP1

L1

L2

= 6V, V

ΔI = 50mA TO 500mA

25

–75 –50 –25

0

50 75 100 125 150 175

= C

= 0.01μF

V

IN

= V

= 5V

OUT1

OUT2

TEMPERATURE (°C)

3029 G24

Output Noise Spectral Density

10

1

10

1

T

= 25°C

OUT

= 500mA

T

= 25°C

J

C

I

= 10μF

C

I

= 10μF

OUT

= 0

L

BYP

= 500mA

V

= 5V

L

V

= 5V

OUT

C

= 1000pF

BYP

V

= V

ADJ

OUT

C

=

BYP

V

=V

OUT

ADJ

100pF

0.1

0.01

C

= 0.01μF

BYP

0.01

0.1

1

10

100

0.1

1

10

100

FREQUENCY (kHz)

3029 G26

3029 G25

RMS Output Noise

vs Load Current

RMS Output Noise

vs Bypass Capacitor

160

140

120

100

80

160

140

120

100

80

T

= 25°C

T

= 25°C

OUT

= 500mA

J

C

= 10μF

C

I

= 10μF

OUT

C

V

= 5V

OUT

= 0

BYP

L

BW

= 10nF

f

= 10Hz TO 100kHz

V

= 5V

OUT

V

= 1.215V

OUT

V

=V

ADJ

OUT

60

40

V

= 5V

OUT

20

V

=V

ADJ

OUT

0

0.01

0

0.1

1

10

100

10

100

1000

10000

LOAD CURRENT (mA)

C

(pF)

BYP

3029 G28

3029 G27

3029f

8

LT3029

T_J= 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

10Hz to 100kHz Output Noise,

C_BYP= 0pF

10Hz to 100kHz Output Noise,

C_BYP= 100pF

V

OUT

100μV/DIV

OUT

100μV/DIV

3029 G29

3029 G30

1ms/DIV

C

L

V

= 10μF

C

= 10μF

OUT

I

= 500mA

I = 500mA

L

= 5V

V

= 5V

OUT

10Hz to 100kHz Output Noise,

C_BYP= 1000pF

10Hz to 100kHz Output Noise,

C_BYP= 0.01μF

V

OUT

100μV/DIV

3029 G31

3029 G32

1ms/DIV

C

I

= 10μF

C

I

= 10μF

OUT

L

OUT

L

= 500mA

V

= 5V

OUT

V

= 5V

OUT

3029f

9

LT3029

T_J= 25°C, unless otherwise noted.

Transient Response, C_BYP= 0.01μF

TYPICAL PERFORMANCE CHARACTERISTICS

Transient Response, C_BYP= 0pF

V

DEVIATION

OUT

V

DEVIATION

OUT

200mV/DIV

250mA/DIV

50mV/DIV

LOAD CURRENT DEVIATION

250mA/DIV

3029 G33

3029 G34

200μs/DIV

= 100mA

20μs/DIV

I = 100mA

L

V

C

= 6V

I

V

C

= 6V

IN

L

J

IN

= 10μF

T = 25°C

= 10μF

T = 25°C

J

= 10μF

V

= 5V

= 10μF

V

= 5V

OUT

Start-Up Time from Shutdown,

C_BYP= 0pF

Start-Up Time from Shutdown,

C_BYP= 0.01μF

V

OUT

1V/DIV

SHDN

VOLTAGE

2V/DIV

SHDN

VOLTAGE

2V/DIV

3029 G35

3029 G36

1ms/DIV

V

C

= 2.5V

OUT

= 3Ω

I

= 500mA

V

C

= 2.5V

OUT

= 3Ω

I

= 500mA

IN

L

IN

L

= 10μF

V

= 1.5V

OUT

= 10μF

V

= 1.5V

OUT

R

L

3029f

10

LT3029

PIN FUNCTIONS

BYP1/BYP2 (Pin 1/Pin 8): Bypass. Use the BYP1/BYP2

pins to bypass the reference of the LT3029 regulator and

achieve low output noise performance. Internal circuitry

Include a bypass capacitor in battery-powered circuits,

as a battery’s output impedance rises with frequency. A

bypass capacitor in the range of 1μF to 10μF sufﬁces. The

LT3029’sdesignwithstandsreversevoltagesontheINpins

with respect to ground and the OUT pins. In the case of

a reversed input, which occurs if a battery is plugged in

backwards, the LT3029 acts as if a diode is in series with

its input. No reverse current ﬂows into the LT3029 and no

reverse voltage appears at the load. The device protects

itself and the load.

clamps the BYP1/BYP2 pins to 0.6V (one V ) from

BE

ground. A small capacitor from the corresponding output

to this pin bypasses the reference to lower the output

voltage noise. Using a maximum value of 10nF reduces

the output voltage noise to a typical 20μV

to 100kHz bandwidth. If not used, this pin must be left

unconnected.

over a 10Hz

RMS

NC (Pin 2): No Connect. This pin is not connected to

SHDN1/SHDN2 (Pin 15/Pin 10): Shutdown. Pulling the

SHDN1 or SHDN2 pin low puts its corresponding LT3029

channelintoalowpowerstateandturnsitsoutputoff. The

SHDN1 and SHDN2 pins are completely independent of

each other, and each SHDN pin only affects operation on

its corresponding channel. Drive the SHDN1 and SHDN2

pinswitheitherlogicoranopencollector/drainwithpull-up

resistors. The resistors supply the pull-up current to the

open collectors/drains and the SHDN1 or SHDN2 current,

typically less than 1μA. If unused, connect the SHDN1 and

SHDN2 to their corresponding IN pins. Each channel will

be in its low power shutdown state if its corresponding

SHDN pin is not connected.

any internal circuitry. It may be ﬂoated, tied to V or tied

IN

to GND.

OUT1/OUT2 (Pins 3, 4/Pins 6, 7): Output. The outputs

supply power to the loads. A minimum 3.3μF output ca-

pacitor prevents oscillations on each output. Applications

with large output load transients require larger values of

output capacitance to limit peak voltage transients. See

the Applications Information section for more on output

capacitance and reverse output characteristics.

GND (Pin 5, 17): Ground. The exposed pad (Pin 17) of

the DFN and MSOP packages is an electrical connection

to GND. To ensure proper electrical and thermal perfor-

mance, solder Pin 17 to the PCB ground and tie directly

to Pin 5. Connect the bottom of the output voltage setting

resistor divider directly to GND (Pin 5) for optimum load

regulation performance.

ADJ1/ADJ2: (Pin 16/Pin 9) Adjust Pin. These are the error

ampliﬁer inputs. These pins are internally clamped to 9V.

A typical input bias current of 30nA ﬂows into the pins

(see curve of ADJ1/ADJ2 Pin Bias Current vs Temperature

in the Typical Performance Characteristics section). The

ADJ1andADJ2pinvoltageis1.215Vreferencedtoground

and the output voltage range is 1.215V to 19.5V.

IN1/IN2 (Pins 13, 14/Pins 11, 12): Inputs. The IN1/IN2

pins supply power to each channel. The LT3029 requires

a bypass capacitor at the IN1/IN2 pins if located more

than six inches away from the main input ﬁlter capacitor.

3029f

11

LT3029

APPLICATIONS INFORMATION

TheLT3029isadual500mA/500mAlowdropoutregulator

with independent inputs, micropower quiescent current

andshutdown.Thedevicesuppliesupto500mAfromeach

channel’s output at a typical dropout voltage of 300mV.

The two regulators share a common GND pin and are

thermally coupled. However, the two inputs and outputs of

the LT3029 operate independently. Each channel can be

shut down independently, but a thermal shutdown fault

on either channel shuts off the output on both channels.

The addition of a 10nF reference bypass capacitor lowers

LT3029

⎛

⎞

⎟

R2

R1⎠

OUT1/OUT2

V

V_OUT= 1.215V 1+

+ I

(

R2

(

OUT

)

⎜

⎝

ADJ

V

IN1/IN2

IN

R2

C

V_ADJ= 1.215V

I_ADJ= 30nA AT 25°C

OUTPUT RANGE = 1.215V TO 19.5V

ADJ1/ADJ2

GND

R1

3029 F01

Figure 1. Adjustable Operation

and ADJ Pin Bias Current vs Temperature appear in the

Typical Performance Characteristics section.

output voltage noise to 20μV

over a 10Hz to 100kHz

RMS

bandwidth. Additionally, the reference bypass capacitor

improves transient response of the regulator, lowering

the settling time for transient load conditions. The low

operating quiescent current (55μA per channel) drops to

less than 1μA in shutdown. In addition to the low quies-

cent current, the LT3029 regulator incorporates several

protection features that make it ideal for use in battery-

powered systems. Most importantly, the device protects

itself against reverse input voltages. Current limiting with

foldback necessitates a minimum load current of 20μA

for input/output voltage differentials of more than 10V to

keep the output regulated.

LinearTechnologytestsandspeciﬁeseachLT3029channel

with its ADJ pin tied to the corresponding OUT pin for a

1.215V output voltage. Speciﬁcations for output voltages

greaterthan1.215Vareproportionaltotheratioofdesired

output voltage to 1.215V:

V_OUT

1.215V

Forexample, loadregulationoneitheroutputforanoutput

current change of 1mA to 500mA is typically –2.5mV at

V

OUT

= 1.215V. At V

= 2.5V, load regulation is:

OUT

2.5V

1.215V

Adjustable Operation

• (−2.5mV) = − 5.14mV

EachoftheLT3029’schannelshasanoutputvoltagerange

of 1.215V to 19.5V. Figure 1 illustrates that output voltage

is set by the ratio of two external resistors. The device

regulates the output to maintain the corresponding ADJ

pin voltage at 1.215V referenced to ground. R1’s current

equals 1.215V/R1. R2’s current equals R1’s current plus

theADJpinbiascurrent. TheADJpinbiascurrent, 30nAat

25°C, ﬂows through R2 into the ADJ pin. Use the formula

in Figure 1 to calculate output voltage. Linear Technology

recommends that the value of R1 be less than 243k to

minimizeerrorsintheoutputvoltageduetotheADJpinbias

current. In shutdown, the output turns off and the divider

current is zero. Curves of ADJ Pin Voltage vs Temperature

Table 1 shows 1% resistor divider values for some com-

mon output voltages with a resistor divider current of

approximately 5μA.

Table 1. Output Voltage Resistor Divider Values

V

R1

(k)

R2

(k)

OUT

(V)

1.5

1.8

2.5

3

237

243

232

210

200

54.9

113

255

340

357

619

3.3

5

3029f

12

LT3029

APPLICATIONS INFORMATION

Bypass Capacitance and Low Noise Performance

Output Capacitance and Transient Response

The LT3029 design is stable with a wide range of output

capacitors. The ESR of the output capacitor affects stabil-

ity, most notably with small capacitors. Linear Technology

recommends a minimum output capacitor of 3.3μF with

an ESR of 3Ω, or less, to prevent oscillations. The LT3029

is a micropower device, and output transient response is

a function of output capacitance. Larger values of output

capacitance decrease the peak deviations and provide

improved transient response for larger load current

changes.

Using a bypass capacitor connected between a channel’s

BYP pin and its corresponding OUT pin signiﬁcantly low-

ers LT3029 output voltage noise, but is not required in

all applications. Linear Technology recommends a good

quality low leakage capacitor. This capacitor bypasses

the regulator’s reference, providing a low frequency noise

pole. A 10nF bypass capacitor introduces a noise pole that

decreases output voltage noise to as low as 20μV

.

RMS

Using a bypass capacitor provides the added beneﬁt of

improving transient response. With no bypass capacitor,

and a 10μF output capacitor, a 100mA to 500mA load step

settles to within 1% of its ﬁnal value in approximately

100μs. With the addition of a 10nF bypass capacitor and

evaluating the same load step, output voltage excursion

stays within 1% (see Transient Response in the Typical

Performance Characteristics section). Using a bypass

capacitor makes regulator start-up time proportional to

the value of the bypass capacitor. For example, a 10nF

bypass capacitor and 10μF output capacitor slow start-up

time to 15ms.

Ceramic capacitors require extra consideration. Manufac-

turersmakeceramiccapacitorswithavarietyofdielectrics,

each with different behavior across temperature and

applied voltage. The most common dielectrics specify

the EIA temperature characteristic codes of Z5U, Y5V,

X5R and X7R. Z5U and Y5V dielectrics provide high C-V

products in a small package at low cost, but exhibit strong

voltage and temperature coefﬁcients, as shown in Figures

2 and 3. When used with a 5V regulator, a 16V 10μF Y5V

capacitor can exhibit an effective value as low as 1μF to

40

20

BOTH CAPACITORS ARE 16V,

1210 CASE SIZE, 10μF

0

X5R

0

–20

–40

Y5V

–60

Y5V

–80

BOTH CAPACITORS ARE 16V,

1210 CASE SIZE, 10μF

–100

0

8

12 14

–50 –25

0

25

50

75

100 125

2

4

6

10

16

DC BIAS VOLTAGE (V)

TEMPERATURE (°C)

3029 F02

3029 F03

Figure 2. Ceramic Capacitor DC Bias Characteristics

Figure 3. Ceramic Capacitor Temperature Characteristics

3029f

13

LT3029

APPLICATIONS INFORMATION

2μF for the applied DC bias voltage and over the operat-

ing temperature range. X5R and X7R dielectrics result in

more stable characteristics and are more suitable for use

as the output capacitor. The X7R type has better stability

across temperature, while the X5R is less expensive and

is available in higher values.

Voltage and temperature coefﬁcients are not the only

sources of problems. Some ceramic capacitors have a

piezoelectric response. A piezoelectric device generates

voltage across its terminals due to mechanical stress,

similar to the way a piezoelectric accelerometer or micro-

phone works. For a ceramic capacitor, the stress can be

induced by vibrations in the system or thermal transients.

The resulting voltages produced can cause appreciable

amounts of noise, especially when a ceramic capacitor is

used for noise bypassing. A ceramic capacitor produced

Figure 4’s trace in response to light tapping from a pencil.

Similar vibration induced behavior can masquerade as

increased output voltage noise.

Exercise care even when using X5R and X7R capacitors;

theX5RandX7Rcodesonlyspecifyoperatingtemperature

rangeandmaximumcapacitancechangeovertemperature.

Capacitance change due to DC bias (voltage coefﬁcient)

with X5R and X7R capacitors is better than with Y5V and

Z5U capacitors, but can still be signiﬁcant enough to drop

capacitor values below appropriate levels. Capacitor DC

biascharacteristicstendtoimproveascasesizeincreases.

LinearTechnologyrecommendsverifyingexpectedversus

actual capacitance values at operating voltage in situ for

an application.

C

LOAD

= 10μF

= 0.01μF

= 500mA

OUT

BYP

I

V

OUT

500μV/DIV

3029 F04

100ms/DIV

Figure 4. Noise Resulting from Tapping on a Ceramic Capacitor

3029f

14

LT3029

APPLICATIONS INFORMATION

Thermal Considerations

board stiffeners and plated through-holes can also spread

the heat generated by power devices.

TheLT3029’spowerhandlingcapabilitylimitsthemaximum

rated junction temperature (125°C, LT3029E/LT3029I/

LT3029MPor150°C,LT3029H).Twocomponentscomprise

the power dissipated by each channel:

The following tables list thermal resistance as a function

of copper area in a ﬁxed board size. All measurements

were taken in still air on a four-layer FR-4 board with 1oz

solid internal planes, and 2oz external trace planes with a

total board thickness of 1.6mm. For further information

onthermalresistanceandusingthermalinformation,refer

to JEDEC standard JESD51, notably JESD51-12.

1. Output current multiplied by the input/output voltage

differential: (I )(V – V ), and

OUT

IN

OUT

2. GND pin current multiplied by the input voltage:

(I )(V ).

GND

IN

Table 2. DE Package, 16-Lead DFN

Ground pin current is found by examining the GND Pin

Current curves in the Typical Performance Characteristics

section.

COPPER AREA

THERMAL RESISTANCE

TOPSIDE*

BACKSIDE BOARD AREA

(JUNCTION-TO-AMBIENT)

2

2500mm

36°C/W

2

1000mm

37°C/W

Power dissipation for each channel equals the sum of the

two components listed above. Total power dissipation for

the LT3029 equals the sum of the power dissipated by

each channel.

2

225mm

38°C/W

2

100mm

40°C/W

*Device is mounted on topside.

TheLT3029’sinternalthermalshutdowncircuitryprotects

bothchannelsofthedeviceifeitherchannelexperiences

an overload or fault condition. Activation of the thermal

shutdowncircuitryturnsbothchannelsoff.Iftheoverload

or fault condition is removed, both outputs are allowed

to turn back on. For continuous normal conditions, do

not exceed the maximum junction temperature rating of

125°C(LT3029E/LT3029I/LT3029MP)or150°C(LT3029H).

Carefully consider all sources of thermal resistance from

junction-to-ambient, including additional heat sources

mounted in proximity to the LT3029. For surface mount

devices,usetheheatspreadingcapabilitiesofthePCboard

and its copper traces to accomplish heat sinking. Copper

Table 3. MSE Package, 16-Lead MSOP

COPPER AREA

THERMAL RESISTANCE

TOPSIDE*

BACKSIDE BOARD AREA

(JUNCTION-TO-AMBIENT)

2

2500mm

35°C/W

36°C/W

37°C/W

39°C/W

2

1000mm

2

225mm

2

100mm

*Device is mounted on topside.

The junction-to-case thermal resistance (θ ), measured

JC

at the Exposed Pad on the back of the die, is 4.3°C/W for

the DFN package, and 5°C/W to 10°C/W for the MSOP

package.

3029f

15

LT3029

APPLICATIONS INFORMATION

Calculating Junction Temperature

Protection Features

Example: Channel 1’s output voltage is set to 1.8V. Chan-

nel 2’s output voltage is set to 1.5V. Each channel’s input

voltage is 2.5V. Each channel’s output current range is

0mA to 500mA. The application has a maximum ambient

temperature of 50°C. What is the LT3029’s maximum

junction temperature?

The LT3029 regulator incorporates several protection fea-

tures that make it ideal for use in battery-powered circuits.

In addition to the normal protection features associated

with monolithic regulators, such as current limiting and

thermal limiting, the device protects itself against reverse

input voltages and reverse voltages from output to input.

The two regulators have independent inputs, a common

GND pin and are thermally coupled. However, the two

channels of the LT3029 operate independently. Each

channel’s output can be shut down independently, and

a fault condition on one output does not affect the other

output electrically, unless the thermal shutdown circuitry

is activated.

The power dissipated by each channel equals:

I

(V – V ) + I (V )

OUT(MAX) IN OUT GND IN

where for each output:

= 500mA

I

OUT(MAX)

V = 2.5V

IN

Current limit protection and thermal overload protection

protect the device against current overload conditions at

each output of the LT3029. For normal operation, do not

allowthejunctiontemperaturetoexceed125°C(LT3029E/

LT3029I/LT3029MP)or150°C(LT3029H).Thetypicalther-

mal shutdown temperature threshold is 165°C and the

circuitry incorporates approximately 5°C of hysteresis.

I

at (I

= 500mA, V = 2.5V) = 8.5mA

GND

OUT IN

So, for output 1:

P = 500mA (2.5V – 1.8V) + 8.5mA (2.5V) = 0.37W

For output 2:

P = 500mA (2.5V – 1.5V) + 8.5mA (2.5V) = 0.52W

Thethermalresistanceisintherangeof35°C/Wto40°C/W,

dependingonthecopperarea.So,thejunctiontemperature

rise above ambient temperature approximately equals:

Each channel’s input withstands reverse voltages of 22V.

Current ﬂow into the device is limited to less than 1mA

(typicallylessthan100μA)andnonegativevoltageappears

at the respective channel’s output. The device protects

both itself and the load against batteries that are plugged

in backwards.

(0.37W + 0.52W) 39°C/W = 34.7°C

The maximum junction temperature then equals the maxi-

mum ambient temperature plus the maximum junction

temperature rise above ambient temperature, or:

The LT3029 incurs no damage if either channel’s output

is pulled below ground. If the input is left open-circuit,

or grounded, the output can be pulled below ground by

T

JMAX

= 50°C + 34.7°C = 84.7°C

3029f

16

LT3029

APPLICATIONS INFORMATION

22V. The output acts like an open circuit, and no current

ﬂows from the output. However, current ﬂows in (but

is limited by) the external resistor divider that sets the

output voltage.

into the ADJ pin to less than 5mA when the ADJ pin is

at 9V. The 11V difference between the OUT and ADJ pins

divided by the 5mA maximum current into the ADJ pin

yields a minimum top resistor value of 2.2k.

The LT3029 incurs no damage if either ADJ pin is pulled

above or below ground by 9V. If the input is left open

circuit or grounded, the ADJ pins perform like an open

circuit down to –1.5V, and then like a 1.2k resistor down

to –9V when pulled below ground. When pulled above

ground, the ADJ pins perform like an open circuit up to

0.5V, then like a 5.7k resistor up to 3V, then like a 1.8k

resistor up to 9V.

In circuits where a backup battery is required, several

different input/output conditions can occur. The output

voltage may be held up while the input is either pulled

to ground, pulled to some intermediate voltage or is left

open-circuit. Current ﬂow back into the output follows the

curve shown in Figure 5.

If either of the LT3029’s IN pins is forced below its cor-

responding OUT pin, or the OUT pin is pulled above its

corresponding IN pin, input current for that channel typi-

cally drops to less than 2μA. This occurs if the IN pin is

connectedtoadischarged(lowvoltage)battery,andeither

a backup battery or a second regulator circuit holds up

the output. The state of that channel’s SHDN pin has no

effect on the reverse output current if the output is pulled

above the input.

In situations where an ADJ pin connects to a resistor

divider that would pull the pin above its 9V clamp volt-

age if the output is pulled high, the ADJ pin input current

must be limited to less than 5mA. For example, assume

a resistor divider sets the regulated output voltage to

1.5V, and the output is forced to 20V. The top resistor of

the resistor divider must be chosen to limit the current

5.0

T

V

= 25°C

J

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

= 0V

IN

ADJ

= V

OUT

I

ADJ

OUT

4

0

1

2

3

5

6

7

8

9

OUTPUT VOLTAGE (V)

I

FLOWS INTO ADJ PIN TO GND PIN

FLOWS INTO OUT PIN TO IN PIN

ADJ

OUT

3029 F05

Figure 5. Reverse Output Current

3029f

17

LT3029

PACKAGE DESCRIPTION

DE Package

16-Lead Plastic DFN (4mm × 3mm)

(Reference LTC DWG # 05-08-1732 Rev Ø)

0.70 ±0.05

3.30 ±0.05

1.70 ± 0.05

3.60 ±0.05

2.20 ±0.05

PACKAGE

OUTLINE

0.25 ± 0.05

0.45 BSC

3.15 REF

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

R = 0.115

TYP

0.40 ± 0.10

16

4.00 ±0.10

(2 SIDES)

9

R = 0.05

TYP

3.30 ±0.10

3.00 ±0.10

(2 SIDES)

1.70 ± 0.10

PIN 1 NOTCH

R = 0.20 OR

PIN 1

TOP MARK

(SEE NOTE 6)

0.35 × 45°

CHAMFER

(DE16) DFN 0806 REV Ø

8

1

0.23 ± 0.05

0.45 BSC

0.75 ±0.05

0.200 REF

3.15 REF

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC

PACKAGE OUTLINE MO-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

3029f

18

LT3029

PACKAGE DESCRIPTION

MSE Package

16-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1667 Rev A)

BOTTOM VIEW OF

EXPOSED PAD OPTION

2.845 p 0.102

(.112 p .004)

2.845 p 0.102

(.112 p .004)

0.889 p 0.127

(.035 p .005)

1

8

0.35

REF

5.23

(.206)

MIN

1.651 p 0.102

(.065 p .004)

1.651 p 0.102

(.065 p .004)

3.20 – 3.45

(.126 – .136)

0.12 REF

DETAIL “B”

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

DETAIL “B”

16

9

0.305 p 0.038

0.50

(.0197)

BSC

NO MEASUREMENT PURPOSE

4.039 p 0.102

(.159 p .004)

(NOTE 3)

(.0120 p .0015)

TYP

0.280 p 0.076

(.011 p .003)

RECOMMENDED SOLDER PAD LAYOUT

16151413121110

9

REF

DETAIL “A”

0.254

(.010)

3.00 p 0.102

(.118 p .004)

(NOTE 4)

0o – 6o TYP

4.90 p 0.152

(.193 p .006)

GAUGE PLANE

0.53 p 0.152

(.021 p .006)

1 2 3 4 5 6 7 8

DETAIL “A”

0.86

(.034)

REF

1.10

(.043)

MAX

0.18

(.007)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.1016 p 0.0508

(.004 p .002)

MSOP (MSE16) 0608 REV A

0.50

(.0197)

BSC

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

3029f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

19

LT3029

TYPICAL APPLICATION

Coincident Tracking Supply Application

3.3V

V

C

OUT1

GATE

0.1μF

3.3V

OUT1

V

GATE

CC

1.8V

0.1μF

IN1

3.3μF

10nF 113k

1%

500mA

3.3μF

OFF

ON

RAMP

LTC2923

ON

BYP1

ADJ1

LT3029

SHDN1

V

OUT1

OUT2

1M

237k

1%

500mV/DIV

RAMPBUF

TRACK1

TRACK2

FB1

SDO

FB2

113k

1%

2.5V

IN2

OUT2

V

OUT2

54.9k

10nF

90.9k

1%

3.3μF 1.5V

54.9k

1%

500mA

BYP2

ADJ2

3029 TA02b

SHDN2

10ms/DIV

63.4k

1%

237k

1%

GND

3029 TA02

RELATED PARTS

PART NUMBER DESCRIPTION

COMMENTS

LT1761

100mA, Low Noise Micropower LDO

V : 1.8V to 20V, V

= 1.22V, V = 0.3V, I = 20μA, I < 1μA,

OUT(MIN) DO Q SD

IN

Low Noise < 20μV

, Stable with 1μF Ceramic Capacitors, ThinSOT^TMPackage

RMS

LT1763

500mA, Low Noise Micropower LDO

V : 1.8V to 20V, V

= 1.22V, V = 0.3V, I = 30μA, I < 1μA,

DO Q SD

IN

OUT(MIN)

Low Noise < 20μV

, S8 and DFN Packages

RMS

LT1963/

LT1963A

1.5A, Low Noise, Fast Transient

Response LDOs

V : 2.1V to 20V, V

= 1.21V, V = 0.34V, I = 1mA, I < 1μA,

OUT(MIN) DO Q SD

RMS

IN

Low Noise: < 40μV

, “A” Version Stable with Ceramic Capacitors;

DD, TO220-5, SOT223, S8 and TSSOP Packages

LT1964

LT1965

200mA, Low Noise Micropower,

Negative LDO

V : –1.9V to –20V, V

= –1.22V, V = 0.34V, I = 30μA, I = 3μA,

OUT(MIN) DO Q SD

IN

Low Noise: <30μV

, Stable with Ceramic Capacitors, ThinSOT Package

RMS

1.1A, Low Noise LDO

V : 1.8V to 20V, V

= 1.20V, V = 0.31V, I = 0.5mA, I < 1μA,

OUT(MIN) DO Q SD

IN

Low Noise: <40μV

, Stable with Ceramic Capacitors; 3mm × 3mm DFN,

RMS

MS8E, DD-Pak and TO-220 Packages

LT3020

LT3021

LT3023

LT3024

LTC3025

LTC3026

LT3027

LT3028

100mA, Low Voltage VLDO

500mA, Low Voltage VLDO

V : 0.9V to 10V, V = 0.20V, V = 0.15V, I = 120μA, I < 3μA;

IN

OUT(MIN)

DO

Q

SD

3mm × 3mm DFN and MS8 Packages

V : 0.9V to 10V, V = 0.20V, V = 0.16V, I = 120μA, I < 3μA;

IN

OUT(MIN)

DO

Q

SD

5mm × 5mm DFN and SO8 Packages

Dual 100mA, Low Noise,

Micropower LDO

V : 1.8V to 20V, V = 1.22V, V = 0.30V, I = 40μA, I < 1μA;

IN

OUT(MIN)

DO

Q

SD

DFN and MS10E Packages

Dual 100mA/500mA, Low Noise,

Micropower LDO

V : 1.8V to 20V, V

= 1.22V, V = 0.30V, I = 60μA, I < 1μA;

IN

OUT(MIN)

DO

Q

SD

DFN and TSSOP-16E Packages

300mA, Low Voltage Micropower VLDO

V : 0.9V to 5.5V, Low I : 54μA, Low Noise < 80μV

, 45mV Dropout Voltage;

IN

Q

RMS

2mm × 2mm 6-Lead DFN Package

V : 1.14V to 5.5V, Low I : 950μA, Low Noise < 110μV , 100mV Dropout Voltage;

RMS

1.5A, Low Input Voltage VLDO

IN

Q

10-Lead 3mm × 3mm DFN and MS10E Packages

Dual 100mA, Low Noise, Micropower

LDO with Independent Inputs

V : 1.8V to 20V, V = 1.22V, V = 0.30V, I = 50μA, I < 1μA;

IN

OUT(MIN)

DO

Q

SD

DFN and MS10E Packages

Dual 100mA/500mA, Low Noise, Micropower V : 1.8V to 20V, V

LDO with Independent Inputs

= 1.22V, V = 0.32V, I = 60μA, I < 1μA;

IN

OUT(MIN)

DO

Q

SD

DFN and TSSOP-16E Packages

LT3080/

LT3080-1

1.1A, Parallelable, Low Noise LDO

V : 1.2V to 36V, V : 0V to 35.7V, Low Noise < 40μV

, 300mV Dropout Voltage

IN

OUT

RMS

(2-Supply Operation), Current-Based Reference with 1-Resistor V

Set, Directly

OUT

Parallelable (No Op Amp Required), Stable with Ceramic Capacitors;

TO-220, SOT-223, MS8E and 3mm × 3mm DFN Packages

ThinSOT is a trademark of Linear Technology Corporation.

3029f

LT 0110 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

20

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT3029EDETR
厂家：	Linear
描述：	Dual 500mA/500mA Low Dropout, Low Noise, Micropower Linear Regulator 双500毫安/ 500毫安低压差，低噪声，微功耗线性稳压器稳压器
文件：	总20页 (文件大小：1587K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT3029EDETR [Linear]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E