LT3070EUFD#PBF [Linear]
LT3070 - 5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator; Package: QFN; Pins: 28; Temperature Range: -40°C to 85°C;
| 型号： | LT3070EUFD#PBF |
| 厂家： | 
Linear |
| 描述： | LT3070 - 5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator; Package: QFN; Pins: 28; Temperature Range: -40°C to 85°C 输出元件 调节器 |
| 文件： | 总28页 (文件大小：675K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3070
5A, Low Noise,
Programmable Output,
85mV Dropout
Linear Regulator
FEATURES
DESCRIPTION
The LT®3070 is a low voltage, UltraFast™ transient re-
sponse linear regulator. The device supplies up to 5A of
output current with a typical dropout voltage of 85mV.
A 0.01µF reference bypass capacitor decreases output
n
Output Current: 5A
n
Dropout Voltage: 85mV Typical
n
Digitally Programmable V : 0.8V to 1.8V
OUT
n
Digital Output Margining: 1ꢀ, ꢁꢀ or 5ꢀ
n
Low Output Noise: 25µV
(10Hz to 100kHz)
voltage noise to 25µV
. The LT3070’s high bandwidth
RMS
RMS
n
n
n
n
Parallel Multiple Devices for 10A or More
permits the use of low ESR ceramic capacitors, saving
bulk capacitance and cost. The LT3070’s features make
it ideal for high performance FPGAs, microprocessors or
sensitive communication supply applications.
Precision Current Limit: 20ꢀ
1ꢀ Accuracy Over Line, Load and Temperature
Stable with Low ESR Ceramic Output Capacitors
(15µF Minimum)
Output voltage is digitally selectable in 50mV increments
over a 0.8V to 1.8V range. A margining function allows
the user to adjust system output voltage in increments of
1ꢀ, 3ꢀ or 5ꢀ. The IC incorporates a uniꢁue tracking
functiontocontrolabuckregulatorpoweringtheLT3070’s
input. This tracking function drives the buck regulator to
n
n
n
High Freꢁuency PSRR: 30dB at 1MHz
Enable Function Turns Output On/Off
VIOC Pin Controls Buck Converter to Maintain Low
Power Dissipation and Optimize Efficiency
PWRGD/UVLO/Thermal Shutdown Flag
Current Limit with Foldback Protection
Thermal Shutdown
n
n
n
n
maintain the LT3070’s input voltage to V
minimizing power dissipation.
+ 300mV,
OUT
28-Lead (4mm × 5mm × 0.75mm) QFN Package
InternalprotectionincludesUVLO,reverse-currentprotec-
tion, precision current limiting with power foldback and
thermal shutdown. The LT3070 regulator is available in a
thermally enhanced 28-lead, 4mm × 5mm QFN package.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
UltraFast and VLDO are trademarks of Linear Technology Corporation. All other trademarks are
the property of their respective owners. Patents pending.
APPLICATIONS
n
FPGA and DSP Supplies
n
ASIC and Microprocessor Supplies
n
Servers and Storage Devices
n
Post Buck Regulation and Supply Isolation
TYPICAL APPLICATION
Dropout Voltage
0.9V, 5A Regulator
150
V
= V
OUT(NOMINAL)
IN
50k
V
BIAS
2.2V TO 3.6V
PWRGD
2.2µF
120
90
60
30
0
BIAS
V
IN
1.2V
IN
EN
V
PWRGD
SENSE
330µF
V
0.9V
5A
OUT
V
= 1.8V
= 3.3V
OUT
LT3070
OUT
O0
V
BIAS
2.2µF*
4.7µF*
10µF*
V
O1
V
O2
V
V
= 0.8V
= 2.5V
OUT
BIAS
*X5R OR X7R CAPACITORS
MARGSEL
MARGTOL
VIOC
REF/BYP
GND
1nF
0.01µF
0
1
2
3
4
5
3070 TA01a
OUTPUT CURRENT (A)
3070 TA01b
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For more information www.linear.com/LT3070
LT3070
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
IN, OUT ..................................................... –0.3V to 3.3V
BIAS............................................................. –0.3V to 4V
O2 O1 O0
28 27 26 25 24 23
V , V , V Inputs .................................... –0.3V to 4V
VIOC
PWRGD
REF/BYP
GND
IN
1
2
3
4
5
6
7
8
22
21
20
19
18
17
16
15
MARGTOL
MARGSEL
GND
MARGSEL, MARGTOL Input ........................ –0.3V to 4V
EN Input....................................................... –0.3V to 4V
SENSE Input................................................. –0.3V to 4V
VIOC, PWRGD Outputs ................................ –0.3V to 4V
REF/BYP Output........................................... –0.3V to 4V
Output Short-Circuit Duration……...................Indefinite
Operating Junction Temperature (Note 2)
LT3070E/LT3070I ............................. –40°C to 125°C
LT3070MP ......................................... –55°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
SENSE
OUT
29
GND
IN
OUT
IN
OUT
IN
OUT
9
10 11 12 13 14
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
T
= 125°C, θ = 30°C/W TO 35°C/W
JMAX
JA
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LT3070EUFD#PBF
LT3070IUFD#PBF
LT3070MPUFD#PBF
LEAD BASED FINISH
LT3070EUFD
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3070EUFD#TRPBF
LT3070IUFD#TRPBF
LT3070MPUFD#TRPBF
TAPE AND REEL
3070
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
PACKAGE DESCRIPTION
3070
3070
PART MARKING*
3070
LT3070EUFD#TR
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
LT3070IUFD
LT3070IUFD#TR
3070
LT3070MPUFD
LT3070MPUFD#TR
3070
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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For more information www.linear.com/LT3070
LT3070
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. COUT = 15µF (Note 9), VIN = VOUT + 0.ꢁV (Note 5), VBIAS = 2.5V unless
otherwise noted.
PARAMETER
CONDITIONS
MIN
0.95
2.2
TYP
MAX
3.0
UNITS
l
l
IN Pin Voltage Range
BIAS Pin Voltage Range (Note 3)
Regulated Output Voltage
V
≥ V
+ 150mV, I = 5A
V
V
IN
OUT
OUT
3.6
l
l
l
l
l
l
l
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
= 0.8V, 10mA ≤ I
= 0.9V, 10mA ≤ I
≤ 5A, 1.05V ≤ V ≤ 1.25V
0.792
0.891
0.990
1.089
1.188
1.485
1.782
0.800
0.900
1.000
1.100
1.200
1.500
1.800
0.808
0.909
1.010
1.111
1.212
1.515
1.818
V
V
V
V
V
V
V
OUT
OUT
OUT
IN
≤ 5A, 1.15V ≤ V ≤ 1.35V
IN
= 1V, 10mA ≤ I
≤ 5A, 1.25V ≤ V ≤ 1.45V
IN
= 1.1V, 10mA ≤ I
= 1.2V, 10mA ≤ I
= 1.5V, 10mA ≤ I
= 1.8V, 10mA ≤ I
≤ 5A, 1.35V ≤ V ≤ 1.55V
IN
OUT
OUT
OUT
OUT
≤ 5A, 1.45V ≤ V ≤ 1.65V, V
= 3.3V
= 3.3V
= 3.3V
IN
BIAS
BIAS
BIAS
≤ 5A, 1.75V ≤ V ≤ 1.95V, V
IN
≤ 5A, 2.05V ≤ V ≤ 2.25V, V
IN
l
l
Regulated Output Voltage Margining
(Note 3)
MARGTOL = 0V, MARGSEL = V
0.8
–1.2
1
–1
1.2
–0.8
ꢀ
ꢀ
BIAS
OUT
MARGTOL = 0V, MARGSEL = 0V, I
= 10mA
l
l
MARGTOL = FLOAT, MARGSEL = V
2.7
3
3.3
ꢀ
ꢀ
BIAS
MARGTOL = FLOAT, MARGSEL = 0V, I
= 10mA
–3.3
–3
–2.7
OUT
OUT
l
l
MARGTOL = V
MARGTOL = V
, MARGSEL= V
4.6
–5.4
5
–5
5.4
–4.6
ꢀ
ꢀ
BIAS
BIAS
BIAS
, MARGSEL = 0V, I
= 10mA
l
l
Line Regulation to V
1.0
1.0
mV
mV
V
V
= 0.8V, ∆V = 1.05V to 2.7V, V
= 3.3V, I
= 3.3V, I
= 10mA
= 10mA
IN
OUT
OUT
IN
BIAS
BIAS
OUT
OUT
= 1.8V, ∆V = 2.05V to 2.7V, V
IN
l
l
Line Regulation to V
2.0
1.0
mV
mV
V
OUT
V
OUT
= 0.8V, ∆V
= 1.8V, ∆V
= 2.2V to 3.6V, V = 1.1V, I
= 10mA
OUT
BIAS
BIAS
BIAS
IN
= 3.25V to 3.6V, V = 2.1V, I
= 10mA
OUT
IN
Load Regulation,
OUT
V
V
V
V
V
= 2.5V, V = 1.05V, V
= 0.8V
= 1.0V
= 1.2V
= 1.5V
= 1.8V
–1.5
–2
–3.0
–5.5
mV
mV
BIAS
BIAS
BIAS
BIAS
BIAS
IN
OUT
OUT
OUT
OUT
OUT
l
l
l
l
∆I
= 10mA to 5A
= 2.5V, V = 1.25V, V
–4.0
–7.5
mV
mV
IN
= 3.3V, V = 1.45V, V
–2
–4.0
–7.5
mV
mV
IN
= 3.3V, V = 1.75V, V
–2.5
–3
–5.0
–9.0
mV
mV
IN
= 3.3V, V = 2.05V, V
–7.0
–13
mV
mV
IN
l
l
Dropout Voltage,
= V
I
I
= 1A, V
= 1V
20
50
35
mV
OUT
OUT
OUT
V
(Note 6)
OUT(NOMINAL)
IN
= 2.5A, V
= 1V
65
85
mV
mV
OUT
l
l
I
= 5A, V
= 1V
85
120
150
mV
mV
OUT
OUT
l
l
SENSE Pin Current
Ground Pin Current,
V
V
= 1.1V, V
BIAS
= 0.8V
SENSE
IN
35
50
65
µA
µA
IN
= 3.3V, V = 2.1V, V
= 1.8V
200
300
400
SENSE
l
l
I
I
= 10mA
= 5A
0.65
0.9
1.1
1.35
1.8
2.3
mA
mA
OUT
OUT
V
= 1.3V, V
= 1V
OUT
IN
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For more information www.linear.com/LT3070
LT3070
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. COUT = 15µF (Note 9), VIN = VOUT + 0.ꢁV (Note 5), VBIAS = 2.5V unless
otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
BIAS Pin Current in Nap Mode
EN = Low
120
200
320
µA
l
l
l
l
l
l
BIAS Pin Current,
IN
I
I
I
I
I
I
= 10mA
= 100mA
= 500mA
= 1A
= 2.5A
= 5A
0.75
1.25
2.0
1.08
1.8
3.0
3.8
5.2
6.9
1.5
2.4
mA
mA
mA
mA
mA
mA
OUT
OUT
OUT
OUT
OUT
OUT
V
= 1.3V, V
= 1V
OUT
4.0
2.6
5.0
3.5
4.5
7.0
10.0
l
l
l
Current Limit (Note 5)
V
V
V
– V
< 0.3V, V
= 1.0V, V
= 1.7V, V
= 3.3V
= 3.3V
= 3.3V
5.1
3.2
1.2
6.4
4.5
2.5
7.7
5.8
4.3
A
A
A
IN
IN
IN
OUT
OUT
OUT
BIAS
BIAS
BIAS
– V
– V
l
Reverse Output Current (Note 8)
V
= 0V, V
= 1.8V
OUT
300
450
µA
IN
l
l
PWRGD V
Threshold
Percentage of V
Percentage of V
, V
OUT(NOMINAL) OUT
OUT(NOMINAL) OUT
Rising
Falling
87
82
90
85
93
88
ꢀ
ꢀ
OUT
, V
l
PWRGD V
I
= 200µA (Fault Condition)
50
150
mV
OL
PWRGD
l
l
V
Undervoltage Lockout
V
V
Rising
Falling
1.1
0.9
1.55
1.4
2.1
1.7
V
V
BIAS
BIAS
BIAS
l
V -V
IN OUT
Servo Voltage by VIOC
250
300
350
mV
l
l
VIOC Output Current
V
V
= V
+ 150mV, Sourcing Out of the Pin
+ 450mV, Sinking Into the Pin
160
170
235
255
310
340
µA
µA
IN
IN
OUT(NOMINAL)
= V
OUT(NOMINAL)
l
l
l
V
V
Input Threshold (Logic-0 State),
O2 O1 O0
Input Falling
0.25
V
IL
, V , V , MARGSEL, MARGTOL
V
V
Input Range (Logic-Z State),
, V , V , MARGSEL, MARGTOL
0.75
V
– 0.9
V
IZ
BIAS
O2 O1 O0
V
V
Input Threshold (Logic-1 State),
, V , V , MARGSEL, MARGTOL
Input Rising
V
– 0.25
V
IH
BIAS
O2 O1 O0
Input Hysteresis (Both Thresholds),
, V , V , MARGSEL, MARGTOL
60
25
25
mV
µA
µA
V
O2 O1 O0
l
l
Input Current High,
, V , V , MARGSEL, MARGTOL
V
V
= V
= 2.5V, Current Flows Into Pin
40
40
IH
BIAS
V
O2 O1 O0
Input Current Low,
, V , V , MARGSEL, MARGTOL
= 0V, V
= 2.5V, Current Flows Out of Pin
BIAS
IL
V
O2 O1 O0
l
l
l
l
EN Pin Threshold
V
OUT
V
OUT
V
OUT
V
OUT
= Off to On, V
= On to Off, V
= Off to On, V
= On to Off, V
= 2.5V
1.4
V
V
V
V
BIAS
BIAS
BIAS
BIAS
= 2.5V
0.9
=2.2V to 3.6V
=2.2V to 3.6V
0.56 • V
BIAS
0.36 • V
BIAS
l
l
EN Pin Logic High Current
EN Pin Logic Low Current
V
V
= V
= 2.5V
BIAS
2.5
4.0
6.5
0.1
µA
µA
EN
EN
= 0V
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For more information www.linear.com/LT3070
LT3070
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. COUT = 15µF (Note 9), VIN = VOUT + 0.ꢁV (Note 5), VBIAS = 2.5V unless
otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Ripple Rejection
V
V
= V
OUT
+ 1.5V , V
=0.5V , f = 120Hz,
P-P RIPPLE
75
dB
BIAS
BIAS
IN
OUT
AVG RIPPLE
– V
= 300mV, I
= 2.5A
OUT
V
Ripple Rejection
V
V
= 2.5V, V
OUT
= 50mV , f = 120Hz,
P-P RIPPLE
OUT
66
10
25
dB
IN
BIAS
IN
RIPPLE
(Notes 3, 4, 5)
– V
= 300mV, I
= 2.5A
Reference Voltage Noise
(REF/BYP Pin)
C
= 10nF, BW = 10Hz to 100kHz
µV
µV
REF/BYP
RMS
RMS
Output Voltage Noise
V
OUT
= 1V, I
= 5A, C
= 10nF, C
= 15µF,
OUT
OUT
REF/BYP
BW = 10Hz to 100kHz
Note 5: The LT3070 incorporates safe operating area protection circuitry.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Current limit decreases as the V -V
voltage increases. Current limit
IN OUT
foldback starts at V – V
Characteristics for a graph of Current Limit vs V – V
> 500mV. See the Typical Performance
IN
OUT
voltage. The
IN
OUT
current limit foldback feature is independent of the thermal shutdown
circuity.
Note 2: The LT3070 regulators are tested and specified under pulse load
conditions such that T ≅ T . The LT3070E is 100ꢀ tested at T = 25°C.
J
A
A
Note 6: Dropout voltage, V , is the minimum input to output voltage
Performance at –40°C and 125°C is assured by design, characterization
and correlation with statistical process controls. The LT3070I is
guaranteed over the –40°C to 125°C operating junction temperature range.
The LT3070MP is 100ꢀ tested and guaranteed over the –55°C to 125°C
operating junction temperature range.
DO
differential at a specified output current. In dropout, the output voltage
eꢁuals V – V
.
DO
IN
Note 7: GND pin current is tested with V = V
+ 300mV and a
OUT(NOMINAL)
IN
current source load. VIOC is a buffered output determined by the value of
as programmed by the V -V pins. VIOC’s output is independent of
V
OUT
Note ꢁ: To maintain proper performance and regulation, the BIAS supply
O2 O0
the margining function.
voltage must be higher than the IN supply voltage. For a given V , the
OUT
BIAS voltage must satisfy the following conditions: 2.2V ≤ V
≤ 3.6V
Note 8: Reverse output current is tested with the IN pins grounded and the
OUT + SENSE pins forced to the rated output voltage. This is measured as
current into the OUT + SENSE pins.
BIAS
and V
≥ (1.25 • V
+ 1V). For V
≤ 0.95V, the minimum BIAS
BIAS
OUT
OUT
voltage is limited to 2.2V.
Note 4: Operating conditions are limited by maximum junction
temperature. The regulated output voltage specification does not apply
for all possible combinations of input voltage and output current. When
operating at maximum output current, limit the input voltage range to
Note 9: Freꢁuency Compensation: The LT3070 must be freꢁuency
compensated at its OUT pins with a minimum C
of 15µF configured
OUT
as a cluster of (15×) 1µF ceramic capacitors or as a graduated cluster
of 10µF/4.7µF/2.2µF ceramic capacitors of the same case size. Linear
Technology only recommends X5R or X7R dielectric capacitors.
V
< V
+ 500mV.
IN
OUT
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For more information www.linear.com/LT3070
LT3070
TYPICAL PERFORMANCE CHARACTERISTICS
Dropout Voltage vs IOUT
Dropout Voltage vs Temperature
Dropout Voltage vs Temperature
100
90
80
70
60
50
40
30
20
10
0
150
120
90
30
25
V
= V
V
I
= V
IN OUT(NOMINAL)
OUT
V
I
= V
OUT(NOMINAL)
OUT
IN
OUT(NOMINAL)
IN
T = 25°C
J
= 1A
= 2.5A
20
15
V
BIAS
= 1.8V
= 3.3V
OUT
V
60
30
0
10
5
V
V
= 0.8V
= 2.5V
OUT
BIAS
V
V
V
= 1.8V, V
= 0.8V, V
= 1.2V, V
= 3.3V
= 2.5V
= 3.3V
V
V
V
= 1.8V, V
= 0.8V, V
= 1.2V, V
= 3.3V
= 2.5V
= 3.3V
OUT
OUT
OUT
BIAS
BIAS
BIAS
OUT
OUT
OUT
BIAS
BIAS
BIAS
0
–75 –50 –25
0
25 50 75 100 125 150 175
0
1
2
3
4
5
–75 –50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
TEMPERATURE (°C)
OUTPUT CURRENT (A)
3070 G03
3070 G01
3070 G02
Output Voltage (0.8V)
vs Temperature
Dropout Voltage vs Temperature
Dropout Voltage vs VBIAS
200
180
160
140
120
100
80
0.808
0.806
0.804
0.802
0.800
0.798
0.796
0.794
0.792
150
120
90
I
= 5A
I
= 10mA
V
I
= V
OUT(NOMINAL)
OUT
OUT
J
LOAD
IN
T = 25°C
= 5A
60
30
0
60
40
V
V
V
= 1.8V, V
= 0.8V, V
= 1.2V, V
= 3.3V
= 2.5V
= 3.3V
OUT = 1.8V
OUT = 1.5V
OUT = 0.8V
OUT
OUT
OUT
BIAS
BIAS
BIAS
20
0
2.2
2.6 2.8 3.0
3.2 3.4 3.6
–75 –50 –25
0
25 50 75 100 125 150 175
2.4
–75 –50 –25
0
25 50 75 100 125 150 175
BIAS VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
3070 G05
3070 G06
3070 G04
Output Voltage (1V)
vs Temperature
Output Voltage (1.2V)
vs Temperature
Output Voltage (1.5V)
vs Temperature
1.010
1.008
1.006
1.004
1.002
1.000
0.998
0.996
0.994
0.992
0.990
1.212
1.208
1.515
1.510
I
= 10mA
I
= 10mA
LOAD
I
= 10mA
LOAD
LOAD
1.204
1.200
1.505
1.500
1.196
1.192
1.188
1.495
1.490
1.485
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3070 G07
3070 G08
3070 G09
3070fb
6
For more information www.linear.com/LT3070
LT3070
TYPICAL PERFORMANCE CHARACTERISTICS
Output Voltage (1.8V)
vs Temperature
REF/BYP Pin Voltage
vs Temperature
GND Pin Current vs IOUT
606
604
1.818
1.814
1.810
1.806
1.802
1.798
1.794
1.790
1.786
1.782
3.0
2.5
I
= 10mA
V
= V
+ 300mV
C
= 0.01µF
REF/BYP
LOAD
IN
OUT
T = 25°C
J
602
600
2.0
1.5
598
596
594
1.0
0.5
0
V
OUT
V
OUT
V
OUT
= 1.8V, V
= 1.2V, V
= 0.8V, V
= 3.3V
= 3.3V
= 2.5V
BIAS
BIAS
BIAS
–75 –50 –25
0
25 50 75 100 125 150 175
0
1
2
3
4
5
–75 –50 –25
0
25 50
175
75 100 125 150
TEMPERATURE (°C)
OUTPUT CURRENT (A)
TEMPERATURE (°C)
3070 G10
3070 G12
3070 G11
BIAS Pin Undervoltage Lockout
Threshold
BIAS Pin Current in Nap Mode
BIAS Pin Current vs IOUT
400
350
300
250
200
150
100
50
10
9
8
7
6
5
4
3
2
1
0
2.5
2.0
1.5
V
J
= V
+ 300mV
OUT
V
V
= 2.5V
IN
BIAS
EN
T = 25°C
= 0V
V
RISING
BIAS
V
BIAS
= 1.8V
= 3.3V
OUT
V
V
V
= 0.8V
OUT
BIAS
V
BIAS
FALLING
= 2.5V
1.0
0.5
0
0
0
1
2
3
4
5
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
OUTPUT CURRENT (A)
TEMPERATURE (°C)
TEMPERATURE (°C)
3070 G14
3070 G15
3070 G13
Enable Pin Threshold and
Hysteresis vs VBIAS
EN Pin Thresholds
PWRGD Threshold Voltage
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.00
0.95
0.90
0.85
0.80
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
T
= –55°C TO 125°C
V
= 2.5V
J
V
V
= 2.5V
= 1V
BIAS
BIAS
OUT
TYPICAL HYSTERESIS = 150mV
V
BIAS
EN PIN RISING
V
RISING
OUT
MAX ENABLE
TYP ENABLE
EN PIN FALLING
V
FALLING
OUT
MIN DISABLE
TYP DISABLE
3
2
2.5
3.5
4
–75 –50 –25
0
25 50 75 100 125 150 175
–50 –25
50
75 100 125 150 175
–75
0
25
BIAS VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
3070 G52
3070 G16
3070 G17
3070fb
7
For more information www.linear.com/LT3070
LT3070
TYPICAL PERFORMANCE CHARACTERISTICS
Logic Input Threshold Voltages
PWRGD VOL vs Temperature
Logic Input Threshold Voltages
Logic Low to Hi-Z State Transitions
Logic Hi-Z to High State Transitions
100
V
I
= 2.5V
= 200µA
BIAS
0.8
0.7
0.6
3.0
2.9
2.8
SEE APPLICATIONS INFORMATION
FOR MORE DETAILS
PWRGD
V
= 3.3V
BIAS
LOGIC Hi-Z TO HIGH THRESHOLD IS
RELATIVE TO V VOLTAGE
80
60
BIAS
SEE APPLICATIONS INFORMATION
FOR MORE DETAILS
INPUT RISING
LOGIC LOW TO Hi-Z
INPUT RISING
LOGIC Hi-Z TO HIGH
40
20
0
INPUT FALLING
0.5
0.4
0.3
2.7
2.6
2.5
LOGIC Hi-Z TO LOW
INPUT FALLING
LOGIC HIGH TO Hi-Z
–75 –50 –25
0
25 50 75 100 125 150
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3070 G50
3070 G18
3070 G19
Logic Pin Input Current,
High State
Logic Pin Input Current,
Low State
EN Pin Logic High Current
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
V
= V
= 2.5V
BIAS
V
= V
= 2.5V
V
V
= 2.5V
BIAS
LOGIC
CURRENT FLOWS OUT OF THE PIN
EN
LOGIC
BIAS
CURRENT FLOWS INTO THE PIN
= 0V
0
0
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3070 G16
3070 G21
3070 G22
SENSE Pin Current
SENSE Pin Current
Current Limit vs Temperature
65
60
55
50
45
40
35
30
25
400
375
350
325
300
275
250
225
200
7.50
7.25
7.00
6.75
6.50
6.25
6.00
5.75
5.50
5.25
5.00
V
V
= 2.5V
= 0.8V
V
V
= 3.3V
= 1.8V
V
– V
= 300mV
OUT(NOMINAL)
BIAS
OUT
BIAS
OUT
IN
CURRENT FLOWS INTO SENSE
CURRENT FLOWS INTO SENSE
V
V
V
= 1.8V, V
= 1.2V, V
= 0.8V, V
= 3.3V
= 3.3V
= 2.5V
OUT
OUT
OUT
BIAS
BIAS
BIAS
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3070 G23
3070 G24
3070 G25
3070fb
8
For more information www.linear.com/LT3070
LT3070
TYPICAL PERFORMANCE CHARACTERISTICS
BIAS Pin Ripple Rejection
IN Pin Ripple Rejection
Current Limit vs VIN – VOUT
100
90
80
70
60
50
40
30
20
10
0
8
7
6
5
4
3
2
1
0
V
V
= 1.3V
= 1V
V
= 3.3V
IN
OUT
OUT
BIAS
T = 25°C
J
I
= 5A
80
C
OUT
= 10µF + 4.7µF + 2.2µF
70
60
50
40
30
20
10
0
C
C
= 117µF
= 16.9µF
OUT
OUT
V
V
V
I
= 1V
OUT
IN
BIAS
OUT
V
V
V
= 1.8V
= 1.2V
= 0.8V
V
V
V
= 2.5V + 500mV
= 2.7V + 500mV
= 3.3V + 500mV
= 1.3V + 50mV RIPPLE
OUT
OUT
OUT
BIAS
BIAS
BIAS
P-P
P-P
P-P
P-P
= 2.5V
= 1A
1.00 1.25
0
0.25 0.50 0.75
1.50 1.75 2.00
10
100
1k
10k 100k
1M
10M
10
100
1k
10k 100k
1M
10M
IN-TO-OUT VOLTAGE DIFFERENTIAL (V)
FREQUENCY (Hz)
FREQUENCY (Hz)
3070 G27
3070 G28
3070 G26
Minimum BIAS Voltage
vs Temperature
IN Pin Ripple Rejection
Minimum BIAS Voltage vs IOUT
80
70
60
50
40
30
20
10
0
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
V
∆V
= V
OUT
V
V
V
V
+ 300mV
OUT(NOMINAL)
IN
V
V
V
= 1.8V
= 1.2V
= 0.8V
I
= 5A
OUT
OUT
OUT
OUT
= –1%, T = 25°C
J
= 1.8V
OUT
= 1.5V
OUT
OUT
OUT
= 1.2V
= 0.8V TO 1V
C
C
= 117µF
= 16.9µF
OUT
OUT
V
V
V
= 1V
OUT
IN
BIAS
= 1.3V + 50mV RIPPLE
P-P
= 2.5V
= 5A
I
OUT
1
2
4
–75 –50 –25
0
25 50 75 100 125 150 175
0
5
3
10
100
1k
10k 100k
1M
10M
TEMPERATURE (°C)
OUTPUT CURRENT (A)
FREQUENCY (Hz)
3070 G29
3070 G30
3070 G31
Minimum BIAS Voltage vs VOUT
Bias Voltage Line Regulation
Load Regulation
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
800
700
600
500
400
300
200
100
0
0
–2
–4
I
= 5A
V
V
V
= 2.2V TO 3.6V
BIAS
OUT
J
T = 25°C
= 1.1V
IN
= 0.8V
OUT
OUT
I
= 10mA
–6
–8
V
V
= V
+ 300mV
OUT(NOMINAL)
IN
= 3.3V
BIAS
∆I
= 100mA TO 5A
OUT
V
V
V
= 0.8V
= 1.2V
= 1.8V
OUT
OUT
OUT
–10
0.7
0.9
1.1
1.3
1.5
1.7
1.9
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
OUTPUT VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
3070 G51
3070 G32
3070 G33
3070fb
9
For more information www.linear.com/LT3070
LT3070
TYPICAL PERFORMANCE CHARACTERISTICS
Input Voltage Line Regulation
Input Voltage Line Regulation
Bias Voltage Line Regulation
400
300
300
250
300
250
V
V
V
I
= 3.3V
V
V
V
I
= 3.25V TO 3.6V
V
V
V
I
= 3.3V
BIAS
IN
OUT
BIAS
IN
OUT
BIAS
IN
OUT
= 2.05V TO 2.7V
= 1.8V
= 2.1V
= 1.05V TO 2.7V
= 0.8V
= 1.8V
= 10mA
= 10mA
= 10mA
OUT
OUT
OUT
200
200
150
200
150
100
0
–100
–200
–300
–400
100
50
0
100
50
0
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3070 G36
3070 G35
3070 G34
Output Voltage Start-Up Time
vs CREF/BYP
Nap Mode Recovery Time vs IOUT
Output Noise Spectral Density
20
18
16
14
12
10
8
400
350
300
250
1.0
0.1
V
V
= 3.3V
OUT(NOM)
EN = LOW TO HIGH
BIAS
IN
V
I
= 2.5V TO 3.3V
V
V
I
C
C
= 2.5V
= 1V
BIAS
OUT
OUT
BIAS
OUT
OUT
= V
+ 300mV
= 10mA
C
= 10µF + 4.7µF + 2.2µF
= 5A
I
= 5A (SET BY A RESISTOR LOAD)
OUT
T = 25°C
J
= 16.9µF
OUT
REF/BYP
T = 25°C
J
SEE APPLICATIONS
INFORMATION FOR
START-UP DETAILS
= 0.01µF
V
= 1.8V,
= 117µF
= 1.2V,
= 117µF
= 0.8V,
= 117µF
OUT
C
V
C
V
C
OUT
OUT
OUT
OUT
OUT
200
150
0.01
0.001
6
100
50
0
4
2
0
1
2
4
0
5
3
0
0.1
0.2
0.3
0.4
0.5
10
100
1k
FREQUENCY (Hz)
10k
100k
OUTPUT CURRENT (A)
REF/BYP CAPACITANCE (µF)
3070 G38
3070 G39
3070 G37
RMS Output Noise
vs Output Current
Input Voltage Line Transient
Response
Output Noise (10Hz to 100kHz)
80
70
60
50
40
30
20
10
0
V
V
C
= V
+ 300mV
OUT(NOMINAL)
IN
= 3.3V
BIAS
OUT
= 16.9µF
V
OUT
1mV/DIV
V
OUT
100µV/DIV
V
IN
50mV/DIV
V
V
V
= 1.8V
= 1.2V
= 0.8V
3070 G42
OUT
OUT
OUT
3070 G41
V
V
I
= 1.3V
= 1V
20µs/DIV
V
I
= 1V
1ms/DIV
IN
OUT
OUT
OUT
OUT
= 5A
= 5A
C
= 16.9µF
OUT
C
= 16.9µF
0.01
0.1
1
10
OUT
OUTPUT CURRENT (A)
3070 G40
3070fb
10
For more information www.linear.com/LT3070
LT3070
TYPICAL PERFORMANCE CHARACTERISTICS
Bias Voltage Line Transient
Response
VIOC Amplifier IN-to-OUT Servo
Voltage
VIOC Amplifier Output Current
vs Temperature
350
340
330
320
310
300
290
280
270
260
250
300
275
V
= 2.5V
BIAS
V
OUT
10mV/DIV
I
SOURCING
VIOC
250
225
I
SINKING
VIOC
V
BIAS
200mV/DIV
200
175
150
3070 G43
V
V
V
I
= 1.3V
20µs/DIV
IN
= 2.5V
= 1V
BIAS
OUT
OUT
= 5A
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
C
= 16.9µF
OUT
TEMPERATURE (°C)
TEMPERATURE (°C)
3070 G44
3070 G45
Transient Load Response
Transient Load Response
V
V
OUT
OUT
50mV/DIV
AC-COUPLED
50mV/DIV
AC-COUPLED
I
OUT
I
OUT
2A/DIV
∆I = 500mA
TO 5A
2A/DIV
∆I = 500mA
TO 5A
3070 G46
3070 G47
V
C
I
= 1V
20µs/DIV
= 10µF + 4.7µF + 2.2µF
/t = 100ns
V
C
I
= 1V
= 117µF
/t
20µs/DIV
= 100ns
OUT
OUT
OUT
OUT
t
t
OUT RISE FALL
OUT RISE FALL
Transient Load Response
Transient Load Response
V
V
OUT
OUT
50mV/DIV
50mV/DIV
AC-COUPLED
AC-COUPLED
I
I
OUT
OUT
2A/DIV
∆I = 500mA
TO 5A
2A/DIV
∆I = 500mA
TO 5A
3070 G48
3070 G49
V
C
= 1V
20µs/DIV
= 10µF + 4.7µF + 2.2µF
/t = 1µs
V
C
= 1V
20µs/DIV
= 1µs
OUT
OUT
OUT
OUT
= 117µF
I
t
I
t
/t
OUT RISE FALL
OUT RISE FALL
3070fb
11
For more information www.linear.com/LT3070
LT3070
PIN FUNCTIONS
VIOC (Pin 1): Voltage for In-to-Out Control. The IC in-
corporates a uniꢁue tracking function to control a buck
regulator powering the LT3070’s input. The VIOC pin is
the output of this tracking function that drives the buck
IN (Pins 5, 6, 7, 8): Input Supply. These pins supply
power to the high current pass transistor. Tie all IN pins
together for proper performance. The LT3070 reꢁuires a
bypass capacitor at IN to maintain stability and low input
impedance over freꢁuency. A 47µF input bypass capacitor
suffices for most battery and power plane impedances.
Minimizinginputtraceinductanceoptimizesperformance.
regulator to maintain the LT3070’s input voltage at V
+
OUT
300mV. This function maximizes efficiency and minimizes
power dissipation. See the Applications Information sec-
tion for more information on proper control of the buck
regulator.
Applications that operate with low V -V
differential
IN OUT
voltagesandthathavelarge,fastloadtransientsmayreꢁuire
much higher input capacitor reꢁuirements to prevent the
input supply from drooping and allowing the regulator to
enter dropout. See the Applications Information section
for more information on input capacitor reꢁuirements.
PWRGD (Pin 2): Power Good. The PWRGD pin is an open-
drain NMOS output that actively pulls low if any one of
these fault modes is detected:
• V
is less than 90ꢀ of V
on the rising
OUT
edge of V
OUT(NOMINAL)
drops below 85ꢀ of V
OUT(NOMINAL)
OUT (Pins 15, 16, 17, 18): Output. These pins supply
power to the load. Tie all OUT pins together for proper
performance. A minimum output capacitance of 15µF is
reꢁuired for stability. LTC recommends low ESR, X5R or
X7R dielectric ceramic capacitors for best performance.
A parallel ceramic capacitor combination of 10µF + 4.7µF
+ 2.2µF or 15 1µF ceramic capacitors in parallel provide
excellent stability and load transient response. Large load
transient applications reꢁuire larger output capacitors to
limit peak voltage transients. See the Applications Infor-
mation section for more information on output capacitor
reꢁuirements.
.
OUT
• V
for more than
OUT
25µs.
• Junction temperature typically exceeds 145°C.
• V is less than its undervoltage lockout threshold.
BIAS
• The OUT-to-IN reverse-current detector activates.
See the Applications Information section for more infor-
mation on PWRGD fault modes.
REF/BYP (Pin ꢁ): Reference Filter. The pin is the output
of the bandgap reference and has an impedance of ap-
proximately 19kΩ. This pin must not be externally loaded.
Bypassing the REF/BYP pin to GND with a 10nF capacitor
decreases output voltage noise and provides a soft-start
function to the reference. LTC recommends the use of a
high ꢁuality, low leakage capacitor. See the Applications
Information section for more information on noise and
output voltage margining considerations.
SENSE (Pin 19): Kelvin Sense for OUT. The SENSE pin is
theinvertinginputtotheerroramplifier.Optimumregulation
is obtained when the SENSE pin is connected to the OUT
pins of the regulator. In critical applications, the resistance
(R )ofPCBtracesbetweentheregulatorandtheloadcause
P
small voltage drops, creating a load regulation error at the
pointofload.ConnectingtheSENSEpinattheloadinstead
of directly to OUT eliminates this voltage error. Figure 1
illustratesthisKelvin-Senseconnectionmethod.Notethat
thevoltagedropacrosstheexternalPCBtracesaddstothe
dropout voltage of the regulator. The SENSE pin input bias
current depends on the selected output voltage. SENSE
GND (Pins 4, 9-14, 20, 26, 29): Ground. The exposed pad
(Pin 29) of the QFN package is an electrical connection to
GND.Toensureproperelectricalandthermalperformance,
solder Pin 29 to the PCB ground and tie to all GND pins
of the package. These GND pins are fused to the internal
die attach paddle and the exposed pad to optimize heat
sinkingandthermalresistancecharacteristics.SeetheAp-
plications Information section for thermal considerations
and calculating junction temperature.
pin input current varies from 50µA typically at V
= 0.8V
OUT
to 300µA typically at V
= 1.8V.
OUT
3070fb
12
For more information www.linear.com/LT3070
LT3070
PIN FUNCTIONS
V , V and V (Pins 2ꢁ, 24, 25): Output Voltage Se-
+
O0 O1
O2
V
BIAS
lect. These three-state pins combine to select a nominal
output voltage from 0.8V to 1.8V in increments of 50mV.
Output voltage is limited to 1.8V maximum by an internal
override of V when V = high. The input logic low
BIAS
EN
IN
SENSE
OUT
R
P
LT3070
V
V
V
O2
O1
O0
PWRGD
O1
O2
+
threshold is less than 250mV referenced to GND and the
LOAD
V
IN
MARGSEL
MARGTOL
VIOC
logic high threshold is greater than V
– 250mV. The
BIAS
range between these two thresholds as set by a window
REF/BYP
GND
comparator defines the logic Hi-Z state. See Table 1 in the
Applications Information section that defines the V , V
O2 O1
R
P
3070 F01
and V settings versus V
.
O0
OUT
BIAS (Pin 27): Bias Supply. This pin supplies current to
the internal control circuitry and the output stage driving
the pass transistor. The LT3070 reꢁuires a minimum 2.2µF
bypass capacitor for stability and proper operation. To
ensure proper operation, the BIAS voltage must satisfy
Figure 1. Kelvin Sense Connection
MARGSEL (Pin 21): Margining Enable and Polarity Selec-
tion. This three-state pin determines both the polarity and
the active state of the margining function. The logic low
threshold is less than 250mV referenced to GND and en-
ablesnegativevoltagemargining.Thelogichigh threshold
the following conditions: 2.2V ≤ V
≤ 3.6V and V
≥
BIAS
BIAS
(1.25 • V
+ 1V). For V
≤ 0.95V, the minimum BIAS
OUT
OUT
voltage is limited to 2.2V.
isgreaterthanV
–250mVandenablespositivevoltage
BIAS
EN (Pin 28): Enable. This pin enables/disables the output
margining. The voltage range between these two logic
thresholds as set by a window comparator defines the
logic Hi-Z state and disables the margining function.
deviceonly.Theinternalreferenceandallsupportfunctions
are active if V
is above its UVLO threshold. Pulling
BIAS
EN low keeps the reference circuit active, but disables
the output pass transistor and puts the LT3070 into a low
power nap mode. The maximum rising EN threshold is
MARGTOL (Pin 22): Margining Tolerance. This three-
state pin selects the absolute value of margining (1ꢀ,
3ꢀ or 5ꢀ) if enabled by the MARGSEL input. The logic
low threshold is less than 250mV referenced to GND and
ratioed to 0.56 ꢀ of V
and the minimum falling ENx
BIAS
threshold is 0.36 ꢀ of V
. Drive the EN pin with either
BIAS
enableseither 1ꢀ change in V
depending onthe state
OUT
a digital logic port or an open-collector NPN or an open-
of the MARGSEL pin. The logic high threshold is greater
than V – 250mV and enables either 5ꢀ change in
drain NMOS terminated with a pull-up resistor to V
.
BIAS
BIAS
The pull-up resistor must be less than 35k to meet the V
IH
V
depending on the state of the MARGSEL pin. The
OUT
condition of the EN pin. If unused, connect EN to BIAS.
voltage range between these two logic thresholds as set
by a window comparator defines the logic Hi-Z state and
enableseither 3ꢀ changeinV
of the MARGSEL pin.
depending onthe state
OUT
3070fb
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LT3070
BLOCK DIAGRAM
UVLO AND
BIAS
27
THERMAL
SHUTDOWN
IN
5-8
+
–
I
SENSE
REF/BYP
+
–
EAMP
BUF
OUT
15-18
LDO CORE
SENSE
19
2
PWRGD
DETECT
–
+
VIOC
GND
V
+ 300mV
1
OUT(NOM)
REF/BYP
600mV
V
3
REF
4,9-14,20,26,29
PROGRAM CONTROL
EN
28
V
V
V
O0
MARGSEL MARGTOL
22
O2
O1
25 24 23 21
3070 BD
LOGIC HIGH STATE
–
+
V
– 0.25V
BIAS
TO INTERNAL ENABLE
SEE ENABLE THRESHOLD
CURVE
EN
100k
LOGIC Hi-Z STATE
TO LOGIC
V
BIAS
HIGH IF IN > V
– 0.25V
– 0.9V
BIAS
V
– 0.9V
+
–
+
–
BIAS
100k
V
, V , VO0
O2 O1
HIGH IF IN < V
BIAS
MARGSEL OR
MARGTOL
AND IN > 0.75V
0.75V
100k
HIGH IF IN < 0.25V
LOGIC LOW STATE
–
+
0.25V
3070fb
14
For more information www.linear.com/LT3070
LT3070
APPLICATIONS INFORMATION
Introduction
This combines the efficiency of a switching regulator
with superior linear regulator response. It also permits
thermal management of the system even with a maximum
5A output load.
Current generation FPGA and ASIC processors place
stringent demands on the power supplies that power the
core,I/Oandtransceiverchannels.Thesemicroprocessors
may cycle load current from near zero to amps in tens of
nanoseconds. Output voltage specifications, especially in
the 1V range, reꢁuire tight tolerances including transient
responseaspartofthereꢁuirement.SomeASICprocessors
reꢁuire only a single output voltage from which the core
and I/O circuitry operate. Some high performance FPGA
processorsreꢁuireseparatepowersupplyvoltagesforthe
processor core, the I/O, and the transceivers. Often, these
supply voltages must be low noise and high bandwidth
to achieve the lowest bit-error rates. These reꢁuirements
mandate the need for very accurate, low noise, high cur-
rent, very high speed regulator circuits that operate at low
input and output voltages.
LT3070 internal protection includes input undervoltage
lockout(UVLO),reverse-currentprotection,precisioncur-
rent limiting with power foldback and thermal shutdown.
The LT3070 regulator is available in a thermally enhanced
28-lead, 4mm × 5mm QFN package.
The LT3070’s architecture drives an internal N-channel
power MOSFET as a source follower. This configuration
permits a user to obtain an extremely low dropout, Ultra-
Fast transient response regulator with excellent high fre-
ꢁuencyPSRRperformance.TheLT3070achievessuperior
regulator bandwidth and transient load performance by
eliminatingexpensivebulktantalumorelectrolyticcapaci-
tors in the most modern and demanding microprocessor
applications. Users realize significant cost savings as all
additional bulk capacitance is removed. The additional
savings of insertion cost, purchasing/inventory cost and
board space are readily apparent. Precision incremental
output voltage control accommodates legacy and future
microprocessor power supply voltages.
The LT3070 is a low voltage, UltraFast transient response
linear regulator. The device supplies up to 5A of output
current with a typical dropout voltage of 85mV. A 0.01µF
referencebypasscapacitordecreasesoutputvoltagenoise
to 25µV
(BW = 10Hz to 100kHz). The LT3070’s high
RMS
bandwidthprovidesUltraFasttransientresponseusinglow
ESR ceramic output capacitors (15µF minimum), saving
bulk capacitance, PCB area and cost.
Output capacitor networks simplify to direct parallel com-
binations of ceramic capacitors. Often, the high freꢁuency
ceramic decoupling capacitors reꢁuired by these various
FPGA and ASIC processors are sufficient to stabilize the
system(seeStabilityandOutputCapacitancesection).This
regulator design provides ample bandwidth and responds
to transient load changes in a few hundred nanoseconds
versus regulators that respond in many microseconds.
TheLT3070’sfeaturespermitstate-of-the-art linearregula-
torperformance.TheLT3070isidealforhighperformance
FPGAs, microprocessors, sensitive communication sup-
plies, and high current logic applications that also operate
over low input and output voltages.
Output voltage for the LT3070 is digitally selectable in
50mV increments over a 0.8V to 1.8V range. A margining
function allows the user to adjust system output voltage
in increments of 1ꢀ, 3ꢀ or 5ꢀ.
The LT3070 also incorporates precision current limiting,
enable/disable control of output voltage and integrated
overvoltage and thermal shutdown protection. The
LT3070’s uniꢁue design combines the benefits of low
dropout voltage, high functional integration, precision
performance and UltraFast transient response, as well as
providingsignificantcostsavingsontheoutputcapacitance
needed in fast load transient applications.
The IC incorporates a uniꢁue tracking function, which if
enabled by the user, controls an upsteam regulator power-
ingtheLT3070’sinput(seeFigure8).Thistrackingfunction
drives the buck regulator to maintain the LT3070’s input
voltage to V
+ 300mV. This input-to-output voltage
OUT
control allows the user to change the regulator output
voltage, and have the switching regulator powering the
LT3070’s input to track to the optimum input voltage with
no component changes.
As lower voltage applications become increasingly preva-
lent with higher freꢁuency switching power supplies, the
LT3070 offers superior regulation and an appreciable
3070fb
15
For more information www.linear.com/LT3070
LT3070
APPLICATIONS INFORMATION
component cost savings. The LT3070 steps to the next
levelofperformanceforthelatestgenerationFPGAs,DSPs
and microprocessors. The simple versatility and benefits
derivedfromthesecircuitsexceedthepowersupplyneeds
of today’s high performance microprocessors.
REF/BYP—Voltage Reference
This pin is the buffered output of the internal bandgap
reference and has an output impedance of ≅19kΩ. The
design includes an internal compensation pole at f =
C
4kHz. A 10nF REF/BYP capacitor to GND creates a low-
pass pole at f = 840Hz. The 10nF capacitor decreases
LP
Programming Output Voltage
reference voltage noise to about 10µV
and soft-starts
RMS
Three tri-level input pins, V , V and V , select the
the reference. The LT3070 only soft-starts the reference
voltage during an initial turn-on seꢁuence. If the EN pin
is toggled low after initial turn-on, the reference remains
powered-up. Therefore, toggling the EN pin from low to
high does not soft-start the reference. Only by turning
the BIAS supply voltage on and off will the reference be
soft-started. Output voltage noise is the RMS sum of the
reference voltage noise in addition to the amplifier noise.
O2 O1
O0
value of output voltage. Table 1 illustrates the 3-bit digital
word to output voltage resulting from setting these pins
high, low or allowing them to float.
These pins may be tied high or low by either pin-strapping
them to V
or driving them with digital ports. Pins that
BIAS
float may either actually float or reꢁuire logic that has
Hi-Z output capability. This allows output voltage to be
dynamically changed if necessary.
TheREF/BYPpinmustnotbeDCloadedbyanythingexcept
for applications that parallel other LT3070 regulators for
higher output currents. Consult the Applications Section
on Paralleling for further details.
Output voltage is selectable from a minimum of 0.8V to
a maximum of 1.8V in increments of 50mV. The MSB,
V , sets the pedestal voltage, and the LSB’s, V and
O2
O0
O1
V
increment V
.
OUT
Output Voltage Margining
Output voltage is limited to 1.8V maximum by an internal
override of V (default to low) when V = high.
Twotri-levelinputpins,MARGSEL(polarity)andMARGTOL
(scale), select the polarity and amount of output voltage
margining. Margining is programmable in increments of
1ꢀ, 3ꢀ and 5ꢀ. Margining is internally implemented
as a scaling of the reference voltage.
O1
O2
Table 1: VO2 to VO0 Settings vs Output Voltage
V
V
V
V
V
V
V
V
OUT(NOM)
O2
O1
O0
OUT(NOM)
O2
O1
O0
0
0
0
0
0
0
0
0
0
Z
Z
0
0
0
Z
Z
Z
1
1
1
0
0
0
Z
1
0
Z
1
0
Z
1
0
Z
0.80V
Z
Z
Z
Z
Z
Z
Z
1
1
1
0
Z
Z
Z
1
1
1
X
X
X
1
0
Z
1
0
Z
1
0
Z
1
1.35V
0.85V
0.90V
0.95V
1.00V
1.05V
1.10V
1.15V
1.20V
1.25V
1.30V
1.40V
1.45V
1.50V
1.55V
1.60V
1.65V
1.70V
1.75V
1.80V
Table 2 illustrates the 2-bit digital word to output voltage
margining resulting from setting these pins high, low or
allowing them to float.
These pins may be set high or low by either pin-strapping
them to V
or driving them with digital ports. Pins that
BIAS
float may either actually float or reꢁuire logic that has
“Hi-Z” output capability. This allows output voltage to be
dynamically margined if necessary.
TheMARGSELpindeterminesboththepolarityandtheac-
tivestateofthemarginingfunction.Thelogiclow threshold
islessthan250mVreferencedtoGNDandenablesnegative
voltagemargining.Thelogichighthresholdisgreaterthan
X = Don’t Care, 0 = Low, Z = Float, 1 = High
The input logic low threshold is less than 250mV refer-
enced to GND and the logic high threshold is greater than
V
– 250mV and enables positive voltage margining.
BIAS
V
– 250mV. The range between these two thresholds
The voltage range between these two logic thresholds as
set by a window comparator defines the logic Hi-Z state
and disables the margining function.
3070fb
BIAS
as set by a window comparator defines the logic Hi-Z
state.
16
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LT3070
APPLICATIONS INFORMATION
The MARGTOL pin selects the absolute value of margin-
ing (1ꢀ, 3ꢀ or 5ꢀ) if enabled by the MARGSEL input.
The logic low threshold is less than 250mV referenced to
typical BIAS pin UVLO threshold is 1.55V on the rising
edgeofV
.TheUVLOcircuitincorporatesabout150mV
BIAS
of hysteresis on the falling edge of V
.
BIAS
GND and enables either 1ꢀ change in V
depending
OUT
High Efficiency Linear Regulator—Input-to-Output
Voltage Control
on the state of the MARGSEL pin. The logic high threshold
is greater than V – 250mV and enables either 5ꢀ
BIAS
change in V
depending on the state of the MARGSEL
OUT
TheVIOC(voltageinput-to-outputcontrol)pinisafunction
tocontrolaswitchingregulatorandfacilitateadesignsolu-
tionthatmaximizessystemefficiencyathighloadcurrents
and still provides low dropout voltage performance.
pin. The voltage range between these two logic thresholds
as set by a window comparator defines the logic Hi-Z state
and enables either 3ꢀ change in V
state of the MARGSEL pin.
depending on the
OUT
The VIOC pin is the output of an integrated transcon-
ductance amplifier that sources and sinks about 250µA
of current. It typically regulates the output of most LTC®
switching regulators or LTM® power modules, by sinking
currentfromtheITHcompensationnode.TheVIOCfunction
controls a buck regulator powering the LT3070’s input by
Table 2: Programming Margining
MARGSEL
MARGTOL
ꢀ OF V
OUT(NOM)
0
0
0
Z
Z
Z
1
1
1
0
Z
1
0
Z
1
0
Z
1
–1
–3
–5
0
maintaining the LT3070’s input voltage to V
+ 300mV.
OUT
0
This 300mV V -V
differential voltage is chosen to
IN OUT
0
provide fast transient response and good high freꢁuency
PSRRwhileminimizingpowerdissipationandmaximizing
efficiency. For example, 1.5V to 1.2V conversion and 1.3V
to 1V conversion yield 1.5W maximum power dissipation
at 5A full output current.
1
3
5
Enable Function—Turning On and Off
Figure 2 depicts that the switcher’s feedback resistor net-
worksetsthemaximumswitchingregulatoroutputvoltage
ifthelinearregulatorisdisabled.However,oncetheLT3070
isenabled,theVIOCfeedbackloopdecreasestheswitching
The EN pin enables/disables the output device only. The
LT3070 reference and all support functions remain active
if V
is above its UVLO threshold. Pulling the EN pin
BIAS
low puts the LT3070 into nap mode. In nap mode, the
reference circuit is active, but the output is disabled and
ꢁuiescent current decreases.
regulator output voltage back to V
+ 300mV.
OUT
Using the VIOC function creates a feedback loop between
the LT3070 and the switching regulator. As such, the feed-
back loop must be freꢁuency compensated for stability.
Fortunately,theconnectionofVIOCtomanyLTCswitching
regulator ITH pins represents a high impedance charac-
teristic which is the optimum circuit node to freꢁuency
compensate the feedback loop. Figure 2 illustrates the
typical freꢁuency compensation network used at the VIOC
node to GND.
Drive the EN pin with either a digital logic port or an open-
collector NPN or an open-drain NMOS terminated with
a pull-up resistor to V
. The pull-up resistor must be
IH
BIAS
less than 35k to meet the V condition of the EN pin. If
unused, connect EN to BIAS.
Input Undervoltage Lockout on BIAS Pin
An internal undervoltage lockout (UVLO) comparator
The VIOC amplifier characteristics are:
monitors the BIAS supply voltage. If V
drops below
BIAS
g = 3.2mS, I
= 250µA, BW = 10MHz.
the UVLO threshold, all functions shut down, the pass
m
OUT
transistor is gated off and output current falls to zero. The
IftheVIOCfunctionisnotused,terminatetheVIOCpintoGND
with a small capacitor (1000pF) to prevent oscillations.
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17
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LT3070
APPLICATIONS INFORMATION
LT3070
IN
OUT
LOAD
SWITCHING REGULATOR
REF
+
–
–
+
PWM
FB
VIOC
V
+
OUT
V
300mV
REF
REFERENCE
I
TH
3070 F02
Figure 2. VIOC Control Block Diagram
PWRGD—Power Good
Low ESR, X5R or X7R ceramic chip capacitors are the
LTC recommended choice for stabilizing the LT3070. Ad-
ditional bulk capacitors distributed beyond the immediate
decouplingcapacitorsareacceptableastheirparasiticESL
and ESR, combined with the distributed PCB inductance
isolatesthemfromtheprimarycompensationpoleprovided
by the local surface mount ceramic capacitors.
PWRGD pin is an open-drain NMOS digital output that
actively pulls low if any one of these fault modes is de-
tected:
• V
is less than 90ꢀ of V
on the rising
OUT
edge of V
OUT(NOMINAL)
drops below 85ꢀ of V
OUT(NOMINAL)
.
OUT
• V
for more than
The LT3070 reꢁuires a minimum output capacitance of
15µFforstability.LTCstronglyrecommendsthattheoutput
capacitor network consist of several low value ceramic
capacitors in parallel.
OUT
25µs.
• V
is less than its undervoltage lockout threshold.
BIAS
• The OUT-to-IN reverse-current detector activates.
• Junction temperature exceeds 145°C typically.*
Why Do Multiple, Small-Value Output Capacitors
Connected in Parallel Work Better?
*The junction temperature detector is an early warning
indicator that trips approximately 20°C before thermal
shutdown engages.
The LT3070’s unity-gain bandwidth with C
of 15µF is
OUT
about1MHzatitsfull-loadcurrentof5A. Surfacemounted
MLCC capacitors have a self-resonance freꢁuency of
f =1/(2π√LC),whichmustbepushedtoafreꢁuencyhigher
R
Stability and Output Capacitance
than the regulator bandwidth. Standard MLCC capacitors
are acceptable. To keep the resonant freꢁuency greater
than 1MHz, the product 1/(2π√LC) must be greater than
1MHz. At this bandwidth, PCB vias can add significant
inductance, thus the fundamental decoupling capacitors
must be mounted on the same plane as the LT3070.
The LT3070’s feedback loop reꢁuires an output capacitor
for stability. Choose C
carefully and mount it in close
OUT
proximitytotheLT3070’sOUTandGNDpins. Includewide
routing planes for OUT and GND to minimize inductance.
If possible, mount the regulator immediately adjacent to
the application load to minimize distributed inductance
for optimal load transient performance. Point-of-Load
applications present the best case layout scenario for
extracting full LT3070 performance.
Typical0603or0805case-sizecapacitorshaveanESLof
~800pHandPCBmountingcancontributeupto~200pH.
Thus, it becomes necessary to reduce the parasitic
3070fb
18
For more information www.linear.com/LT3070
LT3070
APPLICATIONS INFORMATION
inductance by using a parallel capacitor combination.
applications, this total value of capacitance may be close
to the LT3070’s minimum 15µF capacitance reꢁuirement.
Thismayreducethereꢁuiredvalueofcapacitancedirectly
at the LT3070’s output. Multiple low value capacitors in
parallel present a favorable freꢁuency characteristic that
pushes many of the parasitic poles/zeroes beyond the
LT3070’s unity-gain crossover freꢁuency. This techniꢁue
illustrates the method that extracts the full bandwidth
performance of the LT3070.
A suitable methodology must control this paralleling as
capacitorswiththesameself-resonantfreꢁuency, f , will
R
form a tank circuit that can induce ringing of their own
accord.SmallamountsofESR(5mΩto20mΩ)havesome
benefit in dampening the resonant loop, but higher ESRs
degrade the capacitor response to transient load steps
with rise/fall times less than 1µs. The most area efficient
parallel capacitor combination is a graduated 4/2/1 scale
of f of the same case size. Under these conditions, the
R
Giveadditionalconsiderationtotheuseofceramiccapaci-
tors.Ceramiccapacitorsaremanufacturedwithavarietyof
dielectrics,eachwithdifferentbehavioracrosstemperature
and applied voltage. The most common dielectrics used
arespecifiedwithEIAtemperaturecharacteristiccodesof
Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics are
good for providing high capacitances in a small package,
but they tend to have strong voltage and temperature
coefficients as shown in Figures 4 and 5. When used with
a 5V regulator, a 16V 10µF Y5V capacitor can exhibit an
effective value as low as 1µF to 2µF for the DC bias voltage
appliedandovertheoperatingtemperaturerange.TheX5R
and X7R dielectrics result in more stable characteristics
and are more suitable for use as the output capacitor.
The X7R type has better stability across temperature,
while the X5R is less expensive and is available in higher
values. Care still must be exercised when using X5R and
X7R capacitors; the X5R and X7R codes only specify
operating temperature range and maximum capacitance
change over temperature. Capacitance change due to
DC bias with X5R and X7R capacitors is better than Y5V
and Z5U capacitors, but can still be significant enough to
drop capacitor values below appropriate levels. Capacitor
DC bias characteristics tend to improve as component
case size increases, but expected capacitance at operat-
ing voltage should be verified. Voltage and temperature
coefficients are not the only sources of problems. Some
ceramiccapacitorshaveapiezoelectricresponse.Apiezo-
electric device generates voltage across its terminals due
to mechanical stress, similar to the way a piezoelectric
microphone works. For a ceramic capacitor the stress
can be induced by vibrations in the system or thermal
transients.
individual ESLs are relatively uniform, and the resonance
peaks are deconstructively spread beyond the regulator
bandwidth. The recommended parallel combination that
approximates 15µF is 10µF + 4.7µF + 2.2µF. Capacitors
with case sizes larger than 0805 have higher ESL and
lower ESR (<5mΩ). Therefore, more capacitors with
smaller values (<10µF) must be chosen. Users should
consider new generation, low inductance capacitors to
push out f and maximize stability. Refer to the surface
R
mount ceramic capacitor manufacturer’s data sheets for
capacitor specifications. Figure 3 illustrates an optimum
PCB layout for the parallel output capacitor combination,
but also illustrates the GND connection between the IN
capacitor and the OUT capacitors to minimize the AC
GND loop for fast load transients. This tight bypassing
connection minimizes EMI and optimizes bypassing.
Many of the applications in which the LT3070 excels,
such as FPGA, ASIC processor or DSP supplies, typically
reꢁuireahighfreꢁuencydecouplingcapacitornetworkfor
thedevicebeingpowered.Thisnetworkgenerallyconsists
of many low value ceramic capacitors in parallel. In some
LT3070
SENSE
IN OUT
GND
Lo-Z
INPUT
LOAD PLANE
2.2µF
4.7µF
10µF
47µF
3070 F03
Figure ꢁ. Example PCB Layout
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LT3070
APPLICATIONS INFORMATION
20
the LT3070 back to the power supply ground), large input
capacitors are reꢁuired to avoid an unstable application.
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
0
X5R
This is due to the inductance of the wire forming an LC
tank circuit with the input capacitor and not a result of the
LT3070 being unstable. The self inductance, or isolated
inductance, of a wire is directly proportional to its length.
However, the diameter of a wire does not have a major
influence on its self inductance. For example, one inch of
18-AWG, 0.04 inch diameter wire has 28nH of self induc-
tance. The self inductance of a 2-AWG isolated wire with
a diameter of 0.26 inch is about half the inductance of a
18-AWG wire. The overall self inductance of a wire can
be reduced in two ways. One is to divide the current flow-
ing towards the LT3070 between two parallel conductors
which flows in the same direction in each. In this case,
the farther the wires are placed apart from each other, the
more inductance will be reduced, up to a 50ꢀ reduction
when placed a few inches apart. Splitting the wires basi-
cally connects two eꢁual inductors in parallel. However,
when placed in close proximity from each other, mutual
inductance is added to the overall self inductance of the
wires. Themosteffectivewaytoreduceoverallinductance
is to place the forward and return-current conductors (the
wire for the input and the wire for the return ground) in
very close proximity. Two 18-AWG wires separated by
0.05 inch reduce the overall self inductance to about one-
fourth of a single isolated wire. If the LT3070 is powered
by a battery mounted in close proximity with ground and
power planes on the same circuit board, a 47µF input
capacitor is sufficient for stability. However, if the LT3070
is powered by a distant supply, use a low ESR, large value
input capacitor on the order of 330µF. As power supply
output impedance varies, the minimum input capacitance
needed for application stability also varies.
–20
–40
–60
Y5V
–80
–100
10 12
DC BIAS VOLTAGE (V)
0
2
4
6
8
14 16
3070 F04
Figure 4. Ceramic Capacitor DC Bias Characteristics
40
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
20
X5R
0
–20
Y5V
–40
–60
–80
–100
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
3070 F05
Figure 5. Ceramic Capacitor Temperature Characteristics
Stability and Input Capacitance
The LT3070 is stable with a minimum capacitance of
47µF connected to its IN pins. Use low ESR capacitors to
minimize instantaneous voltage drops under large load
transient conditions. Large V droops during large load
IN
transients may cause the regulator to enter dropout with
corresponding degradation in load transient response.
Increased values of input and output capacitance may be
necessary depending on an application’s reꢁuirements.
Sufficient input capacitance is critical as the circuit is
intentionally operated close to dropout to minimize power.
Ideally, the output impedance of the supply that powers
IN should be less than 10mΩ to support a 5A load with
large transients.
Bias Pin Capacitance Requirements
The BIAS pin supplies current to most of the internal
control circuitry and the output stage driving the pass
transistor. The LT3070 reꢁuires a minimum 2.2µF by-
pass capacitor for stability and proper operation. To
ensure proper operation, the BIAS voltage must sat-
isfy the following conditions: 2.2V ≤ V
≤ 3.6V and
BIAS
V
≥ (1.25 • V
+ 1V). For V ≤ 0.95V, the
In cases where wire is used to connect a power supply
to the input of the LT3070 (and also from the ground of
BIAS
OUT
OUT
minimum BIAS voltage is limited to 2.2V.
3070fb
20
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LT3070
APPLICATIONS INFORMATION
Load Regulation
values of input-to-output voltage up to the absolute maxi-
mum voltage rating. See the Current Limit vs V curve in
IN
The LT3070 provides a Kelvin sense pin for V , allowing
OUT
the Typical Performance Characteristics.
the application to correct for parasitic package and PCB
I-R drops. However, LTC recommends that the SENSE pin
terminate in close proximity to the LT3070’s OUT pins.
Thisminimizesparasiticinductanceandoptimizesregula-
tion. The LT3070 handles moderate levels of output line
Duringstart-up,aftertheBIASvoltagehascleareditsUVLO
threshold and V is increasing, output voltage increases
IN
at the rate of current limit charging C
.
OUT
With a high input voltage, a problem can occur where the
removal of an output short will not allow the output volt-
agetorecover. Otherregulatorswithcurrentlimitfoldback
also exhibit this phenomenon, so it is not uniꢁue to the
LT3070. The load line for such a load may intersect the
output current curve at two points: normal operation and
the SOA restricted load current settings. A common situ-
ation is immediately after the removal of a short circuit,
but with a static load ≥ 1A. In this situation, removal of the
impedance, but excessive impedance between V
OUT
and adversely affects stability.
and
OUT
C
causes excessive phase shift in the feedback loop
Figure 1 in the Pin Functions section illustrates the Kelvin-
Sense connection method that eliminates voltage drops
duetoPCBtraceresistance.However,notethatthevoltage
drop across the external PCB traces adds to the dropout
voltage of the regulator. The SENSE pin input bias current
depends on the selected output voltage. SENSE pin input
load or reduction of I
to <1A will clear this condition
OUT
currentvariesfrom50µAtypicallyatV
=0.8Vto300µA
and allow V
to return to normal regulation.
OUT
OUT
typically at V
= 1.8V.
OUT
Reverse Voltage
The LT3070 incorporates a circuit that detects if V de-
Short-Circuit and Overload Recovery
IN
Like many IC power regulators, the LT3070 has safe op-
erating area (SOA) protection. The safe area protection
decreasescurrentlimitasinput-to-outputvoltageincreases
and keeps the power transistor inside a safe operating
region for all values of input-to-output voltage up to the
creases below V . This reverse-voltage detector has
OUT
a typical threshold of about (V – V ) = –6mV. If the
IN
OUT
threshold is exceeded, this detector circuit turns off the
drivetotheinternalNMOSpasstransistor, therebyturning
off the output. The output pulls low with the load current
discharging the output capacitance. This circuit’s intent
is to limit and prevent back-feed current from OUT to IN
if the input voltage collapses due to a fault or overload
condition.
absolute maximum voltage rating. V
must be above
BIAS
the UVLO threshold for any function. The LT3070 has a
precision current limit specified at 20ꢀ that is active if
V
BIAS
is above UVLO.
Under conditions of maximum I
IN OUT
and maximum
LOAD
Thermal Considerations
V -V
the device’s power dissipation peaks at about
The LT3070’s maximum rated junction temperature of
125°C limits its power handling capability and is domi-
nated by the output current multiplied by the input/output
voltage differential:
3W. If ambient temperature is high enough, die junction
temperature will exceed the 125°C maximum operating
temperature. If this occurs, the LT3070 relies on two
additional thermal safety features. At about 145°C, the
PWRGD output pulls low providing an early warning of an
impendingthermalshutdowncondition.At165°Ctypically,
the LT3070’s thermal shutdown engages and the output is
shut down until the IC temperature falls below the thermal
hysteresislimit.TheSOAprotectiondecreasescurrentlimit
as the IN-to-OUT voltage increases and keeps the power
dissipation at safe levels for all values of input-to-output
voltage. The LT3070 provides some output current at all
I
• (V – V
)
OUT
OUT
IN
The LT3070’s internal power and thermal limiting circuitry
protect it under overload conditions. For continuous nor-
mal load conditions, do not exceed the maximum junction
temperature of 125°C. Give careful consideration to all
sources of thermal resistance from junction to ambient.
Thisincludesjunctiontocase, case-to-heatsinkinterface,
3070fb
21
For more information www.linear.com/LT3070
LT3070
APPLICATIONS INFORMATION
heat sink resistance or circuit board to ambient as the
applicationdictates.Also,consideradditionalheatsources
mountedinproximitytotheLT3070.TheLT3070isasurface
mount device and as such, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Surface mount heat sinks and
plated through-holes can also be used to spread the heat
generated by power devices. Junction-to-case thermal
resistance is specified from the IC junction to the bottom
of the case directly below the die. This is the lowest resis-
tance path for heat flow. Proper mounting is reꢁuired to
ensure the best possible thermal flow from this area of the
packagetotheheatsinkingmaterial.Notethattheexposed
pad is electrically connected to GND.
where:
I
= 4A
OUT(MAX)
V
= 1.26V
IN(MAX)
I
I
at (I
= 4A, V
= 2.5V) = 6.91mA
= 2.5V) = 0.87mA
BIAS
GND
OUT
OUT
BIAS
at (I
= 4A, V
BIAS
thus:
P = 4A(1.26V – 0.9V) + (6.91mA – 0.87mA)0.9V +
0.87mA(2.5V) = 1.448W
With the QFN package soldered to maximum copper
area, the thermal resistance is 30°C/W. So the junction
temperature rise above ambient eꢁuals:
Table 3 lists thermal resistance as a function of copper
area in a fixed board size. All measurements were taken
in still air on a 4-layer FR-4 board with 1 oz solid internal
planes and 2 oz top/bottom external trace planes with a
totalboardthicknessof1.6mm.PCBlayers,copperweight,
board layout and thermal vias affect the resultant thermal
resistance. For further information on thermal resistance
and high thermal conductivity test boards, refer to JEDEC
standard JESD51, notably JESD51-12 and JESD51-7.
Achieving low thermal resistance necessitates attention
to detail and careful PCB layout.
1.448W at 30°C/W = 43.44°C
The maximum junction temperature eꢁuals the maximum
ambienttemperatureplusthemaximumjunctiontempera-
ture rise above ambient or:
T
JMAX
= 50°C + 43.44°C = 93.44°C
Applications that cannot support extensive PCB space
for heat sinking the LT3070 reꢁuire a derating of output
current or increased airflow.
Paralleling Devices for Higher I
OUT
Table ꢁ, UFD Plastic Package, 28-Lead QFN
MultipleLT3070smaybeparalleledtoobtainhigheroutput
current.Thisparallelingconceptborrowsfromthescheme
employed by the LT3080.
COPPER AREA
THERMAL RESISTANCE
TOPSIDE* BACK SIDE BOARD AREA (JUNCTION-TO-AMBIENT)
2
2
2
2
2
2
2
2
2
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
30°C/W
32°C/W
33°C/W
35°C/W
To accomplish this paralleling, tie the REF/BYP pins of
the paralleled regulators together. This effectively gives
an averaged value of multiple 600mV reference voltage
sources. Tie the OUT pins of the paralleled regulators to
the common load plane through a small piece of PC trace
ballast or an actual surface mount sense resistor beyond
the primary output capacitors of each regulator. The re-
ꢁuired ballast is dependent upon the application output
voltage and peak load current. The recommended ballast
is that value which contributes 1ꢀ to load regulation. For
example, two LT3070 regulators configured to output 1V,
sharing a 10A load reꢁuire 2mΩ of ballast at each output.
The Kelvin SENSE pins connect to the regulator side of
the ballast resistors to keep the individual control loops
from conflicting with each other (see Figures 8 and 9).
3070fb
2
1000mm
2
225mm
100mm
2
*Device is mounted on topside
Calculating Junction Temperature
Example: Given an output voltage of 0.9V, an input voltage
rangeof1.2V 5ꢀ,aBIASvoltageof2.5V,amaximumout-
put current of 4A and a maximum ambient temperature of
50°C, what will the maximum junction temperature be?
The power dissipated by the device eꢁuals:
I
• (V
BIAS
– V ) + (I
– I ) • V
OUT(MAX)
IN(MAX)
OUT
BIAS GND OUT
+ I
• V
GND
22
For more information www.linear.com/LT3070
LT3070
APPLICATIONS INFORMATION
Keep this ballast trace area free of solder to maintain a
controlled resistance.
noise reduction of reference noise. The LT3070 deviates
from the traditional voltage reference by generating a
low voltage V
from a reference current into an inter-
REF
Table 4 shows a simple guideline for PCB trace resistance
as a function of weight and trace width.
nal resistor ≅19k. This intermediate impedance node
(REF/BYP)facilitatesexternalfilteringdirectly.A10nFfilter
Table 4. PC Board Trace Resistance
capacitor minimizes reference noise to 10µV
at the
RMS
WEIGHT (Oz)
100 MIL WIDTH*
200 MIL WIDTH*
600mV REF/BYP pin, eꢁuivalently a 17µV contribution to
output noise at V = 1V. See the Typical Performance
1
2
5.43
2.71
2.71
1.36
OUT
Characteristics for Noise vs Output Voltage performance
as a function of C
.
*Trace resistance is measured in milliohms/in
REF/BYP
This approach also accommodates reference sharing
between LT3070 regulators that are hooked up in cur-
rent sharing applications. The REF/BYP filter capacitor
delays the initial power-up time by a factor of the RC time
Quieting the Noise
The LT3070 offers numerous noise performance advan-
tages. Each LDO has several sources of noise. An LDO’s
most critical noise source is the reference, followed by
the LDO error amplifier. Traditional low noise regulators
bufferthevoltagereferenceouttoanexternalpin(usually
through a large value resistor) to allow for bypassing and
constant. V remains active in nap mode, thus start-up
REF
time is significantly reduced and well controlled coming
out of nap mode (EN:LO↑HI).
50k
V
BIAS
PWRGD
2.5V TO 3.6V
2.2µF
BIAS
V
IN
IN
PWRGD
SENSE
1.5V
330µF
EN
V
1.2V
5A
OUT
LT3070
OUT
V
O0
V
O1
V
O2
2.2µF*
4.7µF*
10µF*
NC
NC
MARGSEL
MARGTOL
VIOC
*X5R OR X7R CAPACITORS
REF/BYP
GND
1nF
0.01µF
3070 F06
Figure 6. 1.5V to 1.2V Linear Regulator
3070fb
23
For more information www.linear.com/LT3070
LT3070
APPLICATIONS INFORMATION
V
BIAS
3.3V
47µF
6.3V
×3
1Ω
50k
SV
IN
PWRGD
2.2µF*
NC
2.2µF
0.1µF
BIAS
PGOOD RUN PV
PV
SV TRACK
IN
IN
IN
0.2µH
EN
IN
PWRGD
SENSE
OUT
1.3V/5A
SGND
SW
SW
SW
SW
V
1V
5A
OUT
47µF
PV
IN
PV
IN
LT3070
NC
NC
V
O0
V
O1
V
O2
4.7µF*
10µF*
20k
10k
PLLLPF
*X5R OR X7R CAPACITORS
I
TH
NC
NC
MARGTOL
MARGSEL
LTC3415EUHF
MGN
BSEL
100µF
6.3V
×2
NC
NC
NC
CLKOUT
PHMODE
CLKIN
VIOC
REF/BYP
GND
V
FB
SV
IN
2k
4.7nF
PGND
0.01µF
1nF
I
THM
SGND
PGND PGND
MODE
3070 F07
PGND PGND PGND PGND
NOTE: LTC3415 SWITCHER, 2MHz INTERNAL OSCILLATOR
LTC3415 AND LT3070 ON SAME PCB POWER PLANE
Figure 7. Regulator with VIOC Buck Control
V
BIAS
3.3V
50k
47µF
6.3V
×3
PWRGD
1Ω
2.2µF
SV
IN
NC
PGOOD RUN PV
0.1µF
BIAS
PV
SV TRACK
IN
IN
IN
0.2µH
EN
IN
PWRGD
SENSE
OUT
1.3V/7A
SGND
SW
SW
SW
SW
V
OUT
47µF
1V
PV
PV
IN
IN
LT3070
3.5A
2.2µF*
4.7µF*
10µF*
NC
NC
V
O0
V
O1
V
O2
R
TRACE
PLLLPF
3mΩ
*X5R OR X7R CAPACITORS
CONTROLLED
I
TH
NC
NC
MARGTOL
MARGSEL
MGN
BSEL
P.O.L. 1
LTC3415EUHF
NC
NC
CLKOUT
PHMODE
VIOC
REF/BYP
GND
17.5k
1%
POWER
PLANE
1V/8A
1nF
0.01µF
V
FB
15k
1%
100µF
6.3V
×2
P.O.L. 2
PGND
2.2µF
NC
CLKIN
MODE
I
THM
SGND
PGND PGND
R
TRACE
3mΩ
BIAS
PGND PGND PGND PGND
CONTROLLED
EN
IN
PWRGD
SENSE
OUT
V
OUT
47µF
1V
NOTE: LTC3415 SWITCHER, 2MHz INTERNAL OSCILLATOR
LTC3415 AND LT3070 ×2 ON SAME PCB POWER PLANE
LT3070
3.5A
2.2µF*
4.7µF*
10µF*
NC
NC
V
V
V
O0
O1
O2
*X5R OR X7R CAPACITORS
NC
NC
MARGTOL
MARGSEL
VIOC
REF/BYP
1nF
GND
0.01µF
3070 F08
Figure 8. 1V, 7A Point-of-Load Current Sharing Regulators
3070fb
24
For more information www.linear.com/LT3070
LT3070
TYPICAL APPLICATIONS
50k
V
IN
3.3V
PWRGD
2.2µF
BIAS
EN
IN
PWRGD
SENSE
OUT
V
1V
4A
OUT
47µF
NC
NC
V
O0
V
O1
V
O2
LT3070
2.2µF*
4.7µF*
10µF*
R
TRACE
2.5mΩ
CONTROLLED
NC
NC
MARGTOL
MARGSEL
VIOC
*X5R OR X7R CAPACITORS
0.01µF
P.O.L. 1
REF/BYP
POWER
PLANE
1V/7A
1nF
GND
V
IN
3.3V
V
IN
3.3V
P.O.L. 2
2.2µF
NC
NC
NC
NC
NC
R
TRACE
BIAS
2.5mΩ
EN
IN
V
PWRGD
SENSE
OUT
SW1 CLKIN1 CLKOUT1 CLKIN2 CLKOUT2
CONTROLLED
V
1.3V/8A
BUCK1
V
V
OUT1
MGN1
FB1
IN1
SV
V
1V
4A
OUT
100µF
6.3V
X5R
47µF
10µF
NC
NC
IN1
O0
20k
LT3070
RUN1
2.2µF*
10µF*
10µF*
10µF*
4.7µF*
V
V
O1
PLLLPF1
MODE1
PHMODE1
TRACK1
ITH1
O2
ITHM1
BSEL1
PGOOD1
10k
2k
4.7nF
NC
NC
MARGTOL
MARGSEL
VIOC
*X5R OR X7R CAPACITORS
0.01µF
NC
NC
REF/BYP
GND
LTM4616
V
2.1V/8A
BUCK2
1nF
V
V
OUT2
MGN2
FB2
IN2
SV
100µF
6.3V
X5R
10µF
IN2
RUN2
V
IN
3.3V
PLLLPF2
MODE2
PHMODE2
TRACK2
ITH2
2.2µF
ITHM2
BSEL2
PGOOD2
BIAS
NC
NC
EN
IN
PWRGD
SENSE
OUT
V
1.8V
5A
OUT
SW2 SGND1 GND1 SGND2 GND2
47µF
V
O0
V
O1
V
O2
LT3070
2.2µF*
4.7µF*
NC
NC
NC
NC
MARGTOL
MARGSEL
VIOC
*X5R OR X7R CAPACITORS
0.01µF
20k
NOTE: THE TWO LTM4616 MODULE CHANNELS ARE
INDEPENDENTLY CONTROLLED BY THE VIOC
CONTROLS FROM THE LINEAR REGULATORS
REF/BYP
GND
1nF
2k
4.7nF
10k
V
IN
3.3V
2.2µF
BIAS
EN
IN
PWRGD
SENSE
OUT
V
1.5V
3A
OUT
47µF
V
O0
V
O1
V
O2
LT3070
2.2µF*
4.7µF*
NC
NC
NC
NC
MARGTOL
MARGSEL
VIOC
*X5R OR X7R CAPACITORS
REF/BYP
1nF
GND
0.01µF
3070 F09
Figure 9. Triple Output Supply Providing 1V, 8A and 1.8V, 5A and 1.5V, ꢁA
3070fb
25
For more information www.linear.com/LT3070
LT3070
PACKAGE DESCRIPTION
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 ±0.05
4.50 ± 0.05
3.10 ± 0.05
2.50 REF
2.65 ± 0.05
3.65 ± 0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ± 0.05
5.50 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
2.50 REF
R = 0.115
TYP
R = 0.05
TYP
0.75 ± 0.05
4.00 ± 0.10
(2 SIDES)
27
28
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ± 0.10
(2 SIDES)
3.50 REF
3.65 ± 0.10
2.65 ± 0.10
(UFD28) QFN 0506 REV B
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3070fb
26
For more information www.linear.com/LT3070
LT3070
REVISION HISTORY
REV
DATE
5/10
4/13
DESCRIPTION
PAGE NUMBER
A
Entire data sheet revised
1 to 28
B
Clarified Parameter conditions in Electrical Characteristics table
Added Enable Pin Threshold graph
Clarified EN pin operation
4
7
13
14
28
Enhanced Block Diagrams
Added LT3071 to Related Parts
3070fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LT3070
TYPICAL APPLICATION
50k
V
BIAS
PWRGD
2.5V TO 3.6V
2.2µF
BIAS
V
IN
IN
PWRGD
SENSE
1.5V
330µF
EN
V
1.2V
5A
OUT
LT3070
OUT
V
O0
V
O1
V
O2
2.2µF*
4.7µF*
10µF*
NC
NC
MARGSEL
MARGTOL
VIOC
*X5R OR X7R CAPACITORS
REF/BYP
GND
1nF
0.01µF
3070 TA02
1.5V to 1.2V Linear Regulator
RELATED PARTS
PART
DESCRIPTION
500mA, Low Noise LDO
COMMENTS
LT1763
300mV Dropout Voltage, Low Noise: 20µV
SO-8 Package
, V : 1.8V to 20V,
RMS IN
LT1764/LT1764A
LT1963/LT1963A
3A, Fast Transient Response, Low Noise LDO
1.5A Low Noise, Fast Transient Response LDO
340mV Dropout Voltage, Low Noise: 40µV
, V : 2.7V to 20V,
RMS IN
TO-220 and DD Packages “A” Version Stable Also with Ceramic Caps
340mV Dropout Voltage, Low Noise: 40µV
, V : 2.5V to 20V,
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“A” Version Stable with Ceramic Caps, TO-220, DD, SOT-223 and
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LT1965
LT3021
1.1A, Low Noise, Low Dropout Linear Regulator
500mA, Low Voltage, VLDO™ Linear Regulator
290mV Dropout Voltage, Low Noise: 40µV
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V
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OUT
MSOP and 3mm × 3mm DFN Packages
V : 0.9V to 10V, Dropout Voltage = 160mV (Typ), Adjustable Output
IN
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OUT(MIN)
Stable with Low ESR, Ceramic Output Capacitors 16-Pin DFN
(5mm × 5mm) and 8-Lead SO Packages
LT3080/LT3080-1
LT3085
1.1A, Parallelable, Low Noise, Low Dropout Linear Regulator 300mV Dropout Voltage (2-Supply Operation), Low Noise: 40µV
,
RMS
V : 1.2V to 36V, V : 0V to 35.7V, Current-Based Reference with
IN
OUT
1 Resistor V
Set; Directly Parallelable (No Op Amp Reꢁuired),
OUT
Stable with Ceramic Caps, TO-220, SOT-223, MSOP-8 and 3mm
× 3mm DFN-8 Packages; LT3080-1 has Integrated Internal Ballast
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500mA, Parallelable, Low Noise, Low Dropout
Linear Regulator
275mV Dropout Voltage (2-Supply Operation), Low Noise: 40µV
RMS
,
V : 1.2V to 36V, V : 0V to 35.7V, Current-Based Reference with
IN
OUT
1 Resistor V
Set; Directly Parallelable (No Op Amp Reꢁuired),
OUT
Stable with Ceramic Caps, MSOP-8 and 2mm × 3mm DFN-6
Packages
LTC3025-1/
LTC3025-2
500mA Micropower VLDO Linear Regulator
in 2mm × 2mm DFN
V
= 0.9V to 5.5V, Dropout Voltage: 75mV, Low Noise 80µV
,
IN
RMS
Low I : 54µA, Fixed Output: 1.2V (LTC3025-2); Adjustable Output
Q
Range: 0.4V to 3.6V (LTC3025-1) 2mm × 2mm 6-Lead DFN Package
LTC3026
LT3071
1.5A, Low Input Voltage VLDO Regulator
V : 1.14V to 3.5V (Boost Enabled), 1.14V to 5.5V (with External
IN
5V), V = 0.1V, I = 950µA, Stable with 10µF Ceramic Capacitors,
DO
Q
10-Lead MSOP and DFN-10 Packages
5A, Low Noise, Programmable Output, 85mV Dropout Linear V : 0.95V to 3V, V : 0.8V to 1.8V in 50mV Increments, Low
Regulator with Analog Margining
IN
OUT
Noise: 25µV
, Stable with Ceramic Capacitors, 4mm × 5mm
RMS
28-Lead QFN Package
3070fb
LT 0413 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LT3070
●
●
LINEAR TECHNOLOGY CORPORATION 2009
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