LT3070IUFDTR [Linear]
5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator; 5A ，低噪声，可编程输出，一个85mV压差线性稳压器
| 型号： | LT3070IUFDTR |
| 厂家： | 
Linear |
| 描述： | 5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator |
| 文件： | 总24页 (文件大小：202K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Electrical Specifications Subject to Change
LT3070
5A, Low Noise,
Programmable Output,
85mV Dropout
Linear Regulator
FEATURES
DESCRIPTION
The LT®3070 is a low voltage, UltraFast™ transient re-
sponse linear regulator. The device supplies up to 5A of
output current with a typical dropout voltage of 85mV.
A 0.01μF reference bypass capacitor decreases output
n
Output Current: 5A
n
Dropout Voltage: 85mV Typical
n
Digitally Programmable V : 0.8V to 1.8V
OUT
n
Digital Output Margining: 1ꢀ, ꢁꢀ or 5ꢀ
n
Low Output Noise: 25μV
(10Hz to 100kHz)
voltage noise to 25μV
. The LT3070’s high bandwidth
RMS
RMS
n
n
n
n
Parallelable: Use Two for a 10A Output
Precision Current Limit: 10ꢀ
permits the use of low ESR ceramic capacitors, saving
bulk capacitance and cost. The LT3070’s features make
it ideal for high performance FPGAs, microprocessors or
sensitive communication supply applications.
1ꢀ Accuracy Over Line, Load and Temperature
Stable with Low ESR Ceramic Output Capacitors
(15μF Minimum)
High Freꢁuency PSRR: 35dB at 1MHz
Enable Function Turns Output On/Off
VIOC Pin Controls Buck Converter to Maintain Low
Power Dissipation and Optimize Efficiency
PWRGD/UVLO Flag
Output voltage is digitally selectable in 50mV increments
over a 0.8V to 1.8V range. A margining function allows the
user to tolerance system output voltage in increments of
1ꢀ, 3ꢀ or 5ꢀ. The IC incorporates a uniꢁue tracking
functiontocontrolabuckregulatorpoweringtheLT3070’s
input. This tracking function drives the buck regulator to
n
n
n
n
n
n
n
Current Limit Foldback Protection
Thermal Shutdown
maintain the LT3070’s input voltage to V
minimizing power dissipation.
+ 300mV,
OUT
28-Lead (4mm × 5mm) QFN Package
InternalprotectionincludesUVLO,reverse-currentprotec-
tion, precision current limiting with power foldback and
thermal shutdown. The LT3070 regulator is available in a
thermally enhanced 28-lead, 4mm × 5mm QFN package.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. UltraFast is a trade mark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
APPLICATIONS
n
FPGA and DSP Supplies
n
ASIC and Microprocessor Supplies
n
Servers and Storage Devices
n
Post Buck Regulation and Supply Isolation
TYPICAL APPLICATION
0.9V, 5A Regulator
50k
Dropout Voltage
V
BIAS
2.2V TO 3.6V
PWRGD
4
2.2μF
BIAS
V
IN
1.2V
3
IN
EN
V
PWRGD
SENSE
330μF
V
0.9V
5A
OUT
LT3070
OUT
O0
2
2.2μF
4.7μF
10μF
PLACE HOLDER
V
O1
V
O2
MARGSEL
MARGTOL
VIOC
1
0
REF/BYP
GND
1nF
0.01μF
3070 TA01a
0
20
30
40
10
XXX
LTXXXX • TPCXX
3070p
1
LT3070
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
IN, OUT......................................................... 3.3V, –0.3V
BIAS................................................................. 4V, –0.3V
O2 O1 O0
28 27 26 25 24 23
V , V , V Inputs ........................................ 4V, –0.3V
VIOC
PWRGD
REF/BYP
GND
IN
1
2
3
4
5
6
7
8
22
21
20
19
18
17
16
15
MARGTOL
MARGSEL
GND
MARGSEL, MARGTOL Input ............................ 4V, –0.3V
EN Input........................................................... 4V, –0.3V
SENSE Input .................................................... 4V, –0.3V
VIOC, PWRGD Outputs .................................... 4V, –0.3V
REF/BYP Output............................................... 4V, –0.3V
Output Short-Circuit Duration……...................Indefinite
Operating Junction Temperature (Note 2)
LT3070E/LT3070I.............................. –40°C to 125°C
LT3070MP......................................... –55°C to 125°C
Storage Temperature Range................... –65°C to 150°C
SENSE
OUT
29
IN
OUT
IN
OUT
IN
OUT
9
10 11 12 13 14
UFD PACKAGE
28-LEAD (4mm s 5mm) PLASTIC QFN
T
= 125°C, θ = 30°C/W
JMAX
JA
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LT3070EUFD#PBF
LT3070IUFD#PBF
LT3070MPUFD#PBF
LEAD BASED FINISH
LT3070EUFD
TAPE AND REEL
PART MARKING*
3070
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3070EUFD#TRPBF
LT3070IUFD#TRPBF
LT3070MPUFD#TRPBF
TAPE AND REEL
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
PACKAGE DESCRIPTION
3070
070MP
PART MARKING*
3070
LT3070EUFD#TR
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
LT3070IUFD
LT3070IUFD#TR
3070
LT3070MPUFD
LT3070MPUFD#TR
070MP
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3070p
2
LT3070
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. COUT = 15μF (Note 9), VIN = VOUT + 0.ꢁV (Note 5), VBIAS = 2.5V unless
otherwise noted.
PARAMETER
CONDITIONS
MIN
0.95
2.2
TYP
MAX
3.0
UNITS
l
l
Minimum IN Pin Voltage
Minimum BIAS Pin Voltage (Note 3)
Regulated Output Voltage
V
IN
≥ V
+ 150mV, I = 5A
V
V
OUT
OUT
3.6
l
l
l
l
l
l
l
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
= 0.8V, 10mA ≤ I
= 0.9V, 10mA ≤ I
≤ 5A, 1V ≤ V ≤ 1.25V
0.792
0.891
0.990
1.089
1.189
1.485
1.782
0.800
0.900
1.000
1.100
1.200
1.500
1.800
0.808
0.909
1.010
1.111
1.212
1.515
1.818
V
V
V
V
V
V
V
OUT
OUT
IN
≤ 5A, 1.1V ≤ V ≤ 1.35V
IN
= 1V, 10mA ≤ I
≤ 5A, 1.2V ≤ V ≤ 1.45V
OUT
IN
= 1.1V, 10mA ≤ I
= 1.2V, 10mA ≤ I
= 1.5V, 10mA ≤ I
= 1.8V, 10mA ≤ I
≤ 5A, 1.3V ≤ V ≤ 1.55V
IN
OUT
OUT
OUT
OUT
≤ 5A, 1.4V ≤ V ≤ 1.65V
IN
≤ 5A, 1.7V ≤ V ≤ 1.95V
IN
≤ 5A, 2.0V ≤ V ≤ 2.25V
IN
l
l
Regulated Output Voltage Margining
(Note 3)
MARGTOL = 0V, MARGSEL = V
0.7
–1.3
1
–1
1.3
–0.7
ꢀ
ꢀ
BIAS
OUT
MARGTOL = 0V, MARGSEL = 0V, I
= 10mA
l
l
MARGTOL = FLOAT, MARGSEL = V
2.7
–3.3
3
–3
3.3
–2.7
ꢀ
ꢀ
BIAS
OUT
MARGTOL = FLOAT, MARGSEL = 0V, I
= 10mA
l
l
MARGTOL = V
MARGTOL = V
, MARGSEL= V
4.7
–5.3
5
–5
5.3
–4.7
ꢀ
ꢀ
BIAS
BIAS
BIAS
, MARGSEL = 0V, I
= 10mA
OUT
l
l
Line Regulation to V
1.0
1.0
mV
mV
V
V
= 0.8V, ΔV = 1.1V to 3.0V, V
= 3.3V, I
= 3.3V, I
= 10mA
= 10mA
IN
OUT
OUT
IN
BIAS
BIAS
OUT
OUT
= 1.8V, ΔV = 2.1V to 3.0V, V
IN
l
l
Line Regulation to V
2.0
1.0
mV
mV
V
V
= 0.8V, ΔV
= 1.8V, ΔV
= 2.2V to 3.6V, V = 1.1V, I
= 10mA
= 10mA
BIAS
OUT
OUT
BIAS
BIAS
IN
OUT
OUT
= 3.1V to 3.6V, V = 2.1V, I
IN
V
V
V
V
V
= 3.3V, V = 1.1V, V
= 0.8V
= 1.0V
= 1.2V
= 1.5V
= 1.8V
–1.5
–1.5
–1.8
–2.3
–2.7
–3.0
–5.0
mV
mV
Load Regulation, ΔI
= 10mA to 5A
BIAS
BIAS
BIAS
BIAS
BIAS
IN
OUT
OUT
OUT
OUT
OUT
OUT
l
l
l
l
= 3.3V, V = 1.3V, V
–3.0
–5.0
mV
mV
IN
= 3.3V, V = 1.5V, V
–3.6
–6.0
mV
mV
IN
= 3.3V, V = 1.8V, V
–4.5
–7.5
mV
mV
IN
= 3.3V, V = 2.1V, V
–5.4
–9.0
mV
mV
IN
l
l
Dropout Voltage, V = V
I
I
= 1A
20
mV
IN
OUT(NOMINAL)
OUT
(Note 6)
= 2.5A
45
85
55
63
mV
mV
OUT
l
l
I
= 5A
105
150
mV
mV
OUT
l
l
SENSE Pin Current
V
BIAS
V
BIAS
= 3.3V, V = 1.1V, V
= 0.8
= 1.8V
35
210
50
300
65
390
μA
μA
IN
OUT
OUT
= 3.3V, V = 2.1V, V
IN
l
l
Ground Pin Current, V = 1.3V,
OUT
I
I
= 10mA
= 5A
0.45
0.62
0.72
0.88
1.15
1.45
mA
mA
IN
OUT
OUT
V
= 1V
3070p
3
LT3070
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. COUT = 15μF (Note 9), VIN = VOUT + 0.ꢁV (Note 5), VBIAS = 2.5V unless
otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
BIAS Pin Current in Nap Mode
EN = Low (After POR Completed)
300
420
650
μA
l
l
l
l
l
l
BIAS Pin Current, V = 1.3V, V
= 1V
I
I
I
I
I
I
= 10mA
= 100mA
= 500mA
= 1A
= 2.5A
= 5A
1.20
2.05
2.75
3.40
4.85
5.20
1.80
2.60
3.70
4.60
6.40
7.25
2.40
3.70
5.45
6.80
9.40
11.45
mA
mA
mA
mA
mA
mA
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
l
l
l
l
Current Limit (Note 5)
V
IN
V
IN
V
IN
V
IN
– V
< 0.5V
5.2
4.8
3.4
1.0
6
A
A
A
A
OUT
OUT
OUT
OUT
– V
– V
– V
= 0.6V
= 1.0V
= 1.5V
5.2
4.4
1.8
Reverse Output Current (Note 8)
V
IN
= 0V, V
= 3V
OUT
200
400
μA
l
l
PWRGD V
Threshold
Percentage of V
Percentage of V
, V
OUT(NOMINAL) OUT
OUT(NOMINAL) OUT
Rising
Falling
87.5
83.5
90
86
92.5
88.5
ꢀ
ꢀ
OUT
, V
l
PWRGD V
I
= 200μA (Fault Condition)
100
mV
OL
PWRGD
l
l
V
Undervoltage Lockout
EN = 3.3V, V
EN = 3.3V, V
Rising
Falling
1.11
0.96
1.50
1.30
2.03
1.62
V
V
BIAS
BIAS
BIAS
l
V -V
IN OUT
Servo Voltage by VIOC
250
300
350
mV
l
l
VIOC Output Current
V
IN
V
IN
= V
= V
+ 150mV, Sourcing
+ 450mV, Sinking
175
175
256
256
335
335
μA
μA
OUT(NOMINAL)
OUT(NOMINAL)
l
l
l
l
l
l
V
V
Input Threshold (Logic-0 State),
O2 O1 O0
Input Falling
0.22
0.42
V
IL
, V , V , MARGSEL, MARGTOL
V
V
Input Range (Logic-Z State),
, V , V , MARGSEL, MARGTOL
0.75
1.76
2.25
70
V
IZ
O2 O1 O0
V
V
Input Threshold (Logic-1 State),
, V , V , MARGSEL, MARGTOL
Input Rising
2.00
52
V
IH
O2 O1 O0
Input Hysteresis (Both Thresholds),
, V , V , MARGSEL, MARGTOL
40
mV
μA
μA
V
O2 O1 O0
Input Current High,
, V , V , MARGSEL, MARGTOL
V
V
= V
= 2.5V, Current Flows Into Pin
BIAS
27
43
IH
IL
V
O2 O1 O0
Input Current Low,
, V , V , MARGSEL, MARGTOL
= 0V, V
= 2.5V, Current Flows Out of Pin
26
38
BIAS
V
O2 O1 O0
l
l
EN Pin Threshold
V
V
= Off to On
= On to Off
1.35
V
V
OUT
OUT
0.94
3.8
l
l
EN Pin Logic High Current
EN Pin Logic Low Current
V
EN
V
EN
= V
= 2.5V
BIAS
5.0
7.1
0.1
μA
μA
= 0V
3070p
4
LT3070
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. COUT = 15μF (Note 9), VIN = VOUT + 0.ꢁV (Note 5), VBIAS = 2.5V unless
otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Ripple Rejection
V
V
= V
OUT
+ 1.5V , V
=0.5V , f = 120Hz,
P-P RIPPLE
60
72
dB
BIAS
BIAS
IN
OUT
AVG RIPPLE
– V
= 300mV, I
= 2.5A
OUT
V
Ripple Rejection (Notes 3, 4, 5)
V
V
= 2.5V, V – V
= 300mV, I = 2.5A,
OUT
60
68
dB
IN
BIAS
IN
OUT
= 50mV , f
= 120Hz
RIPPLE
P-P RIPPLE
Reference Voltage Noise (REF/BYP Pin)
Output Voltage Noise
C
V
= 10nF, BW = 10Hz to 100kHz
10
25
μV
μV
REF/BYP
RMS
= 1V, I
= 5A, C
= 10nF, C
= 15μF,
OUT
OUT
OUT
REF/BYP
RMS
BW = 10Hz to 100kHz
Note 6: Dropout voltage, V , is the minimum input to output voltage
differential at a specified output current. In dropout, the output voltage
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
DO
eꢁuals V – V
.
DO
IN
Note 7: GND pin current is tested with V = V
+ 300mV and a
OUT(NOMINAL)
IN
current source load. VIOC is a buffered output determined by the value of
as programmed by the V -V pins. VIOC’s output is independent of
the margining function.
Note 8: Reverse output current is tested with the IN pins grounded and the
OUT + SENSE pins forced to the rated output voltage. This is measured as
current into the OUT + SENSE pins.
Note 2: The LT3070 regulators are tested and specified under pulse load
conditions such that T ≅ T . The LT3070E is 100ꢀ tested at T = 25°C.
Performance at –40°C and 125°C is assured by design, characterization
and correlation with statistical process controls. The LT3070I is
guaranteed over the –40°C to 125°C operating junction temperature range.
The LT3070MP is 100ꢀ tested and guaranteed over the –55°C to 125°C
operating junction temperature range.
V
OUT
O2 O0
J
A
A
Note 9: Freꢁuency Compensation: The LTC3070 must be freꢁuency
Note ꢁ: To maintain proper performance and regulation, the BIAS supply
compensated at its OUT pins with a minimum C
of 15μF configured
OUT
voltage must be higher than the IN supply voltage. For a given V , the
as a cluster of (15×) 1μF ceramic capacitors or as a graduated cluster
of 10μF/4.7μF/2.2μF ceramic capacitors of the same case size. Linear
Technology only recommends X5R or X7R dielectric capacitors.
OUT
BIAS voltage must be in the range: (1.2 • V
+ 935mV) ≤ V
≤ 3.6V.
OUT
BIAS
Note 4: Operating conditions are limited by maximum junction
temperature. The regulated output voltage specification does not apply
for all possible combinations of input voltage and output current. When
operating at maximum output current, limit the input voltage range to:
V
< V
+ 500mV.
IN
OUT
Note 5: The LT3070 incorporates safe operating area protection circuitry.
Current limit decreases as the V -V
voltage increases. Current limit
IN OUT
foldback starts at V – V
Characteristics for a graph of Current Limit vs V – V
> 500mV. See the Typical Performance
IN
OUT
voltage. The
OUT
IN
current limit foldback feature is independent of the thermal shutdown
circuity.
3070p
5
LT3070
TYPICAL PERFORMANCE CHARACTERISTICS
V
OUT Distribution
VOUT vs Temperature
Load Regulation
Dropout Voltage vs VIN
Dropout Voltage vs VBIAS
Load Transient Response
Current Limit vs VIN
Output Voltage Noise
3070p
6
LT3070
TYPICAL PERFORMANCE CHARACTERISTICS
Ripple Rejection vs VIN
Ripple Rejection vs VBIAS
Minimum VIN vs Temperature
Line Transient Response vs VIN
Line Transient Response vs VBIAS
Noise vs Output Voltage
BIAS Pin Current vs Load
GND Pin Current vs Load
3070p
7
LT3070
PIN FUNCTIONS
VIOC (Pin 1): Voltage for In-to-Out Control. The IC in-
corporates a uniꢁue tracking function to control a buck
regulator powering the LT3070’s input. The VIOC pin is
the output of this tracking function that drives the buck
voltagesandthathavelarge,fastloadtransientsmayreꢁuire
much higher input capacitor reꢁuirements to prevent the
input supply from drooping and allowing the regulator to
enter dropout. See the Applications Information section
for more information on input capacitor reꢁuirements.
regulator to maintain the LT3070’s input voltage at V
+
OUT
300mV. This function maximizes efficiency and minimizes
power dissipation. See the Applications Information sec-
tion for more information on proper control of the buck
regulator.
OUT (Pins 15, 16, 17, 18): Output. These pins supply
power to the load. Tie all OUT pins together for proper
performance. A minimum output capacitance of 15μF is
reꢁuired for stability. LTC recommends low ESR, X5R or
X7R dielectric ceramic capacitors for best performance.
A parallel ceramic capacitor combination of 10μF + 4.7μF
+ 2.2μF provides excellent stability and load transient
response. Large load transient applications reꢁuire larger
output capacitors to limit peak voltage transients. See the
Applications Information section for more information on
output capacitor reꢁuirements.
PWRGD (Pin 2): Power Good. The PWRGD pin is an open-
drain NMOS output that is active low if any one of these
fault modes is detected:
• V
is less than 90ꢀ of V
on the rising
OUT
edge of V
OUT(NOMINAL)
drops below 85ꢀ of V
OUT(NOMINAL)
OUT
• V
for more than
OUT
25μs
SENSE (Pin 19): Kelvin Sense for OUT. The SENSE pin is
theinvertinginputtotheerroramplifier.Optimumregulation
is obtained when the SENSE pin is connected to the OUT
pins of the regulator. In critical applications, the resistance
• Junction temperature exceeds 145°C
See the Applications Information section for more infor-
mation on PWRGD fault modes.
(R )ofPCBtracesbetweentheregulatorandtheloadcause
P
REF/BYP (Pin ꢁ): Reference Filter. The pin is the output
of the bandgap reference and has an impedance of ap-
proximately 19kΩ. This pin must not be externally loaded.
Bypassing the REF/BYP pin to GND with a 10nF capacitor
decreases output voltage noise and provides a soft-start
functiontothereference.SeetheApplicationsInformation
section for more information on noise and output voltage
margining considerations.
small voltage drops, creating a load regulation error at the
pointofload.ConnectingtheSENSEpinattheloadinstead
of directly to OUT eliminates this voltage error. Figure 1
illustratesthisKelvin-Senseconnectionmethod.Notethat
thevoltagedropacrosstheexternalPCBtracesaddstothe
dropout voltage of the regulator. The SENSE pin input bias
current depends on the selected output voltage. SENSE
pin input current varies from 50μA typically at V
= 0.8V
OUT
to 300μA typically at V
= 1.8V.
GND (Pins 4, 9-14, 20, 26): Ground. All GND pins must
be tied together and to Pin 29, the exposed backside of
the package for proper thermal performance. These GND
pinsarefusedtotheinternaldieattachpaddleandexposed
package backside to optimize heat sinking and thermal
resistance performance.
OUT
+
V
BIAS
BIAS
IN
EN
SENSE
OUT
R
P
LT3070
V
O2
V
O1
V
O0
PWRGD
IN (Pins 5, 6, 7, 8): Input Supply. These pins supply
power to the high current pass transistor. Tie all IN pins
together for proper performance. The LT3070 reꢁuires a
bypass capacitor at IN to maintain stability and low input
impedance over freꢁuency. A 47μF input bypass capacitor
suffices for most battery and power plane impedances.
Minimizinginputtraceinductanceoptimizesperformance.
+
LOAD
V
MARGSEL
MARGTOL
VIOC
IN
REF/BYP
GND
R
P
3070 F01
Applications that operate with low V -V
differential
Figure 1. Kelvin Sense Connection
IN OUT
3070p
8
LT3070
PIN FUNCTIONS
MARGSEL (Pin 21): Margining Enable and Polarity Se-
lection. This three-state pin determines both the polarity
and the active state of the margining function. The logic
low threshold is less than 220mV referenced to GND and
enables negative voltage margining. The logic “high”
BIAS (Pin 27): Bias Supply. This pin supplies current
to most of the internal control circuitry and the output
stage driving the pass transistor. The LT3070 reꢁuires a
minimum 2.2μF bypass capacitor for stability and proper
operation. To ensure proper operation, the BIAS voltage
must conform to the eꢁuation:
threshold is greater than V
– 500mV and enables
BIAS
positive voltage margining. The voltage range between
these two logic thresholds defines the logic Hi-Z state
and disables the margining function.
(1.2 • V ) + 935mV ≤ V
≤ 3.6V
BIAS
OUT
EN (Pin 28): Enable. This pin starts the internal reference,
enables all outputs and enables all support functions.
After start-up, pulling the EN pin low keeps the reference
circuit active, but disables the output transistor and puts
the LT3070 into a lower power “nap” mode. Drive the EN
pinwitheitheradigitallogicportoranopen-collectorNPN
or open-drain NMOS terminated with a pull-up resistor to
MARGTOL (Pin 22): Margining Tolerance. This three-
state pin selects the absolute value of margining (1ꢀ,
3ꢀ or 5ꢀ) if enabled by the MARGSEL input. The logic
low threshold is less than 220mV referenced to GND and
enableseither 1ꢀchangeinV
dependingonthestate
OUT
of the MARGSEL pin. The logic high threshold is greater
than V – 500mV and enables either 5ꢀ change in
V
. The pull-up resistor must be no larger than 35k to
BIAS
BIAS
meet the V condition of the EN pin. If unused, connect
IH
V
OUT
depending on the state of the MARGSEL pin. The
the EN pin to V
.
BIAS
voltage range between these two logic thresholds defines
Exposed Pad (Pin 29): GND. Tie the Exposed Pad to all
GND pins and directly to the PCB GND. This Exposed Pad
provides enhanced thermal performance with its connec-
tion to the PCB GND. See the Applications Information
sectionforthermalconsiderationsandcalculatingjunction
temperature.
thelogicHi-Zstateandenableseither 3ꢀchangeinV
OUT
depending on the state of the MARGSEL pin.
V ,V andV (Pins2ꢁ,24,25):OutputVoltageSelect.
O2 O1
O0
These three-state pins combine to select a nominal output
voltage from 0.8V to 1.8V in increments of 50mV. Output
voltage is limited to 1.8V maximum by an internal override
ofV whenV =“1”. Theinputlogic“0”thresholdisless
O1
O2
than220mVreferencedtoGNDandthelogic“1”threshold
is greater than V – 500mV. The range between these
BIAS
two thresholds defines the logic Hi-Z state. See Table 1 in
the Applications Information section that defines the V ,
O2
V
and V settings versus V
.
O1
O0
OUT
3070p
9
LT3070
BLOCK DIAGRAM
UVLO AND
BIAS
27
THERMAL
SHUTDOWN
IN
5-8
+
–
I
SENSE
REF/BYP
+
–
EAMP
BUF
OUT
15-18
LDO CORE
SENSE
19
2
PWRGD
DETECT
–
+
VIOC
GND
V
+ 300mV
1
OUT(NOM)
REF/BYP
V
3
REF
4,9-14,20,26,29
PROGRAM CONTROL
EN
V
V
V
MARGSEL MARGTOL
22
O2
O1
O0
28 25 24 23 21
3070 BD
3070p
10
LT3070
APPLICATIONS INFORMATION
Introduction
This combines the efficiency of a switching regulator
with superior linear regulator response. It also permits
thermal management of the system even with a maximum
5A output load.
Current generation FPGA and ASIC processors place
stringent demands on the power supplies that power the
core,I/Oandtransceiverchannels.Thesemicroprocessors
may cycle load current from near zero to amps in tens of
nanoseconds. Output voltage specifications, especially in
the 1V range, reꢁuire tight tolerances including transient
responseaspartofthereꢁuirement.SomeASICprocessors
reꢁuire only a single output voltage from which the core
and I/O circuitry operate. Some high performance FPGA
processorsreꢁuireseparatepowersupplyvoltagesforthe
processor core, the I/O, and the transceivers. Often, these
supply voltages must be low noise and high bandwidth
to achieve the lowest bit-error rates. These reꢁuirements
mandate the need for very accurate, low noise, high cur-
rent, very high speed regulator circuits that operate at low
input and output voltages.
LT3070 internal protection includes input undervoltage
lockout(UVLO),reverse-currentprotection,precisioncur-
rent limiting with power foldback and thermal shutdown.
The LT3070 regulator is available in a thermally enhanced
28-lead, 4mm × 5mm QFN package.
The LT3070’s architecture drives an internal N-channel
power MOSFET as a source follower. This configuration
permits a user to realize an extremely low dropout, Ultra-
Fast transient response regulator with excellent high fre-
ꢁuencyPSRRperformance.TheLT3070achievessuperior
regulator bandwidth and transient load performance by
eliminatingexpensivebulktantalumorelectrolyticcapaci-
tors in the most modern and demanding microprocessor
applications. Users realize significant cost savings as all
additional bulk capacitance is removed. The additional
savings of insertion cost, purchasing/inventory cost and
board space are readily apparent. Precision incremental
output voltage control accommodates legacy and future
microprocessor power supply voltages.
The LT3070 is a low voltage, UltraFast transient response
linear regulator. The device supplies up to 5A of output
current with a typical dropout voltage of 85mV. A 0.01μF
referencebypasscapacitordecreasesoutputvoltagenoise
to 25μV
(BW = 10Hz to 100kHz). The LT3070’s high
RMS
bandwidthprovidesUltraFasttransientresponseusinglow
ESR ceramic output capacitors (15μF minimum), saving
bulk capacitance, PCB area and cost.
Output capacitor networks simplify to direct parallel com-
binations of ceramic capacitors. Often, the high freꢁuency
ceramic decoupling capacitors reꢁuired by these various
FPGA and ASIC processors are sufficient to stabilize the
system(seeStabilityandOutputCapacitancesection).This
regulator design provides ample bandwidth and responds
to transient load changes in a few hundred nanoseconds
versus regulators that respond in many microseconds.
TheLT3070’sfeaturespermitstate-of-the-art linearregula-
torperformance.TheLT3070isidealforhighperformance
FPGAs, microprocessors, sensitive communication sup-
plies, and high current logic applications that also operate
over low input and output voltages.
Output voltage for the LT3070 is digitally selectable in
50mV increments over a 0.8V to 1.8V range. A margining
functionallowstheusertotolerancesystemoutputvoltage
in increments of 1ꢀ, 3ꢀ or 5ꢀ.
The LT3070 also incorporates precision current limiting,
enable/disable control of output voltage and integrated
overvoltage and thermal shutdown protection. The
LT3070’s uniꢁue design combines the benefits of low
dropout voltage, high functional integration, precision
performance and UltraFast transient response, as well as
providingsignificantcostsavingsontheoutputcapacitance
needed in fast load transient applications.
The IC incorporates a uniꢁue tracking function, which if
enabled by the user, controls an upsteam regulator power-
ingtheLT3070’sinput(seeFigure8).Thistrackingfunction
drives the buck regulator to maintain the LT3070’s input
voltage to V
+ 300mV. This input-to-output voltage
OUT
control allows the user to change the regulator output
voltage, and have the switching regulator powering the
LT3070’s input to track to the optimum input voltage with
no component changes.
As lower voltage applications become increasingly preva-
lent with higher freꢁuency switching power supplies, the
LT3070 offers superior regulation and an appreciable
3070p
11
LT3070
APPLICATIONS INFORMATION
component cost savings. The LT3070 steps to the next
levelofperformanceforthelatestgenerationFPGAs,DSPs
and microprocessors. The simple versatility and benefits
derivedfromthesecircuitsexceedthepowersupplyneeds
of today’s high performance microprocessors.
REF/BYP—Voltage Reference
This pin is the buffered output of the internal bandgap
reference and has an output impedance of ≅19kΩ. The
designincludesaninternalcompensationpoleatf =4kHz.
C
A 10nF REF/BYP capacitor to GND creates a lowpass pole
at f = 840Hz. The 10nF capacitor decreases reference
LP
Programming Output Voltage
voltage noise to about 10μV
and soft-starts the refer-
RMS
Three tri-level input pins, V , V and V , select the
ence. The LT3070 only soft-starts the reference voltage
during an initial turn-on seꢁuence. If the EN pin is toggled
lowafterinitialturn-on,thereferenceremainspowered-up.
Therefore, toggling the EN pin from low to high does not
soft-start the reference. Only by turning the BIAS supply
voltageonandoffwillthereferencebesoft-started.Output
voltage noise is the RMS sum of the reference voltage
noise in addition to the amplifier noise.
O2 O1
O0
value of output voltage. Table 1 illustrates the 3-bit digital
word to output voltage table resulting from setting these
pins high, low or allowing them to float.
Thesepinsmaybetiedhighortiedlowbyeitherpin-strap-
ping them to V
or driving them with digital ports. Pins
BIAS
that float may either actually float or reꢁuire logic that has
Hi-Z output capability. This allows output voltage to be
dynamically changed if necessary.
TheREF/BYPpinmustnotbeDCloadedbyanythingexcept
for applications that parallel other LT3070 regulators for
higher output currents. Consult the Applications Section
on Paralleling for further details.
Output voltage is selectable from a minimum of 0.8V to
a maximum of 1.8V in increments of 50mV. The MSB,
V , sets the pedestal voltage, and the LSB’s, V and
O2
O0
O1
V
increment V
.
OUT
Output Voltage Margining
Output voltage is limited to 1.8V maximum by an internal
Twotri-levelinputpins,MARGSEL(polarity)andMARGTOL
(scale), select the polarity and amount of output voltage
margining. Margining is programmable in increments of
1ꢀ, 3ꢀ and 5ꢀ. Margining is internally implemented
as a scaling of the reference voltage.
override of V (default to “0”) when V = “1”.
O1
O2
Table 1: VO2-VO0 Settings vs Output Voltage
V
V
V
O0
V
V
V
O1
V
V
OUT(NOM)
O2
O1
OUT(NOM)
O2
O0
0
0
0
0
0
0
0
0
0
Z
Z
0
0
0
Z
Z
Z
1
1
1
0
0
0
Z
1
0
Z
1
0
Z
1
0
Z
0.80V
Z
Z
Z
Z
Z
Z
Z
1
1
1
0
Z
Z
Z
1
1
1
X
X
X
1
0
Z
1
0
Z
1
0
Z
1
1.35V
0.85V
0.90V
0.95V
1.00V
1.05V
1.10V
1.15V
1.20V
1.25V
1.30V
1.40V
1.45V
1.50V
1.55V
1.60V
1.65V
1.70V
1.75V
1.80V
Table 2 illustrates the 2-bit digital word to output voltage
margining resulting from setting these pins high, low or
allowing them to float.
These pins may be set high or set low by either pin-strap-
ping them to V
or driving them with digital ports. Pins
BIAS
that float may either actually float or reꢁuire logic that has
“Hi-Z” output capability. This allows output voltage to be
dynamically margined if necessary.
The MARGSEL pin determines both the polarity and the
active state of the margining function. The logic “low”
threshold is less than 220mV referenced to GND and
enables negative voltage margining. The logic “high”
X = Don’t Care, 0 = GND, Z = Float, 1 = V
BIAS
Theinputlogic“0”thresholdislessthan220mVreferenced
to GND and the logic “1” threshold is greater than V
BIAS
threshold is greater than V
– 500mV and enables
BIAS
– 500mV. The range between these two thresholds defines
the logic Hi-Z state.
3070p
12
LT3070
APPLICATIONS INFORMATION
positive voltage margining. The voltage range between
these two logic thresholds defines the logic Hi-Z state
and disables the margining function.
gated off and output current falls to zero. The typical BIAS
pin UVLO threshold is 1.55V on the rising edge of V
.
BIAS
The UVLO circuit incorporates about 250mV of hysteresis
on the falling edge of V
.
BIAS
TheMARGTOLpinselectstheabsolutevalueofmargining
(1ꢀ, 3ꢀ or 5ꢀ) if enabled by the MARGSEL input. The
logic “low” threshold is less than 220mV referenced to
High Efficiency Linear Regulator—Input-to-Output
Voltage Control
GNDandenableseither 1ꢀchangeinV
dependingon
OUT
TheVIOC(voltageinputtooutputcontrol)pinisafunction
tocontrolaswitchingregulatorandfacilitateadesignsolu-
tionthatmaximizessystemefficiencyathighloadcurrents
and still provides low dropout voltage performance.
the state of the MARGSEL pin. The logic “high” threshold
is greater than V – 500mV and enables either 5ꢀ
BIAS
change in V
depending on the state of the MARGSEL
OUT
pin. The voltage range between these two logic thresholds
definesthelogicHi-Zstateandenableseither 3ꢀchange
The VIOC pin is the output of an integrated transconduc-
tance amplifier that sources and sinks 250μA of current.
It typically regulates the output of most LTC® switching
regulators or LTM® power modules, by sinking current
from the ITH compensation node. The VIOC function
controls a buck regulator powering the LT3070’s input by
in V
depending on the state of the MARGSEL pin.
OUT
Table 2: Programming Margining
MARGSEL
MARGTOL
ꢀ of V
OUT(NOM)
0
0
0
Z
Z
Z
1
1
1
0
Z
1
0
Z
1
0
Z
1
–1
–3
–5
0
maintaining the LT3070’s input voltage to V
+ 300mV.
OUT
This 300mV V -V
differential voltage is chosen to
IN OUT
provide fast transient response and good high freꢁuency
PSRRwhileminimizingpowerdissipationandmaximizing
efficiency. For example, 1.5V to 1.2V conversion and 1.3V
to 1V conversion yield 1.5W maximum power dissipation
at 5A full output current.
0
0
1
3
5
Figure 2 depicts that the switcher’s feedback resistor net-
worksetsthemaximumswitchingregulatoroutputvoltage
ifthelinearregulatorisdisabled.However,oncetheLT3070
isenabled,theVIOCfeedbackloopdecreasestheswitching
Enable Function—Turning On and Off
The first rising edge of the EN enable pin starts the LT3070
reference and all support functions while enabling the
output. After start-up, pulling the EN pin low places the
regulatorintonapmode.Innapmode,thereferencecircuit
remains active, but the output is disabled and ꢁuiescent
current decreases.
regulator output voltage back to V
+ 300mV.
OUT
Using the VIOC function creates a feedback loop between
the LT3070 and the switching regulator. As such, the
feedback loop must be freꢁuency compensated for stabil-
ity. Fortunately, the connection of VIOC to many LTC ITH
pins represents a high impedance characteristic which is
the optimum circuit node to freꢁuency compensate the
feedback loop. Figure 2 illustrates the typical freꢁuency
compensation network used at the VIOC node to GND.
Drive the EN pin with either a digital logic port or an open-
collector NPN or open-drain NMOS terminated with a
pull-up resistor to V
. The pull-up resistor must be no
BIAS
larger than 35k to meet the V condition of the EN pin. If
IH
unused, connect the EN pin to V
.
BIAS
The VIOC amplifier characteristics are:
Input Undervoltage Lockout on BIAS Pin
g = 3.2mS, I
m
= 250μA, BW = 10MHz.
OUT
An internal undervoltage lockout (UVLO) comparator
If the VIOC is not used, terminate the VIOC pin to GND with
a small capacitor (1000pF) to prevent oscillations.
monitors the BIAS rail. If V
drops below the UVLO
BIAS
threshold, all functions shut down, the pass transistor is
3070p
13
LT3070
APPLICATIONS INFORMATION
LT3070
IN
OUT
LOAD
SWITCHING REGULATOR
REF
+
–
PWM
FB
VIOC
V
+
OUT
V
300mV
REF
REFERENCE
I
TH
3070 F02
Figure 2. VIOC Control Block Diagram
PWRGD—Power Good
and ESR, combined with the distributed PCB inductance
isolatesthemfromtheprimarycompensationpoleprovided
by the local surface mount ceramic capacitors.
PWRGDisanopen-draindigitaloutputpinthatpulls“low”
if it detects any one of several fault modes including:
The LT3070 reꢁuires a minimum output capacitance of
15μFforstability.LTCstronglyrecommendsthattheoutput
capacitor network consist of several low value ceramic
capacitors in parallel.
• V
is less than 90ꢀ of V
on the rising
OUT
edge of V
OUT(NOMINAL)
OUT
• V
decreases below 85ꢀ of V
OUT(NOMINAL)
for more
OUT
than 25μs
Why Do Multiple, Small-Value Output Capacitors
Connected in Parallel Work Better?
• V decreases below V
IN
OUT
• Junction temperature exceeds 145°C typically*
The LT3070’s unity-gain bandwidth with C
of 15μF is
OUT
*The junction temperature detector is an early warning
indicator that trips approximately 20°C before thermal
shutdown engages.
about1MHzatitsfull-loadcurrentof5A. Surfacemounted
MLCC capacitors have a self-resonance freꢁuency of
f =1/(2π√LC),whichmustbepushedtoafreꢁuencyhigher
R
than the regulator bandwidth. Standard MLCC capacitors
are acceptable. To keep the resonant freꢁuency greater
than 1MHz, the product 1/(2π√LC) must be greater than
1MHz. At this bandwidth, PCB vias can add significant
inductance, thus the fundamental decoupling capacitors
must be mounted on the same plane as the LT3070.
Stability and Output Capacitance
The LT3070’s feedback loop reꢁuires an output capacitor
for stability. Choose C
carefully and mount it in close
OUT
proximitytotheLT3070’sOUTandGNDpins. Includewide
routing planes for OUT and GND to minimize inductance.
If possible, mount the regulator immediately adjacent to
the application load to minimize distributed inductance
for optimal load transient performance. Point-of-Load
applications present the best case layout scenario for
extracting full LT3070 performance.
Typical 0603 or 0805 case-size capacitors have an ESL of
~800pH and PCB mounting can contribute up to ~200pH.
Thus, it becomes necessary to reduce the parasitic induc-
tance by using a parallel capacitor combination. A suitable
methodology must control this paralleling as capacitors
with the same self-resonant freꢁuency, f , will form a tank
Low ESR, X5R or X7R ceramic chip capacitors are the
LTC recommended choice for stabilizing the LT3070. Ad-
ditional bulk capacitors distributed beyond the immediate
decouplingcapacitorsareacceptableastheirparasiticESL
R
circuit that can induce ringing of their own accord. Small
amounts of ESR (5mΩ to 20mΩ) have some benefit in
dampening the resonant loop, but higher ESRs degrade
3070p
14
LT3070
APPLICATIONS INFORMATION
the capacitor response to transient load steps with rise/
LT3070’s unity-gain crossover freꢁuency. This techniꢁue
illustrates the method that extracts the full bandwidth
performance of the LT3070.
fall times less than 1μs. The most area efficient parallel
capacitor combination is a graduated 4/2/1 scale of f of
R
the same case size. Under these conditions, the individual
ESLs are relatively uniform, and the resonance peaks are
deconstructively spread beyond the regulator bandwidth.
Therecommendedparallelcombinationthatapproximates
15μF is 10μF + 4.7μF + 2.2μF. Capacitors with case sizes
larger than 0805 have higher ESL and lower ESR (<5mΩ).
Therefore, more capacitors with smaller values (<10μF)
must be chosen. Users should consider new generation,
Give additional consideration to the use of ceramic
capacitors. Ceramic capacitors are manufactured with
a variety of dielectrics, each with different behavior
across temperature and applied voltage. The most com-
mon dielectrics used are specified with EIA temperature
characteristic codes of Z5U, Y5V, X5R and X7R. The Z5U
and Y5V dielectrics are good for providing high capaci-
tances in a small package, but they tend to have strong
voltage and temperature coefficients as shown in Figures
4 and 5. When used with a 5V regulator, a 16V 10μF Y5V
capacitor can exhibit an effective value as low as 1μF to
2μF for the DC bias voltage applied and over the operating
low inductance capacitors to push out f and maximize
R
stability. Refer to the surface mount ceramic capacitor
manufacturer’s data sheets for capacitor specifications.
Figure 3 illustrates an optimum PCB layout for the paral-
lel output capacitor combination, but also illustrates the
GND connection between the IN capacitor and the OUT
capacitors to minimize the AC GND loop for fast load
transients. This tight bypassing connection minimizes
EMI and optimizes bypassing.
20
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
0
X5R
–20
–40
LT3070
SENSE
IN OUT
–60
Y5V
GND
Lo-Z
–80
INPUT
LOAD PLANE
2.2μF
4.7μF
10μF
–100
47μF
10 12
DC BIAS VOLTAGE (V)
0
2
4
6
8
14 16
3070 F04
Figure 4. Ceramic Capacitor DC Bias Characteristics
3070 F03
40
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
Figure ꢁ. Example PCB Layout
20
X5R
Many of the applications in which the LT3070 excels,
such as FPGA, ASIC processor or DSP supplies, typically
reꢁuireahighfreꢁuencydecouplingcapacitornetworkfor
thedevicebeingpowered.Thisnetworkgenerallyconsists
of many low value ceramic capacitors in parallel. In some
applications, this total value of capacitance may be close
to the LT3070’s minimum 15μF capacitance reꢁuirement.
Thismayreducethereꢁuiredvalueofcapacitancedirectly
at the LT3070’s output. Multiple low value capacitors in
parallel present a favorable freꢁuency characteristic that
pushes many of the parasitic poles/zeroes beyond the
0
–20
Y5V
–40
–60
–80
–100
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
3070 F05
Figure 5. Ceramic Capacitor Temperature Characteristics
3070p
15
LT3070
APPLICATIONS INFORMATION
temperature range. The X5R and X7R dielectrics result in
more stable characteristics and are more suitable for use
as the output capacitor. The X7R type has better stability
across temperature, while the X5R is less expensive and
is available in higher values. Care still must be exercised
when using X5R and X7R capacitors; the X5R and X7R
codesonlyspecifyoperatingtemperaturerangeandmaxi-
mum capacitance change over temperature. Capacitance
change due to DC bias with X5R and X7R capacitors
is better than Y5V and Z5U capacitors, but can still be
significant enough to drop capacitor values below ap-
propriate levels. Capacitor DC bias characteristics tend to
improve as component case size increases, but expected
capacitanceatoperatingvoltageshouldbeverified.Voltage
and temperature coefficients are not the only sources of
problems. Some ceramic capacitors have a piezoelectric
response.Apiezoelectricdevicegeneratesvoltageacross
its terminals due to mechanical stress, similar to the way
a piezoelectric microphone works. For a ceramic capaci-
tor the stress can be induced by vibrations in the system
or thermal transients. For this reason, an X7R capacitor
with a 16V maximum voltage rating is recommended for
the REF/BYP pin.
This is due to the inductance of the wire forming an LC
tank circuit with the input capacitor and not a result of the
LT3070 being unstable. The self inductance, or isolated
inductance, of a wire is directly proportional to its length.
However, the diameter of a wire does not have a major
influence on its self inductance. For example, one inch of
18-AWG, 0.04 inch diameter wire has 28nH of self induc-
tance. The self inductance of a 2-AWG isolated wire with
a diameter of 0.26 inch is about half the inductance of a
18-AWG wire. The overall self inductance of a wire can
be reduced in two ways. One is to divide the current flow-
ing towards the LT3070 between two parallel conductors
which flows in the same direction in each. In this case,
the farther the wires are placed apart from each other, the
more inductance will be reduced, up to a 50ꢀ reduction
when placed a few inches apart. Splitting the wires basi-
cally connects two eꢁual inductors in parallel. However,
when placed in close proximity from each other, mutual
inductance is added to the overall self inductance of the
wires. Themosteffectivewaytoreduceoverallinductance
is to place the forward and return-current conductors (the
wire for the input and the wire for the return ground) in
verycloseproximity.Two18-AWGwiresseparatedby0.05
inch reduce the overall self inductance to about one-forth
of a single isolated wire. If the LT3070 is powered by a
batterymountedincloseproximitywithgroundandpower
planes on the same circuit board, a 47μF input capacitor
is sufficient for stability. However, if the LT3070 is pow-
ered by a distant supply, use a low ESR, large value input
capacitor on the order of 330μF. As power supply output
impedancevaries,theminimuminputcapacitanceneeded
for application stability also varies.
Stability and Input Capacitance
The LT3070 is stable with a minimum capacitance of
47μF connected to its IN pins. Use low ESR capacitors to
minimize instantaneous voltage drops under large load
transient conditions. Large V droops during large load
IN
transients may cause the regulator to enter dropout with
corresponding degradation in load transient response.
Increased values of input and output capacitance may be
necessary depending on an application’s reꢁuirements.
Sufficient input capacitance is critical as the circuit is
intentionally operated close to dropout to minimize power.
Ideally, the output impedance of the supply that powers
IN should be less than 10mΩ to support a 5A load with
large transients.
Bias Pin Capacitance Requirements
The BIAS pin supplies current to most of the internal
control circuitry and the output stage driving the pass
transistor. The LT3070 reꢁuires a minimum 2.2μF bypass
capacitor for stability and proper operation. To ensure
proper operation, the BIAS voltage must conform to the
following eꢁuation:
In cases where wire is used to connect a power supply
to the input of the LT3070 (and also from the ground of
the LT3070 back to the power supply ground), large input
capacitors are reꢁuired to avoid an unstable application.
(1.2 • V ) + 935mV ≤ V
≤ 3.6V
BIAS
OUT
3070p
16
LT3070
APPLICATIONS INFORMATION
Load Regulation
values of input-to-output voltage up to the absolute maxi-
mum voltage rating. See the Current Limit vs V curve in
IN
The LT3070 provides a Kelvin sense pin for V , allowing
OUT
the Typical Performance Characteristics.
the application to correct for parasitic package and PCB
I-R drops. However, LTC recommends that the SENSE pin
terminate in close proximity to the LT3070’s OUT pins;
this minimizes parasitic inductance and optimizes regula-
tion. The LT3070 handles moderate levels of output line
Duringstart-up,aftertheBIASvoltagehascleareditsUVLO
threshold and V is increasing, output voltage increases
IN
at the rate of current limit charging C
.
OUT
With a high input voltage, a problem can occur where
in removal of an output short will not allow the output
voltage to recover. Other regulators also exhibit this phe-
nomenon, so it is not uniꢁue to the LT3070. The load line
for such a load may intersect the output current curve at
two points: normal operation and the 50A restricted load
current settings. A common situation is immediately after
the removal of a short circuit, but with a static load ≥ 1A.
impedance, but excessive impedance between V
OUT
and adversely affects stability.
and
OUT
C
causes excessive phase shift in the feedback loop
Figure 1 in the Pin Functions section illustrates the Kelvin-
Sense connection method that eliminates voltage drops
duetoPCBtraceresistance.However,notethatthevoltage
drop across the external PCB traces adds to the dropout
voltage of the regulator. The SENSE pin input bias current
depends on the selected output voltage. SENSE pin input
In this situation, removal of the load or reduction of I
OUT
to return
to <1A will clear this condition and allow V
to normal regulation.
OUT
currentvariesfrom50μAtypicallyatV
=0.8Vto300μA
OUT
typically at V
= 1.8V.
OUT
Reverse Voltage
Short-Circuit and Overload Recovery
The LT3070 incorporates a circuit that detects if V de-
IN
Like many IC power regulators, the LT3070 has safe op-
erating area (SOA) protection. The safe area protection
decreasescurrentlimitasinput-to-outputvoltageincreases
and keeps the power transistor inside a safe operating
region for all values of input-to-output voltage up to the
creases below V . This reverse-voltage detector has
OUT
a typical threshold of about (V – V ) = –6mV. If the
IN
OUT
threshold is exceeded, this detector circuit turns off the
drivetotheinternalNMOSpasstransistor, therebyturning
off the output. The output pulls low with the load current
discharging the output capacitance. This circuit’s intent
is to limit and prevent back-feed current from OUT to IN
if the input voltage collapses due to a fault or overload
condition.
absolute maximum voltage rating. V
must be above
BIAS
the UVLO threshold for any function. The LT3070 has a
precision current limit specified at 10ꢀ that is active if
V
is above UVLO, regardless of the value of V .
BIAS
IN
Under conditions of maximum I
IN OUT
and maximum
LOAD
Thermal Considerations
V -V
the device’s power dissipation peaks at about
The LT3070’s maximum rated junction temperature of
125°C limits its power handling capability and is domi-
nated by the output current multiplied by the input/output
voltage differential:
3W. If ambient temperature is high enough, die junction
temperature will exceed the 125°C maximum operating
temperature. If this occurs, the LT3070 relies on two
additional thermal safety features. At about 145°C, the
PWRGD output pulls low providing an early warning of an
impendingthermalshutdowncondition.At165°Ctypically,
the LT3070’s thermal shutdown engages and the output is
shut down until the IC temperature falls below the thermal
hysteresislimit.TheSOAprotectiondecreasescurrentlimit
as the IN-to-OUT voltage increases and keeps the power
dissipation at safe levels for all values of input-to-output
voltage. The LT3070 provides some output current at all
I
• (V – V
)
OUT
IN
OUT
The LT3070’s internal power and thermal limiting circuitry
protect it under overload conditions. For continuous nor-
mal load conditions, do not exceed the maximum junction
temperature of 125°C. Give careful consideration to all
sources of thermal resistance from junction to ambient.
Thisincludesjunctiontocase, case-to-heatsinkinterface,
3070p
17
LT3070
APPLICATIONS INFORMATION
heat sink resistance or circuit board to ambient as the
applicationdictates.Also,consideradditionalheatsources
mountedinproximitytotheLT3070.TheLT3070isasurface
mount device and as such, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Surface mount heat sinks and
plated through-holes can also be used to spread the heat
generated by power devices. Junction-to-case thermal
resistance is specified from the IC junction to the bottom
of the case directly below the die. This is the lowest resis-
tance path for heat flow. Proper mounting is reꢁuired to
ensure the best possible thermal flow from this area of the
packagetotheheatsinkingmaterial.NotethattheExposed
Pad is electrically connected to GND. Table 3 lists thermal
resistance for several different copper areas given a fixed
board size. All measurements were taken in still air on a
4-layer 1/16" FR-4 board with one ounce copper.
thus:
P = 4A(1.26V – 0.9V) + (6.91mA – 0.87mA)0.9V +
0.87mA(2.5V) = 1.448W
With the QFN package soldered to maximum copper
area, the thermal resistance is 30°C/W. So the junction
temperature rise above ambient eꢁuals:
1.448W at 30°C/W = 43.44°C
The maximum junction temperature eꢁuals the maximum
ambienttemperatureplusthemaximumjunctiontempera-
ture rise above ambient or:
T
= 50°C + 43.44°C = 93.44°C
JMAX
Applications that cannot support extensive PCB space for
heatsinking the LT3070 will reꢁuire a derating of output
current or increased airflow.
Paralleling Devices for Higher I
Table ꢁ, UDF Plastic Package, 28-Lead QFN
OUT
COPPER AREA
MultipleLT3070smaybeparalleledtoobtainhigheroutput
current.Thisparallelingconceptborrowsfromthescheme
employed by the LT3080.
THERMAL RESISTANCE
TOPSIDE* BACK SIDE BOARD AREA (JUNCTION-TO-AMBIENT)
2
2
2
2
2
2
2
2
2
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
30°C/W
32°C/W
33°C/W
35°C/W
2
1000mm
To accomplish this paralleling, tie the IN pins and the OUT
pinsofthemultipledevicestogether. Also, tietheREF/BYP
pins of the multiple outputs together. This effectively gives
an averaged value of multiple 600mV reference voltage
sources. The OUT of each LT3070 is connected to the
common load using a small piece of PC trace as a ballast
resistor (≅2mΩ) or an actual sense resistor, beyond the
primary output capacitors of each regulator. The ballast
resistorensuresoutputcurrentsharing(seeFigures8and
9). Keep this ballast trace area free of solder to maintain
a controlled resistance.
2
225mm
100mm
2
*Device is mounted on topside
Calculating Junction Temperature
Example: Given an output voltage of 0.9V, an input voltage
range of 1.2V 5ꢀ, a BIAS voltage of 2.5V, a maximum
outputcurrentof4Aandamaximumambienttemperature
of 50°C, what will the maximum junction temperature
be?
The power dissipated by the device eꢁuals:
Table 4 shows a simple guideline for PCB trace resistance
as a function of weight and trace width.
I
• (V
BIAS
– V ) + (I – I ) • V
BIAS GND OUT
OUT(MAX)
IN(MAX)
OUT
+ I
• V
GND
Table 4. PC Board Trace Resistance
where:
WEIGHT (Oz)
100 MIL WIDTH
200 MIL WIDTH
1
2
5.43
2.71
2.71
1.36
I
= 4A
OUT(MAX)
V
= 1.26V
IN(MAX)
*Trace resistance is measured in milliohms/in
I
I
at (I
= 4A, V
= 2.5V) = 6.91mA
= 2.5V) = 0.87mA
BIAS
GND
OUT
OUT
BIAS
at (I
= 4A, V
BIAS
3070p
18
LT3070
APPLICATIONS INFORMATION
Quieting the Noise
capacitor minimizes reference noise to 10μV
at the
RMS
600mV REF/BYP pin, eꢁuivalently a 17μV contribution to
output noise at V = 1V. See the Typical Performance
The LT3070 offers numerous noise performance advan-
tages. Each LDO has several sources of noise. An LDO’s
most critical noise source is the reference, followed by
the LDO error amplifier. Traditional low noise regulators
bufferthevoltagereferenceouttoanexternalpin(usually
through a large value resistor) to allow for bypassing and
noise reduction of reference noise. The LT3070 deviates
from the traditional voltage reference by generating a
OUT
Characteristics for Noise vs Output Voltage performance
as a function of C
.
BYP/REF
This approach also accommodates reference sharing
between LT3070 regulators that are hooked up in cur-
rent sharing applications. The REF/BYP filter capacitor
delays the initial power-up time by a factor of the RC time
low voltage V
from a reference current into an inter-
constant. V remains active in nap mode, thus start-up
REF
REF
nal resistor ≅19k. This intermediate impedance node
(REF/BYP)facilitatesexternalfilteringdirectly.A10nFfilter
time is significantly reduced and well controlled coming
out of nap mode (EN:LO↑HI).
50k
V
BIAS
PWRGD
3.3V
2.2μF
BIAS
V
IN
IN
PWRGD
SENSE
1.5V
330μF
EN
V
1.2V
5A
OUT
LT3070
OUT
V
V
V
O0
O1
O2
2.2μF*
0.01μF
4.7μF*
10μF*
NC
NC
MARGSEL
MARGTOL
VIOC
*X5R OR X7R
REF/BYP
GND
1nF
3070 F06
Figure 6. 1.5V to 1.2V Linear Regulator
3070p
19
LT3070
APPLICATIONS INFORMATION
50k
V
BIAS
3.3V
PWRGD
47μF
6.3V
s3
2.2μF
1Ω
50k
BIAS
EN
IN
PWRGD
SENSE
0.1μF
CLKOUT RUN PV PV
IN
SV
I
I
V
OUT
= 1V/5A
4.7μF*
IN
IN THM
TH
NC
47μF
LOAD
10μF*
LT3070
OUT
V
V
V
O2
O1
O0
NC
NC
NC
NC
NC
15k
1ꢀ
2.2μF*
SGND
PLLLPF
TRACK
15k
V
MARGSEL
MARGTOL
VIOC
FB
*X5R OR X7R
20k
1ꢀ
100pF
10pF
PV
PV
PV
PV
IN
IN
IN
IN
REF/BYP
GND
0.01μF
TBD
TBD
TBD
SW
SW
SW
LTC3415EUHF
3070 F07
SW
SW
SW
NOTE: LTC3415 SWITCHER 2MHz INTERNAL OSCILLATOR
SW
SW
MODE
CLKIN
PHMODE
PGOOD
BSEL
MGN
PGND
PGND PGND PGND PGND PGND PGND PGND
100μF
6.3V
s3
1.3V/7A
0.2μH
Figure 7. Regulator with VIOC Buck Control
3070p
20
LT3070
APPLICATIONS INFORMATION
50k
V
BIAS
3.3V
PWRGD
47μF
6.3V
s3
2.2μF
1Ω
50k
BIAS
SGND
EN
IN
SENSE
OUT
0.1μF
V
= 1.0V/5A
P.O.L 1
OUT
CLKOUT RUN PV PV
IN
SV
I
I
IN
IN THM
TH
NC
47μF
LT3070
10μF*
V
V
V
2.2μF*
4.7μF*
O2
O1
O0
NC
NC
NC
NC
NC
PWRGD
15k
1ꢀ
SGND
PLLLPF
TRACK
R
TRACE
*X5R OR X7R
15k
2mΩ
V
FB
MARGSEL
MARGTOL
VIOC
CONTROLLED
18k
1ꢀ
100pF
10pF
PV
PV
PV
PV
IN
IN
IN
IN
REF/BYP
1nF
GND
0.01μF
SW
SW
SW
LTC3415EUHF
1V
10A
POWER PLANE
SW
SW
SW
SW
SW
2.2μF
50k
MODE
CLKIN
PHMODE
PGOOD
BSEL
MGN
R
TRACE
2mΩ
BIAS
PGND
CONTROLLED
EN
IN
SENSE
OUT
V
= 1.0V/5A
4.7μF*
OUT
P.O.L 2
PGND PGND PGND PGND PGND PGND PGND
47μF
1nF
LT3070
10μF*
V
V
V
2.2μF*
O2
NC
NC
NC
NC
PWRGD
O1
O0
100μF
6.3V
s3
*X5R OR X7R
MARGSEL
MARGTOL
VIOC
1.3V/7A
REF/BYP
0.2μH
GND
0.01μF
3070 F08
NOTE: LTC3415 SWITCHER 2MHz INTERNAL OSCILLATOR
Figure 8. 1V, 10A Point-of-Load Current Sharing Regulators
3070p
21
LT3070
TYPICAL APPLICATIONS
50k
PWRGD
2.2μF*
2.2μF
V
BIAS
OUT
1V
IN
SENSE
OUT
P.O.L. 1
47μF
4.7μF*
10μF*
EN
R
TRACE
2mΩ
CONTROLLED
LT3070 (1)
V
V
V
O2
O1
O0
*X5R OR X7R
NC
NC
NC
NC
PWRGD
MARGSEL
MARGTOL
VIOC
1V
10A
REF/BYP
POWER PLANE
1nF
GND
0.01μF
V
BIAS
3.3V
R
TRACE
2mΩ
2.2μF
50k
CONTROLLED
SW1 CLKIN1 CLKOUT1 CLKIN2 CLKOUT2
V
BUCK1
= 1.3V/8A
V
BIAS
OUT
1V
V
V
IN
EN
V
SENSE
OUT
IN1
SV
OUT1
100μF
6.3V
s3
P.O.L. 2
2.2μF*
4.7μF*
10μF*
10μF
MGN1
FB1
47μF
IN1
RUN1
LT3070 (2)
O2
R
FB1
PLLLPF1
MODE1
PHMODE1
TRACK1
ITH1
*X5R OR X7R
8.5k
NC
NC
NC
NC
V
O1
V
O0
PWRGD
ITHM1
BSEL1
PGOOD1
MARGSEL
MARGTOL
VIOC
LTM4616
V
BUCK2
= 2.1V/8A
REF/BYP
TBD
TBD
TBD
V
V
OUT2
MGN2
FB2
IN2
SV
GND
0.01μF
100μF
6.3V
s3
10μF
IN2
RUN2
R
FB2
3.96k
PLLLPF2
MODE2
PHMODE2
TRACK2
ITH2
2.2μF
ITHM2
BSEL2
PGOOD2
50k
V
1.8V
5A
OUT
BIAS
SW2 SGND1 GND1 SGND2 GND2
IN
SENSE
OUT
47μF
2.2μF*
4.7μF*
10μF*
EN
LT3070 (3)
V
V
V
O2
NOTE:
*X5R OR X7R
NC
NC
NC
NC
PWRGD
O1
O0
THE TWO LTM4616 MODULE CHANNELS ARE
INDEPENDENTLY CONTROLLED BY THE VIOC
CONTROLS FROM THE LINEAR REGULATORS
MARGSEL
MARGTOL
VIOC
REF/BYP
GND
TBD
TBD
TBD
0.01μF
2.2μF*
2.2μF
V
1.5V
2.5A
BIAS
OUT
IN
SENSE
OUT
47μF
4.7μF*
10μF*
EN
LT3070 (4)
NC
NC
V
V
V
O2
*X5R OR X7R
PWRGD
O1
O0
NC
NC
MARGSEL
MARGTOL
VIOC
REF/BYP
1nF
GND
0.01μF
3070 F09
Figure 9. Triple Output Supply Providing 1V, 10A and 1.8V, 5A and 1.5V, 2.5A
3070p
22
LT3070
PACKAGE DESCRIPTION
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 p0.05
4.50 p 0.05
3.10 p 0.05
2.50 REF
2.65 p 0.05
3.65 p 0.05
PACKAGE OUTLINE
0.25 p0.05
0.50 BSC
3.50 REF
4.10 p 0.05
5.50 p 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.20 OR 0.35
s 45o CHAMFER
2.50 REF
R = 0.115
TYP
R = 0.05
TYP
0.75 p 0.05
4.00 p 0.10
(2 SIDES)
27
28
0.40 p 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 p 0.10
(2 SIDES)
3.50 REF
3.65 p 0.10
2.65 p 0.10
(UFD28) QFN 0506 REV B
0.25 p 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3070p
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LT3070
RELATED PARTS
PART
DESCRIPTION
COMMENTS
LT1761
100mA, Low Noise LDO
300mV Dropout Voltage, Low Noise: 20μV
, V : 1.8V to 20V,
RMS IN
ThinSOT package
LT1762
150mA, Low Noise LDO
300mV Dropout Voltage, Low Noise: 20μV
, V : 1.8V to 20V,
RMS IN
MS8 package
LT1763
500mA, Low Noise LDO
300mV Dropout Voltage, Low Noise: 20μV
, V : 1.8V to 20V,
RMS IN
SO-8 Package
LT1764/A
LTC®1844
LT1962
3A, Fast Transient Response, Low Noise LDO
150mA, Very Low Dropout LDO
300mA, Low Noise LDO
340mV Dropout Voltage, Low Noise: 40μV
, V : 2.7V to 20V,
RMS IN
TO-220 and DD Packages “A” Version Stable Also with Ceramic Caps
80mV Dropout Voltage, Low Noise <30μV
, V : 1.6V to 6.5V,
RMS IN
Stable with 1μF Output Capacitors, ThinSOT Package
270mV Dropout Voltage, Low Noise: 20μV
MS8 Package
, V : 1.8V to 20V,
RMS IN
LT1963/A
1.5A Low Noise, Fast Transient Response LDO
340mV Dropout Voltage, Low Noise: 40μV
, V : 2.5V to 20V,
RMS IN
“A” Version Stable with Ceramic Caps, TO-220, DD, SOT-223 and
SO-8 Packages
LT1965
LT3020
LT3021
1.1A, Low Noise, Low Dropout Linear Regulator
100mA, Low Voltage VLDO™ Linear Regulator
290mV Dropout Voltage, Low Noise: 40μV
, V : 1.8V to 20V,
RMS IN
V
: 1.2V to 19.5V, Stable with Ceramic Caps, TO-220, DD-Pak,
OUT
MSOP and 3mm × 3mm DFN Packages
V : 0.9V to 10V, V : 0.2V to 5V (Min), V = 0.15V, I = 120μA,
IN
OUT
RMS(P-P)
DO
Q
Noise: <250μV
, Stable with 2.2μF Ceramic Capacitors,
DFN-8, MS8 Packages
500mA, Low Voltage, Very Low Dropout VLDO
Linear Regulator
V : 0.9V to 10V, Dropout Voltage = 160mV (Typ), Adjustable Output
IN
(V = V
= 200mV), Fixed Output Voltages: 1.2V, 1.5V, 1.8V,
REF
OUT(MIN)
Stable with Low ESR, Ceramic Output Capacitors 16-Pin DFN
(5mm × 5mm) and 8-Lead SO Packages
LT3080/LT3080-1
1.1A, Parallelable, Low Noise, Low Dropout Linear Regulator 300mV Dropout Voltage (2-Supply Operation), Low Noise: 40μV
,
RMS
V : 1.2V to 36V, V : 0V to 35.7V, Current-Based Reference with
IN
OUT
1 Resistor V
Set; Directly Parallelable (No Op Amp Reꢁuired),
OUT
Stable with Ceramic Caps, TO-220, SOT-223, MSOP-8 and 3mm
× 3mm DFN-8 Packages; LT3080-1 has Integrated Internal Ballast
Resistor
LT3085
500mA, Parallelable, Low Noise, Low Dropout
Linear Regulator
275mV Dropout Voltage (2-Supply Operation), Low Noise: 40μV
RMS
,
V : 1.2V to 36V, V : 0V to 35.7V, Current-Based Reference with
IN
OUT
1 Resistor V
Set; Directly Parallelable (No Op Amp Reꢁuired),
OUT
Stable with Ceramic Caps, MSOP-8 and 2mm × 3mm DFN-6
Packages
LTC3025
300mA Micropower VLDO Linear Regulator
V : 0.9V to 5.5V, Dropout Voltage: 45mV, Low Noise: 80μV
Q
, Low
RMS
IN
I : 54μA, 2mm × 2mm 6-Lead DFN Package
LTC3025-1/
LTC3025-2
500mA Micropower VLDO Linear Regulator
in 2mm × 2mm DFN
V = 0.9V to 5.5V, Dropout Voltage: 75mV, Low Noise 80μVRMS,
IN
Low I : 54μA, Fixed Output: 1.2V (LTC3025-2); Adjustable Output
Q
Range: 0.4V to 3.6V (LTC3025-1) 2mm × 2mm 6-Lead DFN Package
LTC3026
LTC3035
1.5A, Low Input Voltage VLDO Regulator
V : 1.14V to 3.5V (Boost Enabled), 1.14V to 5.5V (with External
IN
5V), V = 0.1V, I = 950μA, Stable with 10μF Ceramic Capacitors,
DO
Q
10-Lead MSOP and DFN-10 Packages
300mA VLDO Linear Regulator with Charge Pump
V : 1.7V to 5.5V, V : 0.4V to 3.6V, Dropout Voltage: 45mV,
IN
OUT
I = 100μA, 3mm × 2mm DFN-8 Bias Generator
Q
VLDO is a trademark of Linear Technology Corporation.
3070p
LT 0709 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
© LINEAR TECHNOLOGY CORPORATION 2009
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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