LT3071MPUFD-TR [Linear]
5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator with Analog Margining; 5A ，低噪声，可编程输出，一个85mV压差线性稳压器，具有模拟裕
| 型号： | LT3071MPUFD-TR |
| 厂家： | 
Linear |
| 描述： | 5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator with Analog Margining |
| 文件： | 总28页 (文件大小：536K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3071
5A, Low Noise,
Programmable Output, 85mV
Dropout Linear Regulator
with Analog Margining
FeAtures
Description
TheꢀLT®3071ꢀisꢀaꢀlowꢀvoltage,ꢀUltraFast™ꢀtransientꢀre-
sponseꢀlinearꢀregulator.ꢀTheꢀdeviceꢀsuppliesꢀupꢀtoꢀ5Aꢀofꢀ
outputꢀcurrentꢀwithꢀaꢀtypicalꢀdropoutꢀvoltageꢀofꢀ85mV.ꢀ
Aꢀ0.01µFꢀreferenceꢀbypassꢀcapacitorꢀdecreasesꢀoutputꢀ
n
ꢀ Output Current: 5A
n
Dropout Voltage: 85mV Typical
n
Digitally Programmable V : 0.8V to 1.8V
OUT
n
Analog Output Margining: 10ꢀ Range
n
Low Output Noise: 25µV
(10Hz to 100kHz)
voltageꢀnoiseꢀtoꢀ25µV
.ꢀTheꢀLT3071’sꢀhighꢀbandwidthꢀ
RMS
RMS
n
n
n
n
n
Parallel Multiple Devices for 10A or More
permitsꢀtheꢀuseꢀofꢀlowꢀESRꢀceramicꢀcapacitors,ꢀsavingꢀ
bulkꢀcapacitanceꢀandꢀcost.ꢀTheꢀLT3071’sꢀfeaturesꢀmakeꢀ
itꢀidealꢀforꢀhighꢀperformanceꢀFPGAs,ꢀmicroprocessorsꢀorꢀ
sensitiveꢀcommunicationꢀsupplyꢀapplications.ꢀ
Precision Current Limit: 20ꢀ
ꢀ OutputꢀCurrentꢀMonitor:ꢀI
ꢀ=ꢀI /2500
MON OUT
ꢀ 1ꢁꢀAccuracyꢀOverꢀLine,ꢀLoadꢀandꢀTemperature
ꢀ StableꢀwithꢀLowꢀESRꢀCeramicꢀOutputꢀCapacitorsꢀ
(15µFꢀMinimum)
Outputꢀvoltageꢀisꢀdigitallyꢀselectableꢀinꢀ50mVꢀincrementsꢀ
overꢀaꢀ0.8Vꢀtoꢀ1.8Vꢀrange.ꢀAnꢀanalogꢀmarginingꢀfunctionꢀ
allowsꢀtheꢀuserꢀtoꢀadjustꢀsystemꢀoutputꢀvoltageꢀoverꢀaꢀ
continuousꢀ 10ꢁꢀrange.ꢀTheꢀICꢀincorporatesꢀaꢀuniqueꢀ
trackingꢀfunctionꢀtoꢀcontrolꢀaꢀbuckꢀregulatorꢀpoweringꢀ
theꢀLT3071’sꢀinput.ꢀThisꢀtrackingꢀfunctionꢀdrivesꢀtheꢀbuckꢀ
n
n
n
ꢀ HighꢀFrequencyꢀPSRR:ꢀ30dBꢀatꢀ1MHzꢀ
ꢀ EnableꢀFunctionꢀTurnsꢀOutputꢀOn/Off
ꢀ VIOCꢀPinꢀControlsꢀBuckꢀConverterꢀtoꢀMaintainꢀLowꢀ
PowerꢀDissipationꢀandꢀOptimizeꢀEfficiency
ꢀ PWRGD/UVLO/ThermalꢀShutdownꢀFlag
ꢀ CurrentꢀLimitꢀwithꢀFoldbackꢀProtection
ꢀ ThermalꢀShutdown
n
n
n
n
regulatorꢀtoꢀmaintainꢀtheꢀLT3071’sꢀinputꢀvoltageꢀtoꢀV
+ꢀ300mV,ꢀminimizingꢀpowerꢀdissipation.ꢀ
ꢀ
OUT
InternalꢀprotectionꢀincludesꢀUVLO,ꢀreverse-currentꢀprotec-
ꢀ 28-Leadꢀ(4mmꢀ×ꢀ5mmꢀ×ꢀ0.75mm)ꢀQFNꢀPackage
tion,ꢀprecisionꢀcurrentꢀlimitingꢀwithꢀpowerꢀfoldbackꢀandꢀ
thermalꢀshutdown.ꢀTheꢀLT3071ꢀregulatorꢀisꢀavailableꢀinꢀaꢀ
thermallyꢀenhancedꢀ28-lead,ꢀ4mmꢀ×ꢀ5mmꢀQFNꢀpackage.
ApplicAtions
n
ꢀ FPGAꢀandꢀDSPꢀSupplies
L,ꢀLT,ꢀLTC,ꢀLTM,ꢀLinearꢀTechnologyꢀandꢀtheꢀLinearꢀlogoꢀareꢀregisteredꢀtrademarksꢀofꢀLinearꢀ
TechnologyꢀCorporation.ꢀUltraFastꢀandꢀVLDOꢀareꢀtrademarksꢀofꢀLinearꢀTechnologyꢀCorporation.ꢀꢀ
Allꢀotherꢀtrademarksꢀareꢀtheꢀpropertyꢀofꢀtheirꢀrespectiveꢀowners.ꢀPatentsꢀpending.
n
ꢀ ASICꢀandꢀMicroprocessorꢀSupplies
n
ꢀ ServersꢀandꢀStorageꢀDevices
n
ꢀ PostꢀBuckꢀRegulationꢀandꢀSupplyꢀIsolation
typicAl ApplicAtion
Dropout Voltage
150
0.9V, 5A Regulator
V
= V
OUT(NOMINAL)
IN
50k
V
BIAS
2.2V TO 3.6V
PWRGD
120
90
60
30
0
2.2µF
BIAS
V
IN
1.2V
IN
EN
V
PWRGD
SENSE
V
BIAS
= 1.8V
= 3.3V
330µF
OUT
V
0.9V
5A
OUT
V
LT3071
OUT
O0
2.2µF*
4.7µF*
10µF*
V
O1
V
O2
V
V
= 0.8V
= 2.5V
OUT
BIAS
*X5R OR X7R CAPACITORS
V
MON
NC
2V AT 5A
MARGA
VIOC
I
MON
FULL SCALE
REF/BYP
GND
1k
0
1
2
3
4
5
1nF
0.01µF
OUTPUT CURRENT (A)
3071 TA01b
3071 TA01a
3071f
ꢀ
MARGAꢀInput............................................... –0.3Vꢀtoꢀ4V
VIOC,ꢀPWRGD,ꢀI
REF/BYPꢀOutput
ꢀOutputs
....................... –0.3Vꢀtoꢀ4V
........................................... –0.3Vꢀtoꢀ4V
.......................... Indefinite
OutputꢀShort-CircuitꢀDuration
BIAS............................................................. –0.3Vꢀtoꢀ4V
LT3071
Absolute mAximum rAtings
pin conFigurAtion
(Note 1)
TOP VIEW
IN,ꢀOUTꢀ..................................................... –0.3Vꢀtoꢀ3.3V
28 27 26 25 24 23
V ,ꢀV ,ꢀV ꢀInputsꢀ.................................... –0.3Vꢀtoꢀ4V
O2 O1 O0
VIOC
PWRGD
REF/BYP
GND
IN
1
2
3
4
5
6
7
8
22
21
20
19
18
17
16
15
MARGA
I
MON
ENꢀInputꢀ....................................................... –0.3Vꢀtoꢀ4V
SENSEꢀInput................................................. –0.3Vꢀtoꢀ4V
GND
SENSE
OUT
29
GND
MON
IN
OUT
IN
OUT
IN
OUT
OperatingꢀJunctionꢀTemperatureꢀ(Noteꢀ2)
ꢀ LT3071E/LT3071I.............................. ꢀ–40°Cꢀtoꢀ125°C
9
10 11 12 13 14
UFD PACKAGE
ꢀ LT3071MPꢀ......................................... –55°Cꢀtoꢀ125°C
StorageꢀTemperatureꢀRangeꢀ.................. –65°Cꢀtoꢀ150°C
28-LEAD (4mm s 5mm) PLASTIC QFN
ꢀ
T
JMAX
ꢀ=ꢀ125°C,ꢀθ ꢀ=ꢀ30°C/WꢀTOꢀ35°C/Wꢀ
JA
EXPOSEDꢀPADꢀ(PINꢀ29)ꢀISꢀGND,ꢀMUSTꢀBEꢀSOLDEREDꢀTOꢀPCB
orDer inFormAtion
LEAD FREE FINISH
LT3071EUFD#PBF
LT3071IUFD#PBF
LT3071MPUFD#PBF
LEAD BASED FINISH
LT3071EUFD
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3071EUFD#TRPBF
LT3071IUFD#TRPBF
LT3071MPUFD#TRPBF
TAPE AND REEL
3071
–40°Cꢀtoꢀ125°C
–40°Cꢀtoꢀ125°C
–55°Cꢀtoꢀ125°C
TEMPERATURE RANGE
–40°Cꢀtoꢀ125°C
–40°Cꢀtoꢀ125°C
–55°Cꢀtoꢀ125°C
28-Leadꢀ(4mmꢀ×ꢀ5mm)ꢀPlasticꢀQFN
28-Leadꢀ(4mmꢀ×ꢀ5mm)ꢀPlasticꢀQFN
28-Leadꢀ(4mmꢀ×ꢀ5mm)ꢀPlasticꢀQFN
PACKAGE DESCRIPTION
3071
3071
PART MARKING*
3071
LT3071EUFD#TR
28-Leadꢀ(4mmꢀ×ꢀ5mm)ꢀPlasticꢀQFN
28-Leadꢀ(4mmꢀ×ꢀ5mm)ꢀPlasticꢀQFN
28-Leadꢀ(4mmꢀ×ꢀ5mm)ꢀPlasticꢀQFN
LT3071IUFD
LT3071IUFD#TR
3071
LT3071MPUFD
LT3071MPUFD#TR
3071
ConsultꢀLTCꢀMarketingꢀforꢀpartsꢀspecifiedꢀwithꢀwiderꢀoperatingꢀtemperatureꢀranges.ꢀ*Theꢀtemperatureꢀgradeꢀisꢀidentifiedꢀbyꢀaꢀlabelꢀonꢀtheꢀshippingꢀcontainer.
Forꢀmoreꢀinformationꢀonꢀleadꢀfreeꢀpartꢀmarking,ꢀgoꢀto:ꢀhttp://www.linear.com/leadfree/ꢀꢀ
Forꢀmoreꢀinformationꢀonꢀtapeꢀandꢀreelꢀspecifications,ꢀgoꢀto:ꢀhttp://www.linear.com/tapeandreel/
3071f
ꢁ
LT3071
electricAl chArActeristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. COUT = 15µF (Note 9), VIN = VOUT + 0.3V (Note 5), VBIAS = 2.5V unless
otherwise noted.
PARAMETER
CONDITIONS
MIN
0.95
2.2
TYP
MAX
3.0
UNITS
l
l
INꢀPinꢀVoltageꢀRange
BIASꢀPinꢀVoltageꢀRangeꢀ(Noteꢀ3)
RegulatedꢀOutputꢀVoltage
V ꢀ≥ꢀV ꢀ+ꢀ150mV,ꢀI =ꢀ5A
V
V
IN
OUT
OUT
3.6
l
l
l
l
l
l
l
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
ꢀ=ꢀ0.8V,ꢀ10mAꢀ≤ꢀI ꢀ≤ꢀ5A,ꢀ1.05Vꢀ≤ꢀV ꢀ≤ꢀ1.25Vꢀ
0.792ꢀ
0.891ꢀ
0.990ꢀ
1.089ꢀ
1.188ꢀ
1.485ꢀ
1.782
0.800ꢀ
0.900ꢀ
1.000ꢀ
1.100ꢀ
1.200ꢀ
1.500ꢀ
1.800
0.808ꢀ
0.909ꢀ
1.010ꢀ
1.111ꢀ
1.212ꢀ
1.515ꢀ
1.818
Vꢀ
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
ꢀ=ꢀ0.9V,ꢀ10mAꢀ≤ꢀI ꢀ≤ꢀ5A,ꢀ1.15Vꢀ≤ꢀV ꢀ≤ꢀ1.35Vꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
Vꢀ
V
ꢀ=ꢀ1V,ꢀ10mAꢀ≤ꢀI ꢀ≤ꢀ5A,ꢀ1.25Vꢀ≤ꢀV ꢀ≤ꢀ1.45Vꢀ
IN
ꢀ=ꢀ1.1V,ꢀ10mAꢀ≤ꢀI ꢀ≤ꢀ5A,ꢀ1.35Vꢀ≤ꢀV ꢀ≤ꢀ1.55Vꢀ
IN
IN
IN
IN
ꢀ=ꢀ1.2V,ꢀ10mAꢀ≤ꢀI ꢀ≤ꢀ5A,ꢀ1.45Vꢀ≤ꢀV ꢀ≤ꢀ1.65V,ꢀV
ꢀ=ꢀ3.3Vꢀ
ꢀ=ꢀ3.3Vꢀ
ꢀ=ꢀ3.3V
BIAS
BIAS
BIAS
ꢀ=ꢀ1.5V,ꢀ10mAꢀ≤ꢀI ꢀ≤ꢀ5A,ꢀ1.75Vꢀ≤ꢀV ꢀ≤ꢀ1.95V,ꢀV
ꢀ=ꢀ1.8V,ꢀ10mAꢀ≤ꢀI ꢀ≤ꢀ5A,ꢀ2.05Vꢀ≤ꢀV ꢀ≤ꢀ2.25V,ꢀV
l
l
RegulatedꢀOutputꢀVoltageꢀMarginingꢀ MARGAꢀ=ꢀ1.2Vꢀ
9.5ꢀ
–10.5
ꢀꢀ10ꢀ
–10
10.5ꢀ
–9.5
ꢁꢀ
ꢁ
(Noteꢀ3)
MARGAꢀ=ꢀ0V
l
l
LineꢀRegulationꢀtoꢀV
1.0ꢀ
1.0
mVꢀ
mV
V
OUT
V
OUT
ꢀ=ꢀ0.8V,ꢀ∆V ꢀ=ꢀ1.05Vꢀtoꢀ2.7V,ꢀV
ꢀ=ꢀ3.3V,ꢀI ꢀ=ꢀ10mAꢀ
OUT
IN
IN
BIAS
BIAS
ꢀ=ꢀ1.8V,ꢀ∆V ꢀ=ꢀ2.05Vꢀtoꢀ2.7V,ꢀV
ꢀ=ꢀ3.3V,ꢀI ꢀ=ꢀ10mA
OUT
IN
l
l
LineꢀRegulationꢀtoꢀV
2.0ꢀ
1.0
mVꢀ
mV
V ꢀ=ꢀ0.8V,ꢀ∆V
OUT
V ꢀ=ꢀ1.8V,ꢀ∆V
OUT
ꢀ=ꢀ2.2Vꢀtoꢀ3.6V,ꢀV ꢀ=ꢀ1.1V,ꢀI ꢀ=ꢀ10mAꢀꢀ
IN OUT
BIAS
BIAS
BIAS
ꢀ=ꢀ3.25Vꢀtoꢀ3.6V,ꢀV ꢀ=ꢀ2.1V,ꢀI ꢀ=ꢀ10mA
IN
OUT
LoadꢀRegulation,ꢀꢀ
OUT
V
V
V
V
V
ꢀ=ꢀ2.5V,ꢀV ꢀ=ꢀ1.05V,ꢀV ꢀ=ꢀ0.8V
–1.5
–2
–3.0ꢀ
–5.5
mVꢀ
mV
BIAS
BIAS
BIAS
BIAS
BIAS
IN
OUT
l
l
l
l
∆I ꢀ=ꢀ10mAꢀtoꢀ5A
ꢀ=ꢀ2.5V,ꢀV ꢀ=ꢀ1.25V,ꢀV ꢀ=ꢀ1.0V
–4.0ꢀ
–7.5
mVꢀ
mV
IN
OUT
ꢀ=ꢀ3.3V,ꢀV ꢀ=ꢀ1.45V,ꢀV ꢀ=ꢀ1.2V
–2
–4.0ꢀ
–7.5
mVꢀ
mV
IN
OUT
ꢀ=ꢀ3.3V,ꢀV ꢀ=ꢀ1.75V,ꢀV ꢀ=ꢀ1.5V
–2.5
–3
–5.0ꢀ
–9.0
mVꢀ
mV
IN
OUT
ꢀ=ꢀ3.3V,ꢀV ꢀ=ꢀ2.05V,ꢀV ꢀ=ꢀ1.8V
–7.0ꢀ
–13
mVꢀ
mV
IN
OUT
l
l
DropoutꢀVoltage,ꢀꢀ
I
I
ꢀ=ꢀ1A,ꢀV ꢀ=ꢀ1V
20
50
35
mV
OUT
OUT
V ꢀ=ꢀV
IN
ꢀ(Noteꢀ6)
OUT(NOMINAL)
ꢀ=ꢀ2.5A,ꢀV ꢀ=ꢀ1V
65ꢀ
85
mVꢀ
mV
OUT
OUT
l
l
I
ꢀ=ꢀ5A,ꢀV ꢀ=ꢀ1V
85
120ꢀ
150
mVꢀ
mV
OUT
OUT
l
l
SENSEꢀPinꢀCurrent
V ꢀ=ꢀ1.1V,ꢀV
BIAS
ꢀ=ꢀ0.8Vꢀ
SENSE
IN
35ꢀ
200
50ꢀ
300
65ꢀ
400
µAꢀ
µA
IN
V
ꢀ=ꢀ3.3V,ꢀV ꢀ=ꢀ2.1V,ꢀV
ꢀ=ꢀ1.8V
SENSE
l
l
GroundꢀPinꢀCurrent,ꢀꢀ
V ꢀ=ꢀ1.3V,ꢀV ꢀ=ꢀ1V
I
I
ꢀ=ꢀ10mAꢀ
OUT
ꢀ=ꢀ5A
OUT
0.65ꢀ
0.9
1.1ꢀ
1.35
1.8ꢀ
2.3
mAꢀ
mA
IN
OUT
l
BIASꢀPinꢀCurrentꢀinꢀNapꢀModeꢀ
ENꢀ=ꢀLowꢀ(AfterꢀPORꢀCompleted)
120
200
320
µA
l
l
l
l
l
l
BIASꢀPinꢀCurrent,ꢀꢀ
I
I
I
I
I
I
ꢀ=ꢀ10mAꢀ
ꢀ=ꢀ100mAꢀ
ꢀ=ꢀ500mAꢀ
ꢀ=ꢀ1Aꢀ
0.75ꢀ
1.25ꢀ
2.0ꢀ
2.6ꢀ
3.5ꢀ
4.5
1.08ꢀ
1.8ꢀ
3.0ꢀ
3.8ꢀ
5.2ꢀ
6.9
1.5ꢀ
2.4ꢀ
4.0ꢀ
5.0ꢀ
7.0ꢀ
10.0
mAꢀ
mAꢀ
mAꢀ
mAꢀ
mAꢀ
mA
OUT
OUT
OUT
OUT
OUT
OUT
V ꢀ=ꢀ1.3V,ꢀV ꢀ=ꢀ1Vꢀ
IN
OUT
ꢀ=ꢀ2.5Aꢀ
ꢀ=ꢀ5A
l
l
l
CurrentꢀLimitꢀ(Noteꢀ5)
V ꢀ–ꢀV ꢀ<ꢀ0.3V,ꢀV
ꢀ=ꢀ3.3Vꢀ
ꢀ=ꢀ3.3Vꢀ
ꢀ=ꢀ3.3V
5.1ꢀ
3.2ꢀ
1.2
6.4ꢀ
4.5ꢀ
2.5
7.7ꢀ
5.8ꢀ
4.3
Aꢀ
Aꢀ
A
IN
OUT
BIAS
BIAS
BIAS
V ꢀ–ꢀV ꢀ=ꢀ1.0V,ꢀV
IN
OUT
V ꢀ–ꢀV ꢀ=ꢀ1.7V,ꢀV
IN
OUT
l
l
l
I
I
ꢀFull-ScaleꢀOutputꢀCurrent
I
ꢀ=ꢀ5A,ꢀV ꢀ–ꢀV ꢀ=ꢀ0.3V,ꢀV ꢀ=ꢀ0.8V,ꢀ1.8V
1.6
2.0
400
300
2.4
460
450
mA
µA/A
µA
MON
OUT
IN
OUT
OUT
/I ꢀScale
MON OUT
1Aꢀ≤ꢀI ꢀ≤ꢀ5A,ꢀV ꢀ–ꢀV ꢀ=ꢀ0.3V,ꢀV ꢀ=ꢀ0.8V,ꢀ1.8V
340
OUT
IN
OUT
OUT
ReverseꢀOutputꢀCurrentꢀ(Noteꢀ8)
PWRGDꢀV ꢀThreshold
V ꢀ=ꢀ0V,ꢀV ꢀ=ꢀ1.8V
IN OUT
l
l
PercentageꢀofꢀV
PercentageꢀofꢀV
,ꢀV ꢀRisingꢀ
OUT(NOMINAL) OUT
87ꢀ
82
90ꢀ
85
93ꢀ
88
ꢁꢀ
ꢁ
OUT
,ꢀV ꢀFalling
OUT(NOMINAL) OUT
l
PWRGDꢀV
I
ꢀ=ꢀ200µAꢀ(FaultꢀCondition)
PWRGD
50
150
mV
OL
3071f
ꢂ
LT3071
electricAl chArActeristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. COUT = 15µF (Note 9), VIN = VOUT + 0.3V (Note 5), VBIAS = 2.5V unless
otherwise noted.
PARAMETER
ꢀUndervoltageꢀLockoutꢀ
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
V
V
V
ꢀRisingꢀ
BIAS
ꢀFalling
BIAS
1.1ꢀ
0.9
1.55ꢀ
1.4
2.1ꢀ
1.7
Vꢀ
V
BIAS
l
V -V ꢀServoꢀVoltageꢀbyꢀVIOC
IN OUT
250
300
350
mV
l
l
VIOCꢀOutputꢀCurrent
V ꢀ=ꢀV
IN
ꢀ+ꢀ150mV,ꢀSourcingꢀOutꢀofꢀtheꢀPinꢀ
OUT(NOMINAL)
ꢀ+ꢀ450mV,ꢀSinkingꢀIntoꢀtheꢀPin
OUT(NOMINAL)
160ꢀ
170
235ꢀ
255
310ꢀ
340
µAꢀ
µA
IN
V ꢀ=ꢀV
l
l
l
V ꢀInputꢀThresholdꢀ(Logic-0ꢀState),ꢀ InputꢀFalling
O2 O1 O0
0.25
V
IL
V
,ꢀV ,ꢀV ,ꢀMARGSEL,ꢀMARGTOL
V ꢀInputꢀRangeꢀ(Logic-ZꢀState),ꢀ
0.75
V
ꢀ–ꢀ0.9
BIAS
V
IZ
V
,ꢀV ,ꢀV ,ꢀMARGSEL,ꢀMARGTOL
O2 O1 O0
V ꢀInputꢀThresholdꢀ(Logic-1ꢀState),ꢀ InputꢀRising
V
ꢀ–ꢀ0.25
BIAS
V
IH
V
,ꢀV ,ꢀV ,ꢀMARGSEL,ꢀMARGTOL
O2 O1 O0
InputꢀHysteresisꢀ(BothꢀThresholds),ꢀ
,ꢀV ,ꢀV ,ꢀMARGSEL,ꢀMARGTOL
60
25
25
mV
µA
µA
V
O2 O1 O0
l
l
InputꢀCurrentꢀHigh,ꢀꢀ
,ꢀV ,ꢀV ,ꢀMARGSEL,ꢀMARGTOLꢀ
V ꢀ=ꢀV
ꢀ=ꢀ2.5V,ꢀCurrentꢀFlowsꢀIntoꢀPin
BIAS
40
40
IH
V
O2 O1 O0
InputꢀCurrentꢀLow,ꢀꢀ
,ꢀV ,ꢀV ,ꢀMARGSEL,ꢀMARGTOLꢀ
V ꢀ=ꢀ0V,ꢀV
IL
ꢀ=ꢀ2.5V,ꢀCurrentꢀFlowsꢀOutꢀofꢀPin
BIAS
V
O2 O1 O0
l
l
ENꢀPinꢀThreshold
V
V
ꢀ=ꢀOffꢀtoꢀOnꢀ
OUT
ꢀ=ꢀOnꢀtoꢀOff
OUT
ꢀ
1.4
Vꢀ
V
0.9
l
l
ENꢀPinꢀLogicꢀHighꢀCurrent
ENꢀPinꢀLogicꢀLowꢀCurrent
V
V
V
ꢀ=ꢀV
ꢀ=ꢀ2.5V
BIAS
2.5
4.0
6.5
0.1
µA
µA
dB
EN
ꢀ=ꢀ0V
EN
V
ꢀRippleꢀRejection
BIAS
=ꢀV ꢀ+ꢀ1.5V ,ꢀV
OUT
ꢀ=0.5V ꢀ,ꢀf ꢀ=ꢀ120Hz,ꢀꢀ
P-P RIPPLE
75
66
10
25
BIASꢀ
OUT
AVG RIPPLE
OUT
V ꢀ–ꢀV ꢀ=ꢀ300mV,ꢀI ꢀ=ꢀ2.5A
IN
V ꢀRippleꢀRejectionꢀꢀ
V
ꢀ=ꢀ2.5V,ꢀV
BIAS
ꢀ=ꢀ50mV ,ꢀf ꢀ=ꢀ120Hz,ꢀꢀ
P-Pꢀ RIPPLE
dB
IN
RIPPLE
(Notesꢀ3,ꢀ4,ꢀ5)
V ꢀ–ꢀV ꢀ=ꢀ300mV,ꢀI ꢀ=ꢀ2.5Aꢀ
IN
OUT
OUT
ReferenceꢀVoltageꢀNoiseꢀꢀ
(REF/BYPꢀPin)
C
ꢀ=ꢀ10nF,ꢀBWꢀ=ꢀ10Hzꢀtoꢀ100kHz
µV
µV
REF/BYP
RMS
OutputꢀVoltageꢀNoise
V
ꢀ=ꢀ1V,ꢀI ꢀ=ꢀ5A,ꢀC
OUT
=ꢀ10nF,ꢀC =ꢀ15µF,ꢀꢀ
OUTꢀ
OUT
REF/BYPꢀ
RMS
BWꢀ=ꢀ10Hzꢀtoꢀ100kHzꢀ
Note 5:ꢀTheꢀLT3071ꢀincorporatesꢀsafeꢀoperatingꢀareaꢀprotectionꢀcircuitry.ꢀ
Note 1:ꢀStressesꢀbeyondꢀthoseꢀlistedꢀunderꢀAbsoluteꢀMaximumꢀRatingsꢀ
mayꢀcauseꢀpermanentꢀdamageꢀtoꢀtheꢀdevice.ꢀExposureꢀtoꢀanyꢀAbsoluteꢀ
MaximumꢀRatingꢀconditionꢀforꢀextendedꢀperiodsꢀmayꢀaffectꢀdeviceꢀ
reliabilityꢀandꢀlifetime.
CurrentꢀlimitꢀdecreasesꢀasꢀtheꢀV -V ꢀvoltageꢀincreases.ꢀCurrentꢀlimitꢀ
IN OUT
foldbackꢀstartsꢀatꢀV ꢀ–ꢀV ꢀ>ꢀ500mV.ꢀSeeꢀtheꢀTypicalꢀPerformanceꢀ
IN
OUT
CharacteristicsꢀforꢀaꢀgraphꢀofꢀCurrentꢀLimitꢀvsꢀV ꢀ–ꢀV ꢀvoltage.ꢀTheꢀ
IN
OUT
currentꢀlimitꢀfoldbackꢀfeatureꢀisꢀindependentꢀofꢀtheꢀthermalꢀshutdownꢀ
circuity.
Note 2:ꢀTheꢀLT3071ꢀregulatorsꢀareꢀtestedꢀandꢀspecifiedꢀunderꢀpulseꢀloadꢀ
conditionsꢀsuchꢀthatꢀT ꢀ≅ꢀT .ꢀTheꢀLT3071Eꢀisꢀ100ꢁꢀtestedꢀatꢀT ꢀ=ꢀ25°C.ꢀ
J
A
A
Note 6:ꢀDropoutꢀvoltage,ꢀV ,ꢀisꢀtheꢀminimumꢀinputꢀtoꢀoutputꢀvoltageꢀ
Performanceꢀatꢀ–40°Cꢀandꢀ125°Cꢀisꢀassuredꢀbyꢀdesign,ꢀcharacterizationꢀ
andꢀcorrelationꢀwithꢀstatisticalꢀprocessꢀcontrols.ꢀTheꢀLT3071Iꢀisꢀ
guaranteedꢀoverꢀtheꢀ–40°Cꢀtoꢀ125°Cꢀoperatingꢀjunctionꢀtemperatureꢀrange.ꢀ
TheꢀLT3071MPꢀisꢀ100ꢁꢀtestedꢀandꢀguaranteedꢀoverꢀtheꢀ–55°Cꢀtoꢀ125°Cꢀ
operatingꢀjunctionꢀtemperatureꢀrange.ꢀ
DO
differentialꢀatꢀaꢀspecifiedꢀoutputꢀcurrent.ꢀInꢀdropout,ꢀtheꢀoutputꢀvoltageꢀ
equalsꢀV ꢀ–ꢀV .ꢀ
IN
DO
Note 7:ꢀGNDꢀpinꢀcurrentꢀisꢀtestedꢀwithꢀV ꢀ=ꢀV
ꢀ+ꢀ300mVꢀandꢀaꢀ
OUT(NOMINAL)
IN
currentꢀsourceꢀload.ꢀVIOCꢀisꢀaꢀbufferedꢀoutputꢀdeterminedꢀbyꢀtheꢀvalueꢀofꢀ
ꢀasꢀprogrammedꢀbyꢀtheꢀV -V ꢀpins.ꢀVIOC’sꢀoutputꢀisꢀindependentꢀofꢀ
V
OUT
Note 3:ꢀToꢀmaintainꢀproperꢀperformanceꢀandꢀregulation,ꢀtheꢀBIASꢀsupplyꢀ
O2 O0
theꢀmarginingꢀfunction.
voltageꢀmustꢀbeꢀhigherꢀthanꢀtheꢀINꢀsupplyꢀvoltage.ꢀForꢀaꢀgivenꢀV ,ꢀtheꢀ
OUTꢀ
BIASꢀvoltageꢀmustꢀsatisfyꢀtheꢀfollowingꢀconditions:ꢀ2.2Vꢀ≤ꢀV
ꢀ≤ꢀ3.6Vꢀ
Note 8:ꢀReverseꢀoutputꢀcurrentꢀisꢀtestedꢀwithꢀtheꢀINꢀpinsꢀgroundedꢀandꢀtheꢀ
OUTꢀ+ꢀSENSEꢀpinsꢀforcedꢀtoꢀtheꢀratedꢀoutputꢀvoltage.ꢀThisꢀisꢀmeasuredꢀasꢀ
currentꢀintoꢀtheꢀOUTꢀ+ꢀSENSEꢀpins.
BIAS
andꢀV
ꢀ≥ꢀ(1.25ꢀ•ꢀV ꢀ+ꢀ1V).ꢀForꢀV ꢀ≤ꢀ0.95V,ꢀtheꢀminimumꢀBIASꢀ
BIAS
OUT OUT
voltageꢀisꢀlimitedꢀtoꢀ2.2V.
Note 4:ꢀOperatingꢀconditionsꢀareꢀlimitedꢀbyꢀmaximumꢀjunctionꢀ
Note 9:ꢀFrequencyꢀCompensation:ꢀTheꢀLT3071ꢀmustꢀbeꢀfrequencyꢀ
temperature.ꢀTheꢀregulatedꢀoutputꢀvoltageꢀspecificationꢀdoesꢀnotꢀapplyꢀ
forꢀallꢀpossibleꢀcombinationsꢀofꢀinputꢀvoltageꢀandꢀoutputꢀcurrent.ꢀWhenꢀ
operatingꢀatꢀmaximumꢀoutputꢀcurrent,ꢀlimitꢀtheꢀinputꢀvoltageꢀrangeꢀtoꢀ
V ꢀ<ꢀV ꢀ+ꢀ500mV.
compensatedꢀatꢀitsꢀOUTꢀpinsꢀwithꢀaꢀminimumꢀC ꢀofꢀ15µFꢀconfiguredꢀ
OUT
asꢀaꢀclusterꢀofꢀ(15×)ꢀ1µFꢀceramicꢀcapacitorsꢀorꢀasꢀaꢀgraduatedꢀclusterꢀ
ofꢀ10µF/4.7µF/2.2µFꢀceramicꢀcapacitorsꢀofꢀtheꢀsameꢀcaseꢀsize.ꢀLinearꢀ
TechnologyꢀonlyꢀrecommendsꢀX5RꢀorꢀX7Rꢀdielectricꢀcapacitors.ꢀ
IN
OUT
3071f
ꢃ
LT3071
typicAl perFormAnce chArActeristics
Dropout Voltage vs IOUT
Dropout Voltage vs Temperature
Dropout Voltage vs Temperature
30
25
100
90
80
70
60
50
40
30
20
10
0
150
120
90
V
I
= V
OUT(NOMINAL)
OUT
V
= V
OUT(NOMINAL)
V
I
= V
OUT(NOMINAL)
OUT
IN
IN
IN
= 1A
T = 25°C
J
= 2.5A
20
15
V
BIAS
= 1.8V
= 3.3V
OUT
V
60
30
0
10
5
V
V
= 0.8V
= 2.5V
OUT
BIAS
V
V
V
= 1.8V, V
= 0.8V, V
= 1.2V, V
= 3.3V
= 2.5V
= 3.3V
V
V
V
= 1.8V, V
= 0.8V, V
= 1.2V, V
= 3.3V
= 2.5V
= 3.3V
OUT
OUT
OUT
BIAS
BIAS
BIAS
OUT
OUT
OUT
BIAS
BIAS
BIAS
0
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
0
1
2
3
4
5
TEMPERATURE (°C)
TEMPERATURE (°C)
OUTPUT CURRENT (A)
3071 G02
3071 G03
3071 G01
Output Voltage (0.8V)
vs Temperature
Dropout Voltage vs Temperature
Dropout Voltage vs VBIAS
200
180
160
140
120
100
80
0.808
0.806
0.804
0.802
0.800
0.798
0.796
0.794
0.792
150
120
90
V
OUT
= V
I
= 5A
OUT
I
= 10mA
IN
OUT(NOMINAL)
LOAD
I
= 5A
T = 25°C
J
60
30
0
60
40
V
V
V
= 1.8V, V
= 0.8V, V
= 1.2V, V
= 3.3V
= 2.5V
= 3.3V
OUT = 1.8V
OUT = 1.5V
OUT = 0.8V
OUT
OUT
OUT
BIAS
BIAS
BIAS
20
0
–75 –50 –25
0
25 50 75 100 125 150 175
2.2
2.6 2.8 3.0
3.2
3.6
–75 –50 –25
0
25 50 75 100 125 150 175
2.4
3.4
BIAS VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
3071 G04
3071 G05
3071 G06
Output Voltage (1V)
vs Temperature
Output Voltage (1.2V)
vs Temperature
Output Voltage (1.5V)
vs Temperature
1.010
1.008
1.006
1.004
1.002
1.000
0.998
0.996
0.994
0.992
0.990
1.212
1.208
1.515
1.510
I
= 10mA
I
= 10mA
I
= 10mA
LOAD
LOAD
LOAD
1.204
1.200
1.505
1.500
1.196
1.192
1.188
1.495
1.490
1.485
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3071 G07
3071 G08
3071 G09
3071f
ꢄ
LT3071
typicAl perFormAnce chArActeristics
Output Voltage (1.8V)
REF/BYP Pin Voltage
vs Temperature
vs Temperature
GND Pin Current vs IOUT
606
604
3.0
2.5
1.818
1.814
1.810
1.806
1.802
1.798
1.794
1.790
1.786
1.782
V
= V
+ 300mV
OUT
C
= 0.01µF
I
= 10mA
IN
REF/BYP
LOAD
T = 25°C
J
602
600
2.0
1.5
598
596
594
1.0
0.5
0
V
V
V
= 1.8V, V
= 1.2V, V
= 0.8V, V
= 3.3V
= 3.3V
= 2.5V
OUT
OUT
OUT
BIAS
BIAS
BIAS
–75 –50 –25
0
25 50 75 100 125 150 175
0
1
2
3
4
5
–75 –50 –25
0
25 50
175
75 100 125 150
TEMPERATURE (°C)
OUTPUT CURRENT (A)
TEMPERATURE (°C)
3071 G10
3071 G12
3071 G11
BIAS Pin Undervoltage Lockout
Threshold
BIAS Pin Current in Nap Mode
BIAS Pin Current vs IOUT
400
350
300
250
200
150
100
50
10
9
8
7
6
5
4
3
2
1
0
2.5
2.0
1.5
V
J
= V
+ 300mV
OUT
V
V
= 2.5V
IN
BIAS
EN
T = 25°C
= 0V
V
RISING
BIAS
V
BIAS
= 1.8V
= 3.3V
OUT
V
V
V
= 0.8V
OUT
BIAS
V
FALLING
= 2.5V
BIAS
1.0
0.5
0
0
0
1
2
3
4
5
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
75 100 125 150 175
25 50
OUTPUT CURRENT (A)
TEMPERATURE (°C)
TEMPERATURE (°C)
3071 G14
3071 G13
3071 G15
IMON vs IOUT
PWRGD Threshold Voltage
PWRGD V
OL vs Temperature
2.5
2.0
1.5
1.0
1.00
0.95
0.90
0.85
0.80
100
80
V
I
= 2.5V
PWRGD
V
V
V
= 3.3V
BIAS
V
V
= 2.5V
= 1V
BIAS
OUT
IN
BIAS
OUT
= 200µA
= 0.8V TO 1.8V
– V
= 300mV
OUT
T
= –55°C TO 125°C
J
60
V
RISING
OUT
40
20
0
V
FALLING
OUT
0.5
0
–75 –50 –25
0
25 50 75 100 125 150 175
0
2
1
3
4
5
6
–75 –50 –25
0 25 50 75 100 125 150 175
TEMPERATURE (°C)
OUTPUT CURRENT (A)
TEMPERATURE (°C)
3071 G52
3071 G17
3071 G50
3071f
ꢅ
LT3071
typicAl perFormAnce chArActeristics
Logic Input Threshold Voltages
Logic Low to Hi-Z State Transitions
Logic Input Threshold Voltages
Logic Hi-Z to High State Transitions
EN Pin Thresholds
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
3.0
2.9
2.8
0.8
0.7
0.6
V
= 2.5V
V
= 3.3V
BIAS
SEE APPLICATIONS INFORMATION
FOR MORE DETAILS
BIAS
LOGIC Hi-Z TO HIGH THRESHOLD IS
RELATIVE TO V VOLTAGE
BIAS
SEE APPLICATIONS INFORMATION
FOR MORE DETAILS
INPUT RISING
LOGIC LOW TO Hi-Z
EN PIN RISING
INPUT RISING
LOGIC Hi-Z TO HIGH
EN PIN FALLING
INPUT FALLING
LOGIC Hi-Z TO LOW
2.7
2.6
2.5
0.5
0.4
0.3
INPUT FALLING
LOGIC HIGH TO Hi-Z
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3071 G16
3071 G19
3071 G18
Logic Pin Input Current,
High State
Logic Pin Input Current,
Low State
EN Pin Logic High Current
40
35
30
25
20
15
10
5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
40
35
30
25
20
15
10
5
V
= V
= 2.5V
V
V
= 2.5V
= 0V
V
= V
= 2.5V
EN
BIAS
BIAS
LOGIC
LOGIC
BIAS
CURRENT FLOWS INTO THE PIN
CURRENT FLOWS OUT OF THE PIN
0
0
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3071 G20
3071 G22
3071 G21
SENSE Pin Current
SENSE Pin Current
Current Limit vs Temperature
7.50
7.25
7.00
6.75
6.50
6.25
6.00
5.75
5.50
5.25
5.00
65
60
55
50
45
40
35
30
25
400
375
350
325
300
275
250
225
200
V
= V
+ 300mV
OUT(NOMINAL)
V
V
= 2.5V
= 0.8V
V
V
= 3.3V
= 1.8V
IN
BIAS
OUT
BIAS
OUT
CURRENT FLOWS INTO SENSE
CURRENT FLOWS INTO SENSE
V
V
V
= 1.8V, V
= 1.2V, V
= 0.8V, V
= 3.3V
= 3.3V
= 2.5V
OUT
OUT
OUT
BIAS
BIAS
BIAS
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3071 G25
3071 G23
3071 G24
3071f
ꢆ
LT3071
typicAl perFormAnce chArActeristics
Current Limit vs VIN – VOUT
BIAS Pin Ripple Rejection
IN Pin Ripple Rejection
80
70
60
50
40
30
20
10
0
8
7
6
5
4
3
2
1
0
100
90
V
V
= 1.3V
= 1V
V
= 3.3V
IN
OUT
OUT
BIAS
T = 25°C
J
I
= 5A
80
C
OUT
= 10µF + 4.7µF + 2.2µF
70
60
50
40
30
20
10
0
C
C
= 117µF
= 16.9µF
OUT
OUT
V
V
V
I
= 1V
OUT
V
V
V
= 1.8V
= 1.2V
= 0.8V
V
V
V
= 2.5V + 500mV
= 2.7V + 500mV
= 3.3V + 500mV
= 1.3V + 50mV RIPPLE
OUT
OUT
OUT
BIAS
BIAS
BIAS
P-P
P-P
P-P
IN P-P
= 2.5V
= 1A
BIAS
OUT
1.00 1.25
1.50 1.75 2.00
0
0.25 0.50 0.75
10
100
1k
10k 100k
1M
10M
10
100
1k
10k 100k
1M
10M
IN-TO-OUT VOLTAGE DIFFERENTIAL (V)
FREQUENCY (Hz)
FREQUENCY (Hz)
3071 G28
3071 G27
3071 G26
Minimum BIAS Voltage
vs Temperature
Minimum BIAS Voltage vs IOUT
IN Pin Ripple Rejection
80
70
60
50
40
30
20
10
0
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
V
= V
+ 300mV
OUT(NOMINAL)
IN
V
V
V
= 1.8V
= 1.2V
= 0.8V
I
= 5A
OUT
OUT
OUT
OUT
$V
= –1%, T = 25°C
J
OUT
V
= 1.8V
OUT
V
= 1.5V
OUT
OUT
OUT
V
= 1.2V
V
= 0.8V TO 1V
C
C
= 117µF
= 16.9µF
OUT
OUT
V
V
V
= 1V
OUT
IN
BIAS
= 1.3V + 50mV RIPPLE
P-P
= 2.5V
= 5A
I
OUT
1
2
4
–75 –50 –25
0
25 50 75 100 125 150 175
0
5
10
100
1k
10k 100k
1M
10M
3
TEMPERATURE (°C)
OUTPUT CURRENT (A)
FREQUENCY (Hz)
3071 G29
3071 G30
3071 G31
Minimum BIAS Voltage vs VOUT
Load Regulation
Bias Voltage Line Regulation
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
800
700
600
500
400
300
200
100
0
0
–2
–4
I
= 5A
V
V
V
= 2.2V TO 3.6V
OUT
J
BIAS
IN
OUT
OUT
T
= 25°C
= 1.1V
= 0.8V
= 10mA
I
–6
–8
V
V
= V
+ 300mV
OUT(NOMINAL)
IN
= 3.3V
BIAS
$I
= 100mA TO 5A
OUT
V
V
V
= 0.8V
= 1.2V
= 1.8V
OUT
OUT
OUT
–10
0.7
0.9
1.1
1.3
1.5
1.7
1.9
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
OUTPUT VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
3071 G51
3071 G32
3071 G33
3071f
ꢇ
LT3071
typicAl perFormAnce chArActeristics
Input Voltage Line Regulation
Bias Voltage Line Regulation
Input Voltage Line Regulation
400
300
300
250
300
250
V
V
V
I
= 3.25V TO 3.6V
V
V
V
I
= 3.3V
V
V
V
I
= 3.3V
BIAS
IN
BIAS
IN
OUT
BIAS
IN
OUT
= 2.1V
= 1.05V TO 2.7V
= 0.8V
= 2.05V TO 2.7V
= 1.8V
OUT
= 1.8V
= 10mA
= 10mA
= 10mA
OUT
200
OUT
OUT
200
150
200
150
100
0
–100
–200
–300
–400
100
50
0
100
50
0
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3071 G34
3071 G35
3071 G36
Output Voltage Start-Up Time
vs CREF/BYP
Nap Mode Recovery Time vs IOUT
Output Noise Spectral Density
1.0
0.1
20
18
16
14
12
10
8
400
350
300
250
V
V
= 3.3V
OUT(NOM)
EN = LOW TO HIGH
BIAS
IN
V
OUT
C
= 2.5V TO 3.3V
V
V
OUT
C
C
= 2.5V
= 1V
BIAS
BIAS
OUT
= V
+ 300mV
I
= 10mA
= 10µF + 4.7µF + 2.2µF
I
= 5A
OUT
I
= 5A (SET BY A RESISTOR LOAD)
OUT
T = 25°C
J
= 16.9µF
OUT
REF/BYP
T = 25°C
J
SEE APPLICATIONS
INFORMATION FOR
START-UP DETAILS
= 0.01µF
V
C
V
C
V
C
= 1.8V,
= 117µF
= 1.2V,
= 117µF
= 0.8V,
= 117µF
OUT
OUT
OUT
OUT
OUT
OUT
200
150
0.01
0.001
6
100
50
0
4
2
0
1
2
4
0
5
0
0.1
0.2
0.3
0.4
0.5
3
10
100
1k
FREQUENCY (Hz)
10k
100k
OUTPUT CURRENT (A)
REF/BYP CAPACITANCE (µF)
3071 G39
3071 G38
3071 G37
Input Voltage Line Transient
Response
RMS Output Noise
vs Output Current
Output Noise (10Hz to 100kHz)
80
70
60
50
40
30
20
10
0
V
V
C
= V
+ 300mV
OUT(NOMINAL)
IN
= 3.3V
BIAS
OUT
= 16.9µF
V
OUT
1mV/DIV
V
OUT
100µV/DIV
V
IN
50mV/DIV
V
V
V
= 1.8V
= 1.2V
= 0.8V
3071 G42
OUT
OUT
OUT
3071 G41
V
V
I
= 1.3V
= 1V
20µs/DIV
V
I
= 1V
1ms/DIV
IN
OUT
OUT
OUT
= 5A
= 5A
C
= 16.9µF
OUT
OUT
C
= 16.9µF
0.01
0.1
1
10
OUT
OUTPUT CURRENT (A)
3071 G40
3071f
ꢈ
LT3071
typicAl perFormAnce chArActeristics
Bias Voltage Line Transient
Response
VIOC Amplifier IN-to-OUT Servo
Voltage
VIOC Amplifier Output Current
vs Temperature
350
340
330
320
310
300
290
280
270
260
250
300
275
V
= 2.5V
BIAS
V
OUT
10mV/DIV
I
SOURCING
VIOC
250
225
I
SINKING
VIOC
V
BIAS
200mV/DIV
200
175
150
3071 G43
V
V
V
I
= 1.3V
20µs/DIV
IN
= 2.5V
= 1V
BIAS
OUT
OUT
= 5A
–75 –50 –25
0
25 50 75 100 125 150 175
–75 –50 –25
0
25 50 75 100 125 150 175
C
= 16.9µF
OUT
TEMPERATURE (°C)
TEMPERATURE (°C)
3071 G44
3071 G45
Transient Load Response
Transient Load Response
V
V
OUT
OUT
50mV/DIV
50mV/DIV
AC-COUPLED
AC-COUPLED
I
I
OUT
OUT
2A/DIV
∆I = 500mA
TO 5A
2A/DIV
∆I = 500mA
TO 5A
3071 G46
3071 G47
V
C
I
= 1V
20µs/DIV
= 10µF + 4.7µF + 2.2µF
/t = 100ns
V
C
I
= 1V
= 117µF
/t
20µs/DIV
= 100ns
OUT
OUT
OUT
OUT
t
t
OUT RISE FALL
OUT RISE FALL
Transient Load Response
Transient Load Response
V
V
OUT
OUT
50mV/DIV
50mV/DIV
AC-COUPLED
AC-COUPLED
I
I
OUT
OUT
2A/DIV
∆I = 500mA
TO 5A
2A/DIV
∆I = 500mA
TO 5A
3071 G48
3071 G49
V
C
= 1V
20µs/DIV
= 10µF + 4.7µF + 2.2µF
/t = 1µs
V
C
= 1V
20µs/DIV
= 1µs
OUT
OUT
OUT
OUT
= 117µF
I
t
I
t
/t
OUT RISE FALL
OUT RISE FALL
3071f
ꢀ0
LT3071
pin Functions
VIOC (Pin 1):ꢀVoltageꢀforꢀIn-to-OutꢀControl.ꢀTheꢀICꢀin-
GND(Pins4, 9-14, 20, 26, ExposedPadPin29):ꢀGround.ꢀ
corporatesꢀaꢀuniqueꢀtrackingꢀfunctionꢀtoꢀcontrolꢀaꢀbuckꢀ TheꢀexposedꢀpadꢀofꢀtheꢀQFNꢀpackageꢀisꢀanꢀelectricalꢀcon-
regulatorꢀpoweringꢀtheꢀLT3071’sꢀinput.ꢀTheꢀVIOCꢀpinꢀisꢀ nectionꢀtoꢀGND.ꢀToꢀensureꢀproperꢀelectricalꢀandꢀthermalꢀ
theꢀoutputꢀofꢀthisꢀtrackingꢀfunctionꢀthatꢀdrivesꢀtheꢀbuckꢀ performance,ꢀsolderꢀPinꢀ29ꢀtoꢀtheꢀPCBꢀgroundꢀandꢀtieꢀtoꢀ
regulatorꢀtoꢀmaintainꢀtheꢀLT3071’sꢀinputꢀvoltageꢀatꢀV ꢀ+ꢀ allꢀGNDꢀpinsꢀofꢀtheꢀpackage.ꢀTheseꢀGNDꢀpinsꢀareꢀfusedꢀ
OUT
300mV.ꢀThisꢀfunctionꢀmaximizesꢀefficiencyꢀandꢀminimizesꢀ toꢀtheꢀinternalꢀdieꢀattachꢀpaddleꢀandꢀtheꢀexposedꢀpadꢀtoꢀ
powerꢀdissipation.ꢀSeeꢀtheꢀApplicationsꢀInformationꢀsec-
optimizeꢀheatꢀsinkingꢀandꢀthermalꢀresistanceꢀcharacteris-
tionꢀforꢀmoreꢀinformationꢀonꢀproperꢀcontrolꢀofꢀtheꢀbuckꢀ tics.ꢀSeeꢀtheꢀApplicationsꢀInformationꢀsectionꢀforꢀthermalꢀ
regulator.
considerationsꢀandꢀcalculatingꢀjunctionꢀtemperature.ꢀ
PWRGD (Pin 2):ꢀPowerꢀGood.ꢀTheꢀPWRGDꢀpinꢀisꢀanꢀopen-
IN (Pins 5, 6, 7, 8):ꢀInputꢀSupply.ꢀTheseꢀpinsꢀsupplyꢀ
drainꢀNMOSꢀoutputꢀthatꢀactivelyꢀpullsꢀlowꢀifꢀanyꢀoneꢀofꢀ powerꢀtoꢀtheꢀhighꢀcurrentꢀpassꢀtransistor.ꢀTieꢀallꢀINꢀpinsꢀ
theseꢀfaultꢀmodesꢀisꢀdetected:
togetherꢀforꢀproperꢀperformance.ꢀTheꢀLT3071ꢀrequiresꢀaꢀ
bypassꢀcapacitorꢀatꢀINꢀtoꢀmaintainꢀstabilityꢀandꢀlowꢀinputꢀ
impedanceꢀoverꢀfrequency.ꢀAꢀ47µFꢀinputꢀbypassꢀcapacitorꢀ
sufficesꢀforꢀmostꢀbatteryꢀandꢀpowerꢀplaneꢀimpedances.ꢀ
Minimizingꢀinputꢀtraceꢀinductanceꢀoptimizesꢀperformance.ꢀ
•ꢀ V ꢀisꢀlessꢀthanꢀ90ꢁꢀofꢀV
ꢀonꢀtheꢀrisingꢀ
OUT
edgeꢀofꢀV
OUT(NOMINAL)
OUT(NOMINAL)
.
OUTꢀ
•ꢀ V ꢀdropsꢀbelowꢀ85ꢁꢀofꢀV
ꢀforꢀmoreꢀthanꢀ
OUT
25µs.
ApplicationsꢀthatꢀoperateꢀwithꢀlowꢀV -V ꢀdifferentialꢀ
IN OUT
voltagesꢀandꢀthatꢀhaveꢀlarge,ꢀfastꢀloadꢀtransientsꢀmayꢀrequireꢀ
muchꢀhigherꢀinputꢀcapacitorꢀrequirementsꢀtoꢀpreventꢀtheꢀ
inputꢀsupplyꢀfromꢀdroopingꢀandꢀallowingꢀtheꢀregulatorꢀtoꢀ
enterꢀdropout.ꢀSeeꢀtheꢀApplicationsꢀInformationꢀsectionꢀ
forꢀmoreꢀinformationꢀonꢀinputꢀcapacitorꢀrequirements.ꢀ
•ꢀ Junctionꢀtemperatureꢀtypicallyꢀexceedsꢀ145°C.
•ꢀ V ꢀisꢀlessꢀthanꢀitsꢀundervoltageꢀlockoutꢀthreshold.
BIAS
•ꢀ TheꢀOUT-to-INꢀreverse-currentꢀdetectorꢀactivates.
SeeꢀtheꢀApplicationsꢀInformationꢀsectionꢀforꢀmoreꢀinfor-
mationꢀonꢀPWRGDꢀfaultꢀmodes.
OUT (Pins 15, 16, 17, 18):ꢀOutput.ꢀTheseꢀpinsꢀsupplyꢀ
powerꢀtoꢀtheꢀload.ꢀTieꢀallꢀOUTꢀpinsꢀtogetherꢀforꢀproperꢀ
performance.ꢀAꢀminimumꢀoutputꢀcapacitanceꢀofꢀ15µFꢀisꢀ
requiredꢀforꢀstability.ꢀLTCꢀrecommendsꢀlowꢀESR,ꢀX5Rꢀorꢀ
X7Rꢀdielectricꢀceramicꢀcapacitorsꢀforꢀbestꢀperformance.ꢀ
Aꢀparallelꢀceramicꢀcapacitorꢀcombinationꢀofꢀ10µFꢀ+ꢀ4.7µFꢀ
+ꢀ2.2µFꢀorꢀ15ꢀ1µFꢀceramicꢀcapacitorsꢀinꢀparallelꢀprovideꢀ
excellentꢀstabilityꢀandꢀloadꢀtransientꢀresponse.ꢀLargeꢀloadꢀ
transientꢀapplicationsꢀrequireꢀlargerꢀoutputꢀcapacitorsꢀtoꢀ
limitꢀpeakꢀvoltageꢀtransients.ꢀSeeꢀtheꢀApplicationsꢀInfor-
mationꢀsectionꢀforꢀmoreꢀinformationꢀonꢀoutputꢀcapacitorꢀ
requirements.ꢀ
REF/BYP (Pin 3):ꢀReferenceꢀFilter.ꢀTheꢀpinꢀisꢀtheꢀoutputꢀ
ofꢀtheꢀbandgapꢀreferenceꢀandꢀhasꢀanꢀimpedanceꢀofꢀap-
proximatelyꢀ19kΩ.ꢀThisꢀpinꢀmustꢀnotꢀbeꢀexternallyꢀloaded.ꢀ
BypassingꢀtheꢀREF/BYPꢀpinꢀtoꢀGNDꢀwithꢀaꢀ10nFꢀcapacitorꢀ
decreasesꢀoutputꢀvoltageꢀnoiseꢀandꢀprovidesꢀaꢀsoft-startꢀ
functionꢀtoꢀtheꢀreference.ꢀLTCꢀrecommendsꢀtheꢀuseꢀofꢀaꢀ
highꢀquality,ꢀlowꢀleakageꢀcapacitor.ꢀSeeꢀtheꢀApplicationsꢀ
Informationꢀsectionꢀforꢀmoreꢀinformationꢀonꢀnoiseꢀandꢀ
outputꢀvoltageꢀmarginingꢀconsiderations.
3071f
ꢀꢀ
LT3071
pin Functions
SENSE (Pin 19):ꢀKelvinꢀSenseꢀforꢀOUT.ꢀTheꢀSENSEꢀpinꢀisꢀ V , V and V (Pins 23, 24, 25):ꢀOutputꢀVoltageꢀSe-
O0 O1 O2
theꢀinvertingꢀinputꢀtoꢀtheꢀerrorꢀamplifier.ꢀOptimumꢀregulationꢀ lect.ꢀTheseꢀthree-stateꢀpinsꢀcombineꢀtoꢀselectꢀaꢀnominalꢀ
isꢀobtainedꢀwhenꢀtheꢀSENSEꢀpinꢀisꢀconnectedꢀtoꢀtheꢀOUTꢀ outputꢀvoltageꢀfromꢀ0.8Vꢀtoꢀ1.8Vꢀinꢀincrementsꢀofꢀ50mV.ꢀ
pinsꢀofꢀtheꢀregulator.ꢀInꢀcriticalꢀapplications,ꢀtheꢀresistanceꢀ Outputꢀvoltageꢀisꢀlimitedꢀtoꢀ1.8Vꢀmaximumꢀbyꢀanꢀinternalꢀ
(R )ꢀofꢀPCBꢀtracesꢀbetweenꢀtheꢀregulatorꢀandꢀtheꢀloadꢀcauseꢀ overrideꢀofꢀV ꢀwhenꢀV ꢀ=ꢀhigh.ꢀTheꢀinputꢀlogicꢀlowꢀ
P
O1
O2
smallꢀvoltageꢀdrops,ꢀcreatingꢀaꢀloadꢀregulationꢀerrorꢀatꢀtheꢀ thresholdꢀisꢀlessꢀthanꢀ250mVꢀreferencedꢀtoꢀGNDꢀandꢀtheꢀ
pointꢀofꢀload.ꢀConnectingꢀtheꢀSENSEꢀpinꢀatꢀtheꢀloadꢀinsteadꢀ logicꢀhighꢀthresholdꢀisꢀgreaterꢀthanꢀV
ꢀ–ꢀ250mV.ꢀTheꢀ
BIAS
ofꢀdirectlyꢀtoꢀOUTꢀeliminatesꢀthisꢀvoltageꢀerror.ꢀFigureꢀ1ꢀ rangeꢀbetweenꢀtheseꢀtwoꢀthresholdsꢀasꢀsetꢀbyꢀaꢀwindowꢀ
illustratesꢀthisꢀKelvin-Senseꢀconnectionꢀmethod.ꢀNoteꢀthatꢀ comparatorꢀdefinesꢀtheꢀlogicꢀHi-Zꢀstate.ꢀSeeꢀTableꢀ1ꢀinꢀtheꢀ
theꢀvoltageꢀdropꢀacrossꢀtheꢀexternalꢀPCBꢀtracesꢀaddsꢀtoꢀtheꢀ ApplicationsꢀInformationꢀsectionꢀthatꢀdefinesꢀtheꢀV ,ꢀV ꢀ
O2 O1
dropoutꢀvoltageꢀofꢀtheꢀregulator.ꢀTheꢀSENSEꢀpinꢀinputꢀbiasꢀ andꢀV ꢀsettingsꢀversusꢀV
.
O0
OUTꢀ
currentꢀdependsꢀonꢀtheꢀselectedꢀoutputꢀvoltage.ꢀSENSEꢀ
BIAS (Pin 27):ꢀBiasꢀSupply.ꢀThisꢀpinꢀsuppliesꢀcurrentꢀtoꢀ
theꢀinternalꢀcontrolꢀcircuitryꢀandꢀtheꢀoutputꢀstageꢀdrivingꢀ
theꢀpassꢀtransistor.ꢀTheꢀLT3071ꢀrequiresꢀaꢀminimumꢀ2.2µFꢀ
ꢀ pinꢀ bypassꢀcapacitorꢀforꢀstabilityꢀandꢀproperꢀoperation.ꢀToꢀ
pinꢀinputꢀcurrentꢀvariesꢀfromꢀ50µAꢀtypicallyꢀatꢀV ꢀ=ꢀ0.8Vꢀ
OUT
toꢀ300µAꢀtypicallyꢀatꢀV ꢀ=ꢀ1.8V.
OUT
I
(Pin 21):ꢀ Outputꢀ Currentꢀ Monitor.ꢀ Theꢀ I
MON
MON
sourcesꢀaꢀcurrentꢀtypicallyꢀequalꢀtoꢀI /2500ꢀorꢀ400µAꢀ ensureꢀproperꢀoperation,ꢀtheꢀBIASꢀvoltageꢀmustꢀsatisfyꢀ
OUT
perꢀampꢀofꢀoutputꢀcurrent.ꢀTerminatingꢀthisꢀpinꢀwithꢀaꢀ theꢀfollowingꢀconditions:ꢀ2.2Vꢀ≤ꢀV
ꢀ≤ꢀ3.6VꢀandꢀV
BIAS
ꢀ≥ꢀ
BIAS
resistorꢀtoꢀGNDꢀproducesꢀaꢀvoltageꢀproportionalꢀtoꢀI .ꢀ (1.25ꢀ•ꢀV ꢀ+ꢀ1V).ꢀForꢀV ꢀ≤ꢀ0.95V,ꢀtheꢀminimumꢀBIASꢀ
OUTꢀ
OUT
OUT
Forꢀexample,ꢀatꢀI ꢀ=ꢀ5A,ꢀI
ꢀtypicallyꢀsourcesꢀ2mA.ꢀ voltageꢀisꢀlimitedꢀtoꢀ2.2V.
OUT
MON
Withꢀaꢀ1kꢀresistorꢀtoꢀGND,ꢀthisꢀproducesꢀ2V.ꢀIfꢀI
ꢀisꢀ
MON
EN (Pin 28):ꢀEnable.ꢀThisꢀpinꢀenables/disablesꢀtheꢀoutputꢀ
unused,ꢀtieꢀthisꢀpinꢀtoꢀV
.ꢀ
BIAS
deviceꢀonly.ꢀTheꢀinternalꢀreferenceꢀandꢀallꢀsupportꢀfunctionsꢀ
MARGA (Pin 22):ꢀAnalogꢀMargining:ꢀThisꢀpinꢀmarginsꢀtheꢀ areꢀactiveꢀifꢀV
ꢀisꢀaboveꢀitsꢀUVLOꢀthreshold.ꢀPullingꢀ
BIAS
outputꢀvoltageꢀoverꢀaꢀcontinuousꢀanalogꢀrangeꢀofꢀ 10ꢁ.ꢀ ENꢀlowꢀkeepsꢀtheꢀreferenceꢀcircuitꢀactive,ꢀbutꢀdisablesꢀ
TyingꢀthisꢀpinꢀtoꢀGNDꢀadjustsꢀoutputꢀvoltageꢀbyꢀ–10ꢁ.ꢀ theꢀoutputꢀpassꢀtransistorꢀandꢀputsꢀtheꢀLT3071ꢀintoꢀaꢀlowꢀ
Drivingꢀthisꢀpinꢀtoꢀ1.2Vꢀadjustsꢀoutputꢀvoltageꢀbyꢀ+10ꢁ.ꢀAꢀ powerꢀnapꢀmode.ꢀDriveꢀtheꢀENꢀpinꢀwithꢀeitherꢀaꢀdigitalꢀlogicꢀ
voltageꢀsourceꢀorꢀaꢀvoltageꢀoutputꢀDACꢀisꢀidealꢀforꢀdrivingꢀ portꢀorꢀanꢀopen-collectorꢀNPNꢀorꢀanꢀopen-drainꢀNMOSꢀ
thisꢀpin.ꢀIfꢀtheꢀMARGAꢀfunctionꢀisꢀnotꢀused,ꢀeitherꢀfloatꢀ terminatedꢀwithꢀaꢀpull-upꢀresistorꢀtoꢀV
.ꢀTheꢀpull-upꢀ
IH
BIAS
thisꢀpinꢀorꢀterminateꢀwithꢀaꢀ1nFꢀcapacitorꢀtoꢀGND.
resistorꢀmustꢀbeꢀlessꢀthanꢀ35kꢀtoꢀmeetꢀtheꢀV ꢀconditionꢀ
ofꢀtheꢀENꢀpin.ꢀIfꢀunused,ꢀconnectꢀENꢀtoꢀBIAS.
+
V
BIAS
BIAS
EN
IN
PWRGD
SENSE
LT3071
OUT
V
O0
V
O1
V
O2
R
P
+
V
IN
I
LOAD
MARGA
VIOC
MON
REF/BYP
GND
R
P
3071 F01
Figure 1. Kelvin Sense Connection
3071f
ꢀꢁ
LT3071
block DiAgrAm
UVLO AND
BIAS
27
THERMAL
SHUTDOWN
IN
5-8
+
–
+
–
I
MON
I
21
SENSE
REF/BYP
+
–
EAMP
BUF
OUT
15-18
LDO CORE
SENSE
19
2
PWRGD
DETECT
–
+
VIOC
GND
V
+ 300mV
1
OUT(NOM)
REF/BYP
600mV
V
3
REF
4,9-14,20,26,29
PROGRAM CONTROL
EN
28
V
V
V
O0
MARGA
22
O2
O1
25
24
23
3070 BD
LOGIC HIGH STATE
–
V
– 0.25V
BIAS
+
LOGIC Hi-Z STATE
V
BIAS
HIGH IF IN > V
HIGH IF IN < V
– 0.25V
– 0.9V
BIAS
V
– 0.9V
+
–
+
–
BIAS
100k
V
, V , VO0
O2 O1
BIAS
AND IN > 0.75V
TO LOGIC
MARGSEL OR
MARGTOL
0.75V
100k
HIGH IF IN < 0.25V
LOGIC LOW STATE
–
+
0.25V
3071f
ꢀꢂ
LT3071
ApplicAtions inFormAtion
Introduction
outputꢀcurrent.ꢀThisꢀpermitsꢀaꢀuserꢀtoꢀmeasureꢀsystemꢀ
performanceꢀsuchꢀasꢀoutputꢀpowerꢀorꢀifꢀoutputꢀcurrentꢀ
exceedsꢀorꢀfallsꢀbelowꢀsomeꢀthreshold.
Currentꢀ generationꢀ FPGAꢀ andꢀ ASICꢀ processorsꢀ placeꢀ
stringentꢀdemandsꢀonꢀtheꢀpowerꢀsuppliesꢀthatꢀpowerꢀtheꢀ
core,ꢀI/Oꢀandꢀtransceiverꢀchannels.ꢀTheseꢀmicroprocessorsꢀ TheꢀICꢀincorporatesꢀaꢀuniqueꢀtrackingꢀfunction,ꢀwhichꢀifꢀ
mayꢀcycleꢀloadꢀcurrentꢀfromꢀnearꢀzeroꢀtoꢀampsꢀinꢀtensꢀofꢀ enabledꢀbyꢀtheꢀuser,ꢀcontrolsꢀanꢀupsteamꢀregulatorꢀpower-
nanoseconds.ꢀOutputꢀvoltageꢀspecifications,ꢀespeciallyꢀinꢀ ingꢀtheꢀLT3071’sꢀinputꢀ(seeꢀFigureꢀ8).ꢀThisꢀtrackingꢀfunctionꢀ
theꢀ1Vꢀrange,ꢀrequireꢀtightꢀtolerancesꢀincludingꢀtransientꢀ drivesꢀtheꢀbuckꢀregulatorꢀtoꢀmaintainꢀtheꢀLT3071’sꢀinputꢀ
responseꢀasꢀpartꢀofꢀtheꢀrequirement.ꢀSomeꢀASICꢀprocessorsꢀ voltageꢀtoꢀV ꢀ+ꢀ300mV.ꢀThisꢀinput-to-outputꢀvoltageꢀ
OUT
requireꢀonlyꢀaꢀsingleꢀoutputꢀvoltageꢀfromꢀwhichꢀtheꢀcoreꢀ controlꢀallowsꢀtheꢀuserꢀtoꢀchangeꢀtheꢀregulatorꢀoutputꢀ
andꢀI/Oꢀcircuitryꢀoperate.ꢀSomeꢀhighꢀperformanceꢀFPGAꢀ voltage,ꢀandꢀhaveꢀtheꢀswitchingꢀregulatorꢀpoweringꢀtheꢀ
processorsꢀrequireꢀseparateꢀpowerꢀsupplyꢀvoltagesꢀforꢀtheꢀ LT3071’sꢀinputꢀtoꢀtrackꢀtoꢀtheꢀoptimumꢀinputꢀvoltageꢀwithꢀ
processorꢀcore,ꢀtheꢀI/O,ꢀandꢀtheꢀtransceivers.ꢀOften,ꢀtheseꢀ noꢀcomponentꢀchanges.
supplyꢀvoltagesꢀmustꢀbeꢀlowꢀnoiseꢀandꢀhighꢀbandwidthꢀ
Thisꢀ combinesꢀ theꢀ efficiencyꢀ ofꢀ aꢀ switchingꢀ regulatorꢀ
toꢀachieveꢀtheꢀlowestꢀbit-errorꢀrates.ꢀTheseꢀrequirementsꢀ
withꢀsuperiorꢀlinearꢀregulatorꢀresponse.ꢀItꢀalsoꢀpermitsꢀ
mandateꢀtheꢀneedꢀforꢀveryꢀaccurate,ꢀlowꢀnoise,ꢀhighꢀcur-
thermalꢀmanagementꢀofꢀtheꢀsystemꢀevenꢀwithꢀaꢀmaximumꢀ
rent,ꢀveryꢀhighꢀspeedꢀregulatorꢀcircuitsꢀthatꢀoperateꢀatꢀlowꢀ
5Aꢀoutputꢀload.ꢀ
inputꢀandꢀoutputꢀvoltages.
LT3071ꢀinternalꢀprotectionꢀincludesꢀinputꢀundervoltageꢀ
TheꢀLT3071ꢀisꢀaꢀlowꢀvoltage,ꢀUltraFastꢀtransientꢀresponseꢀ
lockoutꢀ(UVLO),ꢀreverse-currentꢀprotection,ꢀprecisionꢀcur-
linearꢀregulator.ꢀTheꢀdeviceꢀsuppliesꢀupꢀtoꢀ5Aꢀofꢀoutputꢀ
rentꢀlimitingꢀwithꢀpowerꢀfoldbackꢀandꢀthermalꢀshutdown.ꢀ
currentꢀwithꢀaꢀtypicalꢀdropoutꢀvoltageꢀofꢀ85mV.ꢀAꢀ0.01µFꢀ
TheꢀLT3071ꢀregulatorꢀisꢀavailableꢀinꢀaꢀthermallyꢀenhancedꢀ
referenceꢀbypassꢀcapacitorꢀdecreasesꢀoutputꢀvoltageꢀnoiseꢀ
28-lead,ꢀ4mmꢀ×ꢀ5mmꢀQFNꢀpackage.
toꢀ25µV
ꢀ(BWꢀ=ꢀ10Hzꢀtoꢀ100kHz).ꢀTheꢀLT3071’sꢀhighꢀ
RMS
TheꢀLT3071’sꢀarchitectureꢀdrivesꢀanꢀinternalꢀN-channelꢀ
powerꢀMOSFETꢀasꢀaꢀsourceꢀfollower.ꢀThisꢀconfigurationꢀ
permitsꢀaꢀuserꢀtoꢀobtainꢀanꢀextremelyꢀlowꢀdropout,ꢀUltra-
Fastꢀtransientꢀresponseꢀregulatorꢀwithꢀexcellentꢀhighꢀfre-
quencyꢀPSRRꢀperformance.ꢀTheꢀLT3071ꢀachievesꢀsuperiorꢀ
regulatorꢀbandwidthꢀandꢀtransientꢀloadꢀperformanceꢀbyꢀ
eliminatingꢀexpensiveꢀbulkꢀtantalumꢀorꢀelectrolyticꢀcapaci-
torsꢀinꢀtheꢀmostꢀmodernꢀandꢀdemandingꢀmicroprocessorꢀ
applications.ꢀUsersꢀrealizeꢀsignificantꢀcostꢀsavingsꢀasꢀallꢀ
bandwidthꢀprovidesꢀUltraFastꢀtransientꢀresponseꢀusingꢀlowꢀ
ESRꢀceramicꢀoutputꢀcapacitorsꢀ(15µFꢀminimum),ꢀsavingꢀ
bulkꢀcapacitance,ꢀPCBꢀareaꢀandꢀcost.ꢀ
TheꢀLT3071’sꢀfeaturesꢀpermitꢀstate-of-the-artꢀlinearꢀregula-
torꢀperformance.ꢀTheꢀLT3071ꢀisꢀidealꢀforꢀhighꢀperformanceꢀ
FPGAs,ꢀmicroprocessors,ꢀsensitiveꢀcommunicationꢀsup-
plies,ꢀandꢀhighꢀcurrentꢀlogicꢀapplicationsꢀthatꢀalsoꢀoperateꢀ
overꢀlowꢀinputꢀandꢀoutputꢀvoltages.ꢀ
OutputꢀvoltageꢀforꢀtheꢀLT3071ꢀisꢀdigitallyꢀselectableꢀinꢀ additionalꢀbulkꢀcapacitanceꢀisꢀremoved.ꢀTheꢀadditionalꢀ
50mVꢀincrementsꢀoverꢀaꢀ0.8Vꢀtoꢀ1.8Vꢀrange.ꢀAnꢀanalogꢀ savingsꢀofꢀinsertionꢀcost,ꢀpurchasing/inventoryꢀcostꢀandꢀ
marginingꢀfunctionꢀallowsꢀtheꢀuserꢀtoꢀadjustꢀsystemꢀoutputꢀ boardꢀspaceꢀareꢀreadilyꢀapparent.ꢀPrecisionꢀincrementalꢀ
voltageꢀoverꢀaꢀcontinuousꢀ 10ꢁꢀrange.ꢀ
outputꢀvoltageꢀcontrolꢀaccommodatesꢀlegacyꢀandꢀfutureꢀ
microprocessorꢀpowerꢀsupplyꢀvoltages.ꢀ
Theꢀ LT3071ꢀ providesꢀ anꢀ outputꢀ currentꢀ monitorꢀ thatꢀ
typicallyꢀsourcesꢀaꢀcurrentꢀofꢀI /2500ꢀorꢀ400µAꢀperꢀ Outputꢀcapacitorꢀnetworksꢀsimplifyꢀtoꢀdirectꢀparallelꢀcom-
OUT
ampꢀofꢀI ꢀatꢀitsꢀI
ꢀpin.ꢀTerminatingꢀtheꢀI
ꢀpinꢀtoꢀ binationsꢀofꢀceramicꢀcapacitors.ꢀOften,ꢀtheꢀhighꢀfrequencyꢀ
OUT
MON
MON
GNDꢀwithꢀaꢀresistorꢀproducesꢀaꢀvoltageꢀproportionalꢀtoꢀ ceramicꢀdecouplingꢀcapacitorsꢀrequiredꢀbyꢀtheseꢀvariousꢀ
3071f
ꢀꢃ
LT3071
ApplicAtions inFormAtion
FPGAꢀandꢀASICꢀprocessorsꢀareꢀsufficientꢀtoꢀstabilizeꢀtheꢀ Outputꢀvoltageꢀisꢀlimitedꢀtoꢀ1.8Vꢀmaximumꢀbyꢀanꢀinternalꢀ
systemꢀ(seeꢀStabilityꢀandꢀOutputꢀCapacitanceꢀsection).ꢀThisꢀ overrideꢀofꢀV ꢀ(defaultꢀtoꢀlow)ꢀwhenꢀV ꢀ=ꢀhigh.ꢀ
O1
O2
regulatorꢀdesignꢀprovidesꢀampleꢀbandwidthꢀandꢀrespondsꢀ
toꢀtransientꢀloadꢀchangesꢀinꢀaꢀfewꢀhundredꢀnanosecondsꢀ
versusꢀregulatorsꢀthatꢀrespondꢀinꢀmanyꢀmicroseconds.ꢀ
Table 1: VO2 to VO0 Settings vs Output Voltage
V
V
V
V
V
V
V
V
OUT(NOM)
O2
O1
O0
OUT(NOM)
O2
O1
O0
0
0
0
0
0
0
0
0
0
Z
Z
0
0
0
Z
Z
Z
1
1
1
0
0
0
Z
1
0
Z
1
0
Z
1
0
Z
0.80V
Z
Z
Z
Z
Z
Z
Z
1
1
1
0
Z
Z
Z
1
1
1
X
X
X
1
0
Z
1
0
Z
1
0
Z
1
1.35V
TheꢀLT3071ꢀalsoꢀincorporatesꢀprecisionꢀcurrentꢀlimiting,ꢀ
enable/disableꢀcontrolꢀofꢀoutputꢀvoltageꢀandꢀintegratedꢀ
overvoltageꢀ andꢀ thermalꢀ shutdownꢀ protection.ꢀ Theꢀ
LT3071’sꢀ uniqueꢀ designꢀ combinesꢀ theꢀ benefitsꢀ ofꢀ lowꢀ
dropoutꢀ voltage,ꢀ highꢀ functionalꢀ integration,ꢀ precisionꢀ
performanceꢀandꢀUltraFastꢀtransientꢀresponse,ꢀasꢀwellꢀasꢀ
providingꢀsignificantꢀcostꢀsavingsꢀonꢀtheꢀoutputꢀcapacitanceꢀ
neededꢀinꢀfastꢀloadꢀtransientꢀapplications.ꢀ
0.85V
0.90V
0.95V
1.00V
1.05V
1.10V
1.15V
1.20V
1.25V
1.30V
1.40V
1.45V
1.50V
1.55V
1.60V
1.65V
1.70V
1.75V
1.80V
Asꢀlowerꢀvoltageꢀapplicationsꢀbecomeꢀincreasinglyꢀpreva-
lentꢀwithꢀhigherꢀfrequencyꢀswitchingꢀpowerꢀsupplies,ꢀtheꢀ
LT3071ꢀ offersꢀ superiorꢀ regulationꢀ andꢀ anꢀ appreciableꢀ
componentꢀcostꢀsavings.ꢀTheꢀLT3071ꢀstepsꢀtoꢀtheꢀnextꢀ
levelꢀofꢀperformanceꢀforꢀtheꢀlatestꢀgenerationꢀFPGAs,ꢀDSPsꢀ
andꢀmicroprocessors.ꢀTheꢀsimpleꢀversatilityꢀandꢀbenefitsꢀ
derivedꢀfromꢀtheseꢀcircuitsꢀexceedꢀtheꢀpowerꢀsupplyꢀneedsꢀ
ofꢀtoday’sꢀhighꢀperformanceꢀmicroprocessors.
Xꢀ=ꢀDon’tꢀCare,ꢀ0ꢀ=ꢀLow,ꢀZꢀ=ꢀFloat,ꢀ1ꢀ=ꢀHigh
Theꢀinputꢀlogicꢀlowꢀthresholdꢀisꢀlessꢀthanꢀ250mVꢀrefer-
encedꢀtoꢀGNDꢀandꢀtheꢀlogicꢀhighꢀthresholdꢀisꢀgreaterꢀthanꢀ
–ꢀ250mV.ꢀTheꢀrangeꢀbetweenꢀtheseꢀtwoꢀthresholdsꢀ
asꢀsetꢀbyꢀaꢀwindowꢀcomparatorꢀdefinesꢀtheꢀlogicꢀHi-Zꢀ
V
BIASꢀ
state.
Programming Output Voltage
REF/BYP—Voltage Reference
Threeꢀtri-levelꢀinputꢀpins,ꢀV ,ꢀV ꢀandꢀV ,ꢀselectꢀtheꢀ
O2 O1
O0
Thisꢀpinꢀisꢀtheꢀbufferedꢀoutputꢀofꢀtheꢀinternalꢀbandgapꢀ
valueꢀofꢀoutputꢀvoltage.ꢀTableꢀ1ꢀillustratesꢀtheꢀ3-bitꢀdigitalꢀ
wordꢀtoꢀoutputꢀvoltageꢀresultingꢀfromꢀsettingꢀtheseꢀpinsꢀ
high,ꢀlowꢀorꢀallowingꢀthemꢀtoꢀfloat.ꢀ
referenceꢀandꢀhasꢀanꢀoutputꢀimpedanceꢀofꢀ≅19kΩ.ꢀTheꢀ
designꢀincludesꢀanꢀinternalꢀcompensationꢀpoleꢀatꢀf ꢀ=ꢀ4kHz.ꢀ
C
Aꢀ10nFꢀREF/BYPꢀcapacitorꢀtoꢀGNDꢀcreatesꢀaꢀlowpassꢀpoleꢀ
Theseꢀpinsꢀmayꢀbeꢀtiedꢀhighꢀorꢀlowꢀbyꢀeitherꢀpin-strappingꢀ
atꢀf ꢀ=ꢀ840Hz.ꢀTheꢀ10nFꢀcapacitorꢀdecreasesꢀreferenceꢀ
LP
themꢀtoꢀV ꢀorꢀdrivingꢀthemꢀwithꢀdigitalꢀports.ꢀPinsꢀthatꢀ
BIAS
voltageꢀnoiseꢀtoꢀaboutꢀ10µV
ꢀandꢀsoft-startsꢀtheꢀrefer-
RMS
floatꢀmayꢀeitherꢀactuallyꢀfloatꢀorꢀrequireꢀlogicꢀthatꢀhasꢀ
Hi-Zꢀoutputꢀcapability.ꢀThisꢀallowsꢀoutputꢀvoltageꢀtoꢀbeꢀ
dynamicallyꢀchangedꢀifꢀnecessary.
ence.ꢀTheꢀLT3071ꢀonlyꢀsoft-startsꢀtheꢀreferenceꢀvoltageꢀ
duringꢀanꢀinitialꢀturn-onꢀsequence.ꢀIfꢀtheꢀENꢀpinꢀisꢀtoggledꢀ
lowꢀafterꢀinitialꢀturn-on,ꢀtheꢀreferenceꢀremainsꢀpowered-up.ꢀ
Therefore,ꢀtogglingꢀtheꢀENꢀpinꢀfromꢀlowꢀtoꢀhighꢀdoesꢀnotꢀ
soft-startꢀtheꢀreference.ꢀOnlyꢀbyꢀturningꢀtheꢀBIASꢀsupplyꢀ
voltageꢀonꢀandꢀoffꢀwillꢀtheꢀreferenceꢀbeꢀsoft-started.ꢀOutputꢀ
voltageꢀnoiseꢀisꢀtheꢀRMSꢀsumꢀofꢀtheꢀreferenceꢀvoltageꢀ
noiseꢀinꢀadditionꢀtoꢀtheꢀamplifierꢀnoise.ꢀ
Outputꢀvoltageꢀisꢀselectableꢀfromꢀaꢀminimumꢀofꢀ0.8Vꢀtoꢀ
aꢀmaximumꢀofꢀ1.8Vꢀinꢀincrementsꢀofꢀ50mV.ꢀTheꢀMSB,ꢀ
V ,ꢀsetsꢀtheꢀpedestalꢀvoltage,ꢀandꢀtheꢀLSB’s,ꢀV andꢀ
O2
O1ꢀ
V ꢀincrementꢀV .ꢀ
O0
OUTꢀ
3071f
ꢀꢄ
LT3071
ApplicAtions inFormAtion
TheꢀREF/BYPꢀpinꢀmustꢀnotꢀbeꢀDCꢀloadedꢀbyꢀanythingꢀexceptꢀ High Efficiency Linear Regulator—Input-to-Output
forꢀapplicationsꢀthatꢀparallelꢀotherꢀLT3071ꢀregulatorsꢀforꢀ Voltage Control
higherꢀoutputꢀcurrents.ꢀConsultꢀtheꢀApplicationsꢀSectionꢀ
TheꢀVIOCꢀ(voltageꢀinput-to-outputꢀcontrol)ꢀpinꢀisꢀaꢀfunctionꢀ
onꢀParallelingꢀforꢀfurtherꢀdetails.ꢀ
toꢀcontrolꢀaꢀswitchingꢀregulatorꢀandꢀfacilitateꢀaꢀdesignꢀsolu-
tionꢀthatꢀmaximizesꢀsystemꢀefficiencyꢀatꢀhighꢀloadꢀcurrentsꢀ
Output Voltage Margining
andꢀstillꢀprovidesꢀlowꢀdropoutꢀvoltageꢀperformance.
TheꢀLT3071’sꢀanalogꢀmarginingꢀpin,ꢀMARGA,ꢀprovidesꢀaꢀ
TheꢀVIOCꢀpinꢀisꢀtheꢀoutputꢀofꢀanꢀintegratedꢀtranscon-
continuousꢀoutputꢀvoltageꢀadjustmentꢀrangeꢀofꢀ 10ꢁ.ꢀItꢀ
ductanceꢀamplifierꢀthatꢀsourcesꢀandꢀsinksꢀaboutꢀ250µAꢀ
marginsꢀV ꢀbyꢀadjustingꢀtheꢀinternalꢀ600mVꢀreferenceꢀ
OUT
ofꢀcurrent.ꢀItꢀtypicallyꢀregulatesꢀtheꢀoutputꢀofꢀmostꢀLTC®ꢀ
switchingꢀregulatorsꢀorꢀLTM®ꢀpowerꢀmodules,ꢀbyꢀsinkingꢀ
currentꢀfromꢀtheꢀITHꢀcompensationꢀnode.ꢀTheꢀVIOCꢀfunctionꢀ
controlsꢀaꢀbuckꢀregulatorꢀpoweringꢀtheꢀLT3071’sꢀinputꢀbyꢀ
voltageꢀ upꢀ andꢀ down.ꢀ Theꢀ MARGAꢀ pin’sꢀ typicalꢀ inputꢀ
impedanceꢀisꢀ190kΩꢀbetweenꢀMARGAꢀandꢀtheꢀinternalꢀ
V ꢀnode.ꢀDrivingꢀMARGAꢀwithꢀ600mVꢀtoꢀ1.2Vꢀprovidesꢀ
REF
0ꢁꢀtoꢀ10ꢁꢀofꢀadjustment.ꢀDrivingꢀMARGAꢀwithꢀ600mVꢀtoꢀ
0Vꢀprovidesꢀ0ꢁꢀtoꢀ–10ꢁꢀofꢀadjustment.ꢀIfꢀunused,ꢀallowꢀ
MARGAꢀtoꢀfloatꢀorꢀbypassꢀthisꢀpinꢀwithꢀaꢀ1nFꢀcapacitorꢀ
toꢀGND.ꢀNoteꢀthatꢀtheꢀanalogꢀmarginingꢀfunctionꢀdoesꢀnotꢀ
adjustꢀtheꢀPWRGDꢀthreshold.ꢀTherefore,ꢀnegativeꢀanalogꢀ
marginingꢀmayꢀtripꢀtheꢀPWRGDꢀcomparatorꢀandꢀtoggleꢀ
theꢀPWRGDꢀflag.
maintainingꢀtheꢀLT3071’sꢀinputꢀvoltageꢀtoꢀV ꢀ+ꢀ300mV.ꢀ
OUT
Thisꢀ300mVꢀ V -V ꢀdifferentialꢀvoltageꢀisꢀchosenꢀtoꢀ
IN OUT
provideꢀfastꢀtransientꢀresponseꢀandꢀgoodꢀhighꢀfrequencyꢀ
PSRRꢀwhileꢀminimizingꢀpowerꢀdissipationꢀandꢀmaximizingꢀ
efficiency.ꢀForꢀexample,ꢀ1.5Vꢀtoꢀ1.2Vꢀconversionꢀandꢀ1.3Vꢀ
toꢀ1Vꢀconversionꢀyieldꢀ1.5Wꢀmaximumꢀpowerꢀdissipationꢀ
atꢀ5Aꢀfullꢀoutputꢀcurrent.
Figureꢀ2ꢀdepictsꢀthatꢀtheꢀswitcher’sꢀfeedbackꢀresistorꢀnet-
workꢀsetsꢀtheꢀmaximumꢀswitchingꢀregulatorꢀoutputꢀvoltageꢀ
ifꢀtheꢀlinearꢀregulatorꢀisꢀdisabled.ꢀHowever,ꢀonceꢀtheꢀLT3071ꢀ
isꢀenabled,ꢀtheꢀVIOCꢀfeedbackꢀloopꢀdecreasesꢀtheꢀswitchingꢀ
Enable Function—Turning On and Off
TheꢀENꢀpinꢀenables/disablesꢀtheꢀoutputꢀdeviceꢀonly.ꢀTheꢀ
LT3071ꢀreferenceꢀandꢀallꢀsupportꢀfunctionsꢀremainꢀactiveꢀ
ifꢀV
ꢀisꢀaboveꢀitsꢀUVLOꢀthreshold.ꢀPullingꢀtheꢀENꢀpinꢀ
BIAS
regulatorꢀoutputꢀvoltageꢀbackꢀtoꢀV ꢀ+ꢀ300mV.
OUT
lowꢀputsꢀtheꢀLT3071ꢀintoꢀnapꢀmode.ꢀInꢀnapꢀmode,ꢀtheꢀ
referenceꢀcircuitꢀisꢀactive,ꢀbutꢀtheꢀoutputꢀisꢀdisabledꢀandꢀ
quiescentꢀcurrentꢀdecreases.
UsingꢀtheꢀVIOCꢀfunctionꢀcreatesꢀaꢀfeedbackꢀloopꢀbetweenꢀ
theꢀLT3071ꢀandꢀtheꢀswitchingꢀregulator.ꢀAsꢀsuch,ꢀtheꢀfeed-
backꢀloopꢀmustꢀbeꢀfrequencyꢀcompensatedꢀforꢀstability.ꢀ
Fortunately,ꢀtheꢀconnectionꢀofꢀVIOCꢀtoꢀmanyꢀLTCꢀswitchingꢀ
regulatorꢀITHꢀpinsꢀrepresentsꢀaꢀhighꢀimpedanceꢀcharac-
teristicꢀwhichꢀisꢀtheꢀoptimumꢀcircuitꢀnodeꢀtoꢀfrequencyꢀ
compensateꢀtheꢀfeedbackꢀloop.ꢀFigureꢀ2ꢀillustratesꢀtheꢀ
typicalꢀfrequencyꢀcompensationꢀnetworkꢀusedꢀatꢀtheꢀVIOCꢀ
nodeꢀtoꢀGND.
DriveꢀtheꢀENꢀpinꢀwithꢀeitherꢀaꢀdigitalꢀlogicꢀportꢀorꢀanꢀopen-
collectorꢀNPNꢀorꢀanꢀopen-drainꢀNMOSꢀterminatedꢀwithꢀ
aꢀpull-upꢀresistorꢀtoꢀV
.ꢀTheꢀpull-upꢀresistorꢀmustꢀbeꢀ
IH
BIAS
lessꢀthanꢀ35kꢀtoꢀmeetꢀtheꢀV ꢀconditionꢀofꢀtheꢀENꢀpin.ꢀIfꢀ
unused,ꢀconnectꢀENꢀtoꢀBIAS.
Input Undervoltage Lockout on BIAS Pin
TheꢀVIOCꢀamplifierꢀcharacteristicsꢀare:
Anꢀ internalꢀ undervoltageꢀ lockoutꢀ (UVLO)ꢀ comparatorꢀ
monitorsꢀtheꢀBIASꢀsupplyꢀvoltage.ꢀIfꢀV
ꢀ g ꢀ=ꢀ3.2mS,ꢀI
=ꢀ 250µA,ꢀBWꢀ=ꢀ10MHz.
OUTꢀ
ꢀdropsꢀbelowꢀ
BIAS
m
theꢀUVLOꢀthreshold,ꢀallꢀfunctionsꢀshutꢀdown,ꢀtheꢀpassꢀ
transistorꢀisꢀgatedꢀoffꢀandꢀoutputꢀcurrentꢀfallsꢀtoꢀzero.ꢀTheꢀ
typicalꢀBIASꢀpinꢀUVLOꢀthresholdꢀisꢀ1.55Vꢀonꢀtheꢀrisingꢀ
Ifꢀ theꢀ VIOCꢀ functionꢀ isꢀ notꢀ used,ꢀ terminateꢀ theꢀ VIOCꢀ
pinꢀtoꢀGNDꢀwithꢀaꢀsmallꢀcapacitorꢀ(1000pF)ꢀtoꢀpreventꢀ
oscillations.
edgeꢀofꢀV
.ꢀTheꢀUVLOꢀcircuitꢀincorporatesꢀaboutꢀ150mVꢀ
BIAS
ofꢀhysteresisꢀonꢀtheꢀfallingꢀedgeꢀofꢀV
.ꢀ
BIAS
3071f
ꢀꢅ
LT3071
ApplicAtions inFormAtion
LT3071
IN
OUT
LOAD
SWITCHING REGULATOR
REF
+
–
PWM
FB
VIOC
V
+
OUT
V
300mV
REF
REFERENCE
I
TH
3071 F02
Figure 2. VIOC Control Block Diagram
PWRGD—Power Good
LowꢀESR,ꢀX5RꢀorꢀX7Rꢀceramicꢀchipꢀcapacitorsꢀareꢀtheꢀ
LTCꢀrecommendedꢀchoiceꢀforꢀstabilizingꢀtheꢀLT3071.ꢀAd-
ditionalꢀbulkꢀcapacitorsꢀdistributedꢀbeyondꢀtheꢀimmediateꢀ
decouplingꢀcapacitorsꢀareꢀacceptableꢀasꢀtheirꢀparasiticꢀESLꢀ
andꢀESR,ꢀcombinedꢀwithꢀtheꢀdistributedꢀPCBꢀinductanceꢀ
isolatesꢀthemꢀfromꢀtheꢀprimaryꢀcompensationꢀpoleꢀprovidedꢀ
byꢀtheꢀlocalꢀsurfaceꢀmountꢀceramicꢀcapacitors.ꢀ
PWRGDꢀpinꢀisꢀanꢀopen-drainꢀNMOSꢀdigitalꢀoutputꢀthatꢀ
activelyꢀpullsꢀlowꢀifꢀanyꢀoneꢀofꢀtheseꢀfaultꢀmodesꢀisꢀde-
tected:
•ꢀ V ꢀisꢀlessꢀthanꢀ90ꢁꢀofꢀV
ꢀonꢀtheꢀrisingꢀ
OUT
edgeꢀofꢀV
OUT(NOMINAL)
.
OUTꢀ
•ꢀ V ꢀdropsꢀbelowꢀ85ꢁꢀofꢀV
ꢀforꢀmoreꢀthanꢀ
TheꢀLT3071ꢀrequiresꢀaꢀminimumꢀoutputꢀcapacitanceꢀofꢀ
15µFꢀforꢀstability.ꢀLTCꢀstronglyꢀrecommendsꢀthatꢀtheꢀoutputꢀ
capacitorꢀnetworkꢀconsistꢀofꢀseveralꢀlowꢀvalueꢀceramicꢀ
capacitorsꢀinꢀparallel.ꢀ
OUT
25µs.
OUT(NOMINAL)
•ꢀ V ꢀisꢀlessꢀthanꢀitsꢀundervoltageꢀlockoutꢀthreshold.
BIAS
•ꢀ TheꢀOUT-to-INꢀreverse-currentꢀdetectorꢀactivates.
•ꢀ Junctionꢀtemperatureꢀexceedsꢀ145°Cꢀtypically.*
Why Do Multiple, Small-Value Output Capacitors
Connected in Parallel Work Better?
ꢀ *Theꢀjunctionꢀtemperatureꢀdetectorꢀisꢀanꢀearlyꢀwarningꢀ
indicatorꢀthatꢀtripsꢀapproximatelyꢀ20°Cꢀbeforeꢀthermalꢀ
shutdownꢀengages.ꢀ
TheꢀLT3071’sꢀunity-gainꢀbandwidthꢀwithꢀC ꢀofꢀ15µFꢀisꢀ
OUT
aboutꢀ1MHzꢀatꢀitsꢀfull-loadꢀcurrentꢀofꢀ5A.ꢀSurfaceꢀmountedꢀ
MLCCꢀ capacitorsꢀ haveꢀ aꢀ self-resonanceꢀ frequencyꢀ ofꢀ
f ꢀ=ꢀ1/(2π√LC),ꢀwhichꢀmustꢀbeꢀpushedꢀtoꢀaꢀfrequencyꢀhigherꢀ
Stability and Output Capacitance
R
thanꢀtheꢀregulatorꢀbandwidth.ꢀStandardꢀMLCCꢀcapacitorsꢀ
areꢀacceptable.ꢀToꢀkeepꢀtheꢀresonantꢀfrequencyꢀgreaterꢀ
thanꢀ1MHz,ꢀtheꢀproductꢀ1/(2π√LC)ꢀmustꢀbeꢀgreaterꢀthanꢀ
1MHz.ꢀAtꢀthisꢀbandwidth,ꢀPCBꢀviasꢀcanꢀaddꢀsignificantꢀ
inductance,ꢀthusꢀtheꢀfundamentalꢀdecouplingꢀcapacitorsꢀ
mustꢀbeꢀmountedꢀonꢀtheꢀsameꢀplaneꢀasꢀtheꢀLT3071.
TheꢀLT3071’sꢀfeedbackꢀloopꢀrequiresꢀanꢀoutputꢀcapacitorꢀ
forꢀstability.ꢀChooseꢀC ꢀcarefullyꢀandꢀmountꢀitꢀinꢀcloseꢀ
OUT
proximityꢀtoꢀtheꢀLT3071’sꢀOUTꢀandꢀGNDꢀpins.ꢀIncludeꢀwideꢀ
routingꢀplanesꢀforꢀOUTꢀandꢀGNDꢀtoꢀminimizeꢀinductance.ꢀ
Ifꢀpossible,ꢀmountꢀtheꢀregulatorꢀimmediatelyꢀadjacentꢀtoꢀ
theꢀapplicationꢀloadꢀtoꢀminimizeꢀdistributedꢀinductanceꢀ
forꢀ optimalꢀ loadꢀ transientꢀ performance.ꢀ Point-of-Loadꢀ
applicationsꢀ presentꢀ theꢀ bestꢀ caseꢀ layoutꢀ scenarioꢀ forꢀ
extractingꢀfullꢀLT3071ꢀperformance.ꢀ
3071f
ꢀꢆ
LT3071
ApplicAtions inFormAtion
Typicalꢀ0603ꢀorꢀ0805ꢀcase-sizeꢀcapacitorsꢀhaveꢀanꢀESLꢀofꢀ ManyꢀofꢀtheꢀapplicationsꢀinꢀwhichꢀtheꢀLT3071ꢀexcels,ꢀ
~800pHꢀandꢀPCBꢀmountingꢀcanꢀcontributeꢀupꢀtoꢀ~200pH.ꢀ suchꢀasꢀFPGA,ꢀASICꢀprocessorꢀorꢀDSPꢀsupplies,ꢀtypicallyꢀ
Thus,ꢀ itꢀ becomesꢀ necessaryꢀ toꢀ reduceꢀ theꢀ parasiticꢀ requireꢀaꢀhighꢀfrequencyꢀdecouplingꢀcapacitorꢀnetworkꢀforꢀ
inductanceꢀbyꢀusingꢀaꢀparallelꢀcapacitorꢀcombination.ꢀ theꢀdeviceꢀbeingꢀpowered.ꢀThisꢀnetworkꢀgenerallyꢀconsistsꢀ
Aꢀsuitableꢀmethodologyꢀmustꢀcontrolꢀthisꢀparallelingꢀasꢀ ofꢀmanyꢀlowꢀvalueꢀceramicꢀcapacitorsꢀinꢀparallel.ꢀInꢀsomeꢀ
capacitorsꢀwithꢀtheꢀsameꢀself-resonantꢀfrequency,ꢀf ,ꢀwillꢀ applications,ꢀthisꢀtotalꢀvalueꢀofꢀcapacitanceꢀmayꢀbeꢀcloseꢀ
R
formꢀaꢀtankꢀcircuitꢀthatꢀcanꢀinduceꢀringingꢀofꢀtheirꢀownꢀ toꢀtheꢀLT3071’sꢀminimumꢀ15µFꢀcapacitanceꢀrequirement.ꢀ
accord.ꢀSmallꢀamountsꢀofꢀESRꢀ(5mΩꢀtoꢀ20mΩ)ꢀhaveꢀsomeꢀ Thisꢀmayꢀreduceꢀtheꢀrequiredꢀvalueꢀofꢀcapacitanceꢀdirectlyꢀ
benefitꢀinꢀdampeningꢀtheꢀresonantꢀloop,ꢀbutꢀhigherꢀESRsꢀ atꢀtheꢀLT3071’sꢀoutput.ꢀMultipleꢀlowꢀvalueꢀcapacitorsꢀinꢀ
degradeꢀtheꢀcapacitorꢀresponseꢀtoꢀtransientꢀloadꢀstepsꢀ parallelꢀpresentꢀaꢀfavorableꢀfrequencyꢀcharacteristicꢀthatꢀ
withꢀrise/fallꢀtimesꢀlessꢀthanꢀ1µs.ꢀTheꢀmostꢀareaꢀefficientꢀ pushesꢀmanyꢀofꢀtheꢀparasiticꢀpoles/zeroesꢀbeyondꢀtheꢀ
parallelꢀcapacitorꢀcombinationꢀisꢀaꢀgraduatedꢀ4/2/1ꢀscaleꢀ LT3071’sꢀunity-gainꢀcrossoverꢀfrequency.ꢀThisꢀtechniqueꢀ
ofꢀf ꢀofꢀtheꢀsameꢀcaseꢀsize.ꢀUnderꢀtheseꢀconditions,ꢀtheꢀ illustratesꢀtheꢀmethodꢀthatꢀextractsꢀtheꢀfullꢀbandwidthꢀ
R
individualꢀESLsꢀareꢀrelativelyꢀuniform,ꢀandꢀtheꢀresonanceꢀ performanceꢀofꢀtheꢀLT3071.
peaksꢀareꢀdeconstructivelyꢀspreadꢀbeyondꢀtheꢀregulatorꢀ
Giveꢀadditionalꢀconsiderationꢀtoꢀtheꢀuseꢀofꢀceramicꢀcapaci-
bandwidth.ꢀTheꢀrecommendedꢀparallelꢀcombinationꢀthatꢀ
tors.ꢀCeramicꢀcapacitorsꢀareꢀmanufacturedꢀwithꢀaꢀvarietyꢀofꢀ
approximatesꢀ15µFꢀisꢀ10µFꢀ+ꢀ4.7µFꢀ+ꢀ2.2µF.ꢀCapacitorsꢀ
dielectrics,ꢀeachꢀwithꢀdifferentꢀbehaviorꢀacrossꢀtemperatureꢀ
withꢀcaseꢀsizesꢀlargerꢀthanꢀ0805ꢀhaveꢀhigherꢀESLꢀandꢀ
andꢀappliedꢀvoltage.ꢀTheꢀmostꢀcommonꢀdielectricsꢀusedꢀ
lowerꢀ ESRꢀ (<5mΩ).ꢀ Therefore,ꢀ moreꢀ capacitorsꢀ withꢀ
areꢀspecifiedꢀwithꢀEIAꢀtemperatureꢀcharacteristicꢀcodesꢀofꢀ
smallerꢀvaluesꢀ(<10µF)ꢀmustꢀbeꢀchosen.ꢀUsersꢀshouldꢀ
Z5U,ꢀY5V,ꢀX5RꢀandꢀX7R.ꢀTheꢀZ5UꢀandꢀY5Vꢀdielectricsꢀareꢀ
considerꢀnewꢀgeneration,ꢀlowꢀinductanceꢀcapacitorsꢀtoꢀ
goodꢀforꢀprovidingꢀhighꢀcapacitancesꢀinꢀaꢀsmallꢀpackage,ꢀ
pushꢀoutꢀf ꢀandꢀmaximizeꢀstability.ꢀReferꢀtoꢀtheꢀsurfaceꢀ
R
butꢀtheyꢀtendꢀtoꢀhaveꢀstrongꢀvoltageꢀandꢀtemperatureꢀ
coefficientsꢀasꢀshownꢀinꢀFiguresꢀ4ꢀandꢀ5.ꢀWhenꢀusedꢀwithꢀ
aꢀ5Vꢀregulator,ꢀaꢀ16Vꢀ10µFꢀY5Vꢀcapacitorꢀcanꢀexhibitꢀanꢀ
effectiveꢀvalueꢀasꢀlowꢀasꢀ1µFꢀtoꢀ2µFꢀforꢀtheꢀDCꢀbiasꢀvoltageꢀ
appliedꢀandꢀoverꢀtheꢀoperatingꢀtemperatureꢀrange.ꢀTheꢀX5Rꢀ
andꢀX7Rꢀdielectricsꢀresultꢀinꢀmoreꢀstableꢀcharacteristicsꢀ
andꢀareꢀmoreꢀsuitableꢀforꢀuseꢀasꢀtheꢀoutputꢀcapacitor.ꢀ
mountꢀceramicꢀcapacitorꢀmanufacturer’sꢀdataꢀsheetsꢀforꢀ
capacitorꢀspecifications.ꢀFigureꢀ3ꢀillustratesꢀanꢀoptimumꢀ
PCBꢀlayoutꢀforꢀtheꢀparallelꢀoutputꢀcapacitorꢀcombination,ꢀ
butꢀalsoꢀillustratesꢀtheꢀGNDꢀconnectionꢀbetweenꢀtheꢀINꢀ
capacitorꢀandꢀtheꢀOUTꢀcapacitorsꢀtoꢀminimizeꢀtheꢀACꢀ
GNDꢀloopꢀforꢀfastꢀloadꢀtransients.ꢀThisꢀtightꢀbypassingꢀ
connectionꢀminimizesꢀEMIꢀandꢀoptimizesꢀbypassing.ꢀ
LT3071
SENSE
IN OUT
GND
Lo-Z
INPUT
47µF
LOAD PLANE
2.2µF
4.7µF
10µF
3071 F03
Figure 3. Example PCB Layout
3071f
ꢀꢇ
LT3071
ApplicAtions inFormAtion
20
coefficientsꢀareꢀnotꢀtheꢀonlyꢀsourcesꢀofꢀproblems.ꢀSomeꢀ
ceramicꢀcapacitorsꢀhaveꢀaꢀpiezoelectricꢀresponse.ꢀAꢀpiezo-
electricꢀdeviceꢀgeneratesꢀvoltageꢀacrossꢀitsꢀterminalsꢀdueꢀ
toꢀmechanicalꢀstress,ꢀsimilarꢀtoꢀtheꢀwayꢀaꢀpiezoelectricꢀ
microphoneꢀworks.ꢀForꢀaꢀceramicꢀcapacitorꢀtheꢀstressꢀ
canꢀbeꢀinducedꢀbyꢀvibrationsꢀinꢀtheꢀsystemꢀorꢀthermalꢀ
transients.ꢀ
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
0
X5R
–20
–40
–60
Y5V
–80
Stability and Input Capacitance
–100
Theꢀ LT3071ꢀ isꢀ stableꢀ withꢀ aꢀ minimumꢀ capacitanceꢀ ofꢀ
47µFꢀconnectedꢀtoꢀitsꢀINꢀpins.ꢀUseꢀlowꢀESRꢀcapacitorsꢀtoꢀ
minimizeꢀinstantaneousꢀvoltageꢀdropsꢀunderꢀlargeꢀloadꢀ
10 12
DC BIAS VOLTAGE (V)
0
2
4
6
8
14 16
3071 F04
transientꢀconditions.ꢀLargeꢀV ꢀdroopsꢀduringꢀlargeꢀloadꢀ
Figure 4. Ceramic Capacitor DC Bias Characteristics
IN
transientsꢀmayꢀcauseꢀtheꢀregulatorꢀtoꢀenterꢀdropoutꢀwithꢀ
correspondingꢀ degradationꢀ inꢀ loadꢀ transientꢀ response.ꢀ
Increasedꢀvaluesꢀofꢀinputꢀandꢀoutputꢀcapacitanceꢀmayꢀbeꢀ
necessaryꢀdependingꢀonꢀanꢀapplication’sꢀrequirements.ꢀ
Sufficientꢀ inputꢀ capacitanceꢀ isꢀ criticalꢀ asꢀ theꢀ circuitꢀ isꢀ
intentionallyꢀoperatedꢀcloseꢀtoꢀdropoutꢀtoꢀminimizeꢀpower.ꢀ
Ideally,ꢀtheꢀoutputꢀimpedanceꢀofꢀtheꢀsupplyꢀthatꢀpowersꢀ
INꢀshouldꢀbeꢀlessꢀthanꢀ10mΩꢀtoꢀsupportꢀaꢀ5Aꢀloadꢀwithꢀ
largeꢀtransients.
40
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
20
X5R
0
–20
Y5V
–40
–60
–80
Inꢀcasesꢀwhereꢀwireꢀisꢀusedꢀtoꢀconnectꢀaꢀpowerꢀsupplyꢀ
toꢀtheꢀinputꢀofꢀtheꢀLT3071ꢀ(andꢀalsoꢀfromꢀtheꢀgroundꢀofꢀ
theꢀLT3071ꢀbackꢀtoꢀtheꢀpowerꢀsupplyꢀground),ꢀlargeꢀinputꢀ
capacitorsꢀareꢀrequiredꢀtoꢀavoidꢀanꢀunstableꢀapplication.ꢀ
–100
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
3071 F05
Figure 5. Ceramic Capacitor Temperature Characteristics
ThisꢀisꢀdueꢀtoꢀtheꢀinductanceꢀofꢀtheꢀwireꢀformingꢀanꢀLCꢀ
tankꢀcircuitꢀwithꢀtheꢀinputꢀcapacitorꢀandꢀnotꢀaꢀresultꢀofꢀtheꢀ
LT3071ꢀbeingꢀunstable.ꢀTheꢀselfꢀinductance,ꢀorꢀisolatedꢀ
inductance,ꢀofꢀaꢀwireꢀisꢀdirectlyꢀproportionalꢀtoꢀitsꢀlength.ꢀ
However,ꢀtheꢀdiameterꢀofꢀaꢀwireꢀdoesꢀnotꢀhaveꢀaꢀmajorꢀ
influenceꢀonꢀitsꢀselfꢀinductance.ꢀForꢀexample,ꢀoneꢀinchꢀofꢀ
18-AWG,ꢀ0.04ꢀinchꢀdiameterꢀwireꢀhasꢀ28nHꢀofꢀselfꢀinduc-
tance.ꢀTheꢀselfꢀinductanceꢀofꢀaꢀ2-AWGꢀisolatedꢀwireꢀwithꢀ
aꢀdiameterꢀofꢀ0.26ꢀinchꢀisꢀaboutꢀhalfꢀtheꢀinductanceꢀofꢀaꢀ
18-AWGꢀwire.ꢀTheꢀoverallꢀselfꢀinductanceꢀofꢀaꢀwireꢀcanꢀ
beꢀreducedꢀinꢀtwoꢀways.ꢀOneꢀisꢀtoꢀdivideꢀtheꢀcurrentꢀflow-
ingꢀtowardsꢀtheꢀLT3071ꢀbetweenꢀtwoꢀparallelꢀconductorsꢀ
whichꢀflowsꢀinꢀtheꢀsameꢀdirectionꢀinꢀeach.ꢀInꢀthisꢀcase,ꢀ
TheꢀX7Rꢀtypeꢀhasꢀbetterꢀstabilityꢀacrossꢀtemperature,ꢀ
whileꢀtheꢀX5Rꢀisꢀlessꢀexpensiveꢀandꢀisꢀavailableꢀinꢀhigherꢀ
values.ꢀCareꢀstillꢀmustꢀbeꢀexercisedꢀwhenꢀusingꢀX5Rꢀandꢀ
X7Rꢀcapacitors;ꢀtheꢀX5RꢀandꢀX7Rꢀcodesꢀonlyꢀspecifyꢀ
operatingꢀtemperatureꢀrangeꢀandꢀmaximumꢀcapacitanceꢀ
changeꢀ overꢀ temperature.ꢀ Capacitanceꢀ changeꢀ dueꢀ toꢀ
DCꢀbiasꢀwithꢀX5RꢀandꢀX7RꢀcapacitorsꢀisꢀbetterꢀthanꢀY5Vꢀ
andꢀZ5Uꢀcapacitors,ꢀbutꢀcanꢀstillꢀbeꢀsignificantꢀenoughꢀtoꢀ
dropꢀcapacitorꢀvaluesꢀbelowꢀappropriateꢀlevels.ꢀCapacitorꢀ
DCꢀbiasꢀcharacteristicsꢀtendꢀtoꢀimproveꢀasꢀcomponentꢀ
caseꢀsizeꢀincreases,ꢀbutꢀexpectedꢀcapacitanceꢀatꢀoperat-
ingꢀvoltageꢀshouldꢀbeꢀverified.ꢀVoltageꢀandꢀtemperatureꢀ
3071f
ꢀꢈ
TheꢀLT3071ꢀprovidesꢀaꢀKelvinꢀsenseꢀpinꢀforꢀV
,ꢀallowingꢀ
LT3071
ApplicAtions inFormAtion
theꢀfartherꢀtheꢀwiresꢀareꢀplacedꢀapartꢀfromꢀeachꢀother,ꢀtheꢀ Figureꢀ1ꢀinꢀtheꢀPinꢀFunctionsꢀsectionꢀillustratesꢀtheꢀKelvin-
moreꢀinductanceꢀwillꢀbeꢀreduced,ꢀupꢀtoꢀaꢀ50ꢁꢀreductionꢀ Senseꢀconnectionꢀmethodꢀthatꢀeliminatesꢀvoltageꢀdropsꢀ
whenꢀplacedꢀaꢀfewꢀinchesꢀapart.ꢀSplittingꢀtheꢀwiresꢀbasi-
dueꢀtoꢀPCBꢀtraceꢀresistance.ꢀHowever,ꢀnoteꢀthatꢀtheꢀvoltageꢀ
callyꢀconnectsꢀtwoꢀequalꢀinductorsꢀinꢀparallel.ꢀHowever,ꢀ dropꢀacrossꢀtheꢀexternalꢀPCBꢀtracesꢀaddsꢀtoꢀtheꢀdropoutꢀ
whenꢀplacedꢀinꢀcloseꢀproximityꢀfromꢀeachꢀother,ꢀmutualꢀ voltageꢀofꢀtheꢀregulator.ꢀTheꢀSENSEꢀpinꢀinputꢀbiasꢀcurrentꢀ
inductanceꢀisꢀaddedꢀtoꢀtheꢀoverallꢀselfꢀinductanceꢀofꢀtheꢀ dependsꢀonꢀtheꢀselectedꢀoutputꢀvoltage.ꢀSENSEꢀpinꢀinputꢀ
wires.ꢀTheꢀmostꢀeffectiveꢀwayꢀtoꢀreduceꢀoverallꢀinductanceꢀ currentꢀvariesꢀfromꢀ50µAꢀtypicallyꢀatꢀV ꢀ=ꢀ0.8Vꢀtoꢀ300µAꢀ
OUT
isꢀtoꢀplaceꢀtheꢀforwardꢀandꢀreturn-currentꢀconductorsꢀ(theꢀ typicallyꢀatꢀV ꢀ=ꢀ1.8V.
OUT
wireꢀforꢀtheꢀinputꢀandꢀtheꢀwireꢀforꢀtheꢀreturnꢀground)ꢀinꢀ
Short-Circuit and Overload Recovery
veryꢀcloseꢀproximity.ꢀTwoꢀ18-AWGꢀwiresꢀseparatedꢀbyꢀ
0.05ꢀinchꢀreduceꢀtheꢀoverallꢀselfꢀinductanceꢀtoꢀaboutꢀone-
fourthꢀofꢀaꢀsingleꢀisolatedꢀwire.ꢀIfꢀtheꢀLT3071ꢀisꢀpoweredꢀ
byꢀaꢀbatteryꢀmountedꢀinꢀcloseꢀproximityꢀwithꢀgroundꢀandꢀ
powerꢀplanesꢀonꢀtheꢀsameꢀcircuitꢀboard,ꢀaꢀ47µFꢀinputꢀ
capacitorꢀisꢀsufficientꢀforꢀstability.ꢀHowever,ꢀifꢀtheꢀLT3071ꢀ
isꢀpoweredꢀbyꢀaꢀdistantꢀsupply,ꢀuseꢀaꢀlowꢀESR,ꢀlargeꢀvalueꢀ
inputꢀcapacitorꢀonꢀtheꢀorderꢀofꢀ330µF.ꢀAsꢀpowerꢀsupplyꢀ
outputꢀimpedanceꢀvaries,ꢀtheꢀminimumꢀinputꢀcapacitanceꢀ
neededꢀforꢀapplicationꢀstabilityꢀalsoꢀvaries.
LikeꢀmanyꢀICꢀpowerꢀregulators,ꢀtheꢀLT3071ꢀhasꢀsafeꢀop-
eratingꢀareaꢀ(SOA)ꢀprotection.ꢀTheꢀsafeꢀareaꢀprotectionꢀ
decreasesꢀcurrentꢀlimitꢀasꢀinput-to-outputꢀvoltageꢀincreasesꢀ
andꢀkeepsꢀtheꢀpowerꢀtransistorꢀinsideꢀaꢀsafeꢀoperatingꢀ
regionꢀforꢀallꢀvaluesꢀofꢀinput-to-outputꢀvoltageꢀupꢀtoꢀtheꢀ
absoluteꢀmaximumꢀvoltageꢀrating.ꢀV
ꢀmustꢀbeꢀaboveꢀ
BIAS
theꢀUVLOꢀthresholdꢀforꢀanyꢀfunction.ꢀTheꢀLT3071ꢀhasꢀaꢀ
precisionꢀcurrentꢀlimitꢀspecifiedꢀatꢀ 20ꢁꢀthatꢀisꢀactiveꢀifꢀ
V
BIAS
ꢀisꢀaboveꢀUVLO.ꢀ
Underꢀ conditionsꢀ ofꢀ maximumꢀ I
IN OUT
ꢀ andꢀ maximumꢀ
Bias Pin Capacitance Requirements
LOAD
V -V ꢀtheꢀdevice’sꢀpowerꢀdissipationꢀpeaksꢀatꢀaboutꢀ
TheꢀBIASꢀpinꢀsuppliesꢀcurrentꢀtoꢀmostꢀofꢀtheꢀinternalꢀ
controlꢀcircuitryꢀandꢀtheꢀoutputꢀstageꢀdrivingꢀtheꢀpassꢀ
transistor.ꢀTheꢀLT3071ꢀrequiresꢀaꢀminimumꢀ2.2µFꢀby-
passꢀ capacitorꢀ forꢀ stabilityꢀ andꢀ properꢀ operation.ꢀ Toꢀ
ensureꢀ properꢀ operation,ꢀ theꢀ BIASꢀ voltageꢀ mustꢀ sat-
3W.ꢀIfꢀambientꢀtemperatureꢀisꢀhighꢀenough,ꢀdieꢀjunctionꢀ
temperatureꢀwillꢀexceedꢀtheꢀ125°Cꢀmaximumꢀoperatingꢀ
temperature.ꢀ Ifꢀ thisꢀ occurs,ꢀ theꢀ LT3071ꢀ reliesꢀ onꢀ twoꢀ
additionalꢀthermalꢀsafetyꢀfeatures.ꢀAtꢀaboutꢀ145°C,ꢀtheꢀ
PWRGDꢀoutputꢀpullsꢀlowꢀprovidingꢀanꢀearlyꢀwarningꢀofꢀanꢀ
impendingꢀthermalꢀshutdownꢀcondition.ꢀAtꢀ165°Cꢀtypically,ꢀ
theꢀLT3071’sꢀthermalꢀshutdownꢀengagesꢀandꢀtheꢀoutputꢀisꢀ
shutꢀdownꢀuntilꢀtheꢀICꢀtemperatureꢀfallsꢀbelowꢀtheꢀthermalꢀ
hysteresisꢀlimit.ꢀTheꢀSOAꢀprotectionꢀdecreasesꢀcurrentꢀlimitꢀ
asꢀtheꢀIN-to-OUTꢀvoltageꢀincreasesꢀandꢀkeepsꢀtheꢀpowerꢀ
dissipationꢀatꢀsafeꢀlevelsꢀforꢀallꢀvaluesꢀofꢀinput-to-outputꢀ
voltage.ꢀTheꢀLT3071ꢀprovidesꢀsomeꢀoutputꢀcurrentꢀatꢀallꢀ
valuesꢀofꢀinput-to-outputꢀvoltageꢀupꢀtoꢀtheꢀabsoluteꢀmaxi-
isfyꢀtheꢀfollowingꢀconditions:ꢀ2.2Vꢀ≤ꢀV
ꢀ≤ꢀ3.6Vꢀandꢀ
BIAS
V
ꢀ ≥ꢀ (1.25ꢀ •ꢀ V ꢀ +ꢀ 1V).ꢀ Forꢀ V ꢀ ≤ꢀ 0.95V,ꢀ theꢀ
BIAS
OUT OUT
minimumꢀBIASꢀvoltageꢀisꢀlimitedꢀtoꢀ2.2V.ꢀ
Load Regulation
OUT
theꢀapplicationꢀtoꢀcorrectꢀforꢀparasiticꢀpackageꢀandꢀPCBꢀ
I-Rꢀdrops.ꢀHowever,ꢀLTCꢀrecommendsꢀthatꢀtheꢀSENSEꢀpinꢀ
terminateꢀinꢀcloseꢀproximityꢀtoꢀtheꢀLT3071’sꢀOUTꢀpins.ꢀ
Thisꢀminimizesꢀparasiticꢀinductanceꢀandꢀoptimizesꢀregula-
tion.ꢀTheꢀLT3071ꢀhandlesꢀmoderateꢀlevelsꢀofꢀoutputꢀlineꢀ
mumꢀvoltageꢀrating.ꢀSeeꢀtheꢀCurrentꢀLimitꢀvsꢀV ꢀcurveꢀinꢀ
theꢀTypicalꢀPerformanceꢀCharacteristics.ꢀ
IN
Duringꢀstart-up,ꢀafterꢀtheꢀBIASꢀvoltageꢀhasꢀclearedꢀitsꢀUVLOꢀ
impedance,ꢀbutꢀexcessiveꢀimpedanceꢀbetweenꢀV ꢀandꢀ
OUT
thresholdꢀandꢀV ꢀisꢀincreasing,ꢀoutputꢀvoltageꢀincreasesꢀ
IN
C
ꢀcausesꢀexcessiveꢀphaseꢀshiftꢀinꢀtheꢀfeedbackꢀloopꢀ
OUT
atꢀtheꢀrateꢀofꢀcurrentꢀlimitꢀchargingꢀC .ꢀ
OUTꢀ
andꢀadverselyꢀaffectsꢀstability.
3071f
ꢁ0
LT3071
ApplicAtions inFormAtion
Withꢀaꢀhighꢀinputꢀvoltage,ꢀaꢀproblemꢀcanꢀoccurꢀwhereꢀtheꢀ Thisꢀincludesꢀjunctionꢀtoꢀcase,ꢀcase-to-heatꢀsinkꢀinterface,ꢀ
removalꢀofꢀanꢀoutputꢀshortꢀwillꢀnotꢀallowꢀtheꢀoutputꢀvolt- heatꢀsinkꢀresistanceꢀorꢀcircuitꢀboardꢀtoꢀambientꢀasꢀtheꢀ
ageꢀtoꢀrecover.ꢀOtherꢀregulatorsꢀwithꢀcurrentꢀlimitꢀfoldbackꢀ applicationꢀdictates.ꢀAlso,ꢀconsiderꢀadditionalꢀheatꢀsourcesꢀ
alsoꢀexhibitꢀthisꢀphenomenon,ꢀsoꢀitꢀisꢀnotꢀuniqueꢀtoꢀtheꢀ mountedꢀinꢀproximityꢀtoꢀtheꢀLT3071.ꢀTheꢀLT3071ꢀisꢀaꢀsurfaceꢀ
LT3071.ꢀTheꢀloadꢀlineꢀforꢀsuchꢀaꢀloadꢀmayꢀintersectꢀtheꢀ mountꢀdeviceꢀandꢀasꢀsuch,ꢀheatꢀsinkingꢀisꢀaccomplishedꢀ
outputꢀcurrentꢀcurveꢀatꢀtwoꢀpoints:ꢀnormalꢀoperationꢀandꢀ byꢀusingꢀtheꢀheatꢀspreadingꢀcapabilitiesꢀofꢀtheꢀPCꢀboardꢀ
theꢀSOAꢀrestrictedꢀloadꢀcurrentꢀsettings.ꢀAꢀcommonꢀsitu-
andꢀ itsꢀ copperꢀ traces.ꢀ Surfaceꢀ mountꢀ heatꢀ sinksꢀ andꢀ
ationꢀisꢀimmediatelyꢀafterꢀtheꢀremovalꢀofꢀaꢀshortꢀcircuit,ꢀ platedꢀthrough-holesꢀcanꢀalsoꢀbeꢀusedꢀtoꢀspreadꢀtheꢀheatꢀ
butꢀwithꢀaꢀstaticꢀloadꢀ≥ꢀ1A.ꢀInꢀthisꢀsituation,ꢀremovalꢀofꢀtheꢀ generatedꢀ byꢀ powerꢀ devices.ꢀ Junction-to-caseꢀ thermalꢀ
loadꢀorꢀreductionꢀofꢀI ꢀtoꢀ<1Aꢀwillꢀclearꢀthisꢀconditionꢀ resistanceꢀisꢀspecifiedꢀfromꢀtheꢀICꢀjunctionꢀtoꢀtheꢀbottomꢀ
OUT
andꢀallowꢀV ꢀtoꢀreturnꢀtoꢀnormalꢀregulation.
ofꢀtheꢀcaseꢀdirectlyꢀbelowꢀtheꢀdie.ꢀThisꢀisꢀtheꢀlowestꢀresis-
tanceꢀpathꢀforꢀheatꢀflow.ꢀProperꢀmountingꢀisꢀrequiredꢀtoꢀ
ensureꢀtheꢀbestꢀpossibleꢀthermalꢀflowꢀfromꢀthisꢀareaꢀofꢀtheꢀ
packageꢀtoꢀtheꢀheatꢀsinkingꢀmaterial.ꢀNoteꢀthatꢀtheꢀexposedꢀ
padꢀisꢀelectricallyꢀconnectedꢀtoꢀGND.ꢀ
OUT
Reverse Voltage
TheꢀLT3071ꢀincorporatesꢀaꢀcircuitꢀthatꢀdetectsꢀifꢀV ꢀde-
IN
creasesꢀbelowꢀV .ꢀThisꢀreverse-voltageꢀdetectorꢀhasꢀ
OUTꢀ
aꢀtypicalꢀthresholdꢀofꢀaboutꢀ(V ꢀ–ꢀV )ꢀ=ꢀ–6mV.ꢀIfꢀtheꢀ
Tableꢀ3ꢀlistsꢀthermalꢀresistanceꢀasꢀaꢀfunctionꢀofꢀcopperꢀ
areaꢀinꢀaꢀfixedꢀboardꢀsize.ꢀAllꢀmeasurementsꢀwereꢀtakenꢀ
inꢀstillꢀairꢀonꢀaꢀ4-layerꢀFR-4ꢀboardꢀwithꢀ1ꢀozꢀsolidꢀinternalꢀ
planesꢀandꢀ2ꢀozꢀtop/bottomꢀexternalꢀtraceꢀplanesꢀwithꢀaꢀ
totalꢀboardꢀthicknessꢀofꢀ1.6mm.ꢀPCBꢀlayers,ꢀcopperꢀweight,ꢀ
boardꢀlayoutꢀandꢀthermalꢀviasꢀaffectꢀtheꢀresultantꢀthermalꢀ
resistance.ꢀForꢀfurtherꢀinformationꢀonꢀthermalꢀresistanceꢀ
andꢀhighꢀthermalꢀꢀconductivityꢀtestꢀboards,ꢀreferꢀtoꢀJEDECꢀ
standardꢀ JESD51,ꢀ notablyꢀ JESD51-12ꢀ andꢀ JESD51-7.ꢀ
Achievingꢀlowꢀthermalꢀresistanceꢀnecessitatesꢀattentionꢀ
toꢀdetailꢀandꢀcarefulꢀPCBꢀlayout.
IN
OUT
thresholdꢀisꢀexceeded,ꢀthisꢀdetectorꢀcircuitꢀturnsꢀoffꢀtheꢀ
driveꢀtoꢀtheꢀinternalꢀNMOSꢀpassꢀtransistor,ꢀtherebyꢀturningꢀ
offꢀtheꢀoutput.ꢀTheꢀoutputꢀpullsꢀlowꢀwithꢀtheꢀloadꢀcurrentꢀ
dischargingꢀtheꢀoutputꢀcapacitance.ꢀThisꢀcircuit’sꢀintentꢀ
isꢀtoꢀlimitꢀandꢀpreventꢀback-feedꢀcurrentꢀfromꢀOUTꢀtoꢀINꢀ
ifꢀtheꢀinputꢀvoltageꢀcollapsesꢀdueꢀtoꢀaꢀfaultꢀorꢀoverloadꢀ
condition.
Thermal Considerations
Theꢀ LT3071’sꢀ maximumꢀ ratedꢀ junctionꢀ temperatureꢀ ofꢀ
125°Cꢀlimitsꢀitsꢀpowerꢀhandlingꢀcapabilityꢀandꢀisꢀdomi-
natedꢀbyꢀtheꢀoutputꢀcurrentꢀmultipliedꢀbyꢀtheꢀinput/outputꢀ
voltageꢀdifferential:ꢀ
Table 3, UFD Plastic Package, 28-Lead QFN
COPPER AREA
THERMAL RESISTANCE
TOPSIDE* BACK SIDE BOARD AREA (JUNCTION-TO-AMBIENT)
2
2
2
2
2
2
2
2
2
ꢀ I ꢀ•ꢀ(V ꢀ–ꢀV )ꢀ
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
30°C/W
32°C/W
33°C/W
35°C/W
OUT
IN
OUT
2
1000mm
TheꢀLT3071’sꢀinternalꢀpowerꢀandꢀthermalꢀlimitingꢀcircuitryꢀ
protectꢀitꢀunderꢀoverloadꢀconditions.ꢀForꢀcontinuousꢀnor-
malꢀloadꢀconditions,ꢀdoꢀnotꢀexceedꢀtheꢀmaximumꢀjunctionꢀ
temperatureꢀofꢀ125°C.ꢀGiveꢀcarefulꢀconsiderationꢀtoꢀallꢀ
sourcesꢀofꢀthermalꢀresistanceꢀfromꢀjunctionꢀtoꢀambient.ꢀ
2
225mm
100mm
2
*Deviceꢀisꢀmountedꢀonꢀtopside
3071f
ꢁꢀ
LT3071
ApplicAtions inFormAtion
Calculating Junction Temperature
Paralleling Devices for Higher I
OUT
Example:ꢀGivenꢀanꢀoutputꢀvoltageꢀofꢀ0.9V,ꢀanꢀinputꢀvoltageꢀ MultipleꢀLT3071sꢀmayꢀbeꢀparalleledꢀtoꢀobtainꢀhigherꢀoutputꢀ
rangeꢀofꢀ1.2Vꢀ ꢀ5ꢁ,ꢀaꢀBIASꢀvoltageꢀofꢀ2.5V,ꢀaꢀmaximumꢀout- current.ꢀThisꢀparallelingꢀconceptꢀborrowsꢀfromꢀtheꢀschemeꢀ
putꢀcurrentꢀofꢀ4Aꢀandꢀaꢀmaximumꢀambientꢀtemperatureꢀofꢀ employedꢀbyꢀtheꢀLT3080.
50°C,ꢀwhatꢀwillꢀtheꢀmaximumꢀjunctionꢀtemperatureꢀbe?
Toꢀaccomplishꢀthisꢀparalleling,ꢀtieꢀtheꢀREF/BYPꢀpinsꢀofꢀ
Theꢀpowerꢀdissipatedꢀbyꢀtheꢀdeviceꢀequals:
ꢀ•ꢀ(V ꢀ–ꢀV )ꢀ+ꢀ(I –ꢀI )ꢀ•ꢀV ꢀ
OUT
theꢀparalleledꢀregulatorsꢀtogether.ꢀThisꢀeffectivelyꢀgivesꢀ
anꢀaveragedꢀvalueꢀofꢀmultipleꢀ600mVꢀreferenceꢀvoltageꢀ
sources.ꢀTieꢀtheꢀOUTꢀpinsꢀofꢀtheꢀparalleledꢀregulatorsꢀtoꢀ
theꢀcommonꢀloadꢀplaneꢀthroughꢀaꢀsmallꢀpieceꢀofꢀPCꢀtraceꢀ
ballastꢀorꢀanꢀactualꢀsurfaceꢀmountꢀsenseꢀresistorꢀbeyondꢀ
theꢀprimaryꢀoutputꢀcapacitorsꢀofꢀeachꢀregulator.ꢀTheꢀre-
quiredꢀballastꢀisꢀdependentꢀuponꢀtheꢀapplicationꢀoutputꢀ
voltageꢀandꢀpeakꢀloadꢀcurrent.ꢀTheꢀrecommendedꢀballastꢀ
isꢀthatꢀvalueꢀwhichꢀcontributesꢀ1ꢁꢀtoꢀloadꢀregulation.ꢀForꢀ
example,ꢀtwoꢀLT3071ꢀregulatorsꢀconfiguredꢀtoꢀoutputꢀ1V,ꢀ
sharingꢀaꢀ10Aꢀloadꢀrequireꢀ2mΩꢀofꢀballastꢀatꢀeachꢀoutput.ꢀ
TheꢀKelvinꢀSENSEꢀpinsꢀconnectꢀtoꢀtheꢀregulatorꢀsideꢀofꢀ
theꢀballastꢀresistorsꢀtoꢀkeepꢀtheꢀindividualꢀcontrolꢀloopsꢀ
fromꢀconflictingꢀwithꢀeachꢀotherꢀ(seeꢀFiguresꢀ8ꢀandꢀ9).ꢀ
Keepꢀthisꢀballastꢀtraceꢀareaꢀfreeꢀofꢀsolderꢀtoꢀmaintainꢀaꢀ
controlledꢀresistance.ꢀ
I
OUT(MAX)
+ꢀI ꢀ•ꢀV
IN(MAX)
OUT
BIASꢀ GND
GND
BIAS
where:
ꢀ I
ꢀ=ꢀ4A
OUT(MAX)
ꢀ V ꢀ=ꢀ1.26V
IN(MAX)
ꢀ I
ꢀatꢀ(I ꢀ=ꢀ4A,ꢀV
ꢀ=ꢀ2.5V)ꢀ=ꢀ6.91mA
BIAS
BIAS
OUT
ꢀ I ꢀatꢀ(I ꢀ=ꢀ4A,ꢀV ꢀ=ꢀ2.5V)ꢀ=ꢀ0.87mA
BIAS
GND
OUT
thus:
Pꢀ=ꢀ4Aꢀ•ꢀ(1.26Vꢀ–ꢀ0.9V)ꢀ+ꢀ(6.91mAꢀ–ꢀ0.87mA)ꢀ•ꢀ0.9Vꢀ
+ꢀ0.87mAꢀ•ꢀ2.5Vꢀ=ꢀ1.448W
Withꢀ theꢀ QFNꢀ packageꢀ solderedꢀ toꢀ maximumꢀ copperꢀ
area,ꢀtheꢀthermalꢀresistanceꢀisꢀ30°C/W.ꢀSoꢀtheꢀjunctionꢀ
temperatureꢀriseꢀaboveꢀambientꢀequals:
Tableꢀ4ꢀshowsꢀaꢀsimpleꢀguidelineꢀforꢀPCBꢀtraceꢀresistanceꢀ
asꢀaꢀfunctionꢀofꢀweightꢀandꢀtraceꢀwidth.
ꢀ 1.448Wꢀatꢀ30°C/Wꢀ=ꢀ43.44°C
Table 4. PC Board Trace Resistance
Theꢀmaximumꢀjunctionꢀtemperatureꢀequalsꢀtheꢀmaximumꢀ
ambientꢀtemperatureꢀplusꢀtheꢀmaximumꢀjunctionꢀtempera-
tureꢀriseꢀaboveꢀambientꢀor:ꢀ
WEIGHT (Oz)
100 MIL WIDTH*
200 MIL WIDTH*
1
2
5.43
2.71
2.71
1.36
*Traceꢀresistanceꢀisꢀmeasuredꢀinꢀmilliohms/in
ꢀ T ꢀ=ꢀ50°Cꢀ+ꢀ43.44°Cꢀ=ꢀ93.44°C
JMAX
Applicationsꢀ thatꢀ cannotꢀ supportꢀ extensiveꢀ PCBꢀ spaceꢀ
forꢀheatꢀsinkingꢀtheꢀLT3071ꢀrequireꢀaꢀderatingꢀofꢀoutputꢀ
currentꢀorꢀincreasedꢀairflow.ꢀ
3071f
ꢁꢁ
LT3071
ApplicAtions inFormAtion
Quieting the Noise
capacitorꢀminimizesꢀreferenceꢀnoiseꢀtoꢀ10µV
ꢀatꢀtheꢀ
RMS
600mVꢀREF/BYPꢀpin,ꢀequivalentlyꢀaꢀ17µVꢀcontributionꢀtoꢀ
TheꢀLT3071ꢀoffersꢀnumerousꢀnoiseꢀperformanceꢀadvan-
tages.ꢀEachꢀLDOꢀhasꢀseveralꢀsourcesꢀofꢀnoise.ꢀAnꢀLDO’sꢀ
mostꢀcriticalꢀnoiseꢀsourceꢀisꢀtheꢀreference,ꢀfollowedꢀbyꢀ
theꢀLDOꢀerrorꢀamplifier.ꢀTraditionalꢀlowꢀnoiseꢀregulatorsꢀ
outputꢀnoiseꢀatꢀV ꢀ=ꢀ1V.ꢀSeeꢀtheꢀTypicalꢀPerformanceꢀ
OUT
CharacteristicsꢀforꢀNoiseꢀvsꢀOutputꢀVoltageꢀperformanceꢀ
asꢀaꢀfunctionꢀofꢀC
.
REF/BYPꢀ
bufferꢀtheꢀvoltageꢀreferenceꢀoutꢀtoꢀanꢀexternalꢀpinꢀ(usuallyꢀ Thisꢀ approachꢀ alsoꢀ accommodatesꢀ referenceꢀ sharingꢀ
throughꢀaꢀlargeꢀvalueꢀresistor)ꢀtoꢀallowꢀforꢀbypassingꢀandꢀ betweenꢀLT3071ꢀregulatorsꢀthatꢀareꢀhookedꢀupꢀinꢀcur-
noiseꢀreductionꢀofꢀreferenceꢀnoise.ꢀTheꢀLT3071ꢀdeviatesꢀ rentꢀsharingꢀapplications.ꢀTheꢀREF/BYPꢀfilterꢀcapacitorꢀ
fromꢀtheꢀtraditionalꢀvoltageꢀreferenceꢀbyꢀgeneratingꢀaꢀ delaysꢀtheꢀinitialꢀpower-upꢀtimeꢀbyꢀaꢀfactorꢀofꢀtheꢀRCꢀtimeꢀ
lowꢀvoltageꢀV ꢀfromꢀaꢀreferenceꢀcurrentꢀintoꢀanꢀinter-
constant.ꢀV ꢀremainsꢀactiveꢀinꢀnapꢀmode,ꢀthusꢀstart-upꢀ
REF
REF
nalꢀ resistorꢀ ≅19k.ꢀ Thisꢀ intermediateꢀ impedanceꢀ nodeꢀ timeꢀisꢀsignificantlyꢀreducedꢀandꢀwellꢀcontrolledꢀcomingꢀ
(REF/BYP)ꢀfacilitatesꢀexternalꢀfilteringꢀdirectly.ꢀAꢀ10nFꢀfilterꢀ outꢀofꢀnapꢀmodeꢀ(EN:LO↑HI).
50k
V
BIAS
PWRGD
2.2V TO 3.6V
2.2µF
BIAS
V
IN
IN
PWRGD
SENSE
1.5V
EN
330µF
V
1.2V
5A
OUT
LT3071
OUT
V
O0
V
O1
V
O2
2.2µF*
4.7µF*
10µF*
*X5R OR X7R CAPACITORS
V
MON
NC
I
2V AT 5A
MARGA
VIOC
MON
FULL SCALE
REF/BYP
GND
1k
1nF
0.01µF
3071 F06
Figure 6. 1.5V to 1.2V Linear Regulator
3071f
ꢁꢂ
LT3071
typicAl ApplicAtions
V
BIAS
3.3V
47µF
6.3V
s3
1Ω
50k
SV
IN
PWRGD
2.2µF*
NC
2.2µF
0.1µF
BIAS
PGOOD RUN PV
PV
SV
TRACK
IN
IN
IN
0.2µH
IN
PWRGD
SENSE
OUT
1.3V/5A
SGND
SW
SW
SW
SW
EN
V
1V
5A
OUT
47µF
PV
IN
PV
IN
LT3071
NC
NC
V
O0
V
O1
V
O2
4.7µF*
10µF*
20k
PLLLPF
*X5R OR X7R CAPACITORS
I
TH
LTC3415EUHF
V
MON
MGN
BSEL
2V AT 5A
FULL SCALE
NC
MARGA
VIOC
I
100µF
6.3V
s2
MON
REF/BYP
GND
NC
SV
NC
NC
CLKOUT
PHMODE
CLKIN
V
FB
1k
IN
10k 2k
4.7nF
PGND
I
THM
SGND
PGND PGND
0.01µF
1nF
MODE
3070 F07
PGND PGND PGND PGND
NOTES: LTC3415 SWITCHER, 2MHz INTERNAL OSCILLATOR
LTC3415 AND LT3071 ON SAME PCB POWER PLANE
Figure 7. Regulator with VIOC Buck Control
3071f
ꢁꢃ
LT3071
typicAl ApplicAtions
V
BIAS
3.3V
50k
47µF
6.3V
s3
PWRGD
1Ω
SV
IN
2.2µF
NC
BIAS
0.1µF
PGOOD RUN PV
PV
IN
SV TRACK
IN
IN
0.2µH
EN
IN
PWRGD
SENSE
OUT
1.3V/7A
SGND
SW
SW
SW
SW
V
OUT
47µF
1V
PV
IN
PV
IN
LT3071
3.5A
2.2µF*
4.7µF*
10µF*
NC
NC
V
O0
V
O1
V
O2
R
TRACE
PLLLPF
3mΩ
*X5R OR X7R CAPACITORS
CONTROLLED
I
TH
MGN
BSEL
I
NC
MARGA
VIOC
MON
REF/BYP
GND
P.O.L. 1
LTC3415EUHF
NC
NC
NC
CLKOUT
PHMODE
CLKIN
POWER
PLANE
1V/7A
1nF
17.5k
0.01µF
1%
100µF
6.3V
s2
V
FB
15k
1%
MODE
P.O.L. 2
PGND
2.2µF
I
THM
SGND
PGND PGND
R
TRACE
3mΩ
BIAS
PGND PGND PGND PGND
CONTROLLED
EN
IN
PWRGD
SENSE
OUT
V
OUT
47µF
1V
NOTES: LTC3415 SWITCHER, 2MHz INTERNAL OSCILLATOR
LTC3415 AND LT3071 (s2) ON SAME PCB POWER PLANE
LT3071
3.5A
2.2µF*
4.7µF*
10µF*
NC
NC
V
O0
V
O1
V
O2
*X5R OR X7R CAPACITORS
V
MON
2V AT 7A
NC
MARGA
VIOC
I
MON
REF/BYP
GND
FULL SCALE
715Ω
1nF
0.01µF
3071 F08
Figure 8. 1V, 7A Point-of-Load Current Sharing Regulators
3071f
ꢁꢄ
LT3071
typicAl ApplicAtions
50k
V
IN
3.3V
PWRGD
2.2µF
BIAS
EN
IN
PWRGD
SENSE
V
1V
4A
OUT
47µF
LT3071
NC
NC
V
V
V
OUT
O0
O1
O2
2.2µF*
4.7µF*
10µF*
R
TRACE
2.5mΩ
CONTROLLED
*X5R OR X7R CAPACITORS
I
NC
MARGA
VIOC
MON
REF/BYP
P.O.L. 1
1nF
GND
0.01µF
POWER
PLANE
1V/7A
V
IN
3.3V
P.O.L. 2
2.2µF
V
IN
3.3V
R
TRACE
NC
NC
NC
NC
NC
2.5mΩ
BIAS
CONTROLLED
EN
IN
PWRGD
SENSE
SW1 CLKIN1 CLKOUT1 CLKIN2 CLKOUT2
V
= 1.3V/8A
BUCK1
V
V
OUT1
MGN1
FB1
IN1
SV
V
OUT
100µF
6.3V
X5R
10µF
47µF
LT3071
1V
4A
IN1
NC
NC
V
V
V
OUT
O0
20k
RUN1
2.2µF*
4.7µF*
10µF*
O1
O2
PLLLPF1
MODE1
PHMODE1
TRACK1
ITH1
ITHM1
BSEL1
PGOOD1
10k
2k
4.7nF
*X5R OR X7R CAPACITORS
V
MON
NC
NC
2V AT 8A
I
NC
MARGA
MON
FULL SCALE
V
IOC
REF/BYP
GND
LTM4616
620Ω
V
= 2.1V/8A
BUCK2
1nF
0.01µF
V
V
OUT2
MGN2
FB2
IN2
SV
100µF
6.3V
X5R
10µF
IN2
RUN2
V
IN
3.3V
PLLLPF2
MODE2
PHMODE2
TRACK2
ITH2
2.2µF
ITHM2
BSEL2
PGOOD2
NC
NC
BIAS
SW2 SGND1 GND1 SGND2 GND2
EN
IN
PWRGD
SENSE
OUT
V
OUT
NC
NC
NC
1.8V
47µF
V
O0
V
O1
V
O2
5A
2.2µF*
4.7µF*
10µF*
LT3071
NOTE:
THE TWO LTM4616 MODULE CHANNELS ARE
INDEPENDENTLY CONTROLLED BY THE VIOC
CONTROLS FROM THE LINEAR REGULATORS
*X5R OR X7R CAPACITORS
NC
MARGA
V
MON
20k
I
2V AT 5A
MON
REF/BYP
GND
FULL SCALE
V
IOC
1k
1nF
0.01µF
10k
2k
4.7nF
V
IN
3.3V
2.2µF
BIAS
EN
IN
V
PWRGD
SENSE
OUT
V
1.5V
3A
OUT
47µF
O0
2.2µF*
4.7µF*
10µF*
NC
NC
NC
V
V
O1
O2
LT3071
*X5R OR X7R CAPACITORS
MARGA
V
MON
2V AT 3A
I
MON
REF/BYP
GND
FULL SCALE
VIOC
1.67k
1nF
0.01µF
3071 F09
Figure 9. Triple Output Supply Providing 1V, 8A and 1.8V, 5A and 1.5V, 3A
3071f
ꢁꢅ
LT3071
pAckAge Description
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(ReferenceꢀLTCꢀDWGꢀ#ꢀ05-08-1712ꢀRevꢀB)
0.70 p0.05
4.50 p 0.05
3.10 p 0.05
2.50 REF
2.65 p 0.05
3.65 p 0.05
PACKAGE OUTLINE
0.25 p0.05
0.50 BSC
3.50 REF
4.10 p 0.05
5.50 p 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.20 OR 0.35
s 45o CHAMFER
2.50 REF
R = 0.115
TYP
R = 0.05
TYP
0.75 p 0.05
4.00 p 0.10
(2 SIDES)
27
28
0.40 p 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 p 0.10
(2 SIDES)
3.50 REF
3.65 p 0.10
2.65 p 0.10
(UFD28) QFN 0506 REV B
0.25 p 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3071f
InformationꢀfurnishedꢀbyꢀLinearꢀTechnologyꢀCorporationꢀisꢀbelievedꢀtoꢀbeꢀaccurateꢀandꢀreliable.ꢀ
However,ꢀnoꢀresponsibilityꢀisꢀassumedꢀforꢀitsꢀuse.ꢀLinearꢀTechnologyꢀCorporationꢀmakesꢀnoꢀrepresenta-
tionꢀthatꢀtheꢀinterconnectionꢀofꢀitsꢀcircuitsꢀasꢀdescribedꢀhereinꢀwillꢀnotꢀinfringeꢀonꢀexistingꢀpatentꢀrights.
ꢁꢆ
LT3071
typicAl ApplicAtion
1.5V to 1.2V Linear Regulator
50k
V
BIAS
PWRGD
2.2V TO 3.6V
2.2µF
BIAS
V
IN
IN
PWRGD
SENSE
1.5V
EN
330µF
V
1.2V
5A
OUT
LT3071
OUT
V
O0
V
O1
V
O2
2.2µF*
4.7µF*
10µF*
*X5R OR X7R CAPACITORS
V
MON
NC
I
2V AT 5A
MARGA
VIOC
MON
FULL SCALE
REF/BYP
GND
1k
1nF
0.01µF
3071 TA02
relAteD pArts
PART
DESCRIPTION
COMMENTS
LT1764/LT1764A
3A,ꢀFastꢀTransientꢀResponse,ꢀLowꢀNoiseꢀLDO
340mVꢀDropoutꢀVoltage,ꢀLowꢀNoise:ꢀ40µV ,ꢀV :ꢀ2.7Vꢀtoꢀ20V,ꢀꢀ
RMS IN
TO-220ꢀandꢀDDꢀPackagesꢀ“A”ꢀVersionꢀStableꢀAlsoꢀwithꢀCeramicꢀCaps
LT1963/LT1963A
LT1965
1.5AꢀLowꢀNoise,ꢀFastꢀTransientꢀResponseꢀLDO
340mVꢀDropoutꢀVoltage,ꢀLowꢀNoise:ꢀ40µV ,ꢀV :ꢀ2.5Vꢀtoꢀ20V,ꢀꢀ
RMS IN
“A”ꢀVersionꢀStableꢀwithꢀCeramicꢀCaps,ꢀTO-220,ꢀDD,ꢀSOT-223ꢀandꢀꢀ
SO-8ꢀPackages
1.1A,ꢀLowꢀNoise,ꢀLowꢀDropoutꢀLinearꢀRegulator
500mA,ꢀLowꢀVoltage,ꢀVLDO™ꢀLinearꢀRegulator
290mVꢀDropoutꢀVoltage,ꢀLowꢀNoise:ꢀ40µV ,ꢀV :ꢀ1.8Vꢀtoꢀ20V,ꢀV :ꢀ1.2Vꢀ
RMS IN OUTꢀ
toꢀ19.5V,ꢀStableꢀwithꢀCeramicꢀCaps,ꢀTO-220,ꢀDD-Pak,ꢀMSOPꢀandꢀꢀ
3mmꢀ×ꢀ3mmꢀDFNꢀPackages
LT3021
V :ꢀ0.9Vꢀtoꢀ10V,ꢀDropoutꢀVoltageꢀ=ꢀ160mVꢀ(Typ),ꢀAdjustableꢀOutputꢀ(V
ꢀ
IN
REF
=ꢀV
ꢀ=ꢀ200mV),ꢀFixedꢀOutputꢀVoltages:ꢀ1.2V,ꢀ1.5V,ꢀ1.8V,ꢀStableꢀwithꢀ
OUT(MIN)
LowꢀESR,ꢀCeramicꢀOutputꢀCapacitorsꢀ16-PinꢀDFNꢀꢀ
(5mmꢀ×ꢀ5mm)ꢀandꢀ8-LeadꢀSOꢀPackages
LT3080/LT3080-1
LT3085
1.1A,ꢀParallelable,ꢀLowꢀNoise,ꢀLowꢀDropoutꢀLinearꢀ 300mVꢀDropoutꢀVoltageꢀ(2-SupplyꢀOperation),ꢀLowꢀNoise:ꢀ40µV ,ꢀV :ꢀ
RMS IN
Regulator
1.2Vꢀtoꢀ36V,ꢀV :ꢀ0Vꢀtoꢀ35.7V,ꢀCurrent-BasedꢀReferenceꢀwithꢀ1ꢀResistorꢀ
OUTꢀ
V
ꢀSet;ꢀDirectlyꢀParallelableꢀ(NoꢀOpꢀAmpꢀRequired),ꢀStableꢀwithꢀCeramicꢀ
OUT
Caps,ꢀTO-220,ꢀSOT-223,ꢀMSOP-8ꢀandꢀ3mmꢀ×ꢀ3mmꢀDFN-8ꢀPackages;ꢀ
LT3080-1ꢀhasꢀIntegratedꢀInternalꢀBallastꢀResistor
500mA,ꢀParallelable,ꢀLowꢀNoise,ꢀLowꢀDropoutꢀꢀ
LinearꢀRegulator
275mVꢀDropoutꢀVoltageꢀ(2-SupplyꢀOperation),ꢀLowꢀNoise:ꢀ40µV ,ꢀV :ꢀ
RMS IN
1.2Vꢀtoꢀ36V,ꢀV :ꢀ0Vꢀtoꢀ35.7V,ꢀCurrent-BasedꢀReferenceꢀwithꢀ1ꢀResistorꢀ
OUTꢀ
V
ꢀSet;ꢀDirectlyꢀParallelableꢀ(NoꢀOpꢀAmpꢀRequired),ꢀStableꢀwithꢀCeramicꢀ
OUT
Caps,ꢀMSOP-8ꢀandꢀ2mmꢀ×ꢀ3mmꢀDFN-6ꢀPackages
LTC3025-1/LTC3025-2/ 500mAꢀMicropowerꢀVLDOꢀLinearꢀRegulatorꢀꢀ
LTC3025-3/LTC3025-4 inꢀ2mmꢀ×ꢀ2mmꢀDFNꢀ
V ꢀ=ꢀ0.9Vꢀtoꢀ5.5V,ꢀDropoutꢀVoltage:ꢀ75mV,ꢀLowꢀNoiseꢀ80µV ,ꢀꢀ
IN RMS
LowꢀI :ꢀ54µA,ꢀFixedꢀOutput:ꢀ1.2Vꢀ(LTC3025-2),ꢀ1.5Vꢀ(LTC3025-3),ꢀꢀ
Q
1.8Vꢀ(LTC3025-4);ꢀAdjustableꢀOutputꢀRange:ꢀ0.4Vꢀtoꢀ3.6Vꢀ(LTC3025-1)ꢀꢀ
2mmꢀ×ꢀ2mmꢀ6-LeadꢀDFNꢀPackage
LTC3026ꢀ
LT3070
1.5A,ꢀLowꢀInputꢀVoltageꢀVLDOꢀRegulatorꢀ
V :ꢀ1.14Vꢀtoꢀ3.5Vꢀ(BoostꢀEnabled),ꢀ1.14Vꢀtoꢀ5.5Vꢀ(withꢀExternalꢀ5V),ꢀꢀ
IN
V
ꢀ=ꢀ0.1V,ꢀI ꢀ=ꢀ950µA,ꢀStableꢀwithꢀ10µFꢀCeramicꢀCapacitors,ꢀꢀ
Q
DO
10-LeadꢀMSOPꢀandꢀDFN-10ꢀPackages
5A,ꢀLowꢀNoise,ꢀProgrammableꢀOutput,ꢀ85mVꢀ
DropoutꢀLinearꢀRegulator
V :ꢀ0.95Vꢀtoꢀ3V,ꢀV :ꢀ0.8Vꢀtoꢀ1.8Vꢀinꢀ50mVꢀIncrements,ꢀLowꢀNoise:ꢀ
IN OUTꢀ
25µV ,ꢀStableꢀwithꢀCeramicꢀCapacitors,ꢀ4mmꢀ×ꢀ5mmꢀ28-LeadꢀQFNꢀ
RMS
Package
3071f
LT 0410 • PRINTED IN USA
Linear Technology Corporation
1630ꢀ McCarthyꢀ Blvd.,ꢀ Milpitas,ꢀ CAꢀ 95035-7417
ꢀ
ꢁꢇ
●
●ꢀ
LINEAR TECHNOLOGY CORPORATION 2010
(408)ꢀ432-1900ꢀ ꢀFAX:ꢀ(408)ꢀ434-0507ꢀ www.linear.com
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