LT3431IFE#TR_技术文档

LT3431

High Voltage, 3A,

500kHz Step-Down

Switching Regulator

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FEATURES

DESCRIPTIO

■

Wide Input Range: 5.5V to 60V

TheLT^®3431isa500kHzmonolithicbuckswitchingregu-

latorthatacceptsinputvoltagesupto60V.Ahighefficiency

3A,0.1Ωswitchisincludedonthediealongwithallthenec-

essaryoscillator,controlandlogiccircuitry.Acurrentmode

architectureprovidesfasttransientresponseandgoodloop

stability.

■

3A Peak Switch Current

■

Small Thermally Enhanced 16-Pin TSSOP Package

■

Constant 500kHz Switching Frequency

■

Saturating Switch Design: 0.1Ω

■

Peak Switch Current Maintained Over

Full Duty Cycle Range

Special design techniques and a new high voltage process

achieve high efficiency over a wide input range. Efficiency

ismaintainedoverawideoutputcurrentrangebyusingthe

output to bias the circuitry and by utilizing a supply boost

capacitor to saturate the power switch. Patented circuitry

maintainspeakswitchcurrentoverthefulldutycyclerange.

Ashutdownpinreducessupplycurrentto30µAandthede-

vicecanbeexternallysynchronizedfrom580kHzto700kHz

with logic level inputs.

■

Effective Supply Current: 2.5mA

■

Shutdown Current: 30µA

■

1.2V Feedback Reference Voltage

■

Easily Synchronizable

■

Cycle-by-Cycle Current Limiting

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APPLICATIO S

■

Industrial and Automotive Power Supplies

■

The LT3431 is available in a thermally enhanced 16-pin

TSSOP package.

Portable Computers

■

Battery Chargers

Distributed Power Systems

■

, LTC and LT are registered trademarks of Linear Technology Corporation.

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TYPICAL APPLICATIO

5V, 2A Buck Converter

MMSD914TI

6

0.22µF

Efficiency vs Load Current

BOOST

10µH**

V

IN

OUT

3, 4

2, 5

12V

(TRANSIENTS

TO 60V)

V

SW

5V

IN

100

2.2µF^†

100V

CERAMIC

2A

V

= 12V

IN

30BQ060

LT3431

L = 15µH

V

= 5V

OUT

47µF

CERAMIC

90

80

70

60

50

15

14

10

12

SHDN

BIAS

FB

V

= 3.3V

OUT

15.4k

SYNC

GND

V

C

4.99k

1, 8, 9, 16

11

220pF

1.5k

15nF

0

0.5

1.0

1.5

2.0

2.5

LOAD CURRENT (A)

**

INCREASE INDUCTOR VALUE FOR LOAD CURRENTS ABOVE 2A

(SEE APPLICATIONS INFORMATION—MAXIMUM OUTPUT LOAD CURRENT)

^†UNITED CHEMI-CON THCS50EZA225ZT

3431 TA02

3431 TA01

sn3431 3431fs

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LT3431

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ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

(Note 1)

Input Voltage (V_IN) ................................................. 60V

BOOST Pin Above SW ............................................ 35V

BOOST Pin Voltage ................................................. 68V

SYNC Voltage ........................................................... 7V

SHDN Voltage ........................................................... 6V

BIAS Pin Voltage .................................................... 30V

FB Pin Voltage/Current .................................. 3.5V/2mA

Operating Junction Temperature Range

LT3431EFE (Notes 8, 10) ................. –40°C to 125°C

LT3431IFE (Notes 8, 10) ................. –40°C to 125°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

ORDER PART

TOP VIEW

NUMBER

GND

SW

1

2

3

4

5

6

7

8

16 GND

15 SHDN

14 SYNC

13 NC

LT3431EFE

LT3431IFE

V

IN

V

IN

SW

BOOST

NC

12 FB

11

10 BIAS

GND

V

C

GND

9

FE PART MARKING

FE PACKAGE

16-LEAD PLASTIC TSSOP

3431EFE

3431IFE

T_JMAX= 125°C, θ_JA= 45°C/ W, θ_JC(PAD) = 10°C/W

EXPOSED PAD MUST BE SOLDERED

TO GROUND PLANE

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at T_J= 25°C.

V_IN= 15V, V_C= 1.5V, SHDN = 1V, BOOST open circuit, SW open circuit, unless otherwise noted.

PARAMETER

CONDITIONS

5.5V ≤ V ≤ 60V

MIN

TYP

MAX

UNITS

Reference Voltage (V

)

1.204 1.219 1.234

V

REF

IN

V

+ 0.2 ≤ V ≤ V – 0.2

●

1.195

200

1.243

–1.5

OL

C

OH

FB Input Bias Current

–0.2

475

µA

Error Amp Voltage Gain

(Note 2)

dl (V ) = ±10µA

V/V

Error Amp g

1650

1000

2200

3300

4200

µMho

m

C

●

V to Switch g

3.4

275

0.8

A/V

µA

V

C

m

EA Source Current

EA Sink Current

FB = 1V or V

= 4.1V

●

125

100

450

500

SENSE

FB = 1.4V or V

Duty Cycle = 0

SHDN = 1V

= 5.7V

SENSE

V Switching Threshold

C

V High Clamp

C

2.1

V

Switch Current Limit

V Open, BOOST = V + 5V, FB = 1V or V

= 4.1V –40°C ≤ Tj ≤ 25°C

Tj = 125°C

3.0

2.5

5

4

6.5

5.5

A

C

IN

SENSE

(Note 9)

Switch On Resistance

I

= 2.5A, BOOST = V + 5V (Note 7)

0.1

0.14

0.18

Ω

SW

IN

●

Maximum Switch Duty Cycle

Switch Frequency

FB = 1V or V

= 4.1V

88

80

92

%

SENSE

V Set to Give DC = 50%

460

430

500

540

570

kHz

C

●

f

Line Regulation

5.5V ≤ V ≤ 60V

0.05

0.8

0.15

%/V

V

SW

IN

Shifting Threshold

Df = 10kHz

sn3431 3431fs

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LT3431

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at T_J= 25°C.

V_IN= 15V, V_C= 1.5V, SHDN = 1V, BOOST open circuit, SW open circuit, unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

4.6

1.8

MAX

5.5

3

UNITS

Minimum Input Voltage

Minimum Boost Voltage

Boost Current (Note 5)

(Note 3)

●

V

(Note 4) I ≤ 2.5A

SW

BOOST = V + 5V, I = 0.75A

●

25

75

50

120

mA

IN

SW

BOOST = V + 5V, I = 2.5A

IN

Input Supply Current (I

)

(Note 6) V

= 5V

1.5

3.1

30

2.2

4.2

mA

VIN

BIAS

Bias Supply Current (I

BIAS

Shutdown Supply Current

SHDN = 0V, V ≤ 60V, SW = 0V, V Open

100

200

µA

IN

C

●

Lockout Threshold

V Open,

C

2.30

2.42

2.53

V

Shutdown Thresholds

V Open, Shutting Down

C

●

0.15

0.25

0.37

0.42

0.58

0.6

V

C

V Open, Starting Up

Minimum SYNC Amplitude

SYNC Frequency Range

SYNC Input Resistance

●

1.5

2.2

V

kHz

kΩ

580

700

20

Note 1: Absolute Maximum Ratings are those values beyond which the life

Note 7: Switch on resistance is calculated by dividing V to SW voltage by

the forced current (3A). See Typical Performance Characteristics for the

graph of switch voltage at other currents.

Note 8: The LT3431EFE is guaranteed to meet performance specifications

from 0°C to 125°C junction temperature. Specifications over the –40°C to

125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LT3431IFE is guaranteed over the full –40°C to 125°C operating junction

temperature range.

IN

of a device may be impaired.

Note 2: Gain is measured with a V swing equal to 200mV above the low

C

clamp level to 200mV below the upper clamp level.

Note 3: Minimum input voltage is not measured directly, but is guaranteed

by other tests. It is defined as the voltage where internal bias lines are still

regulated so that the reference voltage and oscillator remain constant.

Actual minimum input voltage to maintain a regulated output will depend

upon output voltage and load current. See Applications Information.

Note 4: This is the minimum voltage across the boost capacitor needed to

guarantee full saturation of the internal power switch.

Note 9: See Typical Performance Graph of Peak Switch Current Limit vs

Junction Temperature.

Note 10. This IC includes overtemperature protection that is intended to

protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

Note 5: Boost current is the current flowing into the BOOST pin with the

pin held 5V above input voltage. It flows only during switch on time.

Note 6: Input supply current is the quiescent current drawn by the input

pin when the BIAS pin is held at 5V with switching disabled. Bias supply

current is the current drawn by the BIAS pin when the BIAS pin is held at

5V. Total input referred supply current is calculated by summing input

supply current (I ) with a fraction of bias supply current (I

):

BIAS

VIN

I

= I + (I

)(V /V )

BIAS OUT IN

TOTAL

VIN

With V = 15V, V

= 5V, I = 1.5mA, I

= 3.1mA, I

= 2.5mA.

IN

OUT

VIN

BIAS

TOTAL

sn3431 3431fs

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LT3431

TYPICAL PERFOR A CE CHARACTERISTICS

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Switch Peak Current Limit

FB Pin Voltage and Current

SHDN Pin Bias Current

6

5

4

1.234

1.229

1.224

1.219

2.0

1.5

250

200

150

100

12

T = 25°C

j

CURRENT REQUIRED TO FORCE SHUTDOWN

(FLOWS OUT OF PIN). AFTER SHUTDOWN,

CURRENT DROPS TO A FEW µA

TYPICAL

VOLTAGE

CURRENT

1.0

0.5

0

1.214

1.209

1.204

GUARANTEED MINIMUM

AT 2.38V STANDBY THRESHOLD

(CURRENT FLOWS OUT OF PIN)

3

2

6

0

20

40

60

80

100

50

100 125

50

100 125

–50 –25

0

25

75

–50 –25

0

25

75

DUTY CYCLE (%)

JUNCTION TEMPERATURE (°C)

3431 G01

3431 G02

3431 G03

Lockout and Shutdown

Thresholds

Shutdown Supply Current

300

250

2.4

2.0

1.6

1.2

0.8

0.4

0

40

35

30

25

20

15

10

5

V

= 0V

SHDN

LOCKOUT

V

IN

= 60V

200

150

V

IN

= 15V

100

50

0

START-UP

SHUTDOWN

0

0.1

0.2

0.3

0.4

0.5

–25

0

25

50

75

100

125

0

10

20

30

40

50

60

–50

SHUTDOWN VOLTAGE (V)

JUNCTION TEMPERATURE (°C)

INPUT VOLTAGE (V)

3431 G06

3431 G04

3431 G05

Frequency Foldback

Error Amplifier Transconductance

3000

2500

2000

1500

1000

500

200

150

100

50

625

500

375

250

125

0

2500

2000

1500

1000

500

SWITCHING

FREQUENCY

PHASE

GAIN

V

C

R

OUT

12pF

OUT

200k

–3

V

2 • 10

(

)

FB

ERROR AMPLIFIER EQUIVALENT CIRCUIT

= 50Ω

0

FB PIN

CURRENT

R

LOAD

–50

0

100

1k

10k

100k

1M

10M

–50

–25

0

25

50

75

100

125

0

0.2

0.4

0.6

(V)

0.8

1.0

1.2

FREQUENCY (Hz)

JUNCTION TEMPERATURE (°C)

V

FB

3431 G08

3431 G07

3431 G09

sn3431 3431fs

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LT3431

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TYPICAL PERFOR A CE CHARACTERISTICS

Minimum Input Voltage

with 5V Output

Switching Frequency

BOOST Pin Current

90

80

70

60

50

40

30

20

10

0

575

550

525

500

475

450

425

7.5

7.0

6.5

6.0

5.5

5.0

MINIMUM INPUT

VOLTAGE TO START

MINIMUM INPUT

VOLTAGE TO RUN

0

1

2

3

–50

–25

0

25

50

75

100

125

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

LOAD CURRENT (A)

SWITCH CURRENT (A)

JUNCTION TEMPERATURE (°C)

3431 G12

3431 G10

3431 G11

Switch Minimum ON Time

vs Temperature

V_CPin Shutdown Threshold

Switch Voltage Drop

2.1

1.9

600

500

400

300

450

400

350

300

250

200

150

100

50

T = 125°C

J

1.7

1.5

1.3

1.1

0.9

T = 25°C

J

200

100

0

T = –40°C

J

0.7

0

50

100 125

50

100 125

–50 –25

0

25

75

0

1

2

3

–50 –25

0

25

75

JUNCTION TEMPERATURE (°C)

SWITCH CURRENT (A)

JUNCTION TEMPERATURE (°C)

3431 G13

3431 G14

3431 G15

Switch Peak Current Limit

6.00

5.50

5.00

4.50

4.00

3.50

3.00

2.50

–25

0

25

50

75

100

125

–50

JUNCTION TEMPERATURE (°C)

3431 G16

sn3431 3431fs

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LT3431

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PI FU CTIO S

GND (Pins 1, 8, 9, 16): The GND pin connections act as

the reference for the regulated output, so load regulation

will suffer if the “ground” end of the load is not at the same

voltage as the GND pins of the IC. This condition will occur

when load current or other currents flow through metal

pathsbetweentheGNDpinsandtheloadground.Keepthe

paths between the GND pins and the load ground short

anduseagroundplanewhenpossible.TheFEpackagehas

an exposed pad that is fused to the GND pins. The pad

should be soldered to the copper ground plane under the

device to reduce thermal resistance. (See Applications

Information—Layout Considerations.)

supply. This architecture increases efficiency especially

when the input voltage is much higher than the output.

Minimumoutputvoltagesettingforthismodeofoperation

is 3V.

V_C(Pin 11) The V_Cpin is the output of the error amplifier

and the input of the peak switch current comparator. It is

normally used for frequency compensation, but can also

serve as a current clamp or control loop override. V_Csits

at about 0.9V for light loads and 2.1V at maximum load. It

can be driven to ground to shut off the regulator, but if

driven high, current must be limited to 4mA.

FB (Pin 12): The feedback pin is used to set the output

voltage using an external voltage divider that generates

1.22V at the pin for the desired output voltage. Three

additionalfunctionsareperformedbytheFBpin.Whenthe

pin voltage drops below 0.6V, switch current limit is

reducedandtheexternalSYNCfunctionisdisabled.Below

0.8V, switching frequency is also reduced. See Feedback

Pin Functions in Applications Information for details.

SW(Pins2, 5):Theswitchpinistheemitteroftheon-chip

power NPN switch. This pin is driven up to the input pin

voltage during switch on time. Inductor current drives the

switch pin voltage negative during switch off time. Nega-

tive voltage is clamped with the external catch diode.

Maximum negative switch voltage allowed is –0.8V.

V_IN(Pins 3, 4): This is the collector of the on-chip power

NPNswitch.V_INpowerstheinternalcontrolcircuitrywhen

a voltage on the BIAS pin is not present. High dI/dt edges

occur on this pin during switch turn on and off. Keep the

path short from the V_INpin through the input bypass

capacitor, through the catch diode back to SW. All trace

inductanceinthispathcreatesvoltagespikesatswitchoff,

adding to the V_CEvoltage across the internal NPN.

SYNC (Pin 14): The SYNC pin is used to synchronize the

internal oscillator to an external signal. It is directly logic

compatible and can be driven with any signal between

10% and 90% duty cycle. The synchronizing range is

equal to initial operating frequency up to 700kHz. See

Synchronizing in Applications Information for details.

SHDN (Pin 15): The SHDN pin is used to turn off the

regulator and to reduce input drain current to a few

microamperes. This pin has two thresholds: one at 2.38V

to disable switching and a second at 0.4V to force com-

plete micropower shutdown. The 2.38V threshold func-

tions as an accurate undervoltage lockout (UVLO); some-

times used to prevent the regulator from delivering power

until the input voltage has reached a predetermined level.

BOOST (Pin 6): The BOOST pin is used to provide a drive

voltage, higher than the input voltage, to the internal bipo-

lar NPN power switch. Without this added voltage, the

typical switch voltage loss would be about 1.5V. The ad-

ditional BOOST voltage allows the switch to saturate and

voltage loss approximates that of a 0.1Ω FET structure.

NC (Pins 7, 13): No Connection.

B

IAS (Pin 10): The BIAS pin is used to improve efficiency

If the SHDN pin functions are not required, the pin can

either be left open (to allow an internal bias current to lift

the pin to a default high state) or be forced high to a level

not to exceed 6V.

when operating at higher input voltages and light load

current. Connecting this pin to the regulated output volt-

age forces most of the internal circuitry to draw its oper-

ating current from the output voltage rather than the input

sn3431 3431fs

6

LT3431

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BLOCK DIAGRA

The LT3431 is a constant frequency, current mode buck

converter. This means that there is an internal clock and

twofeedbackloopsthatcontrolthedutycycleofthepower

switch. In addition to the normal error amplifier, there is a

current sense amplifier that monitors switch current on a

cycle-by-cycle basis. A switch cycle starts with an oscilla-

tor pulse which sets the R_Sflip-flop to turn the switch on.

When switch current reaches a level set by the inverting

input of the comparator, the flip-flop is reset and the

switch turns off. Output voltage control is obtained by

using the output of the error amplifier to set the switch

current trip point. This technique means that the error

amplifier commands current to be delivered to the output

rather than voltage. A voltage fed system will have low

phase shift up to the resonant frequency of the inductor

and output capacitor, then an abrupt 180° shift will occur.

The current fed system will have 90° phase shift at a much

lower frequency, but will not have the additional 90° shift

until well beyond the LC resonant frequency. This makes

itmucheasiertofrequencycompensatethefeedbackloop

and also gives much quicker transient response.

Most of the circuitry of the LT3431 operates from an

internal 2.9V bias line. The bias regulator normally draws

power from the regulator input pin, but if the BIAS pin is

connected to an external voltage equal to or higher than

3V, bias power will be drawn from the external source

(typically the regulated output voltage). This will improve

efficiency if the BIAS pin voltage is lower than regulator

input voltage.

High switch efficiency is attained by using the BOOST pin

to provide a voltage to the switch driver which is higher

than the input voltage, allowing switch to be saturated.

This boosted voltage is generated with an external

capacitor and diode. Two comparators are connected to

the shutdown pin. One has a 2.38V threshold for under-

voltage lockout and the second has a 0.4V threshold for

complete shutdown.

V

IN

3, 4

10

R

SENSE

LIMIT

–

+

2.9V BIAS

REGULATOR

INTERNAL

CC

BIAS

V

CURRENT

COMPARATOR

SLOPE COMP

Σ

SYNC 14

BOOST

6

ANTISLOPE COMP

SHUTDOWN

COMPARATOR

500kHz

OSCILLATOR

–

+

S

Q1

POWER

SWITCH

R

DRIVER

CIRCUITRY

S

FLIP-FLOP

R

0.4V

5.5µA

SW

SHDN 15

+

–

2, 5

FREQUENCY

FOLDBACK

LOCKOUT

COMPARATOR

×1

Q2

FOLDBACK

CURRENT

LIMIT

V

C(MAX)

CLAMP

Q3

ERROR

AMPLIFIER

= 2000µMho

CLAMP

–

+

12

FB

g

m

11

1.22V

2.38V

V

C

GND

1, 8, 9, 16

3431 F01

Figure 1. LT3431 Block Diagram

sn3431 3431fs

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LT3431

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APPLICATIO S I FOR ATIO

FEEDBACK PIN FUNCTIONS

short-circuitcurrentlimitoftheswitch(typically4Aforthe

LT3431, foldingbacktolessthan2A). Minimumswitchon

time limitations would prevent the switcher from attaining

a sufficiently low duty cycle if switching frequency were

maintained at 500kHz, so frequency is reduced by about

5:1 when the feedback pin voltage drops below 0.8V (see

FrequencyFoldbackgraph). Thisdoesnotaffectoperation

with normal load conditions; one simply sees a gear shift

in switching frequency during start-up as the output

voltage rises.

The feedback (FB) pin on the LT3431 is used to set output

voltage and provide several overload protection features.

The first part of this section deals with selecting resistors

to set output voltage and the second part talks about

foldback frequency and current limiting created by the FB

pin. Please read both parts before committing to a final

design.

The suggested value for the output divider resistor (see

Figure 2) from FB to ground (R2) is 5k or less, and a

formula for R1 is shown below. The output voltage error

caused by ignoring the input bias current on the FB pin is

less than 0.25% with R2 = 5k. A table of standard 1%

values is shown in Table 1 for common output voltages.

Please read the following if divider resistors are increased

above the suggested values.

In addition to lower switching frequency, the LT3431 also

operates at lower switch current limit when the feedback

pin voltage drops below 0.6V. Q2 in Figure 2 performs this

function by clamping the V_Cpin to a voltage less than its

normal 2.1V upper clamp level. This foldback current limit

greatly reduces power dissipation in the IC, diode and in-

ductor during short-circuit conditions. External synchro-

nization is also disabled to prevent interference with fold-

back operation. Again, it is nearly transparent to the user

under normal load conditions. The only loads that may be

affected are current source loads which maintain full load

current with output voltage less than 50% of final value. In

theseraresituationsthefeedbackpincanbeclampedabove

0.6Vwithanexternaldiodetodefeatfoldbackcurrentlimit.

Caution: clamping the feedback pin means that frequency

shifting will also be defeated, so a combination of high in-

putvoltageanddeadshortedoutputmaycausetheLT3431

to lose control of current limit.

R2 V_OUT−1.22

(

)

R1=

1.22

Table 1

OUTPUT

VOLTAGE

(V)

R1

% ERROR AT OUTPUT

R2

(NEAREST 1%) DUE TO DISCREET 1%

(kΩ

)

(k

Ω

)

RESISTOR STEPS

+0.32

3

3.3

5

4.99

4.75

4.47

4.32

4.12

7.32

8.45

15.4

18.7

24.9

30.9

36.5

46.4

–0.43

–0.30

6

+0.40

8

+0.20

The internal circuitry which forces reduced switching

frequency also causes current to flow out of the feedback

pin when output voltage is low. The equivalent circuitry is

shown in Figure 2. Q1 is completely off during normal

operation. If the FB pin falls below 0.8V, Q1 begins to

conduct current and reduces frequency at the rate of

approximately 3.5kHz/µA. To ensure adequate frequency

foldback (under worst-case short-circuit conditions), the

external divider Thevinin resistance must be low enough

to pull 115µA out of the FB pin with 0.44V on the pin (R_DIV

≤ 3.8k). The net result is that reductions in frequency and

current limit are affected by output voltage divider imped-

ance. Although divider impedance is not critical, caution

should be used if resistors are increased beyond the

suggested values and short-circuit conditions can possi-

10

12

15

–0.54

+0.24

–0.27

More Than Just Voltage Feedback

The feedback pin is used for more than just output voltage

sensing. It also reduces switching frequency and current

limit when output voltage is very low (see the Frequency

Foldback graph in Typical Performance Characteristics).

ThisisdonetocontrolpowerdissipationinboththeICand

in the external diode and inductor during short-circuit

conditions. A shorted output requires the switching regu-

lator to operate at very low duty cycles, and the average

current through the diode and inductor is equal to the

bly occur with high input voltage. High frequency pickup

sn3431 3431fs

8

LT3431

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APPLICATIO S I FOR ATIO

U

V

SW

LT3431

L1

TO FREQUENCY

SHIFTING

OUTPUT

5V

1.4V

Q1

ERROR

AMPLIFIER

R1

1.2V

+

–

R4

2k

R3

1k

FB

+

C1

BUFFER

Q2

R2

TO SYNC CIRCUIT

V

GND

C

3431 F02

Figure 2. Frequency and Current Limit Foldback

will increase and the protection accorded by frequency

and current foldback will decrease.

V

_OUTUSING

47µF CERAMIC

OUTPUT

CAPACITOR

CHOOSING THE INDUCTOR

10mV/DIV

V_OUTUSING

100µF, 0.08Ω

TANTALUM

OUTPUT

For most applications, the output inductor will fall into the

range of 5µH to 33µH. Lower values are chosen to reduce

physical size of the inductor. Higher values allow more

output current because they reduce peak current seen by

the LT3431 switch, which has a 3A limit. Higher values

also reduce output ripple voltage.

CAPACITOR

1µs/DIV

V_IN= 12V

V_OUT= 5V

L = 10µH

3431 F03

When choosing an inductor you will need to consider

output ripple voltage, maximum load current, peak induc-

tor current and fault current in the inductor. In addition,

other factors such as core and copper losses, allowable

component height, EMI, saturation and cost should also

be considered. The following procedure is suggested as a

way of handling these somewhat complicated and con-

flicting requirements.

Figure 3. LT3431 Output Ripple Voltage Waveforms.

Ceramic vs Tantalum Output Capacitors

Output ripple voltage is determined by ripple current

(I_LP-P) through the inductor and the high frequency

impedance of the output capacitor. At high frequencies,

the impedance of the tantalum capacitor is dominated by

its effective series resistance (ESR).

Output Ripple Voltage

Tantalum Output Capacitor

Figure 3 shows a comparison of output ripple voltage for

the LT3431 using either a tantalum or ceramic output

capacitor. It can be seen from Figure 3 that output ripple

voltagecanbesignificantlyreducedbyusingtheceramic

outputcapacitor;thesignificantdecreaseinoutputripple

voltage is due to the very low ESR of ceramic capacitors.

The typical method for reducing output ripple voltage

when using a tantalum output capacitor is to increase the

inductor value (to reduce the ripple current in the induc-

tor). The following equations will help in choosing the

required inductor value to achieve a desirable output

ripple voltage level. If output ripple voltage is of less

sn3431 3431fs

9

LT3431

W U U

U

APPLICATIO S I FOR ATIO

importance, the subsequent suggestions in Peak Induc-

tor and Fault Current and EMI will additionally help in the

selection of the inductor value.

physically larger inductor with the possibility of increased

component height and cost.

Ceramic Output Capacitor

Peak-to-peak output ripple voltage is the sum of a triwave

(created by peak-to-peak ripple current (I_LP-P) times ESR)

and a square wave (created by parasitic inductance (ESL)

and ripple current slew rate). Capacitive reactance is

assumed to be small compared to ESR or ESL.

An alternative way to further reduce output ripple voltage

is to reduce the ESR of the output capacitor by using a

ceramic capacitor. Although this reduction of ESR re-

moves a useful zero in the overall loop response, this zero

can be replaced by inserting a resistor (R_C) in series with

the V_Cpin and the compensation capacitor C_C. (See

Ceramic Capacitors in Applications Information.)

dI

dt

V

_RIPPLE= I_LP-PESR + ESL Σ

(

)(

) (

)

Peak Inductor Current and Fault Current

where:

To ensure that the inductor will not saturate, the peak

inductor current should be calculated knowing the maxi-

mum load current. An appropriate inductor should then

bechosen.Inaddition,adecisionshouldbemadewhether

or not the inductor must withstand continuous fault

conditions.

ESR = equivalent series resistance of the output

capacitor

ESL = equivalent series inductance of the output

capacitor

dI/dt = slew rate of inductor ripple current = V_IN/L

If maximum load current is 1A, for instance, a 1A inductor

maynotsurviveacontinuous4Aoverloadcondition. Dead

shortswillactuallybemoregentleontheinductorbecause

the LT3431 has frequency and current limit foldback.

Peak-to-peak ripple current (I_LP-P) through the inductor

and into the output capacitor is typically chosen to be

between 20% and 40% of the maximum load current. It is

approximated by:

Peak inductor and switch current can be significantly

higher than output current, especially with smaller induc-

tors and lighter loads, so don’t omit this step. Powdered

iron cores are forgiving because they saturate softly,

whereas ferrite cores saturate abruptly. Other core mate-

rials fall somewhere in between. The following formula

assumes continuous mode of operation, but errs only

slightly on the high side for discontinuous mode, so it can

be used for all conditions.

V_OUTV – V_OUT

(

)( ^IN

)

I_LP-P

=

V

f L

(

^IN)( )( )

Example: with V_IN= 12V, V_OUT= 5V, L = 10µH, ESR =

0.080Ω and ESL = 10nH, output ripple voltage can be

approximated as follows:

5 12 − 5

( )(

)

I_P-P

=

= 0.58A

12 10•10⁻⁶500•10³

V_OUTV – V_OUT

(

)( ^IN

)

(I_LP-P

2

)

( )

(

)(

)

I_PEAK= I_OUT

+

= I_OUT+

2 V f L

( )(

^IN

)( )( )

dI

dt

12

Σ

=

= 10⁶•1.2

10•10⁻⁶

EMI

V

_RIPPLE= 0.58A 0.08 + 10•10⁻⁹10⁶1.2

(

)(

)

(

)

(

)(

Decide if the design can tolerate an “open” core geometry

like a rod or barrel, which have high magnetic field

radiation, or whether it needs a closed core like a toroid to

prevent EMI problems. This is a tough decision because

the rods or barrels are temptingly cheap and small and

sn3431 3431fs

= 0.046 + 0.012 = 58mV_P-P

To reduce output ripple voltage further requires an in-

crease in the inductor value with the trade-off being a

10

LT3431

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APPLICATIO S I FOR ATIO

U

fall off at high duty cycles. Most current mode converters

suffer a drop off of peak switch current for duty cycles

above 50%. This is due to the effects of slope compensa-

tion required to prevent subharmonic oscillations in cur-

rent mode converters. (For detailed analysis, see Applica-

tion Note 19.)

there are no helpful guidelines to calculate when the

magnetic field radiation will be a problem.

Table 2

VENDOR/

PART NUMBER

VALUE

H)

I

DCR

(Ohms)

HEIGHT

(mm)MAX

DC

(

µ

(Amps)

Sumida

The LT3431 is able to maintain peak switch current limit

over the full duty cycle range by using patented circuitry to

cancel the effects of slope compensation on peak switch

current without affecting the frequency compensation it

provides.

CDRH8D28-4R7

CDRH8D28-7R3

CDRH8D43-100

CDRH8D43-150

CEI122-100

4.7

7.3

10

15

10

15

22

33

3.4

2.8

4

0.019

0.030

0.029

0.042

0.029

0.071

0.037

0.054

0.066

3

4.5

3

2.9

3.4

3.6

2.9

Maximum load current would be equal to maximum

switch current for an infinitely large inductor, but with

finite inductor size, maximum load current is reduced by

one-halfpeak-to-peakinductorcurrent(I_LP-P).Thefollow-

ing formula assumes continuous mode operation, imply-

ing that the term on the right is less than one-half of I_P.

CEI122(H)-150

CDRH104R-150

CDRH104R-220

CDRH124-330

Coiltronics

3

4

4.5

UP2B-6R8

6.8

10

22

33

3.6

3.3

3.7

3.0

0.020

0.027

0.049

0.069

6

UP2B-100

6

I_OUT(MAX)

=

UP3B-220

6.8

Continuous Mode

UP3B-330

V_OUT+ V_FV − V_OUT– V_F

Coilcraft

(

)( ^IN

)

I_LP-P

2

I_P–

=I_P−

DO1813P-472

DS3316P-472

DS3316P-682

DO3316P-103

DO3316P-153

4.7

6.8

10

2.6

3.2

2.8

3.8

3.0

0.054

0.075

0.038

0.046

5

2 L f V

( )( )(

^IN

)

5.08

5.21

For V_OUT= 5V, V_IN= 12V, V_F(D1)= 0.52V, f = 500kHz

and L = 10µH:

15

5 + 0.52 12 − 5 – 0.52

(

)(

)

I_{OUT MAX}₎= 3 −

(

2 15•10⁻⁶500•10³12

Additional Considerations

( )

(

)(

)

After making an initial choice, consider additional factors

such as core losses and second sourcing, etc. Use the

experts in Linear Technology’s Applications department if

you feel uncertain about the final choice. They have

experience with a wide range of inductor types and can tell

you about the latest developments in low profile, surface

mounting, etc.

=3 − 0.3 = 2.7A

Note that there is less load current available at the higher

inputvoltagebecauseinductorripplecurrentincreases.At

V_IN= 24V, duty cycle is 23% and for the same set of

conditions:

5 + 0.52 24 − 5 – 0.52

(

)(

)

I_OUT(MAX)= 3 −

Maximum Output Load Current

2 15•10⁻⁶500•10³24

( )

(

)(

)

Maximum load current for a buck converter is limited by

themaximumswitchcurrentrating(I_P).Thecurrentrating

for the LT3431 is 3A. Unlike most current mode convert-

ers, the LT3431 maximum switch current limit does not

= 3 − 0.43 = 2.57A

sn3431 3431fs

11

LT3431

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APPLICATIO S I FOR ATIO

Example: For V_IN= 12V, V_OUT= 5V, V_F= 0.52V, f = 500kHz

and L = 2.2µH.

To calculate actual peak switch current with a given set of

conditions, use:

I_OUT(MAX)

3²•(500•10³)(4.7•10^–6)(12)

=

I_LP-P

2

Discontinuous

I_{SW PEAK}= I_OUT

+

2(5 + 0.52)(12 – 5 – 0.52)

(

)

Mode

(V_OUT+ V_F) V − V_OUT– V_F

I_OUT(MAX)

= 1.66A

(

IN

)

= I_OUT

Discontinuous Mode

2 L f V

( )( )( ^IN

)

What has been shown here is that if high inductor ripple

current and discontinuous mode operation can be toler-

ated, small inductor values can be used. If a higher output

load current is required, the inductor value must be

increased. If I_OUT(MAX)no longer meets the discontinuous

mode criteria, use the I_OUT(MAX)equation for continuous

mode; the LT3431 is designed to operate well in both

modes of operation, allowing a large range of inductor

values to be used.

Reduced Inductor Value and Discontinuous Mode

If the smallest inductor value is of most importance to a

converter design, in order to reduce inductor size/cost,

discontinuous mode may yield the smallest inductor solu-

tion. The maximum output load current in discontinuous

mode, however, must be calculated and is defined later in

this section.

Discontinuous mode is entered when the output load

current is less than one-half of the inductor ripple

current (I_LP-P). In this mode, inductor current falls to

zero before the next switch turn on (see Figure 8). Buck

converters will be in discontinuous mode for output

load current given by:

Short-Circuit Considerations

For a ground short-circuit fault on the regulated output,

the maximum input voltage for the LT3431 is typically

limited to 21V. If a greater input voltage is required,

increasing the resistance in series with the inductor may

suffice (see short-circuit calculations at the end of this

section). Alternatively, the LT3430 can be used since it is

identical to the LT3431 but runs at a lower frequency of

200kHz,allowinghighersustainedinputvoltagecapability

during output short-circuit.

(V_OUT+ V )(V – V_OUT– V )

F

IN

F

I_OUT

<

(2)(V )(f)(L)

Discontinuous Mode

IN

The inductor value in a buck converter is usually chosen

large enough to keep inductor ripple current (I_LP-P) low;

this is done to minimize output ripple voltage and maxi-

mize output load current. In the case of large inductor

values, as seen in the equation above, discontinuous

mode will be associated with “light loads.”

The LT3431 is a current mode controller. It uses the V_C

node voltage as an input to a current comparator which

turns off the output switch on a cycle-by-cycle basis as

peak current is reached. The internal clamp on the V_C

node, nominally 2V, then acts as an output switch peak

current limit. This action becomes the switch current limit

specification. The maximum available output power is

then determined by the switch current limit.

When choosing small inductor values, however, discon-

tinuous mode will occur at much higher output load

currents. The limit to the smallest inductor value that can

be chosen is set by the LT3431 peak switch current (I_P)

and the maximum output load current required, given by:

2

A potential controllability problem could occur under

short-circuit conditions. If the power supply output is

short circuited, the feedback amplifier responds to the low

output voltage by raising the control voltage, V_C, to its

peak current limit value. Ideally, the output switch would

be turned on, and then turned off as its current exceeded

thevalueindicatedbyV_C.However,thereisfiniteresponse

sn3431 3431fs

I_OUT(MAX)

Discontinuous Mode

I_P

=

(2)(I_LP-P

)

2

I_Pf •L•V

(

IN

)

=

2(V_OUT+ V_F)(V – V_OUT– V_F)

IN

12

LT3431

W U U

APPLICATIO S I FOR ATIO

U

time involved in both the current comparator and turnoff

maximum allowable input voltage during an output short

to ground is typically:

of the output switch. These result in a minimum on time

t

_ON(MIN). When combined with the large ratio of V_INto

V_IN= (0.52V + 0.068V)/(100kHz • 275ns)

V_IN(MAX)= 21V

(V_F+ I • R), the diode forward voltage plus inductor I • R

voltage drop, the potential exists for a loss of control.

Expressed mathematically the requirement to maintain

control is:

Increasing the DCR of the inductor will increase the

maximum V_INallowed during an output short to ground

but will also drop overall efficiency during normal opera-

tion.

V_F+I•R

f • t_ON

≤

V

IN

It is recommended that for [V_IN/(V_OUT+ V_F)] ratios > 4, a

soft-start circuit should be used to control the output

capacitor charge rate during start-up or during recovery

from an output short circuit, thereby adding additional

control over peak inductor current. See Buck Converter

with Adjustable Soft-Start later in this data sheet.

where:

f = switching frequency

_ON= switch minimum on time

V_F= diode forward voltage

V_IN= Input voltage

I • R = inductor I • R voltage drop

t

If this condition is not observed, the current will not be

limited at I_PK, but will cycle-by-cycle ratchet up to some

higher value. Using the nominal LT3431 clock frequency

of 500KHz, a V_INof 12V and a (V_F+ I • R) of say 0.6V, the

maximum t_ONto maintain control would be approximately

100ns, an unacceptably short time.

OUTPUT CAPACITOR

The LT3431 will operate with either ceramic or tantalum

output capacitors. The output capacitor is normally cho-

sen by its effective series resistance (ESR), because this

is what determines output ripple voltage. The ESR range

for typical LT3431 applications using a tantalum output

capacitoris0.05Ωto0.2Ω. Atypicaloutputcapacitorisan

AVX type TPS, 100µF at 10V, with a guaranteed ESR less

than 0.1Ω. This is a “D” size surface mount solid tantalum

capacitor. TPS capacitors are specially constructed and

tested for low ESR, so they give the lowest ESR for a given

volume. The value in microfarads is not particularly criti-

cal, and values from 22µF to greater than 500µF work well,

but you cannot cheat mother nature on ESR. If you find a

tiny 22µF solid tantalum capacitor, it will have high ESR,

and output ripple voltage will be terrible. Table 3 shows

some typical solid tantalum surface mount capacitors.

The solution to this dilemma is to slow down the oscilla-

tor when the FB pin voltage is abnormally low thereby

indicatingsomesortofshort-circuitcondition. Oscillator

frequencyisunaffecteduntilFBvoltagedropstoabout2/3

of its normal value. Below this point the oscillator fre-

quency decreases roughly linearly down to a limit of about

100kHz. This lower oscillator frequency during short-

circuit conditions can then maintain control with the

effective minimum on time. Even with frequency foldback,

however, the LT3431 will not survive a permanent output

shortattheabsolutemaximumvoltageratingofV_IN=60V;

this is defined solely by internal semiconductor junction

breakdown effects.

Table 3. Surface Mount Solid Tantalum Capacitor ESR

and Ripple Current

ESR (Max.,

Ω

)

Ripple Current (A)

For the maximum input voltage allowed during an output

short to ground, the previous equation defining minimum

on-time can be used. Assuming V_F(D1 catch diode) =

0.52V at 2.5A (short-circuit current is folded back to

typicalswitchcurrentlimit•0.5), I(inductor)•DCR=2.5A

• 0.027 = 0.068V (L = UP2B-100), typical f = 100kHz

(folded back) and typical minimum on-time = 275ns, the

E Case Size

AVX TPS, Sprague 593D

D Case Size

0.1 to 0.3

0.2 (typ)

0.7 to 1.1

AVX TPS, Sprague 593D

C Case Size

0.7 to 1.1

AVX TPS

0.5 (typ)

sn3431 3431fs

13

LT3431

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APPLICATIO S I FOR ATIO

Many engineers have heard that solid tantalum capacitors

are prone to failure if they undergo high surge currents.

This is historically true, and type TPS capacitors are

speciallytestedforsurgecapability,butsurgeruggedness

is not a critical issue with the output capacitor. Solid

tantalum capacitors fail during very high turn-on surges,

which do not occur at the output of regulators. High

discharge surges, such as when the regulator output is

dead shorted, do not harm the capacitors.

sheet for component references) C3 = 2.2µF, R_C= 1.5k,

C_C= 15nF, C_F= 220pF and C1 = 47µF. See Application

Note 19 for further detail on techniques for proper loop

compensation.

INPUT CAPACITOR

Step-down regulators draw current from the input supply

in pulses. The rise and fall times of these pulses are very

fast. The input capacitor is required to reduce the voltage

ripple this causes at the input of LT3431 and force the

switching current into a tight local loop, thereby minimiz-

ing EMI. The RMS ripple current can be calculated from:

Unlike the input capacitor, RMS ripple current in the

output capacitor is normally low enough that ripple cur-

rent rating is not an issue. The current waveform is

triangular with a typical value of 250mA_RMS. The formula

to calculate this is:

2

IN

I_{RIPPLE RMS}= I_OUTV_OUTV – V_OUT/V

(

IN

)

(

)

Output capacitor ripple current (RMS):

Ceramiccapacitorsareidealforinputbypassing.At500kHz

switching frequency, the energy storage requirement of

the input capacitor suggests that values in the range of

2.2µF to 10µF are suitable for most applications. If opera-

tionisrequiredclosetotheminimuminputrequiredbythe

output of the LT3431, a larger value may be required. This

is to prevent excessive ripple causing dips below the

minimum operating voltage resulting in erratic operation.

0.29 V_OUTV − V_OUT

(

)( ^IN

)

I_{RIPPLE RMS}

=

(

)

L f V

( )( )( ^IN

)

Ceramic Capacitors

Ceramic capacitors are generally chosen for their good

high frequency operation, small size and very low ESR

(effective series resistance). Their low ESR reduces out-

put ripple voltage but also removes a useful zero in the

loop frequency response, common to tantalum capaci-

tors. To compensate for this, a resistor R_Ccan be placed

in series with the V_Ccompensation capacitor C_C. Care

must be taken however, since this resistor sets the high

frequency gain of the error amplifier, including the gain at

the switching frequency. If the gain of the error amplifier

is high enough at the switching frequency, output ripple

voltage (although smaller for a ceramic output capacitor)

may still affect the proper operation of the regulator. A

filter capacitor C_Fin parallel with the R_C/C_Cnetwork is

suggested to control possible ripple at the V_Cpin. An “All

Ceramic” solution is possible for the LT3431 by choosing

the correct compensation components for the given

application.

Depending on how the LT3431 circuit is powered up you

may need to check for input voltage transients.

The input voltage transients may be caused by input

voltage steps or by connecting the LT3431 converter to an

already powered up source such as a wall adapter. The

sudden application of input voltage will cause a large

surge of current in the input leads that will store energy in

the parasitic inductance of the leads. This energy will

causetheinputvoltagetoswingabovetheDClevelofinput

power source and it may exceed the maximum voltage

rating of input capacitor and LT3431.

The easiest way to suppress input voltage transients is to

addasmallaluminumelectrolyticcapacitorinparallelwith

the low ESR input capacitor. The selected capacitor needs

to have the right amount of ESR in order to critically

dampen the resonant circuit formed by the input lead

inductance and the input capacitor. The typical values of

ESRwillfallintherangeof0.5Ωto2Ωandcapacitancewill

fall in the range of 5µF to 50µF.

Example:ForV_IN=8Vto20V, V_OUT=5Vat2A, theLT3431

can be stabilized, provide good transient response and

maintain very low output ripple voltage using the follow-

ing component values: (refer to the first page of this data

sn3431 3431fs

14

LT3431

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APPLICATIO S I FOR ATIO

U

If tantalum capacitors are used, values in the 22µF to

470µF range are generally needed to minimize ESR and

meet ripple current and surge ratings. Care should be

taken to ensure the ripple and surge ratings are not

exceeded. The AVX TPS and Kemet T495 series are surge

rated. AVX recommends derating capacitor operating

voltage by 2:1 for high surge applications.

BOOST PIN

Formostapplications, theboostcomponentsarea0.22µF

capacitor and a MMSD914TI diode. The anode is typically

connected to the regulated output voltage to generate a

voltage approximately V_OUTabove V_INto drive the output

stage. However, the output stage discharges the boost

capacitor during the on time of the switch. The output

driver requires at least 3V of headroom throughout this

period to keep the switch fully saturated. If the output

voltage is less than 3.3V, it is recommended that an

alternate boost supply is used. The boost diode can be

connected to the input, although, care must be taken to

prevent the 2× V_INboost voltage from exceeding the

BOOST pin absolute maximum rating. The additional

voltage across the switch driver also increases power

loss, reducing efficiency. If available, an independent

supply can be used with a local bypass capacitor.

CATCH DIODE

HighestefficiencyoperationrequirestheuseofaSchottky

type diode. DC switching losses are minimized due to its

low forward voltage drop, and AC behavior is benign due

to its lack of a significant reverse recovery time. Schottky

diodes are generally available with reverse voltage ratings

ofupto60Vandeven100V, andarepricecompetitivewith

other types.

The use of so-called “ultrafast” recovery diodes is gener-

ally not recommended. When operating in continuous

mode, the reverse recovery time exhibited by “ultrafast”

diodes will result in a slingshot type effect. The power

internalswitchwillrampupV_INcurrentintothediodeinan

attempt to get it to recover. Then, when the diode has

finallyturnedoff,sometensofnanosecondslater,theV_SW

node voltage ramps up at an extremely high dV/dt, per-

haps 5 to even 10V/ns! With real world lead inductances,

the V_SWnode can easily overshoot the V_INrail. This can

result in poor RFI behavior and if the overshoot is severe

enough, damage the IC itself.

A 0.22µF boost capacitor is recommended for most appli-

cations. Almost any type of film or ceramic capacitor is

suitable, but the ESR should be <1Ω to ensure it can be

fully recharged during the off time of the switch. The

capacitor value is derived from worst-case conditions of

1840ns on time, 75mA boost current and 0.7V discharge

ripple. The boost capacitor value could be reduced under

less demanding conditions, but this will not improve

circuitoperationorefficiency.Underlowinputvoltageand

low load conditions, a higher value capacitor will reduce

discharge ripple and improve start-up operation.

The suggested catch diode (D1) is an International Recti-

fier 30BQ060 Schottky. It is rated at 3A average forward

current and 60V reverse voltage. Typical forward voltage

is 0.52V at 3A. The diode conducts current only during

switch off time. Peak reverse voltage is equal to regulator

input voltage. Average forward current in normal opera-

tion can be calculated from:

SHUTDOWN FUNCTION AND UNDERVOLTAGE

LOCKOUT

Figure 4 shows how to add undervoltage lockout (UVLO)

to the LT3431. Typically, UVLO is used in situations where

the input supply is current limited, or has a relatively high

source resistance. A switching regulator draws constant

power from the source, so source current increases as

source voltage drops. This looks like a negative resistance

loadtothesourceandcancausethesourcetocurrentlimit

or latch low under low source voltage conditions. UVLO

prevents the regulator from operating at source voltages

where these problems might occur.

I_OUTV – V_OUT

(

IN

)

I_D(AVG)

=

V

IN

This formula will not yield values higher than 3A with

maximum load current of 3A.

sn3431 3431fs

15

LT3431

W U U

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APPLICATIO S I FOR ATIO

R

FB

L1

LT3431

OUTPUT

V

SW

2.38V

+

–

IN

INPUT

STANDBY

R

HI

5.5µA

+

SHDN

C1

+

–

TOTAL

SHUTDOWN

R

C2

LO

0.4V

GND

3431 F04

Figure 4. Undervoltage Lockout

Threshold voltage for lockout is about 2.38V. A 5.5µA bias

currentflows outofthepinatthisthreshold. Theinternally

generated current is used to force a default high state on

the shutdown pin if the pin is left open. When low shut-

down current is not an issue, the error due to this current

can be minimized by making R_LO10k or less. If shutdown

currentisanissue, R_LOcanberaisedto100k, buttheerror

due to initial bias current and changes with temperature

should be considered.

25k suggested for R_LO

V_IN= Input voltage at which switching stops as input

voltage descends to trip level

∆V = Hysteresis in input voltage level

Example: output voltage is 5V, switching is to stop if input

voltage drops below 12V and should not restart unless

input rises back to 13.5V. ∆V is therefore 1.5V and

V_IN= 12V. Let R_LO= 25k.

25k 12 − 2.38 1.5/5 +1 + 1.5

R

_LO= 10k to 100k 25k suggested

(

)

[

]

(

)

R_HI=

2.38 – 25k 5.5µA

R_LOV − 2.38V

(

)

(

IN

)

R_HI=

25k 10.41

2.38V − R_LO5.5µA

(

)

(

)

=

= 116k

2.24

V_IN= Minimum input voltage

R_FB= 116k 5/1.5 = 387k

(

)

Keep the connections from the resistors to the shutdown

pin short and make sure that interplane or surface capaci-

tance to the switching nodes are minimized. If high

resistor values are used, the shutdown pin should be

bypassed with a 1000pF capacitor to prevent coupling

problems from the switch node. If hysteresis is desired in

the undervoltage lockout point, a resistor R_FBcan be

added to the output node. Resistor values can be calcu-

lated from:

SYNCHRONIZING

The SYNC input must pass from a logic level low, through

the maximum synchronization threshold with a duty cycle

between 10% and 90%. The input can be driven directly

from a logic level output. The synchronizing range is equal

to initial operating frequency up to 700kHz. This means

that minimum practical sync frequency is equal to the

worst-case high self-oscillating frequency (570kHz), not

the typical operating frequency of 500kHz. Caution should

be used when synchronizing above 662kHz because at

highersyncfrequenciestheamplitudeoftheinternalslope

compensation used to prevent subharmonic switching is

R_LOV − 2.38 ∆V/V_OUT+1 + ∆V

IN

(

)

[

]

R_HI=

2.38 − R_LO5.5µA

(

)

R_FB= R_HIV_OUT

/

∆V

(

)(

)

sn3431 3431fs

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U

reduced. This type of subharmonic switching only occurs

at input voltages less than twice output voltage. Higher

inductor values will tend to eliminate this problem. See

Frequency Compensation section for a discussion of an

entirely different cause of subharmonic switching before

assuming that the cause is insufficient slope compensa-

tion. Application Note 19 has more details on the theory

of slope compensation.

nanosecond range. To prevent noise both radiated and

conducted, the high speed switching current path, shown

inFigure5,mustbekeptasshortaspossible.Thisisimple-

mented in the suggested layout of Figure 6. Shortening

this path will also reduce the parasitic trace inductance of

approximately 25nH/inch. At switch off, this parasitic in-

ductance produces a flyback spike across the LT3431

switch. When operating at higher currents and input volt-

ages, with poor layout, this spike can generate voltages

acrosstheLT3431thatmayexceeditsabsolutemaximum

rating. A ground plane should always be used under the

switcher circuitry to prevent interplane coupling and over-

all noise.

At power-up, when V_Cis being clamped by the FB pin (see

Figure2,Q2),thesyncfunctionisdisabled.Thisallowsthe

frequency foldback to operate in the shorted output con-

dition. During normal operation, switching frequency is

controlledbytheinternaloscillatoruntiltheFBpinreaches

0.6V, after which the SYNC pin becomes operational. If no

synchronization is required, this pin should be connected

to ground.

LT3431

L1

5V

HIGH

FREQUENCY

CIRCULATING

PATH

V

IN

C3

D1 C1

LOAD

LAYOUT CONSIDERATIONS

As with all high frequency switchers, when considering

layout,caremustbetakeninordertoachieveoptimalelec-

trical, thermal and noise performance. For maximum

efficiency, switch rise and fall times are typically in the

3431 F05

Figure 5. High Speed Switching Path

1

2

3

4

5

6

GND

SW

CONNECT TO

V

IN

GROUND PLANE

V

IN

GND

LT3431

SW

L1

BOOST

SOLDER THE EXPOSED PAD

TO THE ENTIRE COPPER

C1

V

PINS 3 AND 4

IN

GROUND PLANE UNDERNEATH

THE DEVICE. NOTE: THE BOOST

AND BIAS COPPER TRACES ARE

ON A SEPARATE LAYER FROM

THE GROUND PLANE

MINIMIZE LT3430

C3-D1 LOOP

ARE SHORTED TOGETHER.

D2

SW PINS 2 AND 5 ARE ALSO

SHORTED TOGETHER (USING

AVAILABLE SPACE UNDERNEATH

THE DEVICE BETWEEN PINS AND

GND PLANE)

V

OUT

D1

C3

C2

GND

1

GND

SW

GND 16

15

KELVIN SENSE

SHDN

V

OUT

2

3

4

5

6

7

8

V

IN

14

SYNC

R2

V

IN

13

CFB

R1

LT3431

SW

FB 12

11

KEEP FB AND V COMPONENTS

C

AWAY FROM HIGH FREQUENCY,

HIGH CURRENT COMPONENTS

BOOST

V

C

BIAS 10

GND

C

R

C

F

GND

9

V

IN

C

PLACE FEEDTHROUGH AROUND

GROUND PINS (4 CORNERS) FOR

GOOD THERMAL CONDUCTIVITY

3431 F06

Figure 6. Suggested Layout

sn3431 3431fs

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The V_Cand FB components should be kept as far away as

possible from the switch and boost nodes. The LT3431

pinout has been designed to aid in this. The ground for

these components should be separated from the switch

current path. Failure to do so will result in poor stability or

subharmonic like oscillation.

absolute max switch voltage. The path around switch,

catch diode and input capacitor must be kept as short as

possibletoensurereliableoperation.Whenlookingatthis,

a >100MHz oscilloscope must be used, and waveforms

should be observed on the leads of the package. This

switch off spike will also cause the SW node to go below

ground. The LT3431 has special circuitry inside which

mitigates this problem, but negative voltages over 0.8V

lasting longer than 10ns should be avoided. Note that

100MHz oscilloscopes are barely fast enough to see the

details of the falling edge overshoot in Figure 7.

Board layout also has a significant effect on thermal

resistance. Pins 1, 8, 9 and 16, GND, are a continuous

copper plate that runs under the LT3431 die. This is an

exposedpadandisthebestthermalpathforheatoutofthe

package. Soldering the exposed pad to the copper ground

plane under the device will reduce die temperature and

increase the power capability of the LT3431. Adding

multiple solder filled feedthroughs under and around the

four corner pins to the ground plane will also help. Similar

treatment to the catch diode and coil terminations will

reduce any additional heating effects.

A second, much lower frequency ringing is seen during

switch off time if load current is low enough to allow the

inductor current to fall to zero during part of the switch off

time (see Figure 8). Switch and diode capacitance reso-

nate with the inductor to form damped ringing at 1MHz to

10MHz. This ringing is not harmful to the regulator and it

hasnotbeenshowntocontributesignificantlytoEMI. Any

attempt to damp it with a resistive snubber will degrade

efficiency.

PARASITIC RESONANCE

Resonance or “ringing” may sometimes be seen on the

switch node (see Figure 7). Very high frequency ringing

followingswitchrisetimeiscausedbyswitch/diode/input

capacitor lead inductance and diode capacitance. Schot-

tky diodes have very high “Q” junction capacitance that

can ring for many cycles when excited at high frequency.

If total lead length for the input capacitor, diode and

switchpathis1inch,theinductancewillbeapproximately

25nH. At switch off, this will produce a spike across the

NPN output device in addition to the input voltage. At

highercurrentsthisspikecanbeintheorderof10Vto20V

or higher with a poor layout, potentially exceeding the

INDUCTOR

0.2A/DIV

5V/DIV

CURRENT AT

I

_OUT= 0.1A

SWITCH NODE

VOLTAGE

V_IN= 12V

V_OUT= 5V

L = 10µH

500ns/DIV

3431 F08

Figure 8. Discontinuous Mode Ringing

SW RISE

SW FALL

THERMAL CALCULATIONS

Power dissipation in the LT3431 chip comes from four

sources: switch DC loss, switch AC loss, boost circuit

current,andinputquiescentcurrent.Thefollowingformu-

las show how to calculate each of these losses. These

formulas assume continuous mode operation, so they

should not be used for calculating efficiency at light load

currents.

2V/DIV

50ns/DIV

3431 F07

Figure 7. Switch Node Resonance

sn3431 3431fs

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U

Switch loss:

When estimating ambient, remember the nearby catch

diode and inductor will also be dissipating power:

2

R_SWI_OUTV_OUT

(

) (

)

P

SW

=

+ t_EFF(1/2) I_OUT

V

f

(

)( ^IN)( )

(V_F)(V – V_OUT)(I_LOAD

)

IN

V

P_DIODE=

IN

V

IN

Boost current loss:

V_F= Forward voltage of diode (assume 0.52V at 2A)

2

V_OUT

I

_OUT/36

(

)

(0.52)(12 – 5)(2)

P_BOOST

=

P_DIODE

=

= 0.61W

V

IN

12

Quiescent current loss:

Notice that the catch diode’s forward voltage contributes

a significant loss in the overall system efficiency. A larger,

lower V_Fdiode can improve efficiency by several percent.

P_Q=V 0.0015 + V_OUT0.003

IN

(

)

(

)

R_SW= Switch resistance (≈0.15) hot

P_INDUCTOR= (I_LOAD)²(R_IND

)

t_EFF= Effective switch current/voltage overlap time

= (t_r+ t_f+ t_Ir+ t_If)

R_IND= Inductor DC resistance (assume 0.1Ω)

P_INDUCTOR(2)²(0.1) = 0.4W

t_r= (V_IN/1.2)ns

t_f= (V_IN/1.1)ns

t_Ir= t_If= (I_OUT/0.05)ns

f = Switch frequency

Typical thermal resistance of the board is 5°C/W. Taking

the catch diode and inductor power dissipation into ac-

count and using the example calculations for LT3431

dissipation, the LT3431 die temperature will be estimated

as:

Example: with V_IN= 12V, V_OUT= 5V and I_OUT= 2A

(0.15)(2)²(5)

P

SW

=

+ (101•10⁻⁹)(1/2)(2)(12)(500•10³)

T_J= T_A+ (θ_JA• P_TOT) + [5 • (P_DIODE+ P_INDUCTOR)]

12

With the TSSOP package (θ_JA= 45°C/W), at an ambient

temperature of 50°C:

= 0.25 + 0.61= 0.86W

(5)²(2 /36)

P_BOOST

=

= 0.12W

T_J= 50 + (45 • 1.01) + (5 • 1.01) = 101°C

12

Die temperature can peak for certain combinations of V_IN,

V_OUTand load current. While higher V_INgives greater

switch AC losses, quiescent and catch diode losses, a

lower V_INmay generate greater losses due to switch DC

losses. In general, the maximum and minimum V_INlevels

should be checked with maximum typical load current for

calculation of the LT3431 die temperature. If a more

accurate die temperature is required, a measurement of

the SYNC pin resistance (to GND) can be used. The SYNC

pin resistance can be measured by forcing a voltage no

greaterthan0.5Vatthepinandmonitoringthepincurrent

over temperature in an oven. This should be done with

minimal device power (low V_INand no switching

(V_C= 0V)) in order to calibrate SYNC pin resistance with

ambient (oven) temperature.

P_Q= 12(0.0015)+ 5(0.003) = 0.033W

Total power dissipation in the IC is given by:

P_TOT= P_SW+ P_BOOST+ P_Q

= 0.86W + 0.12W + 0.03W = 1.01W

Thermal resistance for the LT3431 package is influenced

by the presence of internal or backside planes.

TSSOP(ExposedPad)Package:Withafullplaneunderthe

TSSOP package, thermal resistance (θ_JA) will be about

45°C/W.

To calculate die temperature, use the proper thermal

resistance number for the desired package and add in

worst-case ambient temperature:

T_J= T_A+ (θ_JA• P_TOT

)

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Note: Some of the internal power dissipation in the IC, due

to BOOST pin voltage, can be transferred outside of the IC

to reduce junction temperature, by increasing the voltage

drop in the path of the boost diode D2. (see Figure 9). This

reduction of junction temperature inside the IC will allow

higher ambient temperature operation for a given set of

conditions. BOOST pin circuitry dissipates power given

by:

Example:TheBOOSTpinpowerdissipationfora20Vinput

to 12V output conversion at 2A is given by :

12 • (2 / 36) •12

P_BOOST

=

= 0.4W

20

If a 7V zener D4 is placed in series with D2, then power

dissipation becomes :

12 • (2 / 36) •5

P_BOOST

=

= 0.167W

V

_OUT• (I_SW/ 36) • V_C2

20

P_DISS(BOOST)

=

V

IN

For an FE package with thermal resistance of 45°C/W,

ambient temperature savings would be, T_(AMBIENT)sav-

ings = 0.233W • 45°C/W = 11°C. The 7V zener should be

sizedforexcessof0.233Woperaton. Thetolerancesofthe

zener should be considered to ensure minimum V_C2ex-

Typically V_C2(the boost voltage across the capacitor C2)

equals V_OUT. This is because diodes D1 and D2 can be

considered almost equal, where:

ceeds 3.3V + V_DROOP

.

V_C2= V_OUT– V_FD2– (–V_FD1) = V_OUT

.

Hencetheequationusedforboostcircuitrypowerdissipa-

tion given in the previous Thermal Calculations section is

stated as:

D2 D4

D2

V_OUT• (I_SW/ 36) • V_OUT

C2

P_DISS(BOOST)

=

BOOST

L1

V

IN

V

IN

LT3431 SW

IN

C3

BIAS

Here it can be seen that Boost power dissipation increases

as the square of Vout. It is possible, however, to reduce

V_C2below Vout to save power dissipation by increasing

the voltage drop in the path of D2. Care should be taken

that V_C2does not fall below the minimum 3.3V Boost

voltage required for full saturation of the internal power

switch.Foroutputvoltagesof5V,V_C2isapproximately5V.

During switch turn on, V_C2will fall as the boost capacitor

C2 is dicharged by the boost pin. In a previous BOOST Pin

section, the value of C2 was designed for a 0.7V droop in

V_C2= V_DROOP. Hence, an output voltage as low as 4V

would still allow the minimum 3.3V for the boost function

usingtheC2capacitorcalculated.Ifatargetoutputvoltage

of 12V is required, however, an excess of 8V is placed

across the boost capacitor which is not required for the

boost function, but still dissipates additional power. What

is required is a voltage drop in the path of D2 to achieve

minimal power dissipation while still maintaining mini-

mum boost voltage across C2. A zener, D4, placed in

series with D2 (see Figure 9), drops voltage to C2.

R1

R2

SHDN

SYNC

FB

+

GND

V

C

C1

D1

R

C

F

C

3431 F09

Figure 9. BOOST Pin, Diode Selection

Input Voltage vs Operating Frequency Considerations

TheabsolutemaximuminputsupplyvoltagefortheLT3431

is specified at 60V. This is based on internal semiconduc-

tor junction breakdown effects. The practical maximum

input supply voltage for the LT3431 may be less than 60V

due to internal power dissipation or switch minimum on

time considerations.

For the extreme case of an output short-circuit fault to

ground, see the section Short-Circuit Considerations.

sn3431 3431fs

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A detailed theoretical basis for estimating internal power

dissipation is given in the Thermal Calculations section.

Thiswillallowafirstpasscheckofwhetheranapplication’s

maximum input voltage requirement is suitable for the

LT3431. Be aware that these calculations are for DC input

voltages and that input voltage transients as high as 60V

are possible if the resulting increase in internal power

dissipation is of insufficient time duration to raise die

temperature significantly. For the FE package, this means

high voltage transients on the order of hundreds of milli-

seconds are possible. If LT3431 thermal calculations

show power dissipation is not suitable for the given

application, the LT3430 is a recommended alternative

since it is identical to the LT3431 but runs cooler at

200kHz.

tion, the theoretical analysis considers only first order

non-ideal component behavior. For these reasons, it is

important that a final stability check is made with produc-

tion layout and components.

The LT3431 uses current mode control. This alleviates

many of the phase shift problems associated with the

inductor. The basic regulator loop is shown in Figure 10.

The LT3431 can be considered as two g_mblocks, the error

amplifier and the power stage.

LT3431

CURRENT MODE

POWER STAGE

SW

OUTPUT

ERROR

AMPLIFIER

g

= 2mho

m

C

R1

FB

–

CERAMIC

g

=

m

2000µmho

Switch minimum on time is the other factor that may limit

the maximum operational input voltage for the LT3431 if

pulse-skipping behavior is not allowed. For the LT3431,

pulse-skipping may occur for V_IN/(V_OUT+ V_F) ratios > 4.

(V_F= Schottky diode D1 forward voltage drop, Figure 5.)

If the LT3430 is used, the ratio increases to 10. Pulse-

skippingistheregulator’swayofmissingswitchpulsesto

maintain output voltage regulation. Although an increase

in output ripple voltage can occur during pulse-skipping,

a ceramic output capacitor can be used to keep ripple

voltage to a minimum (see output ripple voltage compari-

son for tantalum vs ceramic output capacitors, Figure 3).

ESR

ESL

C1

+

R

1.22V

O

R

LOAD

200k

+

C1

GND

V

C

TANTALUM

R2

R

C

F

C

3431 F10

Figure 10. Model for Loop Response

Figure 11 shows the overall loop response. At the V_Cpin,

the frequency compensation components used are:

R_C= 3.3k, C_C= 0.022µF and C_F= 220pF. The output

capacitor used is a 100µF, 10V tantalum capacitor with

typical ESR of 100mΩ.

FREQUENCY COMPENSATION

Before starting on the theoretical analysis of frequency

response,thefollowingshouldberemembered—theworse

the board layout, the more difficult the circuit will be to

stabilize. This is true of almost all high frequency analog

circuits, read the Layout Considerations section first.

Common layout errors that appear as stability problems

are distant placement of input decoupling capacitor and/

or catch diode, and connecting the V_Ccompensation to a

ground track carrying significant switch current. In addi-

The ESR of the tantalum output capacitor provides a

useful zero in the loop frequency response for maintain-

ing stability.

This ESR, however, contributes significantly to the ripple

voltage at the output (see Output Ripple Voltage in the

Applications Information section). It is possible to reduce

capacitor size and output ripple voltage by replacing the

sn3431 3431fs

21

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APPLICATIO S I FOR ATIO

tantalum output capacitor with a ceramic output capacitor

because of its very low ESR. The zero provided by the

tantalum output capacitor must now be reinserted back

intotheloop. Alternativelytheremaybecaseswhere, even

with the tantalum output capacitor, an additional zero is

requiredinthelooptoincreasephasemarginforimproved

transient response.

a capacitor, C_FB, can be inserted between the output and

FB pin but care must be taken for high output voltage

applications. Sudden shorts to the output can create

unacceptably large negative transients on the FB pin.

For V_IN-to-V_OUTratios <4, higher loop bandwidths are

possiblebyreadjustingthefrequencycompensationcom-

ponents at the V_Cpin.

A zero can be added into the loop by placing a resistor, R_C,

at the V_Cpin in series with the compensation capacitor, C_C

or by placing a capacitor, C_FB, between the output and the

FB pin.

When checking loop stability, the circuit should be oper-

ated over the application’s full voltage, current and

temperature range. Proper loop compensation may be

obtained by empirical methods as described in detail in

Application Notes 19 and 76.

80

180

150

120

90

60

GAIN

40

CONVERTER WITH BACKUP OUTPUT REGULATOR

20

In systems with a primary and backup supply, for ex-

ample, a battery powered device with a wall adapter input,

the output of the LT3431 can be held up by the backup

supply with the LT3431 input disconnected. In this condi-

tion, the SW pin will source current into the V_INpin. If the

SHDN pin is held at ground, only the shut down current of

30µAwillbepulledviatheSWpinfromthesecondsupply.

With the SHDN pin floating, the LT3431 will consume its

quiescentoperatingcurrentof1.5mA. TheV_INpinwillalso

source current to any other components connected to the

input line. If this load is greater than 10mA or the input

could be shorted to ground, a series Schottky diode must

be added, as shown in Figure 12. With these safeguards,

the output can be held at voltages up to the V_INabsolute

maximum rating.

PHASE

0

60

–20

–40

30

0

10

100

1k

10k

100k

1M

FREQUENCY (Hz)

R

3431 F11

V

= 12V

= 3.3k

= 22nF

= 220pF

IN

C

F

V

= 5V

C

OUT

LOAD

I

= 1A

C

= 100µF, 10V, 0.1Ω

OUT

Figure 11. Overall Loop Response

When using R_C, the maximum value has two limitations.

First, thecombinationofoutputcapacitorESRandR_Cmay

stopthelooprollingoffaltogether. Second, iftheloopgain

is not rolled sufficiently at the switching frequency, output

ripple will perturb the V_Cpin enough to cause unstable

duty cycle switching similar to subharmonic oscillation. If

needed, an additional capacitor (C_F) can be added across

the R_C/C_Cnetwork from V_Cpin to ground to further

suppress V_Cripple voltage.

D2

MMSD914TI

C2

D3

30BQ060

0.22µF

BOOST

10µH

REMOVABLE

INPUT

V

LT3431 SW

IN

5V, 2A

ALTERNATE

SUPPLY

54k

BIAS

R1

15.4k

SHDN

SYNC

With a tantalum output capacitor, the LT3431 already

includesaresistor, R_Candfiltercapacitor, C_F, attheV_Cpin

(see Figures 10 and 11) to compensate the loop over the

entire V_INrange (to allow for stable pulse skipping for high

V_IN-to-V_OUTratios≥4).Aceramicoutputcapacitorcanstill

be used with a simple adjustment to the resistor R_Cfor

stable operation. (See Ceramic Capacitors section for

stabilizingLT3431).Ifadditionalphasemarginisrequired,

FB

R2

GND

V

C

D1

30BQ060

4.99k

25k

+

C1

100µF

10V

R

C

F

C3

4.7µF

3.3k

C

220pF

C

0.022µF

3431 F12

Figure 12. Dual Source Supply with 25µA Reverse Leakage

sn3431 3431fs

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BUCK CONVERTER WITH ADJUSTABLE SOFT-START

Dual Polarity Output Converter

Large capacitive loads or high input voltages can cause

high input currents at start-up. Figure 13 shows a circuit

that limits the dv/dt of the output at start-up, controlling

the capacitor charge rate. The buck converter is a typical

configuration with the addition of R3, R4, C_SSand Q1.

As the output starts to rise, Q1 turns on, regulating switch

current via the V_Cpin to maintain a constant dv/dt at the

output. Output rise time is controlled by the current

through C_SSdefined by R4 and Q1’s V_BE. Once the output

is in regulation, Q1 turns off and the circuit operates

normally. R3 is transient protection for the base of Q1.

The circuit in Figure 14a generates both positive and

negative 5V outputs with all components under 3mm

height. The topology for the 5V output is a standard buck

converter. The –5V output uses a second inductor L2,

diode D3, and output capacitor C6. The capacitor C4

couples energy to L2 and ensures equal voltages across

L2 and L1 during steady state. Instead of using a trans-

former for L1 and L2, uncoupled inductors were used

becausetheyrequirelessheightthanasingletransformer,

can be placed separately in the circuit layout for optimized

space savings and reduce overall cost. This is true even

whentheuncoupledinductorsaresized(twicethevalueof

inductance of the transformer) in order to keep ripple

current comparable to the transformer solution. If a single

transformer becomes available to provide a better height

/cost solution, refer to the Dual Output SEPIC circuit

description in Design Note 100 for correct transformer

connection.

R4 C_SSV_OUT

( )(

)(

)

Rise Time =

V_BE

Using the values shown in Figure 10,

47 •10³15•10^–9

5

( )

(

)(

)

Rise Time =

= 5ms

0.7

During switch on-time, in steady state, the voltage across

both L1 and L2 is positive and equal ; with energy (and

current) ramping up in each inductor. The current in L2 is

provided by the coupling capacitor C4. During switch off-

time, current ramps downward in each inductor. The

currentinL2andC4flowsviathecatchdiodeD3, charging

the negative output capacitor C6. If the negative output is

notloadedenoughitcangoseverelyunregulated(become

more negative). Figure 14b shows the maximum allow-

able –5V output load current (vs load current on the 5V

output) that will maintain the –5V output within 3%

tolerance. Figure 14c shows the –5V output voltage regu-

lation versus its own load current when plotted for three

separate load currents on the 5V output. The efficiency of

the dual polarity output converter circuit shown in Figure

14a is given in Figure 14d.

The ramp is linear and rise times in the order of 100ms are

possible. Since the circuit is voltage controlled, the ramp

rate is unaffected by load characteristics and maximum

outputcurrentisunchanged. Variantsofthiscircuitcanbe

used for sequencing multiple regulator outputs.

D2

MMSD914TI

C2

0.22µF

L1

15µH

BOOST

BIAS

SW

OUTPUT

5V

2A

INPUT

12V

V

IN

C3

D1

C1

100µF

10V

+

R1

4.7µF

25V

CER

30BQ060

LT3431

15.4k

OR B250A

SHDN

SYNC GND

FB

C

R2

4.99k

V

C

SS

15nF

C

F

R3

2k

Q1

220pF

R

C

3.3k

3431 F13

C

R4

47k

0.022µF

L1: CDRH104R-220M

Figure 13. Buck Converter with Adjustable Soft-Start

sn3431 3431fs

23

LT3431

APPLICATIO S I FOR ATIO

W U U

U

V

IN

9V TO 16V

36V TRANSIENT

D2

MMSD914T1

C3

2.2µF

50V

L1

C2

CDRH6D28-100

0.22µF

V

BOOST

SW

IN

10µH

V

OUT1

CER

5V AT

1.5A*

SHDN

LT3431EFE

V

OUT1

SYNC

BIAS

C4

R2

10µF

6.3V

0805

X5R

CER

C5

15.4k

22µF

F

B

6.3V

R3

4.99k

X5R CER

GND

V

C

D1

B140A

R

C

F

220pF

1.5k

C

10nF

C

C6

22µF

6.3V

L2

CDRH6D28-100

X5R CER

†

10µH

FOR LOAD CURRENT LESS THAN 25mA,

A PRELOAD OF 200Ω SHOULD BE USED

TO IMPROVE LOAD REGULATION.

OUT1 OUT2

LOAD CURRENT RELATIONSHIP

†

V

OUT2

–5V AT 0.9A*

*SEE FIGURE 14c FOR V

, V

D3

B140A

3431 F14a

Figure 14a. Dual Polarity Output Converter with all Components Under 3mm Height

100

95

90

85

80

75

70

65

60

5.30

5.25

5.20

5.15

5.10

5.05

5.00

4.95

4.90

4.85

4.80

4/75

4.70

1200

1000

800

600

400

200

0

V

= 12V

V

= 12V

IN

V

= 16V

IN

V

= 12V

IN

V

AT 1A

V

OUT1

V

= 9V

IN

V

OUT1

AT 500mA

V

AT 1.5A

OUT1

V

AT 500mA

OUT1

V

OUT1

AT 1A

400

LOAD CURRENT (mA)

0

200

V

600

800

1000

0

1000

1500

500

2000

0

200

V

400

600

800

1000

V

LOAD CURRENT (mA)

OUT1

OUT2

3431 F14d

3431F14b

3431 F14c

Figure 14b. V_OUT2(–5V) Maximum

Allowable Load Current vs V_OUT1

(5V) Load Current

Figure 14c. V_OUT2(–5V)

Output Voltage vs Load Current

Figure 14d. Dual Polarity

Output Converter Efficiency

sn3431 3431fs

24

LT3431

W U U

APPLICATIO S I FOR ATIO

U

POSITIVE-TO-NEGATIVE CONVERTER

Inductor Value

The circuit in Figure 15 is a positive-to-negative topology

using a grounded inductor. It differs from the standard

approach in the way the IC chip derives its feedback signal

because the LT3431 accepts only positive feedback sig-

nals. Thegroundpinmustbetiedtotheregulatednegative

output. A resistor divider to the FB pin then provides the

proper feedback voltage for the chip.

The criteria for choosing the inductor is typically based on

ensuring that peak switch current rating is not exceeded.

This gives the lowest value of inductance that can be used,

but in some cases (lower output load currents) it may give

a value that creates unnecessarily high output ripple

voltage.

The difficulty in calculating the minimum inductor size

needed is that you must first decide whether the switcher

will be in continuous or discontinuous mode at the critical

point where switch current reaches 3A. The first step is to

use the following formula to calculate the load current

above which the switcher must use continuous mode. If

your load current is less than this, use the discontinuous

mode formula to calculate minimum inductor needed. If

load current is higher, use the continuous mode formula.

Thefollowingequationcanbeusedtocalculatemaximum

load current for the positive-to-negative converter:

(V )(V_OUT

)

IN

I_P–

(V_OUT)(V – 0.15)

IN

2(V_OUT+ V )(f)(L)

IN

I_MAX

=

(V_OUT+ V – 0.15)(V_OUT+ V_F)

IN

I_P= Maximum rated switch current

V_IN= Minimum input voltage

V_OUT= Output voltage

V_F= Catch diode forward voltage

0.15 = Switch voltage drop at 3A

Output current where continuous mode is needed:

(V )²(I_P)²

IN

I_CONT

>

4(V + V_OUT)(V + V_OUT+ V_F)

IN

Example: with V_IN(MIN)= 5.5V, V_OUT= 12V, L = 3.9µH,

V_F= 0.52V, I_P= 3A: I_MAX= 0.6A.

Minimum inductor discontinuous mode:

2(V_OUT)(I_OUT

(f)(I_P)²

)

†

L_MIN

=

D2

MMSD914TI

C2

0.22µF

L1*

Minimum inductor continuous mode:

(V )(V_OUT

3.9µH

INPUT

12V

BOOST

LT3431

SW

FB

V

IN

)

R1

36.5k

IN

L_MIN

=

(V_OUT+ V_F)

GND

V

C

C3

2(f)(V + V_OUT) I_P– I_OUT1+

+

C1

100µF

16V TANT

IN

D1

2.2µF

25V

CER

V

IN

30BQ060

C

R2

C

4.12k

R

F

C

OUTPUT**

–12V, 0.5A

3431 F15

For a 12V to –12V converter using the LT3431 with peak

switch current of 3A and a catch diode of 0.52V:

* INCREASE L1 FOR HIGHER CURRENT APPLICATIONS.

SEE APPLICATIONS INFORMATION

** MAXIMUM LOAD CURRENT DEPENDS ON MINIMUM INPUT VOLTAGE

AND INDUCTOR SIZE. SEE APPLICATIONS INFORMATION

(12)²(3)²

4(12 +12)(12 +12 + 0.52)

I_CONT

=

= 0.742A

Figure 15. Positive-to-Negative Converter

sn3431 3431fs

25

LT3431

W U U

U

APPLICATIO S I FOR ATIO

For a load current of 0.5A, this says that discontinuous

mode can be used and the minimum inductor needed is

found from:

reduces the size required for the output capacitor (versus

placing the input capacitor between V_INand ground).

The peak-to-peak ripple current in both the inductor and

output capacitor (assuming continuous mode) is:

2(12)(0.5)

(500•10³)(3)²

L_MIN

=

= 2.7µH

DC •V

IN

I_P-P

=

In practice, the inductor should be increased by about

30% over the calculated minimum to handle losses and

variations in value. This suggests a minimum inductor of

3.5µH for this application.

f •L

V_OUT+ V_F

V_OUT+ V + V_F

DC = Duty Cycle =

IN

I_P-P

I_COUT(RMS) =

Ripple Current in the Input and Output Capacitors

12

Positive-to-negativeconvertershavehighripplecurrentin

the input capacitor. For long capacitor lifetime, the RMS

value of this current must be less than the high frequency

ripple current rating of the capacitor. The following for-

mula will give an approximate value for RMS ripple cur-

rent. This formula assumes continuous mode and large

inductor value. Small inductors will give somewhat higher

ripple current, especially in discontinuous mode. The

exactformulasareverycomplexandappearinApplication

Note 44, pages 29 and 30. For our purposes here I have

simply added a fudge factor (ff). The value for ff is about

1.2 for higher load currents and L ≥15µH. It increases to

about 2.0 for smaller inductors at lower load currents.

Theoutputripplevoltageforthisconfigurationisaslowas

the typical buck regulator based predominantly on the

inductor’s triangular peak-to-peak ripple current and the

ESR of the chosen capacitor (see Output Ripple Voltage in

Applications Information).

Diode Current

Average diodecurrentisequaltoloadcurrent. Peak diode

current will be considerably higher.

Peak diode current:

Continuous Mode =

V_OUT

V

IN

(V + V_OUT

)

(V )(V_OUT)

IN

Capacitor I_RMS= (ff)(I_OUT

)

I_OUT

+

V

IN

2(L)(f)(V + V_OUT)

IN

ff = 1.2 to 2.0

2(I_OUT)(V_OUT

(L)(f)

)

Discontinuous Mode =

The output capacitor ripple current for the positive-to-

negative converter is similar to that for a typical buck

regulator—it is a triangular waveform with peak-to-peak

valueequaltothepeak-to-peaktriangularwaveformofthe

inductor. The low output ripple design in Figure 15 places

theinputcapacitorbetweenV_INandtheregulatednegative

output. This placement of the input capacitor significantly

Keep in mind that during start-up and output overloads,

average diode current may be much higher than with

normalloads.Careshouldbeusedifdiodesratedlessthan

1A are used, especially if continuous overload conditions

must be tolerated.

sn3431 3431fs

26

LT3431

U

PACKAGE DESCRIPTIO

FE Package

16-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663,

Exposed Pad Variation BB)

4.90 – 5.10*

(.193 – .201)

3.58

(.141)

3.58

(.141)

16 1514 13 12 1110

9

6.60 ±0.10

4.50 ±0.10

2.94

(.116)

SEE NOTE 4

2.94

(.116)

6.40

BSC

0.45 ±0.05

1.05 ±0.10

0.65 BSC

5

7

8

1

2

3

4

6

RECOMMENDED SOLDER PAD LAYOUT

1.10

(.0433)

MAX

4.30 – 4.50*

(.169 – .177)

0° – 8°

0.65

(.0256)

BSC

0.45 – 0.75

0.09 – 0.20

0.05 – 0.15

(.018 – .030)

(.0036 – .0079)

(.002 – .006)

0.195 – 0.30

(.0077 – .0118)

FE16 (BB) TSSOP 0203

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

FOR EXPOSED PAD ATTACHMENT

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

MILLIMETERS

(INCHES)

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

sn3431 3431fs

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

27

LT3431

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

= 7.3V to 45/64V, V

LT1074/LT1074HV

4.4A (I ), 100kHz, High Efficiency

V

= 2.21V, I = 8.5mA, I = 10µA,

OUT Q SD

DD-5/7, TO220-5/7 Packages

OUT

IN

Step-Down DC/DC Converter

LT1076/LT1076HV

LT1616

1.6A (I ), 100kHz, High Efficiency

Step-Down DC/DC Converter

V

IN

= 7.3V to 45/64V, V = 2.21V, I = 8.5mA, I = 10µA,

OUT

Q

SD

DD-5/7, TO220-5/7 Packages

25V, 500mA (I ), 1.4MHz, High Efficiency

V

IN

= 3.6V to 25V, V

= 1.25V, I = 1.9mA, I = <1µA,

Q SD

OUT

Step-Down DC/DC Converter

ThinSOT Package

LT1676

60V, 440mA (I ), 100kHz, High Efficiency

Step-Down DC/DC Converter

V

= 7.4V to 60V, V

= 1.24V, I = 3.2mA, I = 2.5µA,

Q SD

OUT

IN

OUT

S8 Package

LTC1701/LTC1701B

LT1765

700mA (I ), 1MHz, High Efficiency

Step-Down DC/DC Converter

V

= 2.5V to 5V, V

= 1.25V, I = 135µA, I = <1µA,

Q SD

OUT

IN

OUT

ThinSOT Package

25V, 2.75A (I ), 1.25MHz, High Efficiency

V

= 3V to 25V, V

= 1.2V, I = 1mA, I = 15µA,

Q SD

OUT

IN

Step-Down DC/DC Converter

S8, TSSOP16E Packages

LT1766

60V, 1.2A (I ), 200kHz, High Efficiency

Step-Down DC/DC Converter

V

IN

= 5.5V to 60V, V = 1.2V, I = 2.5mA, I = 25µA,

OUT

Q

SD

TSSOP16/E Package

= 3V to 25V; V = 1.2V, I = 1mA, I = 6µA,

OUT Q SD

LT1767

25V, 1.2A (I ), 1.25MHz, High Efficiency

V

IN

OUT

Step-Down DC/DC Converter

MS8/E Packages

LT1776

40V, 550mA (I ), 200kHz, High Efficiency

Step-Down DC/DC Converter

V

= 7.4V to 40V; V

= 1.24V, I = 3.2mA, I = 30µA,

OUT Q SD

OUT

IN

N8, S8 Packages

LTC1875

1.5A (I ), 550kHz, Synchronous

Step-Down DC/DC Converter

V

= 2.7V to 6V; V

= 0.8V, I = 15µA, I = <1µA,

OUT Q SD

OUT

IN

TSSOP16 Package

LTC1877

600mA (I ), 550kHz, Synchronous

Step-Down DC/DC Converter

V

= 2.7V to 10V; V

= 0.8V, I = 10µA, I = <1µA,

OUT Q SD

OUT

IN

MS8 Package

LTC1879

1.2A (I ), 550kHz, Synchronous

Step-Down DC/DC Converter

V

= 2.7V to 10V; V

= 0.8V, I = 15µA, I = <1µA,

Q SD

OUT

IN

OUT

TSSOP16 Package

LT1956

60V, 1.2A (I ), 500kHz, High Efficiency

V

IN

= 5.5V to 60V, V

= 1.2V, I = 2.5mA, I = 25µA,

Q SD

OUT

Step-Down DC/DC Converter

TSSOP16/E Package

LTC3404

600mA (I ), 1.4MHz, Synchronous

Step-Down DC/DC Converter

V

= 2.7V to 6V, V

= 0.8V, I = 10µA, I = <1µA,

Q SD

OUT

IN

OUT

MS8 Package

LTC3405/LTC3405A

LTC3406/LTC3406B

LTC3411

300mA (I ), 1.5MHz, Synchronous

Step-Down DC/DC Converter

V

= 2.7V to 6V, V

= 0.8V, I = 20µA, I = <1µA,

Q SD

OUT

IN

OUT

ThinSOT Package

600mA (I ), 1.5MHz, Synchronous

V

IN

= 2.5V to 5.5V, V

= 0.6V, I = 20µA, I = <1µA,

OUT Q SD

OUT

Step-Down DC/DC Converter

ThinSOT Package

1.25A (I ), 4MHz, Synchronous

V

IN

= 2.5V to 5.5V, V

= 0.8V, I = 60µA, I = <1µA,

Q SD

OUT

Step-Down DC/DC Converter

MS Package

LTC3412

2.5A (I ), 4MHz, Synchronous

V

IN

= 2.5V to 5.5V, V

= 0.8V, I = 60µA, I = <1µA,

Q SD

OUT

Step-Down DC/DC Converter

TSSOP16E Package

LT3430

60V, 2.75A (I ), 200kHz, High Efficiency

V

IN

= 5.5V to 60V, V

= 1.2V, I = 2.5mA, I = 30µA,

Q SD

OUT

Step-Down DC/DC Converter

TSSOP16E Package

ThinSOT is a trademark of Linear Technology Corporation.

sn3431 3431fs

LT/TP 0303 2K • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

28

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com

LINEAR TECHNOLOGY CORPORATION 2003


型号：	LT3431IFE#TR
厂家：	Linear
描述：	LT3431 - High Voltage, 3A, 500kHz Step-Down Switching Regulator; Package: TSSOP; Pins: 16; Temperature Range: -40°C to 85°C 开关光电二极管
文件：	总28页 (文件大小：290K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT3431IFE#TR [Linear]

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