LT3434EFE#TR [Linear]
LT3434 - High Voltage 3A, 200kHz Step-Down Switching Regulator with 100µA Quiescent Current; Package: TSSOP; Pins: 16; Temperature Range: -40°C to 85°C;
| 型号： | LT3434EFE#TR |
| 厂家： | 
Linear |
| 描述： | LT3434 - High Voltage 3A, 200kHz Step-Down Switching Regulator with 100µA Quiescent Current; Package: TSSOP; Pins: 16; Temperature Range: -40°C to 85°C 开关 光电二极管 |
| 文件： | 总24页 (文件大小：376K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3434
High Voltage 3A, 200kHz
Step-Down Switching Regulator
with 100µA Quiescent Current
U
DESCRIPTIO
FEATURES
The LT®3434 is a 200kHz monolithic buck switching
regulator that accepts input voltages up to 60V. A high
efficiency3A,0.1Ωswitchisincludedonthediealongwith
all the necessary oscillator, control and logic circuitry.
Current mode topology is used for fast transient response
and good loop stability.
■
Wide Input Range: 3.3V to 60V
■
3A Peak Switch Current
Burst Mode® Operation: 100µA Quiescent Current**
Low Shutdown Current: IQ < 1µA
Power Good Flag with Programmable Threshold
Load Dump Protection to 60V
200kHz Switching Frequency
Saturating Switch Design: 0.1Ω
Peak Switch Current Maintained Over
Full Duty Cycle Range*
■
■
■
■
■
■
■
Innovative design techniques integrated in a new high
voltage process achieve high efficiency over a wide input
range. Efficiency is maintained over a wide output current
rangebyemployingBurstModeoperationatlowcurrents,
utilizing the output to bias the internal circuitry, and by
using a supply boost capacitor to fully saturate the power
switch. Patented circuitry maintains peak switch current
over the full duty cycle range.* Shutdown reduces input
supply current to less than 1µA. External synchronization
canbeimplementedbydrivingtheSYNCpinwithlogic-level
inputs. A single capacitor from the CSS pin to the output
providesacontrolledoutputvoltageramp(soft-start).The
device also has a power good flag with a programmable
thresholdandtime-out,andthermalshutdownprotection.
■
■
■
■
1.25V Feedback Reference Voltage
Easily Synchronizable
Soft-Start Capability
Small 16-Pin Thermally Enhanced TSSOP Package
U
APPLICATIO S
■
High Voltage Power Conversion
■
14V and 42V Automotive Systems
■
Industrial Power Systems
■
Distributed Power Systems
■
Battery-Powered Systems
The LT3434 is available in a 16-pin TSSOP package with
Exposed Pad leadframe for low thermal resistance.
, LTC and LT are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Burst Mode is a registered
trademark of Linear Technology Corporation. *Protected by U.S. Patents including
6498466. **See Burst Mode Operation section for conditions.
U
TYPICAL APPLICATIO
Efficiency and Power Loss
vs Load Current
Supply Current vs
Input Voltage
14V to 3.3V Step-Down Converter with
150
125
100
75
100µA No Load Quiescent Current
100
75
50
25
0
10
V
= 3.3V
V
IN
= 12V
OUT
V
OUT
= 5V
V
3.3V
2A
OUT
EFFICIENCY
V
IN
V
BOOST
SW
IN
1
4.7µF
100V
CER
33µH
0.68µF
4148
SHDN
V
OUT
= 3.3V
0.1µF
LT3434
30MQ100
C
SS
0.1
0.01
0.001
V
C
C
470pF
V
BIAS
4700pF
10k
TYPICAL POWER
LOSS
165k
1%
50
27pF
FB
100µF
6.3V
TANT
T
PGFB
PG
1µF
SYNC
GND
25
100k
1%
0
3434 TA01
0
10
30
40
50
60
20
0.0001 0.001
0.1
0.01
LOAD CURRENT (A)
1
10
INPUT VOLTAGE (V)
3434 TA02a
3434 TA02b
3434fb
1
LT3434
W W
U W
U
W
U
ABSOLUTE AXI U RATI GS
(Note 1)
PACKAGE/ORDER I FOR ATIO
TOP VIEW
VIN, SHDN, BIAS, PGOOD, SW ............................... 60V
BOOST Pin Above SW ............................................ 35V
BOOST Pin Voltage ................................................. 68V
SYNC, CSS, PGFB, FB................................................ 6V
Operating JunctionTemperature Range
LT3434EFE (Note 2) ........................ –40°C to 125°C
LT3434IFE (Note 2) ......................... –40°C to 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PGOOD
SHDN
SYNC
PGFB
FB
SW
LT3434EFE
LT3434IFE
V
IN
V
IN
17
SW
BOOST
V
C
FE PART
MARKING
C
T
BIAS
GND
C
SS
FE PACKAGE
16-LEAD PLASTIC TSSOP
3434EFE
3434IFE
TJMAX = 125°C, θJA = 45°C/W, θJC(PAD) = 10°C/W
EXPOSED PAD IS GND (PIN 17)
MUST BE SOLDERED TO GND (PIN 8)
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = 12V, SHDN = 12V, BIAS = 5V, FB/PGFB = 1.25V,
J
IN
C
/SYNC = 0V unless otherwise noted.
SS
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
1.3
5
MAX
1.45
20
UNITS
V
V
SHDN Threshold
1.15
SHDN
I
SHDN Input Current
SHDN = 12V
●
●
µA
V
SHDN
Minimum Input Voltage (Note 3)
Supply Shutdown Current
Supply Sleep Current (Note 4)
2.4
0.1
3
I
SHDN = 0V, BOOST = 0V, FB/PGFB = 0V
2
µA
VINS
VIN
BIAS = 0V, FB = 1.35V
FB = 1.35V
●
●
170
45
250
75
µA
µA
I
Supply Quiescent Current
BIAS = 0V, FB = 1.15V
BIAS = 5V, FB = 1.15V
3.2
2.6
6
5
mA
mA
Minimum BIAS Voltage (Note 5)
BIAS Sleep Current (Note 4)
BIAS Quiescent Current
FB = 1.15V
●
●
2.7
110
700
1.8
65
3.1
180
900
V
µA
I
I
BIASS
BIAS
SYNC = 3.3V
µA
Minimum Boost Voltage (Note 6)
Input Boost Current (Note 7)
I
I
= 3A
= 3A
V
SW
SW
85
mA
V
V
Reference Voltage (V
)
3.3V < V < 60V
●
1.225
1.25
75
1.275
200
REF
REF
VIN
I
FB Input Bias Current
nA
FB
EA Voltage Gain (Note 8)
900
650
40
V/V
µMho
µA
EA Voltage g
dI(V )= ±10µA
400
20
900
55
C
m
EA Source Current
EA Sink Current
FB = 1.15V
FB = 1.35V
15
30
40
µA
V to SW g
6
A/V
C
m
3434fb
2
LT3434
ELECTRICAL CHARACTERISTICS
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = 12V, SHDN = 12V, BIAS = 5V, FB/PGFB = 1.25V,
J
IN
C /SYNC = 0V unless otherwise noted.
SS
SYMBOL PARAMETER
CONDITIONS
MIN
2.1
3
TYP
2.2
4.7
0.1
200
92
MAX
2.4
UNITS
V
V High Clamp
C
FB = 1.15V
I
SW Current Limit
●
●
●
6.5
A
PK
Switch On Resistance (Note 9)
Switching Frequency
0.25
230
Ω
180
90
kHz
%
Maximum Duty Cycle
Minimum SYNC Amplitude
SYNC Frequency Range
SYNC Input Impedance
1.5
500
45
2.0
V
230
7
kHz
kΩ
µA
nA
%
I
I
C
Current Threshold (Note 10)
SS
FB = 0V
13
20
100
92
CSS
PGFB Input Current
25
PGFB
V
PGFB Voltage Threshold (Note 11)
●
88
2
90
PGFB
I
C Source Current (Note 11)
T
3.6
2
5.5
µA
mA
V
CT
C Sink Current (Note 11)
T
1
V
C Voltage Threshold (Note 11)
T
1.16
1.2
0.1
200
1.26
1
CT
PG Leakage (Note 11)
µA
µA
PG Sink Current (Note 11)
PGFB = 1V, PG = 400mV
120
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 5: Minimum BIAS voltage is the voltage on the BIAS pin when I
sourced into the pin.
Note 6: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.
is
BIAS
Note 2: The LT3434EFE is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3434IFE is guaranteed and tested over the full –40°C to 125°C
operating junction temperature range.
Note 3: Minimum input voltage is defined as the voltage where switching
starts. Actual minimum input voltage to maintain a regulated output will
depend upon output voltage and load current. See Applications
Information.
Note 7: Boost current is the current flowing into the BOOST pin with the
pin held 3.3V above input voltage. It flows only during switch on time.
Note 8: Gain is measured with a V swing from 1.15V to 750mV.
C
Note 9: Switch on resistance is calculated by dividing V to SW voltage by
IN
the forced current (3A). See Typical Performance Characteristics for the
graph of switch voltage at other currents.
Note 10: The C threshold is defined as the value of current sourced into
SS
the C pin which results in an increase in sink current from the V pin.
SS
C
See the Soft-Start section in Applications Information.
Note 11: The PGFB threshold is defined as the percentage of V voltage
REF
Note 4: Supply input current is the quiescent current drawn by the input
pin. Its typical value depends on the voltage on the BIAS pin and operating
state of the LT3434. With the BIAS pin at 0V, all of the quiescent current
which causes the current source output of the C pin to change from
T
sinking (below threshold) to sourcing current (above threshold). When
sourcing current, the voltage on the C pin rises until it is clamped
T
required to operate the LT3434 will be provided by the V pin. With the
IN
internally. When the clamp is activated, the output of the PG pin will be set
BIAS voltage above its minimum input voltage, a portion of the total
quiescent current will be supplied by the BIAS pin. Supply sleep current is
defined as the quiescent current during the “sleep” portion of Burst Mode
operation. See Applications Information for determining application supply
currents.
to a high impedance state. When the C clamp is inactive the PG pin will
T
be set active low with a current sink capability of 200µA.
3434fb
3
LT3434
U W
TYPICAL PERFOR A CE CHARACTERISTICS
FB Voltage
Oscillator Frequency
SHDN Threshold
1.30
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.20
250
240
230
220
210
200
190
180
170
160
150
1.40
1.35
1.30
1.25
1.20
0.15
1.10
1.05
1.00
–50 –25
0
50
75 100 125
–50
0
25
50
75 100 125
25
–25
–50
0
25
50
75 100 125
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3434 G01
3434 G02
3434 G03
Shutdown Supply Current
Sleep Mode Supply Current
SHDN Pin Current
25
20
15
10
5
200
180
160
140
120
100
80
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0
T
= 25°C
J
V
= 0V
BIAS
V
= 60V
IN
V
= 5V
BIAS
25
60
40
V
IN
= 42V
V
IN
= 12V
20
0
0
–50
–50 –25
50
75 100 125
50
125
0
10
30
SHDN VOLTAGE (V)
40
50
60
0
25
0
75
100
20
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
3434 G05
3434 G06
3434 G04
PGFB Threshold
Bias Sleep Current
PG Sink Current
200
180
160
140
120
100
80
1.20
1.18
1.16
1.14
1.12
1.10
1.08
1.06
1.04
1.02
1.00
250
200
150
100
50
60
40
20
0
0
–50
–25
0
25
50
75 100 125
–50
0
25
50
75 100 125
–25
–50
0
25
50
75 100 125
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3434 G07
3434 G08
3434 G09
3434fb
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LT3434
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Soft-Start Threshold
vs FB Voltage
Oscillator Frequency
vs FB Voltage
Switch Peak Current Limit
6.0
5.5
5.0
4.5
4.0
3.5
3.0
50
45
40
35
30
25
20
15
10
5
250
200
150
100
50
T
= 25°C
T
= 25°C
J
J
SOFT-START
DEFEATED
0
0
–50 –25 –0
25
50
75 100 125
0
0.2
0.6
0.8
1.0
1.2
0
0.2
0.6
0.8
1.0
1.2
0.4
0.4
TEMPERATURE (°C)
FB VOLTAGE (V)
FB VOLTAGE (V)
3434 G10
3434 G11
3434 G12
Switch On Voltage (V
)
Supply Current vs Input Voltage
Minimum Input Voltage
CESAT
500
450
400
350
300
250
200
150
100
50
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
150
125
100
75
V
= 3.3V
OUT
V
= 5V
OUT
T = 125°C
J
RUNNING
START-UP
T = 25°C
J
V
= 3.3V
OUT
T = –40°C
50
J
START-UP
25
RUNNING
0
0
0
10
30
40
50
60
0.5
2.5
20
1.0
1.5
2.0
3.0
0
0.5
1.0
1.5
3.0
2.0
2.5
INPUT VOLTAGE (V)
LOAD CURRENT (A)
LOAD CURRENT (A)
3434 G20
3434 G13
3434 G19
Burst Mode Threshold vs Input
Voltage
Minimum On Time for Continuous
Mode Operation
Boost Current vs Load Current
60
50
40
30
20
10
0
900
800
700
600
500
400
300
200
100
0
700
650
600
550
500
450
400
350
300
250
200
V
= 3.3V
OUT
L = 33µH
C
= 100µF
OUT
LOAD CURRENT = 0.5A
BURST MODE EXIT
(INCREASING LOAD)
LOAD CURRENT = 1A
LOAD CURRENT = 2A
BURST MODE ENTER
(DECREASING LOAD)
0
1.0
1.5
2.0
2.5
3.0
0.5
5
15
20
–50 –25 –0
25
50
75 100 125
10
SWITCH CURRENT (A)
TEMPERATURE (°C)
INPUT VOLTAGE (V)
3434 G23
3434 G21
3434 G22
3434fb
5
LT3434
U W
TYPICAL PERFOR A CE CHARACTERISTICS
3.3V Dropout Operation
5V Dropout Operation
Burst Mode Operation
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
6
5
4
3
V
= 3.3V
V
= 5V
OUT
OUT
BOOST DIODE = DIODES INC B1100
BOOST DIODE = DIODES INC B1100
VOUT
50mV/DIV
LOAD CURRENT
0.25A
LOAD CURRENT
0.25A
LOAD CURRENT
2.5A
LOAD CURRENT
2.5A
IOUT
500mA/DIV
2
1
0
VIN = 12V
VOUT = 3.3V
5ms/DIV
3434 G14
IQ = 100µA
4
6
0
1
2
3
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
3434 G25
3434 G24
Burst Mode Operation
No Load 2A Step Response
Step Response
VOUT
50mV/DIV
VOUT
50mV/DIV
VOUT
50mV/DIV
IOUT
1A/DIV
IOUT
500mA/DIV
IOUT
1A/DIV
VIN = 12V
500µs/DIV
3434 G18
VIN = 12V
VOUT = 3.3V
IQ = 100µA
5µs/DIV
3434 G15
V
IN = 12V
500µs/DIV
3434 G17
VOUT = 3.3V
VOUT = 3.3V
COUT = 100µF
ILOAD(DC) = 500mA
COUT = 100µF
U
U
U
PI FU CTIO S
NC (Pin 1): No Connection.
inductanceonthispathwillcreateavoltagespikeatswitch
off, adding to the VCE voltage across the internal NPN.
SW (Pins 2, 5): The SW pin is the emitter of the on-chip
power NPN switch. This pin is driven up to the input pin
voltage during switch on time. Inductor current drives the
SW pin negative during switch off time. Negative voltage
is clamped with the external catch diode. Maximum nega-
tive switch voltage allowed is –0.8V.
BOOST (Pin 6): The BOOST pin is used to provide a drive
voltage, higher than the input voltage, to the internal
bipolarNPNpowerswitch. Withoutthisaddedvoltage, the
typical switch voltage loss would be about 1.5V. The
additional BOOST voltage allows the switch to saturate
and its voltage loss approximates that of a 0.1Ω FET
structure.
VIN (Pins 3, 4): This is the collector of the on-chip power
NPNswitch.VIN powerstheinternalcontrolcircuitrywhen
a voltage on the BIAS pin is not present. High dI/dt edges
occur on this pin during switch turn on and off. Keep the
path short from the VIN pin through the input bypass
capacitor, through the catch diode back to SW. All trace
CT (Pin7):AcapacitorontheCT pindeterminestheamount
of delay time between the PGFB pin exceeding its thresh-
old (VPGFB) and the PG pin set to a high impedance state.
When the PGFB pin rises above VPGFB, current is sourced
3434fb
6
LT3434
U
U
U
PI FU CTIO S
serve as a current clamp or control loop override. VC sits
at about 0.65V for light loads and 2.2V at maximum load.
During the sleep portion of Burst Mode operation, the VC
pin is held at a voltage slightly below the burst threshold
for better transient response. Driving the VC pin to ground
will disable switching and place the IC into sleep mode.
from the CT pin into the external capacitor. When the volt-
age on the external capacitor reaches an internal clamp
(VCT), the PG pin becomes a high impedance node. The
resultant PG delay time is given by t = CCT • VCT/ICT. If the
voltage on the PGFB pin drops below VPGFB, CCT will be
discharged rapidly to 0V and PG will be active low with a
200µAsinkcapability.IftheCT pinisclamped(PowerGood
condition)duringnormaloperationandSHDNistakenlow,
the CT pin will be discharged and a delay period will occur
when SHDN is returned high. See the Power Good section
in Applications Information for details.
FB (Pin 12): The feedback pin is used to determine the
output voltage using an external voltage divider from the
outputthatgenerates1.25VattheFBpin. WhentheFBpin
drops below 0.9V, switching frequency is reduced, the
SYNC function is disabled and output ramp rate control is
enabled via the CSS pin. See the Feedback section in
Applications Information for details.
GND (Pins 8, 17): The GND pin connection acts as the
reference for the regulated output, so load regulation will
suffer if the “ground” end of the load is not at the same
voltage as the GND pin of the IC. This condition will occur
when load current or other currents flow through metal
paths between the GND pin and the load ground. Keep the
path between the GND pin and the load ground short and
use a ground plane when possible. The GND pin also acts
as a heat sink and should be soldered (along with the
exposed leadframe) to the copper ground plane to reduce
thermal resistance (see Applications Information).
PGFB (PIN 13): The PGFB pin is the positive input to a
comparator whose negative input is set at VPGFB. When
PGFB is taken above VPGFB, current (ICSS) is sourced into
the CT pin starting the PG delay period. When the voltage
on the PGFB pin drops below VPGFB, the CT pin is rapidly
discharged resetting the PG delay period. The PGFB volt-
age is typically generated by a resistive divider from the
regulated output or input supply. See Power Good section
in Applications Information for details.
CSS (Pin 9): A capacitor from the CSS pin to the regulated
output voltage determines the output voltage ramp rate
during start-up. When the current through the CSS capaci-
tor exceeds the CSS threshold (ICSS), the voltage ramp of
the output is limited. The CSS threshold is proportional to
the FB voltage (see Typical Performance Characteristics)
and is defeated for FB voltage greater than 0.9V (typical).
See Soft-Start section in Applications Information for
details.
SYNC (Pin 14): The SYNC pin is used to synchronize the
internal oscillator to an external signal. It is directly logic
compatible and can be driven with any signal between
30% and 70% duty cycle. The synchronizing range is
equaltomaximuminitialoperatingfrequencyupto700kHz.
When the voltage on the FB pin is below 0.9V the SYNC
function is disabled. See the Synchronizing section in
Applications Information for details.
SHDN (Pin 15): The SHDN pin is used to turn off the
regulator and to reduce input current to less than 1µA. The
SHDN pin requires a voltage above 1.3V with a typical
source current of 5µA to take the IC out of the shutdown
state.
BIAS (Pin 10): The BIAS pin is used to improve efficiency
when operating at higher input voltages and light load
current. Connecting this pin to the regulated output volt-
age forces most of the internal circuitry to draw its
operating current from the output voltage rather than the
input supply. This architecture increases efficiency espe-
cially when the input voltage is much higher than the
output. Minimum output voltage setting for this mode of
operation is 3V.
PG (Pin 16): The PG pin is functional only when the SHDN
pin is above its threshold, and is active low when the
internal clamp on the CT pin is below its clamp level and
high impedance when the clamp is active. The PG pin has
a typical sink capability of 200µA. See the Power Good
section in Applications Information for details.
VC (Pin 11): The VC pin is the output of the error amplifier
and the input of the peak switch current comparator. It is
normally used for frequency compensation, but can also
3434fb
7
LT3434
W
BLOCK DIAGRA
V
IN
3
4
V
IN
INTERNAL REF
SLOPE
COMP
2.4V
UNDERVOLTAGE
LOCKOUT
Σ
+
–
BIAS
THERMAL
SHUTDOWN
200kHz
10
CURRENT
COMP
OSCILLATOR
SYNC
SHDN
14
15
BOOST
6
ANTISLOPE
COMP
+
–
R
SHDN
COMP
SWITCH
LATCH
DRIVER
CIRCUITRY
Q
S
SW
SW
2
5
1.3V
BURST MODE
DETECT
C
SS
SOFT-START
9
V
C
CLAMP
FOLDBACK
DETECT
FB
12
–
ERROR
AMP
+
1.25V
V
C
11
13
PG
16
PGFB
+
PG
COMP
1.2V C
T
CLAMP
1.12V
–
GND 17
PGND
C
8
T
7
3434 BD
Figure 1. LT3434 Block Diagram
The LT3434 is a constant frequency, current mode buck
converter.Thismeansthatthereisaninternalclockandtwo
feedback loops that control the duty cycle of the power
switch. In addition to the normal error amplifier, there is a
current sense amplifier that monitors switch current on a
cycle-by-cycle basis. A switch cycle starts with an oscilla-
torpulsewhichsetstheRSlatchtoturntheswitchon.When
switch current reaches a level set by the current compara-
tor the latch is reset and the switch turns off. Output volt-
age control is obtained by using the output of the error
amplifiertosettheswitchcurrenttrippoint.Thistechnique
means that the error amplifier commands current to be
delivered to the output rather than voltage. A voltage fed
system will have low phase shift up to the resonant fre-
quencyoftheinductorandoutputcapacitor,thenanabrupt
180° shift will occur. The current fed system will have 90°
phaseshiftatamuchlowerfrequency,butwillnothavethe
additional 90° shift until well beyond the LC resonant fre-
quency. This makes it much easier to frequency compen-
sate the feedback loop and also gives much quicker tran-
sient response.
Most of the circuitry of the LT3434 operates from an
internal 2.4V bias line. The bias regulator normally draws
3434fb
8
LT3434
W
BLOCK DIAGRA
power from the VIN pin, but if the BIAS pin is connected to
an external voltage higher than 3V bias power will be
drawn from the external source (typically the regulated
output voltage). This improves efficiency.
To further optimize efficiency, the LT3434 automatically
switches to Burst Mode operation in light load situations.
In Burst Mode operation, all circuitry associated with
controlling the output switch is shut down reducing the
input supply current to 45µA.
High switch efficiency is attained by using the BOOST pin
to provide a voltage to the switch driver which is higher
than the input voltage, allowing switch to be saturated.
This boosted voltage is generated with an external capaci-
tor and diode.
The LT3434 contains a power good flag with a program-
mable threshold and delay time. A logic-level low on the
SHDN pin disables the IC and reduces input suppy current
to less than 1µA.
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APPLICATIO S I FOR ATIO
FEEDBACK PIN FUNCTIONS
Table 1
OUTPUT
VOLTAGE
(V)
R1
NEAREST (1%)
(kΩ)
OUTPUT
ERROR
(%)
The feedback (FB) pin on the LT3434 is used to set output
voltage and provide several overload protection features.
The first part of this section deals with selecting resistors
to set output voltage and the remaining part talks about
frequency foldback and soft-start features. Please read
both parts before committing to a final design.
R2
(kΩ, 1%)
2.5
3
100
100
100
100
100
100
100
100
100
140
165
300
383
536
698
866
0
0
3.3
5
0.38
0
Referring to Figure 2, the output voltage is determined by
a voltage divider from VOUT to ground which generates
1.25VattheFBpin.Sincetheoutputdividerisaloadonthe
output care must be taken when choosing the resistor
divider values. For light load applications the resistor
values should be as large as possible to achieve peak
efficiencyinBurstModeoperation. Extremelylargevalues
forresistorR1willcauseanoutputvoltageerrorduetothe
50nA FB pin input current. The suggested value for the
output divider resistor (see Figure 2) from FB to ground
(R2) is 100k or less. A formula for R1 is shown below. A
table of standard 1% values is shown in Table 1 for
common output voltages.
6
0.63
–0.63
–0.25
0.63
8
10
12
V
OUT
LT3434
SW
2
9
C1
C
SS
SOFT-START
200kHz
OSCILLATOR
FOLDBACK
DETECT
R1
R2
FB
VOUT – 1.25
R1= R2 •
12
11
–
+
ERROR
AMP
1.25 + R2 • 50nA
1.25V
More Than Just Voltage Feedback
V
C
The FB pin is used for more than just output voltage
sensing. It also reduces switching frequency and con-
trolsthesoft-startvoltagerampratewhenoutputvoltage
is below the regulated level (see the Frequency Foldback
3434 F02
Figure 2. Feedback Network
3434fb
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APPLICATIO S I FOR ATIO
and Soft-Start Current graphs in Typical Performance
Characteristics).
INPUT CAPACITOR
Step-down regulators draw current from the input supply
in pulses. The rise and fall times of these pulses are very
fast. The input capacitor is required to reduce the voltage
ripple this causes at the input of LT3434 and force the
switching current into a tight local loop, thereby minimiz-
ing EMI. The RMS ripple current can be calculated from:
Frequencyfoldbackisdonetocontrolpowerdissipationin
both the IC and in the external diode and inductor during
short-circuit conditions. A shorted output requires the
switching regulator to operate at very low duty cycles. As
a result the average current through the diode and induc-
tor is equal to the short-circuit current limit of the switch
(typically 4.7A for the LT3434). Minimum switch on time
limitations would prevent the switcher from attaining a
sufficiently low duty cycle if switching frequency were
maintained at 200kHz, so frequency is reduced by about
4:1 when the FB pin voltage drops below 0.4V (see
Frequency Foldback graph). In addition, if the current in
the switch exceeds 1.5 times the current limitations speci-
fied by the VC pin, due to minimum switch on time, the
LT3434 will skip the next switch cycle. As the feedback
voltagerises,theswitchingfrequencyincreasesto200kHz
with 0.95V on the FB pin. During frequency foldback,
external syncronization is disabled to prevent interference
with foldback operation. Frequency foldback does not
affect operation during normal load conditions.
IOUT
V
IN
IRIPPLE(RMS)
=
VOUT V – V
IN OUT
(
)
Ceramiccapacitorsareidealforinputbypassing.At200kHz
switching frequency input capacitor values in the range of
4.7µF to 20µF are suitable for most applications. If opera-
tionisrequiredclosetotheminimuminputrequiredbythe
LT3434 a larger value may be required. This is to prevent
excessive ripple causing dips below the minimum operat-
ing voltage resulting in erratic operation.
Input voltage transients caused by input voltage steps or
by hot plugging the LT3434 to a pre-powered source such
as a wall adapter can exceed maximum VIN ratings. The
sudden application of input voltage will cause a large
surge of current in the input leads that will store energy in
the parasitic inductance of the leads. This energy will
causetheinputvoltagetoswingabovetheDClevelofinput
power source and it may exceed the maximum voltage
rating of the input capacitor and LT3434. All input voltage
transient sequences should be observed at the VIN pin of
the LT3434 to ensure that absolute maximum voltage
ratings are not violated.
In addition to lowering switching frequency the soft-start
ramp rate is also affected by the feedback voltage. Large
capacitive loads or high input voltages can cause a high
input current surge during start-up. The soft-start func-
tion reduces input current surge by regulating switch
current via the VC pin to maintain a constant voltage ramp
rate(dV/dt)attheoutput. Acapacitor(C1inFigure2)from
the CSS pin to the output determines the maximum output
dV/dt. Whenthefeedbackvoltageisbelow0.4V, theVC pin
will rise, resulting in an increase in switch current and
outputvoltage.IfthedV/dtoftheoutputcausesthecurrent
through the CSS capacitor to exceed ICSS the VC voltage is
reduced resulting in a constant dV/dt at the output. As the
feedback voltage increases ICSS increases, resulting in an
increased dV/dt until the soft-start function is defeated
with 0.9V present at the FB pin. The soft-start function
does not affect operation during normal load conditions.
However, if a momentary short (brown out condition) is
present at the output which causes the FB voltage to drop
below 0.9V, the soft-start circuitry will become active.
The easiest way to suppress input voltage transients is to
addasmallaluminumelectrolyticcapacitorinparallelwith
the low ESR input capacitor. The selected capacitor needs
to have the right amount of ESR to critically damp the
resonant circuit formed by the input lead inductance and
theinputcapacitor. ThetypicalvaluesofESRwillfallinthe
range of 0.5Ω to 2Ω and capacitance will fall in the range
of 5µF to 50µF.
If tantalum capacitors are used, values in the 22µF to
470µF range are generally needed to minimize ESR and
meet ripple current and surge ratings. Care should be
3434fb
10
LT3434
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APPLICATIO S I FOR ATIO
U
taken to ensure the ripple and surge ratings are not
exceeded. The AVX TPS and Kemet T495 series are surge
rated AVX recommends derating capacitor operating volt-
age by 2:1 for high surge applications.
Unlike the input capacitor RMS, ripple current in the
output capacitor is normally low enough that ripple cur-
rent rating is not an issue. The current waveform is
triangular with a typical value of 200mARMS. The formula
to calculate this is:
OUTPUT CAPACITOR
Output capacitor ripple current (RMS)
The output capacitor is normally chosen by its effective
series resistance (ESR) because this is what determines
output ripple voltage. To get low ESR takes volume, so
physically smaller capacitors have higher ESR. The ESR
range for typical LT3434 applications is 0.05Ω to 0.2Ω. A
typical output capacitor is an AVX type TPS, 100µF at 10V,
with a guaranteed ESR less than 0.1Ω. This is a “D” size
surface mount solid tantalum capacitor. TPS capacitors
are specially constructed and tested for low ESR, so they
give the lowest ESR for a given volume. The value in
microfarads is not particularly critical and values from
22µF to greater than 500µF work well, but you cannot
cheat Mother Nature on ESR. If you find a tiny 22µF solid
tantalum capacitor, it will have high ESR and output ripple
voltage could be unacceptable. Table 2 shows some
typical solid tantalum surface mount capacitors.
0.29 V
OUT)(
V – V
IN OUT
(
)
=
IP-P
12
IRIPPLE(RMS)
=
L f V
( )( )(
)
IN
CERAMIC CAPACITORS
Higher value, lower cost ceramic capacitors are now
becoming available. They are generally chosen for their
good high frequency operation, small size and very low
ESR(effectiveseriesresistance).LowESRreducesoutput
ripple voltage but also removes a useful zero in the loop
frequency response, common to tantalum capacitors. To
compensate for this a resistor RC can be placed in series
with the VC compensation capacitor CC (Figure 10). Care
must be taken however since this resistor sets the high
frequency gain of the error amplifier including the gain at
the switching frequency. If the gain of the error amplifier
is high enough at the switching frequency output ripple
voltage (although smaller for a ceramic output capacitor)
may still affect the proper operation of the regulator. A
filter capacitor CF in parallel with the RC/CC network, along
with a small feedforward capacitor CFB, is suggested to
control possible ripple at the VC pin. The LT3434 can be
stabilized using a 100µF ceramic output capacitor and VC
component values of CC = 4700pF, RC = 10k, CF = 470pF
and CFB = 27pF.
Table 2. Surface Mount Solid Tantalum Capacitor ESR
and Ripple Current
E CASE SIZE
AVX TPS
ESR MAX (Ω)
RIPPLE CURRENT (A)
0.1 to 0.3
0.7 to 1.1
D CASE SIZE
AVX TPS
0.1 to 0.3
0.2
0.7 to 1.1
0.5
C CASE SIZE
AVX TPS
Many engineers have heard that solid tantalum capacitors
are prone to failure if they undergo high surge currents.
This is historically true and type TPS capacitors are
specially tested for surge capability but surge ruggedness
is not a critical issue with the output capacitor. Solid
tantalum capacitors fail during very high turn-on surges
which do not occur at the output of regulators. High
discharge surges, such as when the regulator output is
dead shorted, do not harm the capacitors.
OUTPUT RIPPLE VOLTAGE
Figure 3 shows a typical output ripple voltage waveform
for the LT3434. Ripple voltage is determined by the
impedance of the output capacitor and ripple current
through the inductor. Peak-to-peak ripple current through
the inductor into the output capacitor is:
VOUT V – V
(
)
IN
OUT
IP-P
=
V
L f
IN
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11
LT3434
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APPLICATIO S I FOR ATIO
current mode converters, the LT3434 maximum switch
current limit does not fall off at high duty cycles. Most
current mode converters suffer a drop off of peak switch
current for duty cycles above 50%. This is due to the
effects of slope compensation required to prevent
subharmonic oscillations in current mode converters.
(For detailed analysis, see Application Note 19.)
VOUT
10mV/DIV
100µF
75mΩ TANTALUM
VOUT
10mV/DIV
100µF CERAMIC
ISW
The LT3434 is able to maintain peak switch current limit
over the full duty cycle range by using patented circuitry to
cancel the effects of slope compensation on peak switch
current without affecting the frequency compensation it
provides.
10V/DIV
ILOAD = 2A
1µs/DIV
3434 F03
Figure 3. LT3434 Ripple Voltage Waveform
For high frequency switchers the ripple current slew rate
is also relevant and can be calculated from:
Maximum load current would be equal to maximum
switch current for an infinitely large inductor, but with
finite inductor size, maximum load current is reduced by
one-half peak-to-peak inductor current. The following
formula assumes continuous mode operation, implying
di
dt
V
IN
L
=
Peak-to-peak output ripple voltage is the sum of a triwave
created by peak-to-peak ripple current times ESR and a
square wave created by parasitic inductance (ESL) and
ripple current slew rate. Capacitive reactance is assumed
to be small compared to ESR or ESL.
that the term on the right (IP-P/2) is less than IOUT
.
V
OUT)(
V – V
IN OUT
(
)
= IPK –
IP-P
2
IOUT(MAX) = IPK
–
2 L f V
( )( )(
)
IN
Discontinuous operation occurs when:
di
VRIPPLE = I
ESR + ESL
(
P-P)(
)
(
)
VOUT V – V
dt
(
)
IN
OUT
IOUT(DIS)
≤
2(L)(f)(V )
IN
Example: with VIN = 12V, VOUT = 3.3V, L = 33µH, ESR =
0.08Ω, ESL = 10nH:
For VOUT = 5V, VIN = 8V and L = 20µH:
3.3 12 – 3.3
(
)(
)
IP-P
di
=
= 0.362A
5 8 – 5
( )(
)
IOUT(MAX) = 3 –
12 33e − 6 200e3
( )(
)(
)
2 20e – 6 200e3 8
)( )( )
(
12
=
= 3.63e5
= 3 – 0.24 = 2.76A
dt 3.3e – 5
Note that there is less load current available at the higher
inputvoltagebecauseinductorripplecurrentincreases.At
VIN = 15V, duty cycle is 33% and for the same set of
conditions:
VRIPPLE = (0.362A)(0.08) + (10e – 9)(363e3)
= 0.0289 + 0.003 = 32mVP-P
MAXIMUM OUTPUT LOAD CURRENT
5 15 – 5
( )(
)
IOUT(MAX) = 3 –
Maximum load current for a buck converter is limited by
the maximum switch current rating (IPK). The minimum
peak current rating for the LT3434 is 3A. Unlike most
2 20e – 6 200e3 15
)( )( )
(
= 3 – 0.42 = 2.58A
3434fb
12
LT3434
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APPLICATIO S I FOR ATIO
To calculate actual peak switch current in continuous
mode with a given set of conditions, use:
U
Table 3. Inductor Selection Criteria
VENDOR/
PART NO.
VALUE
H)
I
DCR
HEIGHT
(mm)
DC
(
µ
(Amps)
(Ohms)
Sumida
VOUT V – VOUT
(
IN
)
ISW(PK) = IOUT
+
CDRH104R-150
CDRH104R-220
CDRH104R-330
CDRH124-220
CDRH124-330
CDRH127-330
CDRH127-470
CEI122-220
Coiltronics
15
22
33
22
33
33
47
22
3.6
2.9
2.3
2.9
2.7
3.0
2.5
2.3
0.050
0.073
0.093
0.066
0.097
0.065
0.100
0.085
4
4
2 L f V
( )( )( IN
)
4
If a small inductor is chosen which results in discontinous
mode operation over the entire load range, the maximum
load current is equal to:
4.5
4.5
8
IPK22 f L V
8
( )( )(
)
IN
IOUT(MAX)
=
3
2 V
OUT)(
V – V
IN OUT
(
)
UP3B-330
33
47
68
3
0.069
0.108
0.120
6.8
6.8
7.9
CHOOSING THE INDUCTOR
UP3B-470
2.4
4.3
UP4B-680
For most applications the output inductor will fall in the
range of 15µH to 100µH. Lower values are chosen to
reduce physical size of the inductor. Higher values allow
more output current because they reduce peak current
seenbytheLT3434switch,whichhasaminimum3Alimit.
Highervaluesalsoreduceoutputripplevoltageandreduce
core loss.
Coilcraft
DO3316P-153
DO5022p-683
15
68
3
0.046
0.130
5.2
7.1
3.5
must withstand continuous fault conditions. If maxi-
mumloadcurrentis1A, forinstance, a1Ainductormay
not survive a continuous 4A overload condition.
When choosing an inductor you might have to consider
maximum load current, core and copper losses, allow-
able component height, output voltage ripple, EMI, fault
current in the inductor, saturation and of course cost.
The following procedure is suggested as a way of han-
dling these somewhat complicated and conflicting
requirements.
For applications with a duty cycle above 50%, the
inductor value should be chosen to obtain an inductor
ripple current of less than 40% of the peak switch
current.
2. Calculate peak inductor current at full load current to
ensure that the inductor will not saturate. Peak current
canbesignificantlyhigherthanoutputcurrent,especially
with smaller inductors and lighter loads, so don’t omit
thisstep.Powderedironcoresareforgivingbecausethey
saturate softly, whereas ferrite cores saturate abruptly.
Other core materials fall somewhere in between. The
following formula assumes continuous mode of opera-
tion, but it errs only slightly on the high side for discon-
tinuous mode, so it can be used for all conditions.
1. Choose a value in microhenries such that the maximum
load current plus half of the inductor ripple current is
less than the minimum peak switch current (IPK).
Choosing a small inductor with lighter loads may result
in discontinuous mode of operation, but the LT3434 is
designed to work well in either mode.
Assume that the average inductor current is equal to
load current and decide whether or not the inductor
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Expressed mathematically the requirement to maintain
control is:
VOUT V – V
(
)
IN
OUT
IPEAK = IOUT
+
2 f L V
( )( )(
)
IN
V
+ I•R
F
f • tON
≤
VIN = maximum input voltage
V
IN
f = switching frequency, 200kHz
where:
f = switching frequency
ON = switch on time
3. Decide if the design can tolerate an “open” core geom-
etry like a rod or barrel, which have high magnetic field
radiation, or whether it needs a closed core like a toroid
to prevent EMI problems. This is a tough decision
because the rods or barrels are temptingly cheap and
small and there are no helpful guidelines to calculate
when the magnetic field radiation will be a problem.
t
VF = diode forward voltage
VIN = Input voltage
I • R = inductor I • R voltage drop
If this condition is not observed, the current will not be
limited at IPK but will cycle-by-cycle ratchet up to some
higher value. Using the nominal LT3434 clock frequency
of 200kHz, a VIN of 40V and a (VF + I • R) of say 0.7V, the
maximum tON to maintain control would be approximately
90ns, an unacceptably short time.
4. After making an initial choice, consider the secondary
things like output voltage ripple, second sourcing, etc.
Use the experts in the Linear Technology’s applications
department if you feel uncertain about the final choice.
They have experience with a wide range of inductor
types and can tell you about the latest developments in
low profile, surface mounting, etc.
The solution to this dilemma is to slow down the oscillator
to allow the current in the inductor to drop to a sufficiently
low value such that the current doesn’t continue to ratchet
higher. When the FB pin voltage is abnormally low thereby
indicating some sort of short-circuit condition, the oscil-
lator frequency will be reduced. Oscillator frequency is
reduced by a factor of 4 when the FB pin voltage is below
0.4V and increases linearly to its typical value of 200kHz at
aFBvoltageof0.95V(seeTypicalPerformanceCharacter-
istics). In addition, if the current in the switch exceeds 1.5
• IPK current demanded by the VC pin, the LT3434 will skip
the next on cycle effectively reducing the oscillator fre-
quency by a factor of 2. These oscillator frequency reduc-
tions during short-circuit conditions allow the LT3434 to
maintain current control.
Short-Circuit Considerations
The LT3434 is a current mode controller. It uses the VC
node voltage as an input to a current comparator which
turns off the output switch on a cycle-by-cycle basis as
this peak current is reached. The internal clamp on the VC
node, nominally 2.2V, then acts as an output switch peak
current limit. This action becomes the switch current limit
specification. The maximum available output power is
then determined by the switch current limit.
A potential controllability problem could occur under
short-circuit conditions. If the power supply output is
short circuited, the feedback amplifier responds to the low
output voltage by raising the control voltage, VC, to its
peak current limit value. Ideally, the output switch would
be turned on, and then turned off as its current exceeded
thevalueindicatedbyVC.However,thereisfiniteresponse
time involved in both the current comparator and turn-off
of the output switch. These result in a typical minimum on
time of 250ns. When combined with the large ratio of VIN
to (VF + I • R), the diode forward voltage plus inductor I • R
voltage drop, the potential exists for a loss of control.
SOFT-START
For applications where [VIN/(VOUT + VF)] ratios > 10 or
large input surge currents can’t be tolerated, the LT3434
soft-start feature should be used to control the output
capacitor charge rate during start-up, or during recovery
from an output short circuit thereby adding additional
control over peak inductor current. The soft-start function
3434fb
14
LT3434
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U
limits the switch current via the VC pin to maintain a
constantvoltageramprate(dV/dt)attheoutputcapacitor.
A capacitor (C1 in Figure 2) from the CSS pin to the
regulated output voltage determines the output voltage
ramp rate. When the current through the CSS capacitor
exceeds the CSS threshold (ICSS), the voltage ramp of the
output capacitor is limited by reducing the VC pin voltage.
The CSS threshold is proportional to the FB voltage (see
Typical Performance Characteristics) and is defeated for
FB voltages greater than 0.9V (typical). The output dV/dt
can be approximated by:
averageinputcurrentisgreatlyreducedresultinginhigher
efficiency.
The minimum average input current depends on the VIN to
VOUT ratio, VC frequency compensation, feedback divider
network and Schottky diode leakage. It can be approxi-
mated by the following equation:
I
BIASS + IFB + IS
⎛ VOUT
⎞
⎠
(
)
I
IN(AVG) ≅ IVINS + ISHDN +
⎜
⎟
⎝ V
η
( )
IN
where
VINS = input pin current in sleep mode
I
dV ICSS
=
VOUT = output voltage
dt CSS
VIN = input voltage
but actual values will vary due to start-up load conditions,
compensation values and output capacitor selection.
IBIASS = BIAS pin current in sleep mode
IFB = feedback network current
IS = catch diode reverse leakage at VOUT
CCSS =1000pF
η = low current efficiency (non Burst Mode operation)
CCSS = 0.1µF
Example: For VOUT = 3.3V, VIN = 12V
VOUT
0.5V/DIV
CCSS = 0.01µF
125µA + 12.5µA + 0.5µA
3.3
12
(
)
⎛
⎜
⎝
⎞
⎟
⎠
I
= 45µA + 5µA +
IN(AVG)
0.85
(
)
= 45µA + 5µA + 44µA = 99µA
150
V
= 3.3V
OUT
VIN = 12V
1ms/DIV
3434 F04
VOUT = 3.3V
ILOAD = 500mA
125
100
75
50
25
0
Figure 4. V
dV/dt
OUT
Burst Mode OPERATION
To enhance efficiency at light loads, the LT3434 automati-
cally switches to Burst Mode operation which keeps the
output capacitor charged to the proper voltage while
minimizing the input quiescent current. During Burst
Mode operation, the LT3434 delivers short bursts of
current to the output capacitor followed by sleep periods
where the output power is delivered to the load by the
output capacitor. In addition, VIN and BIAS quiescent
currents are reduced to typically 45µA and 110µA respec-
tively during the sleep time. As the load current increases
towards a no load condition, the percentage of time that
the LT3434 operates in sleep mode increases and the
0
10
30
40
50
60
20
INPUT VOLTAGE (V)
3434 F05
Figure 5. I vs V
Q
IN
During the sleep portion of the Burst Mode cycle, the VC
pin voltage is held just below the level needed for normal
operation to improve transient response. See the Typical
Performance Characteristics section for burst and tran-
sient response waveforms.
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15
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Table 4. Catch Diode Selection Criteria
Ifanoloadconditioncanbeanticipated,thesupplycurrent
can be further reduced by cycling the SHDN pin at a rate
higher than the natural no load burst frequency. Figure 6
shows Burst Mode operation with the SHDN pin. VOUT
burstrippleismaintainedwhiletheaveragesupplycurrent
drops to 15µA. The PG pin will be active low during the
“on” portion of the SHDN waveform due to the CT capaci-
tor discharge when SHDN is taken low. See the Power
Good section for further information.
I at 125°C EFFICIENCY
Q
LEAKAGE
V
=12V
= 3.3 V = 3.3V
V
OUT
=12V
IN
IN
V
OUT
= 3.3V
V AT 1A
F
V
OUT
DIODE
25°C 125°C 25°C 125°C
I = 0A
L
I = 1A
L
IR 10BQ100 0.0µA 59µA 0.72V 0.58V
125µA
215µA
78.2%
82%
Diodes Inc. 0.1µA 242µA 0.48V 0.41V
B260SMA
Diodes Inc. 0.2µA 440µA 0.45V 0.36V
B360SMB
270µA
821µA
1088µA
82.8%
82.7%
80.3%
IR
1µA 1.81mA 0.42V 0.34V
MBRS360TR
VOUT
50mV/DIV
IR 30BQ100 1.7µA 2.64mA 0.40V 0.32V
lackofasignificantreverserecoverytime.Schottkydiodes
are generally available with reverse voltage ratings of 60V
and even 100V and are price competitive with other types.
VSHDN
2V/DIV
The effect of reverse leakage and forward drop on effi-
ciency for various Schottky diodes is shown in Table 4. As
can be seen these are conflicting parameters and the user
mustweightheimportanceofeachspecificationinchoos-
ing the best diode for the application.
ISW
500mA/DIV
V
IN = 12V
TIME (50ms/DIV)
3434 G16
VOUT = 3.3V
IQ = 15µA
Figure 6. Burst Mode with Shutdown Pin
The use of so-called “ultrafast” recovery diodes is gener-
ally not recommended. When operating in continuous
mode, the reverse recovery time exhibited by “ultrafast”
diodes will result in a slingshot type effect. The power
internalswitchwillrampupVIN currentintothediodeinan
attempt to get it to recover. Then, when the diode has
finallyturnedoff,sometensofnanosecondslater,theVSW
node voltage ramps up at an extremely high dV/dt, per-
haps 5V to even 10V/ns! With real world lead inductances
the VSW node can easily overshoot the VIN rail. This can
result in poor RFI behavior and, if the overshoot is severe
enough, damage the IC itself.
CATCH DIODE
The catch diode carries load current during the SW off
time. The average diode current is therefore dependent on
theswitchdutycycle. Athighinputtooutputvoltageratios
the diode conducts most of the time. As the ratio ap-
proaches unity the diode conducts only a small fraction of
the time. The most stressful condition for the diode is
whentheoutputisshortcircuited.Underthisconditionthe
diode must safely handle IPEAK at maximum duty cycle.
To maximize high and low load current efficiency a fast
switching diode with low forward drop and low reverse
leakage should be used. Low reverse leakage is critical to
maximize low current efficiency since its value over tem-
perature can potentially exceed the magnitude of the
LT3434 supply current. Low forward drop is critical for
high current efficiency since the loss is proportional to
forward drop.
BOOST PIN
For most applications the boost components are a 0.68µF
capacitor and a MMSD914 diode. The anode is typically
connected to the regulated output voltage to generate a
voltage approximately VOUT above VIN to drive the output
stage (Figure 7a). However, the output stage discharges
the boost capacitor during the on time of the switch. The
output driver requires at least 2.5V of headroom through-
out this period to keep the switch fully saturated. If the
3434fb
These requirements result in the use of a Schottky type
diode. DC switching losses are minimized due to its low
forward voltage drop and AC behavior is benign due to its
16
LT3434
W U U
APPLICATIO S I FOR ATIO
U
A 0.68µF boost capacitor is recommended for most appli-
cations. Almost any type of film or ceramic capacitor is
suitablebuttheESRshouldbe<1Ωtoensureitcanbefully
recharged during the off time of the switch. The capacitor
value is derived from worst-case conditions of 4700ns on
time, 65mA boost current and 0.7V discharge ripple. The
boost capacitor value could be reduced under less de-
mandingconditionsbutthiswillnotimprovecircuitopera-
tion or efficiency. Under low input voltage and low load
conditions a higher value capacitor will reduce discharge
ripple and improve start-up operation.
output voltage is less than 3.3V it is recommended that an
alternate boost supply is used. The boost diode can be
connected to the input (Figure 7b) but care must be taken
to prevent the boost voltage (VBOOST = VIN • 2) from
exceeding the BOOST pin absolute maximum rating. The
additional voltage across the switch driver also increases
power loss and reduces efficiency. If available, an inde-
pendent supply can be used to generate the required
BOOST voltage (Figure 7c). Tying BOOST to VIN or an
independent supply may reduce efficiency but it will re-
duce the minimum VIN required to start-up with light
loads. If the generated BOOST voltage dissipates too
much power at maximum load, the BOOST voltage the
LT3434 sees can be reduced by placing a Zener diode in
series with the BOOST diode (Figure 7a option).
SHUTDOWN FUNCTION AND UNDERVOLTAGE
LOCKOUT
The SHDN pin on the LT3434 controls the operation of the
IC. When the voltage on the SHDN pin is below the 1.2V
shutdown threshold the LT3434 is placed in a “zero”
supply current state. Driving the SHDN pin above the
shutdown threshold enables normal operation. The SHDN
pin has an internal sink current of 3µA.
OPTIONAL
V
V
BOOST
SW
V
OUT
IN
IN
LT3434
GND
In addition to the shutdown feature, the LT3434 has an
undervoltage lockout function. When the input voltage is
below 2.4V, switching will be disabled. The undervoltage
lockout threshold doesn’t have any hysteresis and is
mainly used to insure that all internal voltages are at the
correct level before switching is enabled. If an undervolt-
age lockout function with hysteresis is needed to limit
input current at low VIN to VOUT ratios refer to Figure 8 and
the following:
V
– V = V
SW OUT
BOOST
V
= V + V
IN OUT
BOOST(MAX)
(7a)
V
V
BOOST
SW
IN
IN
LT3434
V
GND
OUT
V
V
– V = V
SW
BOOST
IN
V
⎛
SHDN
⎝ R3
VSHDN
R2
⎞
⎠
= 2V
BOOST(MAX)
IN
VUVLO = R1
+
+ ISHDN + V
⎟
SHDN
⎜
(7b)
VOUT R1
( )
V
V
BOOST
V
V
IN
IN
DC
VHYST
=
R3
LT3434
GND
SW
OUT
D
SS
R1shouldbechosentominimizequiescentcurrentduring
normal operation by the following equation:
3434 F07
V
– V = V
SW DC
BOOST
V
= V + V
DC IN
BOOST(MAX)
V – 2V
IN
(7c)
Figure 7. BOOST Pin Configurations
R1=
1.5 I
(
)
(
)
SHDN(MAX)
3434fb
17
LT3434
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APPLICATIO S I FOR ATIO
Frequency Compensation section for a discussion of an
entirely different cause of subharmonic switching before
assuming that the cause is insufficient slope compensa-
tion. Application Note 19 has more details on the theory
of slope compensation.
Example:
12 – 2
R1=
= 1.3MΩ
1.5 5µA
(
)
5 1.3MΩ
(
)
= 6.5MΩ (Nearest 1% 6.49MΩ)
R3 =
If the FB pin voltage is below 0.9V (power-up or output
short-circuit conditions) the sync function is disabled.
This allows the frequency foldback to operate to avoid and
hazardous conditions for the SW pin.
1
1.3
R2 =
7 – 1.3
1.3
– 1µA –
1.3MΩ
= 408k (Nearest 1% 412k)
6.49MΩ
If the synchronization signal is present during Burst Mode
operation, synchronization will occur during the burst
portionoftheoutputwaveform.SynchronizingtheLT3434
during Burst Mode operation may alter the natural burst
frequency which can lead to jitter and increased ripple in
the burst waveform.
See the Typical Performance Characteristics section for
graphs of SHDN and VIN currents verses input voltage.
LT3434
If no synchronization is required this pin should be con-
nected to ground.
V
IN
4
+
–
V
IN
COMP
POWER GOOD
2.4V
1.3V
ENABLE
R1
R2
The LT3434 contains a power good block which consists
ofacomparator, delaytimerandactivelowflagthatallows
the user to generate a delayed signal after the power good
threshold is exceeded.
R3
SHDN
V
OUT
15
+
–
SHDN
COMP
3µA
Referring to Figure 2, the PGFB pin is the positive input to
a comparator whose negative input is set at VPGFB. When
PGFB is taken above VPGFB, current (ICSS) is sourced into
the CT pin starting the delay period. When the voltage on
the PGFB pin drops below VPGFB the CT pin is rapidly
discharged resetting the delay period. The PGFB voltage is
typically generated by a resistive divider from the regu-
lated output or input supply.
3434 F08
Figure 8. Undervoltage Lockout
SYNCHRONIZING
Oscillatorsynchronizationtoanexternalinputisachieved
by connecting a TTL logic-compatible square wave with a
duty cycle between 30% and 70% to the LT3434 SYNC
pin. The synchronizing range is equal to initial operating
frequency up to 700kHz. This means that minimum
practical sync frequency is equal to the worst-case high
self-oscillating frequency (230kHz), not the typical oper-
ating frequency of 200kHz. Caution should be used when
synchronizing above 230kHz because at higher sync
frequencies the amplitude of the internal slope compen-
sation used to prevent subharmonic switching is re-
duced. Thistypeofsubharmonicswitchingonlyoccursat
input voltages less than twice output voltage. Higher
inductor values will tend to eliminate this problem. See
The capacitor on the CT pin determines the amount of
delay time between the PGFB pin exceeding its threshold
(VPGFB) and the PG pin set to a high impedance state.
When the PGFB pin rises above VPGFB current is sourced
(ICT) from the CT pin into the external capacitor. When the
voltageontheexternalcapacitorreachesaninternalclamp
(VCT), the PG pin becomes a high impedance node. The
resultant PG delay time is given by t = CCT • (VCT)/(ICT). If
thevoltageonthePGFBpindropsbelowitsVPGFB, CCT will
be discharged rapidly and PG will be active low with a
200µA sink capability. If the SHDN pin is taken below its
3434fb
18
LT3434
W U U
APPLICATIO S I FOR ATIO
U
threshold during normal operation, the CT pin will be
dischargedandPGinactive,resultinginanonPowerGood
cycle when SHDN is taken above its threshold. Figure 9
shows the power good operation with PGFB connected to
FB and the capacitance on CT = 0.1µF. The PGFB pin has
a limited amount of driver capability and is susceptible to
noise during start-up and Burst Mode operation. If erratic
operation occurs during these conditions a small filter
capacitor from the PGFB pin to ground will ensure proper
operation. Figure 10 shows several different configura-
tions for the LT3434 Power Good circuitry.
LAYOUT CONSIDERATIONS
VOUT
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
efficiency switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted the high speed switching current path, shown
in Figure 11, must be kept as short as possible. This is
implemented in the suggested layout of Figure 12. Short-
ening this path will also reduce the parasitic trace induc-
tance of approximately 25nH/inch. At switch off, this
parasitic inductance produces a flyback spike across the
500mV/DIV
PG
100k TO VIN
VCT
500mV/DIV
VSHDN
2V/DIV
TIME (10ms/DIV)
3434 F09
Figure 9. Power Good
PG at 80% V
with 100ms Delay
PG at V > 4V with 100ms Delay
IN
OUT
V
IN
V
IN
200k
200k
PG
LT3434
PG
LT3434
V
= 3.3V
OUT
511k
200k
C
153k
12k
OUT
PGFB
PGFB
V
= 3.3V
OUT
165k
100k
C
OUT
FB
FB
100k
C
C
T
T
0.27µF
0.27µF
V
Disconnect at 80% V
with 100ms Delay
V Disconnect 3.3V Logic Signal
OUT
OUT
OUT
with 100µs Delay
V
V
IN
PG
LT3434
PGFB
IN
PG
LT3434
200k
200k
V
= 3.3V
V
= 12V
OUT
OUT
153k
12k
C
C
OUT
OUT
PGFB
866k
100k
FB
FB
100k
C
C
T
T
0.27µF
270pF
3434 F10
Figure 10. Power Good Circuits
3434fb
19
LT3434
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APPLICATIO S I FOR ATIO
LT3434
Board layout also has a significant effect on thermal
resistance. Pin 8 and the exposed die pad, Pin 17, are a
continuous copper plate that runs under the LT3434 die.
This is the best thermal path for heat out of the package.
Reducing the thermal resistance from Pin 8 and exposed
pad onto the board will reduce die temperature and in-
creasethepowercapabilityoftheLT3434.Thisisachieved
by providing as much copper area as possible around the
exposed pad. Adding multiple solder filled feedthroughs
under and around this pad to an internal ground plane will
also help. Similar treatment to the catch diode and coil
terminations will reduce any additional heating effects.
L1
V
OUT
V
4
2
SW
IN
V
IN
+
HIGH
C2
FREQUENCY
CIRCULATION
PATH
D1
C1 LOAD
3434 F11
Figure 11. High Speed Switching Path
C2
D2
CONNECT PIN 8 GND TO THE
PIN 17 EXPOSED PAD GND
V
OUT
L1
C1
PLACE VIA's UNDER EXPOSED
PAD TO A BOTTOM PLANE TO
ENHANCE THERMAL
KELVIN SENSE
FEEDBACK
TRACE AND
KEEP SEPARATE
FROM BIAS TRACE
D1
CONDUCTIVITY
THERMAL CALCULATIONS
MINIMIZE
D1-C3
GND
1
2
3
4
5
6
7
8
NC
PGOOD 16
SHDN 15
LOOP
Power dissipation in the LT3434 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current,andinputquiescentcurrent.Thefollowingformu-
las show how to calculate each of these losses. These
formulas assume continuous mode operation, so they
should not be used for calculating efficiency at light load
currents.
SW
R3
LT3434
V
IN
V
IN
SYNC 14
PGFB 13
FB 12
C3
R1
R2
C2
V
IN
SW
BOOST
V
11
C
C
T
BIAS 10
C4
C5
GND
C
9
SS
Switch loss:
GND
2
RSW OUT
I
V
OUT
(
) (
)
P
SW
=
+ tEFF 1/2 I
V
f
(
)( OUT )( IN)( )
3434 F12
V
IN
Figure 12. Suggested Layout
Boost current loss:
LT3434 switch. When operating at higher currents and
input voltages, with poor layout, this spike can generate
voltages across the LT3434 that may exceed its absolute
maximum rating. A ground plane should always be used
under the switcher circuitry to prevent interplane coupling
and overall noise.
2
V
I
/40
(
OUT ) ( OUT
)
PBOOST
=
V
IN
Quiescent current loss:
PQ = VIN (0.0026) + VOUT (0.001)
The VC and FB components should be kept as far away as
possible from the switch and boost nodes. The LT3434
pinout has been designed to aid in this. The ground for
these components should be separated from the switch
current path. Failure to do so will result in poor stability or
subharmonic like oscillation.
RSW = switch resistance (≈0.15 when hot )
tEFF = effective switch current/voltage overlap time
(tr + tf + tIR + tIF)
tr = (VIN/1.2)ns
tf = (VIN/1.7)ns
tIR = tIF = (IOUT/0.2)ns
f = switch frequency
3434fb
20
LT3434
W U U
APPLICATIO S I FOR ATIO
U
Example: with VIN = 40V, VOUT = 5V and IOUT = 2A:
ing increase in internal dissipation is of insufficient time
duration to raise die temperature significantly.
2
0.15 2
5
(
)( ) ( )
A second consideration is controllability. A potential limi-
PSW
=
+ 77e–9 1/2 2 40 200e3
(
)
( )( )(
)
)
(
40
tation occurs with a high step-down ratio of VIN to VOUT
,
asthisrequiresacorrespondinglynarrowminimumswitch
on time. An approximate expression for this (assuming
continuous mode operation) is given as follows:
0.08+ 0.62= 0.7
2
5
( )
2/40
(
)
= 0.03
PBOOST
=
40
tON(MIN) = VOUT + VF/VIN(fOSC
where:
VIN = input voltage
OUT = output voltage
)
P = 40 0.0026 + 5 0.001 = 0.109
(
)
(
)
Q
Total power dissipation is:
PTOT = 0.7 + 0.03 + 0.109 = 0.84
V
VF = Schottky diode forward drop
fOSC = switching frequency
Thermal resistance for the LT3434 package is influenced
by the presence of internal or backside planes. With a full
plane under the FE16 package, thermal resistance will be
about 45°C/W. No plane will increase resistance to about
150°C/W. To calculate die temperature, use the proper
thermal resistance number for the desired package and
add in worst-case ambient temperature:
A potential controllability problem arises if the LT3434 is
called upon to produce an on time shorter than its typical
value of 250ns. Feedback loop action will lower then
reduce the VC control voltage to the point where some sort
of cycle-skipping or Burst Mode behavior is exhibited.
TJ = TA + QJA (PTOT
)
In summary:
With the FE16 package (QJA = 45°C/W) at an ambient
temperature of 70°C:
1. Be aware that the simultaneous requirements of high
VIN, high IOUT and high fOSC may not be achievable in
practice due to internal dissipation. The Thermal Con-
siderations section offers a basis to estimate internal
power.Inquestionablecasesaprototypesupplyshould
be built and exercised to verify acceptable operation.
TJ = 70 + 45(0.84) = 108°C
Input Voltage vs Operating Frequency Considerations
TheabsolutemaximuminputsupplyvoltagefortheLT3434
is specified at 60V. This is based solely on internal semi-
conductor junction breakdown effects. Due to internal
power dissipation the actual maximum VIN achievable in a
particular application may be less than this.
2. The simultaneous requirements of high VIN, low VOUT
and high fOSC can result in an unacceptably short
minimum switch on time. Cycle skipping and/or Burst
Mode behavior will result although correct output volt-
age is usually maintained.
A detailed theoretical basis for estimating internal power
loss is given in the section Thermal Considerations. Note
that AC switching loss is proportional to both operating
frequency and output current. The majority of AC switch-
ing loss is also proportional to the square of input voltage.
FREQUENCY COMPENSATION
Before starting on the theoretical analysis of frequency
responsethefollowingshouldberemembered—theworse
the board layout, the more difficult the circuit will be to
stabilize. This is true of almost all high frequency analog
circuits. Read the Layout Considerations section first.
Common layout errors that appear as stability problems
aredistantplacementofinputdecouplingcapacitorand/or
For example, while the combination of VIN = 40V, VOUT
=
5V at 2A and fOSC = 200kHz may be easily achievable,
simultaneously raising VIN to 60V and fOSC to 700kHz is
not possible. Nevertheless, input voltage transients up to
60V can usually be accommodated, assuming the result-
3434fb
21
LT3434
W U U
U
APPLICATIO S I FOR ATIO
catch diode and connecting the VC compensation to a
ground track carrying significant switch current. In addi-
tionthetheoreticalanalysisconsidersonlyfirstordernon-
idealcomponentbehavior.Forthesereasons,itisimportant
that a final stability check is made with production layout
and components.
SW
SW
LT3434
CURRENT MODE
5
2
OUTPUT
POWER STAGE
Ω
g
m
= 6
C
R1
12
R2
FB
Ω
g
m
= 650µ
FB
–
+
V
C
ERROR
AMP
11
ESR
R
1.5M
C
1.25V
The LT3434 uses current mode control. This alleviates
many of the phase shift problems associated with the
inductor. The basic regulator loop is shown in Figure 12.
The LT3434 can be considered as two gm blocks, the error
amplifier and the power stage.
C
OUT
C
F
C
C
3434 F13
Figure 13. Model for Loop Response
Figure13showstheoverallloopresponsewitha470pFVC
capacitor and a typical 100µF tantalum output capacitor.
The response is set by the following terms:
the value of RC is increased, transient response will
generally improve but two effects limit its value. First, the
combination of output capacitor ESR and a large RC may
stop loop gain rolling off altogether. Second, if the loop
gainisnotrolledoffsufficientlyattheswitchingfrequency
output ripple will perturb the VC pin enough to cause
unstable duty cycle switching similar to subharmonic
oscillation. This may not be apparent at the output. Small-
signal analysis will not show this since a continuous time
system is assumed.
Error amplifier: DC gain is set by gm and RO:
Ω
EA Gain = 650µ • 1.5M = 975
The pole set by CF and RL:
EA Pole = 1/(2π • 1.5M • 470pF) = 226Hz
Unity gain frequency is set by CF and gm:
EA Unity Gain Frequency = 650µF/(2π • 470pF)
= 220kHz
When checking loop stability the circuit should be oper-
ated over the application’s full voltage, current and tem-
perature range. Any transient loads should be applied and
the output voltage monitored for a well-damped behavior.
Powerstage: DC gain is set by gm and RL (assume 10Ω):
PS DC Gain = 6 • 10 = 60
Pole set by COUT and RL:
100
80
180
160
120
80
V
C
F
R
= 3.3V
OUT
OUT
PS Pole = 1/(2π • 100µF • 10) = 159Hz
Unity gain set by COUT and gm:
= 100µF, 0.1Ω
C = 470pF
= 10k
C
C
LOAD
= 4700pF
C
I
= 1A
40
PS Unity Gain Freq = 6/(2π • 100µF) = 94kHz.
Tantalum output capacitor zero is set by COUT and COUT
ESR
0
–40
–80
40
Output Capacitor Zero = 1/(2π • 100µF • 0.1) = 15.9kHz
The zero produced by the ESR of the tantalum output
capacitor is very useful in maintaining stability. If the ESR
of the output capacitor is low or better transient response
isrequired, azerocanbeaddedtotheloopusingaresistor
(RC) in series with the compensation capacitor (CC). As
0
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
3434 F14
Figure 14. Overall Loop Response
3434fb
22
LT3434
U
PACKAGE DESCRIPTIO
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BC
4.90 – 5.10*
(.193 – .201)
3.58
(.141)
3.58
(.141)
16 1514 13 12 1110
9
6.60 ±0.10
4.50 ±0.10
2.94
(.116)
6.40
(.252)
BSC
SEE NOTE 4
2.94
(.116)
0.45 ±0.05
1.05 ±0.10
0.65 BSC
5
7
8
1
2
3
4
6
RECOMMENDED SOLDER PAD LAYOUT
1.10
(.0433)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE16 (BC) TSSOP 0204
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
3434fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
23
LT3434
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
V : 7.3V to 45V/64V, V
LT1074/LT1074HV
4.4A (I ), 100kHz, High Efficiency Step-Down DC/DC Converters
: 2.21V, I : 8.5mA,
Q
OUT
IN
OUT(MIN)
: 10µA, DD5/7, TO220-5/7
I
SD
LT1076/LT1076HV
LT1676
1.6A (I ), 100kHz, High Efficiency Step-Down DC/DC Converters
V : 7.3V to 45V/64V, V
: 2.21V, I : 8.5mA,
Q
OUT
IN
OUT(MIN)
I
: 10µA, DD5/7, TO220-5/7
SD
60V, 440mA (I ), 100kHz, High Efficiency Step-Down DC/DC
V : 7.4V to 60V, V
S8
: 1.24V, I : 3.2mA, I : 2.5µA,
OUT(MIN) Q SD
OUT
IN
Converter
LT1765
25V, 2.75A (I ), 1.25MHz, High Efficiency Step-Down DC/DC
Converter
V : 3V to 25V, V
SO-8, TSSOP16E
: 1.20V, I : 1mA, I : 15µA,
OUT(MIN) Q SD
OUT
IN
LT1766
60V, 1.2A (I ), 200kHz, High Efficiency Step-Down DC/DC
Converter
V : 5.5V to 60V, V
TSSOP16/E
: 1.20V, I : 2.5mA, I : 25µA,
OUT(MIN) Q SD
OUT
IN
LT1767
25V, 1.2A (I ), 1.25MHz, High Efficiency Step-Down DC/DC
Converter
V : 3V to 25V, V
MS8/E
: 1.20V, I : 1mA, I : 6µA,
OUT(MIN) Q SD
OUT
IN
LT1776
40V, 550mA (I ), 200kHz, High Efficiency Step-Down DC/DC
Converter
V : 7.4V to 40V, V
N8, S8
: 1.24V, I : 3.2mA, I : 30µA,
OUT(MIN) Q SD
OUT
IN
LTC®1875
LT1940
1.5A (I ), 550kHz, Synchronous Step-Down DC/DC Converter
V : 2.7V to 6V, V
TSSOP16
: 0.8V, I : 15µA, I : <1µA,
OUT
IN
OUT(MIN) Q SD
Dual 1.2A (I ), 1.1MHz, High Efficiency Step-Down DC/DC
V : 3V to 25V, V
: 1.2V, I : 3.8mA, MS10
OUT
IN
OUT(MIN) Q
Converter
LT1956
60V, 1.2A (I ), 500kHz, High Efficiency Step-Down DC/DC
Converter
V : 5.5V to 60V, V
TSSOP16/E
: 1.20V, I : 2.5mA, I : 25µA,
OUT(MIN) Q SD
OUT
IN
LT1976
60V, 1.5A (I ), 200kHz, Step-Down DC/DC
Converter
V : 3V to 60V, V
TSSOP16E
: 1.25V, I : 100µA, I : 4µA,
OUT(MIN) Q SD
OUT
IN
LT3010
80V, 50mA, Low Noise Linear Regulator
V : 1.5V to 80V, V
MS8E
: 1.28V, I : 30µA, I : <1µA,
OUT(MIN) Q SD
IN
LTC3407
LTC3412
LTC3414
LT3430
Dual 600mA (I ), 1.5MHz, High Efficiency Step-Down DC/DC
Converter
V : 2.5V to 5.5V, V
: 0.6V, I : 40µA MS10
Q
OUT
IN
OUT(MIN)
2.5A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
V : 2.5V to 5.5V, V
: 0.8V, I : 60µA, I : <1µA,
Q SD
OUT
IN
OUT(MIN)
TSSOP16E
4A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
V : 2.25V to 5.5V, V
: 0.8V, I : 64µA, I : <1µA,
OUT(MIN) Q SD
OUT
IN
TSSOP20E
60V, 2.5A (I ), 200kHz, High Efficiency Step-Down DC/DC
V : 5.5V to 60V, V
IN
: 1.20V, I : 2.5mA, I : 30µA,
Q SD
OUT
OUT(MIN)
Converter
TSSOP16E
LT3431
60V, 2.5A (I ), 500kHz, High Efficiency Step-Down DC/DC
Converter
V : 5.5V to 60V, V
TSSOP16E
: 1.20V, I : 2.5mA, I : 30µA,
OUT(MIN) Q SD
OUT
IN
LT3433
60V, 400mA (I ), 200kHz, Buck-Boost DC/DC Converter
V : 5V to 60V, V : 3.3V to 20V, I : 100µA, TSSOP-16E
IN OUT Q
OUT
LTC3727/LTC3727-1 36V, 500kHz, High Efficiency Step-Down DC/DC Controllers
V : 4V to 36V, V
QFN-32, SSOP-28
: 0.8V, I : 670µA, I : 20µA,
OUT(MIN) Q SD
IN
3434fb
LT 0306 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2004
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