LT3437EFE#PBF_技术文档

LT3437

High Voltage 500mA, 200kHz

Step-Down Switching Regulator

with 100µA Quiescent Current

U

FEATURES

DESCRIPTIO

The LT^®3437 is a 200kHz monolithic buck switching

regulator that accepts input voltages up to 80V. A high

efficiency500mA,0.8Ωswitchisincludedonthediealong

with all the necessary oscillator, control and logic cir-

cuitry. Current mode topology is used for fast transient

response and good loop stability.

■

Wide Input Range: 3.3V to 60V

■

Load Dump (Input Transient) Protection to 80V

■

500mA Peak Switch Current

Burst Mode^®Operation: 100µA Quiescent Current**

Low Shutdown Current: I_Q< 1µA

Burst Mode Operation Defeat

■

200kHz Switching Frequency

Innovative design techniques along with a new high volt-

age process achieve high efficiency over a wide input

range. Efficiency is maintained over a wide output current

rangebyemployingBurstModeoperationatlowcurrents,

utilizing the output to bias the internal circuitry, and by

using a supply boost capacitor to fully saturate the power

switch. Burst Mode operation can be defeated by a logic

high signal on the SYNC pin which results in lower light

load ripple at the expense of light load efficiency. Patented

circuitry maintains peak switch current over the full duty

cycle range.* Shutdown reduces input supply current to

less than 1µA. External synchronization can be imple-

mented by driving the SYNC pin with logic-level inputs. A

single capacitor from the C_SSpin to the output provides a

controlled output voltage ramp (soft-start).

Saturating Switch Design: 0.8Ω On-Resistance

Peak Switch Current Maintained Over

Full Duty Cycle Range*

■

1.25V Feedback Reference Voltage

Easily Synchronizable

Soft-Start Capability

Small 10-Pin Thermally Enhanced DFN Package

U

APPLICATIO S

■

High Voltage Power Conversion

■

14V and 42V Automotive Systems

■

Industrial Power Systems

■

Distributed Power Systems

■

Battery-Powered Systems

The LT3437 is available in a low profile (0.75mm) 3mm ×

3mm 10-pin DFN package or a 16-Pin TSSOP Package

both with exposed pad leadframes for low thermal

resistance.

■

Powered Ethernet

, LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode

is a registered trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners. *Protected by U.S. Patents including 6498466. **See

Burst Mode Operation section for conditions.

U

TYPICAL APPLICATIO

Input Voltage

Supply Current vs Input Voltage

200

Transient Response

14V to 3.3V Step-Down Converter with

100µA No Load Quiescent Current

180

V

OUT

V

IN

3.3V

V

BOOST

IN

160

140

120

100

80

4.5V TO 80V*

V

IN

2.2µF

100V

CER

100µH

400mA

0.1µF

BAS21

20V/DIV

SHDN

SW

LT3437

0.1µF

10MQ100N

V

C

SS

V

IN

0V

330pF

1500pF

25k

V

BIAS

FB

V

165k

100k

OUT

27pF

100µF

6.3V

TANT

20mV/DIV

60

SYNC

GND

AC COUPLED

40

3437 TA03

I

250mA

OUT

50ms/DIV

COLD CRANK

20

LOAD DUMP

0

3437 TA01

*FOR INPUT VOLTAGES ABOVE 60V RESTRICTIONS APPLY

0

10 20 30 40 50 60 70 80

INPUT VOLTAGE (V)

3435 TA02

3437f

1

LT3437

W W

U W

ABSOLUTE AXI U RATI GS

(Note 1)

Operating Junction Temperature Range

V_IN, SHDN, BIAS, SW Operating ............................. 60V

V_IN, SHDN 100ms Transient, <15% Duty Cycle ....... 80V

BOOST Pin Above SW ............................................ 35V

BOOST Pin Voltage Operating................................. 75V

BOOST Pin 100ms Transient, <15% Duty Cycle ...... 85V

SYNC, C_SS, FB .......................................................... 6V

LT3437EDD (Note 2) ....................... –40°C to 125°C

LT3437IDD (Note 2) ........................ –40°C to 125°C

LT3437EFE (Note 2) ........................ –40°C to 125°C

LT3437IFE (Note 2) ......................... –40°C to 125°C

Storage Temperature Range ................. –65°C to 125°C

U

W

U

PACKAGE/ORDER I FOR ATIO

TOP VIEW

NC

SW

NC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

NC

SHDN

SYNC

NC

SW

1

2

3

4

5

10 SHDN

V

9

8

7

6

SYNC

FB

IN

V

IN

BST

11

17

GND

V

C

NC

BOOST

NC

FB

C

BIAS

SS

V

C

BIAS

DD PACKAGE

10-LEAD (3mm × 3mm) PLASTIC DFN

GND

C

SS

θ

_JA= 45°C/W, θ_JC(PAD)= 10°C/W

FE PACKAGE

16-LEAD PLASTIC TSSOP

EXPOSED PAD IS GND (PIN 11)

MUST BE SOLDERED TO GND (PIN 4)

θ

_JA= 45°C/W, θ_JC(PAD)= 10°C/W

EXPOSED PAD IS GND (PIN 17)

MUST BE SOLDERED TO GND (PIN 8)

ORDER PART NUMBER

FE PART MARKING

ORDER PART NUMBER

DD PART MARKING

LT3437EDD

LT3437IDD

LBDJ

LBDK

LT3437EFE

LT3437IFE

3437EFE

3437IFE

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The

●

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T = 25°C. V = 12V, SHDN = 12V, BIAS = 5V, FB = 1.25V,

J

IN

C

/SYNC = 0V unless otherwise noted.

SS

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

1.3

5

MAX

1.45

30

UNITS

V

SHDN Threshold

●

1.15

SHDN

I

SHDN Input Current

SHDN = 12V

µA

SHDN

Minimum Input Voltage (Note 3)

Supply Shutdown Current

Supply Sleep Current (Note 4)

2.5

0.1

3

V

I

SHDN = 0V, BOOST = 0V, FB/PGFB = 0V

2

µA

VINS

VIN

BIAS = 0V, FB = 1.35V

FB = 1.35V

●

300

25

500

50

µA

I

Supply Quiescent Current

BIAS = 0V, FB = 1.15V, V = 0.8V, SYNC = 2V

BIAS = 5V, FB = 1.15V, V = 0.8V, SYNC = 2V

1.35

0.475

2

1

mA

C

Minimum BIAS Voltage (Note 5)

2.7

3.15

V

3437f

2

LT3437

ELECTRICAL CHARACTERISTICS ^The

●

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T = 25°C. V = 12V, SHDN = 12V, BIAS = 5V, FB = 1.25V,

J

IN

C

SS

/SYNC = 0V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

150

0.75

1.8

MAX

250

1

UNITS

µA

I

BIAS Sleep Current (Note 4)

BIAS Quiescent Current

Minimum Boost Voltage (Note 6)

Input Boost Current (Note 7)

●

BIASS

BIAS

SYNC = 2V

mA

V

I

= 250mA

2.5

SW

I

= 0.5A

= 0.25A

11

8

16

13

mA

SW

V

Reference Voltage (V

)

REF

3.3V < V < 80V

1.225

1.25

50

1.275

200

V

nA

REF

VIN

I

FB Input Bias Current

FB

EA Voltage Gain (Note 8)

900

650

35

V/V

µMho

µA

EA Voltage g

dI(V )= ±10µA

C

m

EA Source Current

EA Sink Current

FB = 1.15V

FB = 1.35V

15

55

30

µA

V to SW g

1

A/V

mV

V

C

m

V Switching Threshold

C

V

= 2V

SYNC

500

1.75

650

V High Clamp

C

1.5

2.1

I

SW Current Limit

●

500

900

mA

PK

SW V

Switch Saturation Voltage

(Note 9)

I

= 250mA

= 500mA

●

200

400

800

mV

CESAT

SW

Switching Frequency

●

170

200

95

240

kHz

%

Maximum Duty Cycle

Minimum SYNC Amplitude

SYNC Frequency Range

SYNC Input Impedance

1.5

2

V

240

4

700

kHz

kΩ

µA

50

10

I

C

Current Threshold (Note 10)

SS

FB = 0V

16

CSS

Note 1: Absolute Maximum Ratings are those values beyond which the life of

defined as the quiescent current during the “sleep” portion of Burst Mode

operation. See Applications Information for determining application supply

currents.

a device may be impaired.

Note 2: The LT3437EDD/LT3437EFE are guaranteed to meet performance

specifications from 0°C to 125°C junction temperature. Specifications over

the –40°C to 125°C operating junction temperature range are assured by

design, characterization and correlation with statistical process controls. The

LT3437IDD/LT3437IFE are guaranteed and tested over the full –40°C to

125°C operating junction temperature range.

Note 3: Minimum input voltage is defined as the voltage where switching

starts. Actual minimum input voltage to maintain a regulated output will

depend upon output voltage and load current. See Applications Information.

Note 5: Minimum BIAS voltage is the voltage on the BIAS pin when I

is

BIAS

sourced into the pin.

Note 6: This is the minimum voltage across the boost capacitor needed to

guarantee full saturation of the internal power switch.

Note 7: Boost current is the current flowing into the BOOST pin with the pin

held 3.3V above input voltage. It flows only during switch on time.

Note 8: Gain is measured with a V swing from 1.15V to 750mV.

C

Note 9: Switch saturation voltage guaranteed by correlation to wafer level

measurements for DD package parts.

Note 4: Supply input current is the quiescent current drawn by the input

pin. Its typical value depends on the voltage on the BIAS pin and operating

state of the LT3437. With the BIAS pin at 0V, all of the quiescent current

Note 10: The C threshold is defined as the value of current sourced into the

SS

C

pin which results in an increase in sink current from the V pin. See the

Soft-Start section in Applications Information.

SS

C

required to operate the LT3437 will be provided by the V pin. With the

IN

BIAS voltage above its minimum input voltage, a portion of the total

quiescent current will be supplied by the BIAS pin. Supply sleep current is

3437f

3

LT3437

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Efficiency and Power Loss

vs Load Current

Oscillator Frequency

vs Temperature

FB Voltage vs Temperature

1.30

1.28

1.26

1.24

1.22

1.20

250

240

230

220

210

200

190

180

170

160

150

500

450

400

350

300

250

200

150

100

50

100

90

80

70

60

50

40

30

20

10

0

V

A

= 12V

IN

OUT

= 25°C

= 3.3V

T

EFFICIENCY

POWER LOSS

0

50

75 100 125

–50

0

25

50

75 100 125

–50 –25

0

25

–25

0.1

1

10

1000

100

TEMPERATURE (°C)

LOAD CURRENT (mA)

3437 G02

3437 G03

3437 G01

Shutdown Supply Current

vs Temperature

SHDN Threshold

SHDN Pin Current

10

9

1.50

10

8

1.45

1.40

8

7

1.35

1.30

6

V

= 80V

VIN

5

4

1.25

1.20

1.15

1.10

V

= 60V

VIN

3

2

1

0

2

V

= 12V

VIN

0

–50

–25

0

25

50

75 100 125

–50

0

25

50

75 100 125

0

10

20

30

40

50

60

–25

V

(V)

TEMPERATURE (°C)

SHDN

3437 G04

3437 G05

3437 G06

Switch Peak Current Limit

vs Temperature

Input Current vs Temperature

Bias Current vs Temperature

700

600

500

900

800

700

600

500

800

700

600

500

400

300

200

100

0

RUN MODE

400

300

200

100

0

SLEEP MODE V

= 0V

BIAS

400

300

200

100

0

SLEEP MODE

SLEEP MODE V

= 5V

50

BIAS

25

–50

0

75 100 125

–50

0

25

50

75 100 125

–25

–50 –25 –0

25

50

75 100 125

TEMPERATURE (°C)

3437 G07

3437 G08

3437 G09

3437f

4

LT3437

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Soft-Start Current Threshold

vs FB Voltage

Oscillator Frequency

vs FB Voltage

Switch On Voltage (V

)

CESAT

600

500

400

300

200

100

0

35

30

25

20

15

10

5

250

200

150

100

50

SOFT-START DEFEATED

T = 125°C

J

T = 25°C

J

T = –40°C

J

0

0.2

0.6

0.8

1.0

1.2

0

0.25

0.75

0.50

FB VOLTAGE (V)

1.00

1.25

400

0.4

100

200

300

500

FB VOLTAGE (V)

LOAD CURRENT (mA)

3437 G10

3437 G11

3437 G12

Burst Mode Threshold

vs Input Voltage

Supply Current vs Input Voltage

Minimum Input Voltage

200

180

160

140

120

100

80

7.5

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

200

180

160

140

120

100

80

V

= 3.3V

V

= 3.3V

OUT

5V TO START

5V TO RUN

ENTER

EXIT

3.3V TO START

60

40

3.3V TO RUN

20

0

3.0

0

10 20 30 40 50 60 70 80

0

40

INPUT VOLTAGE (V)

10

20

30

50

60

0

100

200

300

500

400

INPUT VOLTAGE (V)

LOAD CURRENT (mA)

3437 F13

3437 G15

3437 G14

Minimum On-Time

Boost Current vs Load Current

Dropout Operation

500

450

400

350

300

250

200

150

100

50

12

11

10

9

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

V

LOAD

= 3.3V

OUT

I

= 250mA

BOOST DIODE =

DIODES INC B1100

8

7

0

6

–50

0

25

50

75 100 125

–25

100

400

LOAD CURRENT (mA)

200

300

500

2.0

2.5

3.0

3.5

4.5

4.0

TEMPERATURE (°C)

INPUT VOLTAGE (V)

3437 G16

3437 G17

3437 G18

3437f

5

LT3437

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Maximum Duty Cycle

vs Temperature

V Switching Threshold

C

vs Temperature

Dropout Operation

6

5

4

3

2

1

0

94.5

94.0

93.5

93.0

92.5

92.0

91.5

0.6

0.5

0.4

0.3

0.2

0.1

0

I

= 250mA

V

LOAD

= 5V

LOAD

OUT

I

= 250mA

BOOST DIODE = DIODES INC B1100

–50

0

25

50

75 100 125

–50

0

25

50

75 100 125

–25

2.0 2.5 3.0 3.5

4.5

5.5 6.0

4.0

5.0

TEMPERATURE (°C)

INPUT VOLTAGE (V)

3437 G20

3437 G21

3437 G19

Maximum Sync Frequency

vs Temperature

Burst Mode Operation

Burst Mode Defeated

1600

1500

1400

1300

1200

1100

1000

900

V

I

= 12V

IN

OUT

= 100mA

V_OUT

20mV/DIV

= 3.3V

V_OUT

20mV/DIV

OUT

AC COUPLED

I_SW

100mA/DIV

I_SW

100mA/DIV

800

700

10µs/DIV

3437 G24

V_IN= 12V

V_OUT= 3.3V

I_Q= 100µA

10µs/DIV

3437 G23

V_IN= 12V

600

V_OUT= 3.3V

500

I_Q= 1.7mA

V_SYNC= 3.3V

400

–50

0

25

50

75 100 125

–25

TEMPERATURE (°C)

3437 G22

Step Response

V_OUT

50mV/DIV

V_OUT

50mV/DIV

I_OUT

100mA/DIV

I_OUT

100mA/DIV

1ms/DIV

LOAD STEP 0mA TO 200mA

3437 G25

1ms/DIV

LOAD STEP 100mA TO 300mA

3437 G26

3437f

6

LT3437

U

(DD/FE)

PI FU CTIO S

SW (Pin 1/Pin 2): The SW pin is the emitter of the on-chip

power NPN switch. This pin is driven up to the input pin

voltage during switch on time. Inductor current drives the

SW pin negative during switch off time. Negative voltage

is clamped with the external catch diode. Maximum nega-

tive switch voltage allowed is –0.8V.

BIAS (Pin 6/Pin 10): The BIAS pin is used to improve

efficiency when operating at higher input voltages and

light load current. Connecting this pin to the regulated

output voltage forces most of the internal circuitry to draw

its operating current from the output voltage rather than

the input supply. This architecture increases efficiency

especially when the input voltage is much higher than the

output. Minimum output voltage setting for this mode of

operation is typically 3V.

NC (Pins 1, 3, 5, 7, 13, 16)(FE Package ONLY): No

Connection.

V_IN(Pin 2/Pin4):Thisisthecollectoroftheon-chippower

NPNswitch.V_INpowerstheinternalcontrolcircuitrywhen

a voltage on the BIAS pin is not present. High di/dt edges

occur on this pin during switch turn on and off. Keep the

path short from the V_INpin through the input bypass

capacitor, through the catch diode back to SW. All trace

inductanceonthispathwillcreateavoltagespikeatswitch

off, adding to the V_CEvoltage across the internal NPN.

V_C(Pin 7/Pin 11): The V_Cpin is the output of the error

amplifier and the input of the peak switch current com-

parator. It is normally used for frequency compensation,

but can also serve as a current clamp or control loop

override. V_Csits at about 0.45V for light loads and 1.5V at

maximum load. During the sleep portion of Burst Mode

operation, the V_Cpin is held at a voltage slightly below the

burst threshold for better transient response. Driving the

V_Cpin to ground will disable switching and place the IC

into sleep mode.

BOOST (Pin 3/Pin 6): The BOOST pin is used to provide a

drive voltage, higher than the input voltage, to the internal

bipolarNPNpowerswitch. Withoutthisaddedvoltage, the

typical switch voltage loss would be about 1.5V. The

additional BOOST voltage allows the switch to saturate

and its voltage loss approximates that of a 0.8Ω FET

structure.

FB (Pin 8/Pin 12): The feedback pin is used to determine

the output voltage using an external voltage divider from

the output that generates 1.25V at the FB pin. When the FB

pin drops below 0.9V, switching frequency is reduced, the

SYNC function is disabled and output ramp rate control is

enabled via the C_SSpin. See the Feedback section in

Applications Information for details.

GND (Pins 4, 11/Pins 8, 17): The GND pin connection

acts as the reference for the regulated output, so load

regulation will suffer if the “ground” end of the load is not

at the same voltage as the GND pin of the IC. This

condition will occur when load current or other currents

flow through metal paths between the GND pin and the

load ground. Keep the path between the GND pin and the

load ground short and use a ground plane when possible.

The GND pin also acts as a heat sink and should be

soldered (along with the exposed leadframe) to the cop-

per ground plane to reduce thermal resistance (see Appli-

cations Information).

SYNC(Pin9/Pin14):TheSYNCpinisusedtosynchronize

the internal oscillator to an external signal. It is directly

logic compatible and can be driven with any signal be-

tween 25% and 75% duty cycle. The synchronizing range

is equal to maximum initial operating frequency up to

700kHz. When the voltage on the FB pin is below 0.9V the

SYNC function is disabled. When a synchronization signal

or logic-level high is present at the SYNC pin, Burst Mode

operation is disabled. See the synchronizing section in

Applications Information for details.

C_SS(Pin 5/Pin 9): A capacitor from the C_SSpin to the

regulated output voltage determines the output voltage

ramp rate during start-up. When the current through the

C_SScapacitor exceeds the C_SSthreshold (I_CSS), the volt-

age ramp of the output is limited. The C_SSthreshold is

proportional to the FB voltage (see Typical Performance

Characteristics)andisdefeatedforFBvoltagegreaterthan

0.9V(typical).SeeSoft-StartsectioninApplicationsInfor-

mation for details.

SHDN(Pin10/Pin15):TheSHDNpinisusedtoturnoffthe

regulator and to reduce input current to less than 1µA. The

SHDN pin requires a voltage above 1.3V with a typical

source current of 5µA to take the IC out of the shutdown

state.

Exposed Pad (Pin 11/Pin 17): Ground. Must be soldered

to the PCB.

3437f

7

LT3437

W

BLOCK DIAGRA

V

IN

INTERNAL REF

SLOPE

COMP

2.4V

UNDERVOLTAGE

LOCKOUT

Σ

+

–

BIAS

THERMAL

SHUTDOWN

200kHz

CURRENT

COMP

OSCILLATOR

SYNC

SHDN

BOOST

SW

ANTISLOPE

COMP

+

–

R

SHDN

COMP

SWITCH

LATCH

DRIVER

CIRCUITRY

Q

S

1.3V

BURST MODE

DETECT

C

SS

SOFT-START

V

FOLDBACK

DETECT

C

CLAMP

FB

–

ERROR

AMP

+

GND

1.25V

V

C

PGND

3437 BD

Figure 1. LT3437 Block Diagram

The LT3437 is a constant frequency, current mode buck

converter.Thismeansthatthereisaninternalclockandtwo

feedback loops that control the duty cycle of the power

switch. In addition to the normal error amplifier, there is a

current sense amplifier that monitors switch current on a

cycle-by-cycle basis. A switch cycle starts with an oscilla-

torpulsewhichsetstheRSlatchtoturntheswitchon.When

switch current reaches a level set by the current compara-

tor, the latch is reset and the switch turns off. Output volt-

age control is obtained by using the output of the error

amplifiertosettheswitchcurrenttrippoint.Thistechnique

means that the error amplifier commands current to be

delivered to the output rather than voltage. A voltage fed

system will have low phase shift up to the resonant fre-

quencyoftheinductorandoutputcapacitor,thenanabrupt

180° shift will occur. The current fed system will have 90°

phaseshiftatamuchlowerfrequency,butwillnothavethe

additional 90° shift until well beyond the LC resonant fre-

quency. This makes it much easier to frequency compen-

sate the feedback loop and gives much quicker transient

response and line rejection.

Most of the circuitry of the LT3437 operates from an

internal 2.4V bias line. The bias regulator normally draws

power from the V_INpin, but if the BIAS pin is connected to

an external voltage higher than 3V, bias power will be

drawn from the external source (typically the regulated

output voltage). This improves efficiency.

High switch efficiency is attained by using the BOOST pin

to provide a voltage to the switch driver which is higher

than the input voltage, allowing the switch to be saturated.

This boosted voltage is generated with an external capaci-

tor and diode.

To further optimize efficiency, the LT3437 automatically

switchestoBurstModeoperationinlightloadsituations.In

Burst Mode operation, all circuitry associated with control-

ling the output switch is shut down, reducing the input

supply current to 25µA and bias input current to 150µA.

If lower output ripple is desired over light load efficiency,

BurstModeoperationcanbedefeatedbysettingtheSYNC

pin voltage greater than 2V. A logic-level low on the SHDN

pindisablestheICandreducesinputsupplycurrenttoless

than 1µA. External synchronization can be implemented

by driving the SYNC pin with logic-level inputs.

3437f

8

LT3437

W U U

APPLICATIO S I FOR ATIO

U

FEEDBACK PIN FUNCTIONS

Table 1

OUTPUT

VOLTAGE

(V)

R1

NEAREST (1%)

(kΩ)

OUTPUT

ERROR

(%)

The feedback (FB) pin on the LT3437 is used to set output

voltage and provide several overload protection features.

The first part of this section deals with selecting resistors

to set output voltage, and the remaining part talks about

frequency foldback and soft-start features. Please read

both parts before committing to a final design.

R2

(kΩ, 1%)

2.5

3

100

140

165

300

383

536

698

866

0

3.3

5

0.38

0

Referring to Figure 2, the output voltage is determined by

a voltage divider from V_OUTto ground which generates

1.25VattheFBpin.Sincetheoutputdividerisaloadonthe

output, care must be taken when choosing the resistor

divider values. For light load applications the resistor

values should be as large as possible to achieve peak

efficiencyinBurstModeoperation. Extremelylargevalues

forresistorR1willcauseanoutputvoltageerrorduetothe

50nA FB pin input current. The suggested value for the

output divider resistor (see Figure 2) from FB to ground

(R2) is 100k or less. A formula for R1 is shown below. A

table of standard 1% values is shown in Table 1 for

common output voltages.

6

0.63

–0.63

–0.25

0.63

8

10

12

More Than Just Voltage Feedback

The FB pin is used for more than just output voltage

sensing. It also reduces switching frequency and con-

trolsthesoft-startvoltagerampratewhenoutputvoltage

is below the regulated level (see the Frequency Foldback

and Soft-Start Current graphs in Typical Performance

Characteristics).

Frequencyfoldbackisdonetocontrolpowerdissipationin

both the IC and in the external diode and inductor during

short-circuit conditions. A shorted output requires the

switching regulator to operate at very low duty cycles. As

a result, the average current through the diode and induc-

tor is equal to the short-circuit current limit of the switch

(typically 500mA for the LT3437). Minimum switch on

time limitations would prevent the switcher from attaining

a sufficiently low duty cycle if switching frequency were

maintained at 200kHz, so frequency is reduced by about

10:1 when the FB pin voltage drops below 0.4V (see

FrequencyFoldbackgraph). Asthefeedbackvoltagerises,

the switching frequency increases to 200kHz with 0.95V

on the FB pin. During frequency foldback, external syn-

chronization is disabled to prevent interference with

foldback operation. Frequency foldback does not affect

operation during normal load conditions.

V_OUT– 1.25

1.25 + R2 • 50nA

R1= R2 •

V

OUT

LT3437

SW

1

5

C1

C

SS

SOFT-START

200kHz

OSCILLATOR

FOLDBACK

DETECT

R1

FB

–

+

8

7

ERROR

AMP

R2

1.25V

V

C

3437 F02

In addition to lowering switching frequency, the soft-start

ramp rate is also affected by the feedback voltage. Large

capacitive loads or high input voltages can cause a

high input current surge during start-up. The soft-start

Figure 2. Feedback Network

3437f

9

LT3437

W U U

U

APPLICATIO S I FOR ATIO

function reduces input current surge by regulating switch causetheinputvoltagetoswingabovetheDClevelofinput

current via the V_Cpin to maintain a constant voltage ramp power source and it may exceed the maximum voltage

rate(dV/dt)attheoutput. Acapacitor(C1inFigure2)from rating of the input capacitor and LT3437. All input voltage

the C_SSpin to the output determines the maximum output transient sequences should be observed at the V_INpin of

dV/dt. Whenthefeedbackvoltageisbelow0.4V, theV_Cpin the LT3437 to ensure that absolute maximum voltage

will rise, resulting in an increase in switch current and

outputvoltage.IfthedV/dtoftheoutputcausesthecurrent

through the C_SScapacitor to exceed I_CSS, the V_Cvoltage is

reduced resulting in a constant dV/dt at the output. As the

feedback voltage increases, I_CSSincreases, resulting in an

increased dV/dt until the soft-start function is defeated

with 0.9V present at the FB pin. The soft-start function

does not affect operation during normal load conditions.

However, if a momentary short (brown out condition) is

present at the output which causes the FB voltage to drop

below 0.9V, the soft-start circuitry will become active.

ratings are not violated.

The easiest way to suppress input voltage transients is to

addasmallaluminumelectrolyticcapacitorinparallelwith

the low ESR input capacitor. The selected capacitor needs

to have the right amount of ESR to critically damp the

resonant circuit formed by the input lead inductance and

theinputcapacitor. ThetypicalvaluesofESRwillfallinthe

range of 0.5Ω to 2Ω and capacitance will fall in the range

of 5µF to 50µF.

If tantalum capacitors are used, values in the 22µF to

470µF range are generally needed to minimize ESR and

meet ripple current and surge ratings. Care should be

taken to ensure the ripple and surge ratings are not

exceeded. The AVX TPS and Kemet T495 series are surge

rated. AVX recommends derating capacitor operating

voltage by 2:1 for high surge applications.

INPUT CAPACITOR

Step-down regulators draw current from the input supply

in pulses. The rise and fall times of these pulses are very

fast. The input capacitor is required to reduce the voltage

ripple this causes at the input of LT3437 and force the

switching current into a tight local loop, thereby minimiz-

ing EMI. The RMS ripple current can be calculated from:

OUTPUT CAPACITOR

The output capacitor is normally chosen by its effective

series resistance (ESR) because this is what determines

output ripple voltage. To get low ESR takes volume, so

physically smaller capacitors have higher ESR. The ESR

range for typical LT3437 applications is 0.05Ω to 0.2Ω. A

typical output capacitor is an AVX type TPS, 100µF at 10V,

with a guaranteed ESR less than 0.1Ω. This is a “D” size

surface mount solid tantalum capacitor. TPS capacitors

are specially constructed and tested for low ESR, so they

give the lowest ESR for a given volume. The value in

microfarads is not particularly critical, and values from

22µF to greater than 500µF work well, but you cannot

cheat Mother Nature on ESR. If you find a tiny 22µF solid

tantalum capacitor, it will have high ESR and output ripple

voltage could be unacceptable. Table 2 shows some

typical solid tantalum surface mount capacitors.

I_OUT

V

IN

I_RIPPLE(RMS)

=

V_OUTV – V_OUT

(

IN

)

Ceramiccapacitorsareidealforinputbypassing.At200kHz

switching frequency input capacitor values in the range of

2.2µF to 10µF are suitable for most applications. If opera-

tionisrequiredclosetotheminimuminputrequiredbythe

LT3437, a larger value may be required. This is to prevent

excessive ripple causing dips below the minimum operat-

ing voltage resulting in erratic operation.

Input voltage transients caused by input voltage steps, or

by hot plugging the LT3437 to a pre-powered source such

as a wall adapter, can exceed maximum V_INratings. The

sudden application of input voltage will cause a large

surge of current in the input leads that will store energy in

the parasitic inductance of the leads. This energy will

3437f

10

LT3437

W U U

APPLICATIO S I FOR ATIO

U

Table 2. Surface Mount Solid Tantalum Capacitor ESR

may still affect the proper operation of the regulator. A

filter capacitor C_Fin parallel with the R_C/C_Cnetwork, along

with a small feedforward capacitor C_FB, is suggested to

control possible ripple at the V_Cpin. The LT3437 can be

stabilized using a 100µF ceramic output capacitor and V_C

component values of C_C= 1500nF, R_C= 25k, C_F= 330pF

and C_FB=27pF.

and Ripple Current

E CASE SIZE

AVX TPS

ESR MAX (Ω)

RIPPLE CURRENT (A)

0.1 to 0.3

0.7 to 1.1

D CASE SIZE

AVX TPS

0.1 to 0.3

0.2

0.7 to 1.1

0.5

C CASE SIZE

AVX TPS

OUTPUT RIPPLE VOLTAGE

Many engineers have heard that solid tantalum capacitors

are prone to failure if they undergo high surge currents.

This is historically true, and type TPS capacitors are

speciallytestedforsurgecapability,butsurgeruggedness

is not a critical issue with the output capacitor. Solid

tantalum capacitors fail during very high turn-on surges

which do not occur at the output of regulators. High

discharge surges, such as when the regulator output is

dead shorted, do not harm the capacitors.

Figure 3 shows a typical output ripple voltage waveform

for the LT3437. Ripple voltage is determined by the

impedance of the output capacitor and ripple current

through the inductor. Peak-to-peak ripple current through

the inductor into the output capacitor is:

V_OUTV – V_OUT

(

IN

)

I_P-P

=

V

L f

(

^IN

)( )(

)

Unlike the input capacitor RMS, ripple current in the

output capacitor is normally low enough that ripple cur-

rent rating is not an issue. The current waveform is

triangular with a typical value of 30mA_RMS. The formula to

calculate this is:

For high frequency switchers the ripple current slew rate

is also relevant and can be calculated from:

di

dt

V

IN

L

=

Output capacitor ripple current (RMS)

0.29 V_OUTV – V_OUT

Peak-to-peak output ripple voltage is the sum of a triwave

created by peak-to-peak ripple current times ESR and a

square wave created by parasitic inductance (ESL) and

ripple current slew rate. Capacitive reactance is assumed

to be small compared to ESR or ESL.

(

)( ^IN

)

I_P-P

12

I_RIPPLE(RMS)

=

L f V

( )( )( ^IN

)

CERAMIC CAPACITORS

di

dt

V_RIPPLE= I_P-PESR + ESL

(

)(

) (

)

Higher value, lower cost ceramic capacitors are now

becoming available. They are generally chosen for their

good high frequency operation, small size and very low

ESR(effectiveseriesresistance).LowESRreducesoutput

ripple voltage but also removes a useful zero in the loop

frequency response, common to tantalum capacitors. To

compensate for this, a resistor R_Ccan be placed in series

with the V_Ccompensation capacitor C_C(Figure 10). Care

must be taken, however, since this resistor sets the high

frequency gain of the error amplifier, including the gain at

the switching frequency. If the gain of the error amplifier

is high enough at the switching frequency, output ripple

voltage (although smaller for a ceramic output capacitor)

Example: with V_IN= 12V, V_OUT= 3.3V, L = 100µH, ESR =

0.075Ω, ESL = 10nH:

3.3 12 – 3.3

(

)(

)

I_P-P

di

=

= 0.120A

12 100e − 6 200e3

( )(

)(

)

12

=

= 0.12e6

dt 100e – 6

V_RIPPLE= (0.120A)(0.075) + (10e – 9)(0.12e6)

= 0.009 + 0.0012 = 10.2mV_P-P

3437f

11

LT3437

W U U

U

APPLICATIO S I FOR ATIO

V_OUT

10mV/DIV

100µF TANTALUM

ESR 75mΩ

Discontinuous operation occurs when:

V_OUTV – V_OUT

(

IN

)

I_OUT(DIS)

≤

V_OUT

10mV/DIV

100µF CERAMIC

2(L)(f)(V )

IN

For V_OUT= 5V, V_IN= 8V and L = 68µH:

V_SW

10V/DIV

5 8 – 5

( )(

)

V

_IN= 12V

1µs/DIV

3437 F03

I_OUT(MAX)= 0.5 –

V_OUT= 3.3V

I_LOAD= 500mA

L = 100µH

2 68e – 6 200e3 8

(

)(

)( )

= 0.5 – 0.069 = 0.431A

Figure 3. LT3437 Ripple Voltage Waveform

Note that there is less load current available at the higher

inputvoltagebecauseinductorripplecurrentincreases.At

V_IN= 15V, duty cycle is 33% and for the same set of

conditions:

MAXIMUM OUTPUT LOAD CURRENT

Maximum load current for a buck converter is limited by

the maximum switch current rating (I_PK). The current

ratingfortheLT3437is500mA. Unlikemostcurrentmode

converters, the LT3437 maximum switch current limit

does not fall off at high duty cycles. Most current mode

converters suffer a drop off of peak switch current for duty

cycles above 50%. This is due to the effects of slope

compensation required to prevent subharmonic oscilla-

tions in current mode converters. (For detailed analysis,

see Application Note 19.)

5 15 – 5

( )(

)

I_OUT(MAX)= 0.5 –

2 68e – 6 200e3 15

(

)(

)

= 0.5 – 0.121= 0.379A

To calculate actual peak switch current in continuous

mode with a given set of conditions, use:

The LT3437 is able to maintain peak switch current limit

over the full duty cycle range by using patented circuitry to

cancel the effects of slope compensation on peak switch

current without affecting the frequency compensation it

provides.

V_OUTV – V_OUT

(

IN

)

I_SW(PK)= I_OUT

+

2 L f V

( )( )( ^IN

)

Ifasmallinductorischosenwhichresultsindiscontinuous

mode operation over the entire load range, the maximum

load current is equal to:

Maximum load current would be equal to maximum

switch current for an infinitely large inductor, but with

finite inductor size, maximum load current is reduced by

one-half peak-to-peak inductor current. The following

formula assumes continuous mode operation, implying

I_PK²2 f L V

( )( )( ^IN

)

I_OUT(MAX)

=

2 V_OUTV – V_OUT

(

)( ^IN

)

that the term on the right (I_P-P/2) is less than I_OUT

.

V_OUTV – V_OUT

(

)( ^IN

)

CHOOSING THE INDUCTOR

I_P-P

2

I_OUT(MAX)= I_PK

–

= I_PK–

2 L f V

For most applications the output inductor will fall in the

range of 68µH to 220µH. Lower values are chosen to

reduce physical size of the inductor. Higher values allow

( )( )( ^IN

)

3437f

12

LT3437

W U U

APPLICATIO S I FOR ATIO

U

more output current because they reduce peak current

seen by the LT3437 switch, which has a 0.5A limit. Higher

values also reduce output ripple voltage and reduce core

loss.

V_IN= maximum input voltage

f = switching frequency, 200kHz

3. Decide if the design can tolerate an “open” core geom-

etry like a rod or barrel, which has high magnetic field

radiation, orwhetheritneedsaclosedcorelikeatoroid,

to prevent EMI problems. This is a tough decision

because the rods or barrels are temptingly cheap and

small, and there are no helpful guidelines to calculate

when the magnetic field radiation will be a problem.

When choosing an inductor you might have to consider

maximum load current, core and copper losses, allow-

able component height, output voltage ripple, EMI, fault

current in the inductor, saturation and of course cost.

The following procedure is suggested as a way of han-

dling these somewhat complicated and conflicting

requirements.

4. After making an initial choice, consider the secondary

things like output voltage ripple, second sourcing, etc.

Use the experts in Linear Technology’s applications

department if you feel uncertain about the final choice.

They have experience with a wide range of inductor

types and can tell you about the latest developments in

low profile, surface mounting, etc.

1. Choose a value in microhenries such thatthe maximum

load current plus half of the inductor ripple current is

less than the minimum peak switch current (I_PK).

Choosing a small inductor with lighter loads may result

in discontinuous mode of operation, but the LT3437 is

designed to work well in either mode.

Table 3. Inductor Selection Criteria

Assume that the average inductor current is equal to

load current and decide whether or not the inductor

must withstand continuous fault conditions. If maxi-

mum load current is 0.25A, for instance, a 0.25A

inductor may not survive a continuous minimum peak

switch current overload condition.

VENDOR/

PART NO.

VALUE

H)

I

DCR

(Ohms)

HEIGHT

(mm)

DC(MAX)

(mA)

(

µ

Coiltronics

UP1B-101

100

150

220

530

460

380

1.11

1.61

1.96

5.0

UP1B-151

UP2B-221

For applications with a duty cycle above 50%, the

inductor value should be chosen to obtain an inductor

ripple current of less than 40% of the peak switch

current.

Coilcraft

D01605T-473MX

D01605T-104MX

D03308P-154

D03308P-224

Sumida

47

450

300

600

500

1.1

2.3

1.8

3.0

100

150

220

0.94

1.6

2. Calculate peak inductor current at full load current to

ensure that the inductor will not saturate. Peak current

canbesignificantlyhigherthanoutputcurrent,especially

with smaller inductors and lighter loads, so do not omit

thisstep.Powderedironcoresareforgivingbecausethey

saturate softly, whereas ferrite cores saturate abruptly.

Other core materials fall somewhere in between. The

following formula assumes continuous mode of opera-

tion, but it errs only slightly on the high side for discon-

tinuous mode, so it can be used for all conditions.

CDRH4D28-470

CDRH4D28-101

CDRH5D28-101

47

480

290

420

0.387

1.02

3.0

100

0.520

Short-Circuit Considerations

The LT3437 is a current mode controller. It uses the V_C

node voltage as an input to a current comparator which

turns off the output switch on a cycle-by-cycle basis as

this peak current is reached. The internal clamp on the V_C

node, nominally 1.5V, then acts as an output switch peak

current limit. This action becomes the switch current limit

specification. The maximum available output power is

V_OUTV – V_OUT

(

IN

)

I_PEAK= I_OUT

+

2 f L V

( )( )( ^IN

)

then determined by the switch current limit.

3437f

13

LT3437

W U U

U

APPLICATIO S I FOR ATIO

A potential controllability problem could occur under SOFT-START

short-circuit conditions. If the power supply output is

Forapplicationswhere[V_IN/(V_OUT+V_F)]>10orlargeinput

short circuited, the feedback amplifier responds to the low

output voltage by raising the control voltage, V_C, to its

peak current limit value. Ideally, the output switch would

be turned on, and then turned off as its current exceeded

thevalueindicatedbyV_C.However,thereisfiniteresponse

time involved in both the current comparator and turn-off

of the output switch. This results in a minimum on time

surge currents cannot be tolerated, the LT3437 soft-start

feature should be used to control the output capacitor

charge rate during start-up, or during recovery from an

output short circuit, thereby adding additional control

over peak inductor current. The soft-start function limits

the switch current via the V_Cpin to maintain a constant

voltageramprate(dV/dt)attheoutputcapacitor.Acapaci-

tor(C1inFigure2)fromtheC_SSpintotheregulatedoutput

voltage determines the output voltage ramp rate. When

the current through the C_SScapacitor exceeds the C_SS

threshold (I_CSS), the voltage ramp of the output capacitor

islimitedbyreducingtheV_Cpinvoltage.TheC_SSthreshold

is proportional to the FB voltage (see Typical Performance

Characteristics) and is defeated for FB voltages greater

than0.9V(typical). TheoutputdV/dt canbeapproximated

by:

t_ON(MIN).When combined with the large ratio of V_INto

(V_F+ I • R), the diode forward voltage plus inductor I • R

voltage drop, the potential exists for a loss of control.

Expressed mathematically the requirement to maintain

control is:

V

F

+ I•R

V

IN

f • t_ON

where:

≤

f = switching frequency

dV I_CSS

t_ON= switch on time

=

dt C_SS

V_F= diode forward voltage

V_IN= Input voltage

but actual values will vary due to start-up load conditions,

compensation values and output capacitor selection.

I • R = inductor I • R voltage drop

If this condition is not observed, the current will not be

limited at I_PKbut will cycle-by-cycle ratchet up to some

higher value. Using the nominal LT3437 clock frequency

of 200kHz, a V_INof 40V and a (V_F+ I • R) of say 0.7V, the

maximum t_ONto maintain control would be approximately

90ns, an unacceptably short time.

C_SS= GND

C_SS= 0.1µF

C_SS= 0.01µF

V_OUT

1V/DIV

The solution to this dilemma is to slow down the oscillator

to allow the current in the inductor to drop to a sufficiently

low value such that the current does not continue to

ratchet higher. When the FB pin voltage is abnormally low,

thereby indicating some sort of short-circuit condition,

the oscillator frequency will be reduced. Oscillator fre-

quencyisreducedbyafactorof10whentheFBpinvoltage

is below 0.4V and increases linearly to its typical value of

200kHz at a FB voltage of 0.95V (see Typical Performance

Characteristics). These oscillator frequency reductions

during short-circuit conditions allow the LT3437 to main-

tain current control

V_IN= 12V

1ms/DIV

3437 F04

C_OUT= 100µF

I_LOAD= 200mA

Figure 4. V

dV/dt

OUT

Burst Mode OPERATION

To enhance efficiency at light loads, the LT3437 automati-

cally switches to Burst Mode operation which keeps the

output capacitor charged to the proper voltage while

minimizing the input quiescent current. During Burst

Mode operation, the LT3437 delivers short bursts of

3437f

14

LT3437

W U U

APPLICATIO S I FOR ATIO

U

200

current to the output capacitor followed by sleep periods

where the output power is delivered to the load by the

output capacitor. In addition, V_INand BIAS quiescent

currents are reduced to typically 25µA and 150µA, respec-

tively, duringthesleeptime. Astheloadcurrentdecreases

towards a no load condition, the percentage of time that

the LT3437 operates in sleep mode increases and the

average input current is greatly reduced, resulting in

higher efficiency.

V

OUT

= 3.3V

180

160

140

120

100

80

60

40

20

0

The minimum average input current depends on the V_INto

V_OUTratio, V_Cfrequency compensation, feedback divider

network and Schottky diode leakage. It can be approxi-

mated by the following equation:

0

10 20 30 40 50 60 70 80

INPUT VOLTAGE (V)

3435 F05

Figure 5. I vs V

Q

IN

If Burst Mode operation is undesirable, it can be defeated

by placing 2V or greater on the SYNC pin. When Burst

Modeoperationisdefeated, outputrippleatlightloadswill

be reduced at the expense of light load efficiency.

I

_BIASS+ I_FB+ I_S

⎛

⎞

(

)

V_OUT

I

_IN(AVG)≅ I_VINS+ I_SHDN+

⎜

⎟

V

⎝

⎠

η

( )

IN

where

I_VINS= input pin current in sleep mode

V_OUT= output voltage

V_IN= input voltage

I_BIASS= BIAS pin current in sleep mode

I_FB= feedback network current

I_S= catch diode reverse leakage at V_OUT

CATCH DIODE

The catch diode carries load current during the SW off

time. The average diode current is therefore dependent on

the switch duty cycle. At high input to output voltage

ratios, the diode conducts most of the time. As the ratio

approachesunity, thediodeconductsonlyasmallfraction

of the time. The most stressful condition for the diode is

when the output is short circuited. Under this condition,

thediodemustsafelyhandleI_PEAKatmaximumdutycycle.

η = low current efficiency (non Burst Mode operation)

Example: For V_OUT= 3.3V, V_IN= 12V

To maximize high and low load current efficiency, a fast

switching diode with low forward drop and low reverse

leakage should be used. Low reverse leakage is critical to

maximize low current efficiency since its value over tem-

perature can potentially exceed the magnitude of the

LT3437 supply current. Low forward drop is critical for

high current efficiency since the loss is proportional to

forward drop.

3.3

12

⎛

⎞

I_IN(AVG)≅ 25µA + 5µA +

⎜

⎝

⎟

⎠

150µA + 12.5µA + 0.5µA

(

)

0.75

(

)

= 25µA + 5µA + 60µA = 90µA

During the sleep portion of the Burst Mode cycle, the V_C

pin voltage is held just below the level needed for normal

operation to improve transient response. See the Typical

Performance Characteristics section for burst and tran-

sient response waveforms.

These requirements result in the use of a Schottky type

diode. DC switching losses are minimized due to its low

forward voltage drop, and AC behavior is benign due to its

lackofasignificantreverserecoverytime.Schottkydiodes

are generally available with reverse voltage ratings of 60V,

andeven100V, andarepricecompetitivewithothertypes.

3437f

15

LT3437

W U U

U

APPLICATIO S I FOR ATIO

OPTIONAL

The use of so-called “ultrafast” recovery diodes is gener-

ally not recommended. When operating in continuous

mode, the reverse recovery time exhibited by “ultrafast”

diodes will result in a slingshot type effect. The power

internalswitchwillrampupV_INcurrentintothediodeinan

attempt to get it to recover. When the diode has finally

turned off, some tens of nanoseconds later, the V_SWnode

voltage ramps up at an extremely high dV/dt, perhaps 5V

to even 10V/ns! With real world lead inductances, the V_SW

node can easily overshoot the V_INrail. This can result in

poor RFI behavior, and if the overshoot is severe enough,

damage the IC itself.

V

BOOST

SW

V

OUT

IN

LT3437

GND

V

– V = V

SW OUT

= V + V

IN OUT

BOOST

BOOST(MAX)

V

(6a)

V

BOOST

SW

IN

LT3437

V

GND

OUT

BOOST PIN

For most applications, the boost components are a 0.1µF

capacitor and a BAS21 diode. The anode is typically

connected to the regulated output voltage, to generate a

voltage approximately V_OUTabove V_INto drive the output

stage (Figure 6a). However, the output stage discharges

the boost capacitor during the on time of the switch. The

output driver requires at least 2.5V of headroom through-

out this period to keep the switch fully saturated. If the

outputvoltageislessthan3.3V, itisrecommendedthatan

alternate boost supply is used. The boost diode can be

connected to the input (Figure 6b), but care must be taken

to prevent the boost voltage (V_BOOST= V_IN• 2) from

exceeding the BOOST pin absolute maximum rating. The

additional voltage across the switch driver also increases

power loss and reduces efficiency. If available, an inde-

pendent supply can be used to generate the required

BOOST voltage (Figure 6c). Tying BOOST to V_INor an

independent supply may reduce efficiency, but it will

reduce the minimum V_INrequired to start-up with light

loads. If the generated BOOST voltage dissipates too

much power at maximum load, the BOOST voltage the

LT3437 sees can be reduced by placing a Zener diode in

series with the BOOST diode (Figure 6a option).

V

– V = V

SW IN

BOOST

= 2V

BOOST(MAX)

IN

(6b)

V

BOOST

V

IN

DC

LT3437

GND

SW

OUT

D

SS

3437 F06

V

– V = V

SW DC

= V + V

DC IN

BOOST

V

BOOST(MAX)

(6c)

Figure 6. BOOST Pin Configurations

ripple. The boost capacitor value could be reduced under

less demanding conditions, but this will not improve

circuitoperationorefficiency.Underlowinputvoltageand

low load conditions, a higher value capacitor will reduce

discharge ripple and improve start-up operation.

SHUTDOWN FUNCTION AND UNDERVOLTAGE

LOCKOUT

The SHDN pin on the LT3437 controls the operation of the

IC. When the voltage on the SHDN pin is below the 1.2V

shutdown threshold, the LT3437 is placed in a “zero”

supply current state. Driving the SHDN pin above the

shutdown threshold enables normal operation. The SHDN

pin has an internal sink current with a typical value of 5µA.

A 0.1µF boost capacitor is recommended for most appli-

cations. Almost any type of film or ceramic capacitor is

suitable, but the ESR should be <1Ω to ensure it can be

fully recharged during the off time of the switch. The

capacitor value is derived from worst-case conditions of

4700ns on time, 11mA boost current and 0.7V discharge

In addition to the shutdown feature, the LT3437 has an

undervoltage lockout function. When the input voltage is

3437f

16

LT3437

W U U

APPLICATIO S I FOR ATIO

U

below 2.4V, switching will be disabled. The undervoltage

lockout threshold doesn’t have any hysteresis and is

mainly used to insure that all internal voltages are at the

correct level before switching is enabled. If an undervolt-

age lockout function with hysteresis is needed to limit

inputcurrentatlowV_INtoV_OUTratios, refertoFigure7and

the following:

See the Typical Performance Characteristics section for

graphs of SHDN and V_INcurrents verses input voltage.

SYNCHRONIZING

Oscillatorsynchronizationtoanexternalinputisachieved

by connecting a TTL logic-compatible square wave with a

duty cycle between 25% and 75% to the LT3437 SYNC

pin. The synchronizing range is equal to initial operating

frequency up to 700kHz. This means that minimum

practical sync frequency is equal to the worst-case high

self-oscillating frequency (240kHz), not the typical oper-

ating frequency of 200kHz. Caution should be used when

synchronizing above 300kHz, because at higher sync

frequencies the amplitude of the internal slope compen-

sation used to prevent subharmonic switching is re-

duced. Thistypeofsubharmonicswitchingonlyoccursat

input voltages less than twice output voltage. Higher

inductor values will tend to eliminate this problem. See

Frequency Compensation section for a discussion of an

entirely different cause of subharmonic switching before

assuming that the cause is insufficient slope compensa-

tion. Application Note 19 has more details on the theory

of slope compensation.

V

V_SHDN

R2

⎛

⎝

⎞

⎠

SHDN

R3

V_UVLO= R1

+

+ I_SHDN+ V

⎟

SHDN

⎜

V_OUTR1

(

)

V_HYST

=

R3

LT3437

V

IN

2

+

V

IN

COMP

–

2.4V

1.3V

ENABLE

R1

R3

SHDN

V

OUT

10

+

–

SHDN

COMP

5µA

R2

If the FB pin voltage is below 0.9V (power-up or output

short-circuit conditions), the sync function is disabled.

This allows the frequency foldback to operate to avoid

hazardous conditions for the SW pin.

3437 F07

Figure 7. Undervoltage Lockout

R1shouldbechosentominimizequiescentcurrentduring

normal operation by the following equation:

If a synchronization signal or logic-level above 2V is

presentattheSYNCpin,BurstModeoperationisdisabled.

Burst Mode operation can be enabled or disabled on the

fly. If no synchronization or Burst Mode defeat is required,

this pin should be connected to ground.

V – 2V

IN

R1=

1.5 I

(

)

(

)

SHDN(TYP)

Example:

LAYOUT CONSIDERATIONS

12 – 2

R1=

= 1.3MΩ

As with all high frequency switchers, when considering

layout, care must be taken in order to achieve optimal

electrical, thermal and noise performance. For maximum

efficiency, switch rise and fall times are typically in the

nanosecond range. To prevent noise both radiated and

conducted, the high speed switching current path,

shown in Figure 8, must be kept as short as possible. This

is implemented in the suggested layouts of Figure 9.

Shortening this path will also reduce the parasitic trace

1.5 5µA

(

)

5 1.3MΩ

(

)

R3 =

= 6.5MΩ (Nearest 1% 6.49MΩ)

1

1.3

R2 =

7 – 1.3

1.3MΩ

= 408k (Nearest 1% 412k)

1.3

– 1µA –

6.49MΩ

3437f

17

LT3437

W U U

U

APPLICATIO S I FOR ATIO

inductance of approximately 25nH/inch. At switch off, this

parasitic inductance produces a flyback spike across the

LT3437 switch. When operating at higher currents and

input voltages, with poor layout, this spike can generate

voltages across the LT3437 that may exceed its absolute

maximum rating. A ground plane should always be used

under the switcher circuitry to prevent interplane coupling

and overall noise.

The V_Cand FB components should be kept as far away as

possible from the switch and boost nodes. The LT3437

pinout has been designed to aid in this. The ground for

these components should be separated from the switch

current path. Failure to do so will result in poor stability or

subharmonic oscillation.

Board layout also has a significant effect on thermal

resistance. Pin 4/Pin 10 and the exposed die pad, Pin 11/

Pin 17, are connected by a continuous copper plate that

runs under the LT3437 die. This is the best thermal path

for heat out of the package. Reducing the thermal resis-

tance from Pin 4 and the exposed pad onto the board will

reduce die temperature and increase the power capability

of the LT3437. This is achieved by providing as much

copper area as possible around the exposed pad. Adding

multiple solder filled feedthroughs, under and around this

pad, to an internal ground plane will also help. Similar

treatment to the catch diode and coil terminations will

reduce any additional heating effects.

LT3437

L1

V

OUT

V

IN

SW

V

IN

+

HIGH

C2

FREQUENCY

CIRCULATION

PATH

D1

C1 LOAD

3437 F08

Figure 8. High Speed Switching Path

L1

THERMAL CALCULATIONS

Power dissipation in the LT3437 chip comes from four

sources: switch DC loss, switch AC loss, boost circuit

current,andinputquiescentcurrent.Thefollowingformu-

las show how to calculate each of these losses. These

formulasassumecontinuousmodeoperation, andshould

notbeusedforcalculatingefficiencyatlightloadcurrents.

D1

C1

C2

3437 F09a

FE PACKAGE TOPSIDE METAL

Switch loss:

2

R_SWI_OUTV_OUT

(

) (

)

P_SW

=

+ t_EFF1/2 I_OUT

V

f

(

)(

^IN

)( )

C1

V

IN

L1

Boost current loss:

D1

2

V

(

OUT

I

/30

)

(

)

OUT

P

=

BOOST

V

IN

C2

Quiescent current loss:

P_Q= V_IN(500µA) + V_OUT(800µA)

R_SW= switch resistance (≈1 when hot )

t_EFF= effective switch current/voltage overlap time

3437 F09b

DD PACKAGE TOPSIDE METAL

Figure 9. Suggested Layouts

3437f

18

LT3437

W U U

APPLICATIO S I FOR ATIO

U

(t_r+ t_f+ t_IR+ t_IF)

that AC switching loss is proportional to both operating

frequency and output current. The majority of AC switch-

ing loss is also proportional to the square of input voltage.

t_r= (V_IN/0.6)ns

t_f= (V_IN/2)ns

For example, while the combination of V_IN= 40V, V_OUT

=

t_IR= t_IF= (I_OUT/0.05)ns

f = switch frequency

5V at 700mA and f_OSC= 200kHz may be easily achievable,

simultaneouslyraisingV_INto80Vandf_OSCto700kHzisnot

possible. Nevertheless, input voltage transients up to 80V

can usually be accommodated, assuming the resulting

increase in internal dissipation is of insufficient time dura-

tion to raise die temperature significantly.

Example: with V_IN= 40V, V_OUT= 5V and I_OUT= 250mA:

1 0.25 ²5

( )(

) ( )

+ 92 1/2 0.25 40 200e3

P

SW

=

( )( )

(

)( )(

)

40

A second consideration is controllability. A potential limi-

0.008 + 0.092 = 0.1W

tation occurs with a high step-down ratio of V_INto V_OUT

,

5 ²0.25/30

( )

(

)

= 0.005W

asthisrequiresacorrespondinglynarrowminimumswitch

on time. An approximate expression for this (assuming

continuous mode operation) is given as follows:

P

=

BOOST

40

P = 40 0.0005 + 5 0.0008 = 0.024W

(

)

(

)

Q

t_ON(MIN)= (V_OUT+ V_F)/V_IN(f_OSC

where:

)

Total power dissipation is:

P_TOT= 0.1 + 0.065 + 0.024 = 0.13W

V_IN= input voltage

Thermal resistance for the LT3437 package is influenced

by the presence of internal or backside planes. With a full

plane under the package, thermal resistance will be about

45°C for the FE and DD packages. No plane will increase

resistancetoabout150°C/W.Tocalculatedietemperature,

use the proper thermal resistance number for the desired

package and add in worst-case ambient temperature:

V_OUT= output voltage

V_F= Schottky diode forward drop

f_OSC= switching frequency

A potential controllability problem arises if the LT3437 is

called upon to produce an on time shorter than it is able to

produce. Feedback loop action will lower, then reduce, the

V_Ccontrol voltage to the point where some sort of cycle-

skipping or Burst Mode behavior is exhibited.

T_J= T_A+ Q_JA(P_TOT

)

With the DD package (Q_JA= 45°C/W) at an ambient

temperature of 70°C:

In summary:

T_J= 70 + 45(0.1) = 74.5°C

1. Be aware that the simultaneous requirements of high

V_IN, high I_OUTand high f_OSCmay not be achievable in

practice due to internal dissipation. The Thermal Con-

siderations section offers a basis to estimate internal

power.Inquestionablecases,aprototypesupplyshould

be built and exercised to verify acceptable operation.

Input Voltage vs Operating Frequency Considerations

TheabsolutemaximuminputsupplyvoltagefortheLT3437

is specified at 80V. This is based solely on internal semi-

conductor junction breakdown effects. Due to internal

power dissipation, the actual maximum V_INachievable in

a particular application may be less than this.

2. The simultaneous requirements of high V_IN, low V_OUT

and high f_OSCcan result in an unacceptably short mini-

mumswitchontime. Cycleskippingand/orBurstMode

behavior will result causing an increase in output volt-

age ripple while maintaining the correct output voltage.

A detailed theoretical basis for estimating internal power

loss is given in the section Thermal Considerations. Note

3437f

19

LT3437

W U U

U

APPLICATIO S I FOR ATIO

FREQUENCY COMPENSATION

Azerocanbeaddedintotheloopbyplacingaresistor(R_C)

attheV_Cpininserieswiththecompensationcapacitor,C_C,

or by placing a capacitor (C_FB) between the output and the

FB pin.

Before starting on the theoretical analysis of frequency

response,thefollowingshouldberemembered—theworse

the board layout, the more difficult the circuit will be to

stabilize. This is true of almost all high frequency analog

circuits. Read the Layout Considerations section first.

Common layout errors that appear as stability problems

aredistantplacementofinputdecouplingcapacitorand/or

catch diode, and connecting the V_Ccompensation to a

ground track carrying significant switch current. In addi-

tion, the theoretical analysis considers only first order

non-ideal component behavior. For these reasons, it is

important that a final stability check is made with produc-

tion layout and components.

When using R_C, the maximum value has two limitations.

First, thecombinationofoutputcapacitorESRandR_Cmay

stopthelooprollingoffaltogether. Second, iftheloopgain

is not rolled off sufficiently at the switching frequency,

output ripple will perturb the V_Cpin enough to cause

unstable duty cycle switching, similar to subharmonic

oscillations. If needed, an additional capacitor (C_F) can be

addedacrosstheR_C/C_CnetworkfromtheV_Cpintoground

to further suppress V_Cripple voltage.

With a tantalum output capacitor, the LT3437 already

includes a resistor (R_C) and filter capacitor (C_F) at the V_C

pin (see Figures 10 and 11) to compensate the loop over

the entire V_INrange (to allow for stable pulse skipping for

high V_IN-to-V_OUTratios ≥ 10). A ceramic output capacitor

canstillbeusedwithasimpleadjustmenttotheresistorR_C

for stable operation (see Ceramic Capacitors section for

stabilizingLT3430). Ifadditionalphasemarginisrequired,

a capacitor (C_FB) can be inserted between the output and

FB pin, but care must be taken for high output voltage

applications. Sudden shorts to the output can create

unacceptably large negative transients on the FB pin.

The LT3437 uses current mode control. This alleviates

many of the phase shift problems associated with the

inductor. The basic regulator loop is shown in Figure 10.

The LT3437 can be considered as two g_mblocks, the error

amplifier and the power stage.

Figure 11 shows the overall loop response. At the V_Cpin,

the frequency compensation components used are:

R_C= 25k, C_C= 1500pF and C_F= 330pF. The output

capacitor used is a 100µF, 10V tantalum capacitor with

typical ESR of 100mΩ.

TheESRofthetantalumoutputcapacitorprovidesauseful

zerointheloopfrequencyresponseformaintainingstabil-

ity. This ESR, however, contributes significantly to the

ripple voltage at the output (see Output Ripple Voltage in

the Applications Information section). It is possible to

reduce capacitor size and output ripple voltage by replac-

ing the tantalum output capacitor with a ceramic output

capacitor because of its very low ESR. The zero provided

by the tantalum output capacitor must now be reinserted

back into the loop. Alternatively, there may be cases

where, even with the tantalum output capacitor, an addi-

tional zero is required in the loop to increase phase margin

for improved transient response.

For V_IN-to-V_OUTratios < 10, higher loop bandwidths are

possiblebyreadjustingthefrequencycompensationcom-

ponents at the V_Cpin.

When checking loop stability, the circuit should be oper-

ated over the application’s full voltage, current and tem-

peraturerange.Properloopcompensationmaybeobtained

by empirical methods, as described in Application Notes

19 and 76.

3437f

20

LT3437

W U U

APPLICATIO S I FOR ATIO

U

LT3437

CURRENT MODE

SW

FB

OUTPUT

POWER STAGE

Ω

g

= 1

m

C

R1

R2

FB

Ω

g

= 650µ

m

–

+

V

C

ERROR

AMP

ESR

R

1.6M

C

1.25V

C

OUT

C

F

C

3437 F13

Figure 10. Model for Loop Response

100

80

0

V

C

= 3.3V

OUT

F

= 100µF, 0.1Ω

–20

= 330pF

R

C

= 25k

–40

C

= 1500pF

60

C

–60

I

= 250mA

LOAD

40

–80

–100

–120

–140

–160

–180

20

0

–20

–40

10

100

1k

10k

100k

1M

FREQUENCY (Hz)

3437 F12

Figure 11. Overall Loop Response

3437f

21

LT3437

U

PACKAGE DESCRIPTIO

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699)

0.675 ±0.05

3.50 ±0.05

2.15 ±0.05 (2 SIDES)

1.65 ±0.05

PACKAGE

OUTLINE

0.25 ± 0.05

0.50

BSC

2.38 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

R = 0.115

TYP

6

0.38 ± 0.10

10

3.00 ±0.10

(4 SIDES)

1.65 ± 0.10

(2 SIDES)

PIN 1

TOP MARK

(SEE NOTE 6)

(DD10) DFN 1103

5

1

0.25 ± 0.05

0.50 BSC

0.75 ±0.05

0.200 REF

2.38 ±0.10

(2 SIDES)

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).

CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

3437f

22

LT3437

U

PACKAGE DESCRIPTIO

FE Package

16-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663)

Exposed Pad Variation BC

4.90 – 5.10*

(.193 – .201)

3.58

(.141)

3.58

(.141)

16 1514 13 12 1110

9

6.60 ±0.10

4.50 ±0.10

2.94

(.116)

6.40

(.252)

BSC

SEE NOTE 4

2.94

(.116)

0.45 ±0.05

1.05 ±0.10

0.65 BSC

5

7

8

1

2

3

4

6

RECOMMENDED SOLDER PAD LAYOUT

1.10

(.0433)

MAX

4.30 – 4.50*

(.169 – .177)

0.25

REF

0° – 8°

0.65

(.0256)

BSC

0.09 – 0.20

(.0035 – .0079)

0.50 – 0.75

(.020 – .030)

0.05 – 0.15

(.002 – .006)

0.195 – 0.30

FE16 (BC) TSSOP 0204

(.0077 – .0118)

TYP

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

FOR EXPOSED PAD ATTACHMENT

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

MILLIMETERS

(INCHES)

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

3437f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

23

LT3437

U

TYPICAL APPLICATIO

14V to 3.3V Step-Down Converter with

100µA No Load Quiescent Current

Supply Current vs

Input Voltage

Efficiency and Power Loss

vs Load Current

200

180

160

140

120

100

80

500

450

400

350

300

250

200

150

100

50

100

90

80

70

60

50

40

30

20

10

0

V

T

= 12V

V

IN

OUT

= 25°C

OUT

= 3.3V

3.3V

V

BOOST

SW

IN

V

IN

2.2µF

100V

CER

100µH

400mA

0.1µF

A

BAS21

4.5V TO

80V*

SHDN

LT3437

EFFICIENCY

0.1µF

10MQ100N

V

C

SS

V

BIAS

330pF

1500pF

25k

165k

100k

27pF

100µF

6.3V

TANT

SYNC

GND

FB

60

POWER LOSS

40

20

3437 TA04

*FOR INPUT VOLTAGES ABOVE 60V SOME RESTRICTIONS MAY APPLY

0

1000

0

10 20 30 40 50 60 70 80

0.1

1

10

100

INPUT VOLTAGE (V)

LOAD CURRENT (mA)

3435 TA05

3437 G01

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LT1765

25V, 3A (I ), 1.25MHz, High Efficiency Step-Down DC/DC

Converter

V : 3V to 25V, V

SO-8, TSSOP16E

= 1.20V, I = 1mA, I < 15µA,

OUT(MIN) Q SD

OUT

IN

LT1766

LT1767

LT1776

LT1936

LT1940

LT1956

LT1976

LT1977

LT3010

LT3430

LT3431

60V, 1.2A (I ), 200kHz, High Efficiency Step-Down DC/DC

Converter

V : 5.5V to 60V, V

= 1.20V, I = 2.5mA,

OUT(MIN) Q

OUT

IN

I

< 25µA, TSSOP16/E

SD

25V, 1.5A (I ), 1.25MHz, High Efficiency Step-Down DC/DC

V : 3V to 25V, V

= 1.20V, I = 1mA, I < 6µA,

OUT

IN

OUT(MIN) Q SD

Converter

MS8/E

40V, 550mA (I ), 200kHz, High Efficiency Step-Down DC/DC

V : 7.4V to 40V, V

= 1.24V, I = 3.2mA,

Q

OUT

IN

OUT(MIN)

Converter

I

< 30µA, N8, S8

SD

36V, 1.4A, 500kHz, High Efficiency Step-Down DC/DC Converter

V : 3.6V to 36V, V

= 1.2V, I = 1.8mA,

Q

IN

I

4mA MS8/E

SD

Dual 1.2A (I ), 1.1MHz, High Efficiency Step-Down DC/DC

V : 3V to 25V, V

= 1.2V, I = 3.8mA, TSSOP-16E

OUT

IN

OUT(MIN) Q

Converter

60V, 1.2A (I ), 500kHz, High Efficiency Step-Down DC/DC

V : 5.5V to 60V, V

= 1.20V, I = 2.5mA,

OUT(MIN) Q

OUT

IN

Converter

I

< 25µA, TSSOP16/E

SD

60V, 1.5A (I ), 200kHz, High Efficiency Step-Down DC/DC

V : 3.3V to 60V, I = 100µA, I < 1µA, TSSOP-16E

IN Q SD

OUT

Converter

60V, 1.5A (I ), 500kHz, High Efficiency Step-Down DC/DC

V : 3.3V to 60V, I = 100µA, I < 1µA, TSSOP-16E

IN Q SD

OUT

Converter

80V, 50mA, Low Noise Linear Regulator

V : 1.5V to 80V, V

= 1.28V, I = 30µA, I < 1µA,

Q SD

IN

OUT(MIN)

MS8E

60V, 2.5A (I ), 200kHz, High Efficiency Step-Down DC/DC

V : 5.5V to 60V, V

= 1.20V, I = 2.5mA,

Q

OUT

IN

Converter

I

< 30µA, TSSOP-16E

SD

60V, 2.5A (I ), 500kHz, High Efficiency Step-Down DC/DC

V : 5.5V to 60V, V

= 1.20V, I = 2.5mA,

Q

OUT

IN

Converter

I

< 30µA, TSSOP-16E

SD

LT3433

60V, 400mA (I ), 200kHz/500kHz, Buck-Boost DC/DC Converter

V : 5V to 60V, V : 3.3V to 20V, I = 100µA, TSSOP-16E

IN OUT Q

OUT

LT3434/LT3435

LT3470

60V, 3A (I ), 200kHz, High Efficiency Step-Down DC/DC Converter

V : 3.3V to 60V, I = 100µA, I < 1µA, TSSOP-16E

OUT

IN

Q

SD

40V, 300mA, MicroPower Buck Regulator with Integrated Boost and

Catch Diodes

V : 4V to 40V, V = 1.25V, I = 26µA, ThinSOT

OUT(MIN) Q

IN

LTC3727/LTC3727-1 36V, 500kHz, High Efficiency Step-Down DC/DC Controllers

V : 4V to 36V, V

QFN-32, SSOP-28

= 0.8V, I = 670µA, I < 20µA,

OUT(MIN) Q SD

IN

3437f

LT/TP 0605 500 PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

24

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT3437EFE#PBF
厂家：	Linear
描述：	LT3437 - High Voltage 500mA, 200kHz Step-Down Switching Regulator with 100µA Quiescent Current; Package: TSSOP; Pins: 16; Temperature Range: -40°C to 85°C 稳压器开关高压
文件：	总24页 (文件大小：524K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT3437EFE#PBF [Linear]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E