LT3473A_15 [Linear]
Micropower 1A Boost Converter with Schottky and Output Disconnect;
| 型号： | LT3473A_15 |
| 厂家： | 
Linear |
| 描述： | Micropower 1A Boost Converter with Schottky and Output Disconnect |
| 文件： | 总12页 (文件大小：275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3473/LT3473A
Micropower 1A Boost
Converter with Schottky
and Output Disconnect
U
FEATURES
DESCRIPTIO
The LT®3473/LT3473A are micropower step-up DC/DC
converters with integrated Schottky diode and output
disconnect circuitry in low profile DFN packages. The
small package size, high level of integration and the use of
tiny SMT components yield a solution size of less than
50mm2. Theinternal1Aswitchallowsthedevicetodeliver
25Vatupto80mAfromaLi-Ioncell,whileautomaticBurst
Mode operation maintains efficiency at light load. An
auxiliary reference input (CTRL) allows the user to over-
ride the internal 1.25V feedback reference with any lower
value, allowing full control of the output voltage during
operation. A PGOOD pin sinks current when the output
voltage reaches 90% of final value.
■
Tiny Solution Size
Low Quiescent Current:
■
150µA in Active Mode (VIN = 3.6V, VOUT = 15V,
No Load)
1µA in Shutdown Mode
■
Internal 1A, 36V Switch
■
Integrated Schottky Diode
■
Integrated PNP Output Disconnect
■
Internal Reference Override Pin
■
PGOOD Pin
■
25V at 80mA from 3.6V Input
■
Auxiliary NPNs for Intermediate
Bias Voltages (LT3473A)
Automatic Burst Mode® Operation at Light Load
■
TheLT3473AincludestwoNPNtransistorsforgenerating
intermediate bias voltages from the output and is offered
in a 12-lead (4mm × 3mm) DFN package. The LT3473
does not include these NPNs and is offered in an 8-lead
(3mm × 3mm) package.
■
Constant Switching Frequency: 1.2MHz
Thermal Shutdown
Input Range: 2.2V to 16V
■
■
■
Low Profile (3mm × 3mm) DFN Package (LT3473)
Low Profile (4mm × 3mm) DFN Package (LT3473A)
■
U
The rugged 36V switch and output disconnect circuitry
allow outputs up to 34V to be easily generated in a simple
boost topology.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
APPLICATIO S
■
OLED Bias
CCD Bias
■
U
TYPICAL APPLICATIO
Conversion Efficiency and Power Loss vs Output Current
80
75
70
65
60
55
500
400
300
200
100
0
V
V
= 3.6V
OUT
IN
= 15V
V
OUT
25V
PGOOD
CTRL
OUT
80mA
2.2µF
6.8µH
LT3473
V
IN
3V TO 4.2V
SW
CAP
FB
V
IN
2M
0.47µF
SHDN
100k
GND
4.7µF
3473 TA01a
0.1
1
10
OUTPUT CURRENT (mA)
100
3473 TA01b
3473f
1
LT3473/LT3473A
W W
U W
ABSOLUTE AXI U RATI GS (Note 1)
VIN Voltage ............................................................. 16V
SHDN Voltage .......................................................... 16V
SW Voltage ............................................................. 36V
PGOOD Voltage ...................................................... 36V
CAP Voltage............................................................ 36V
OUT Voltage ........................................................... 36V
FB Voltage .............................................................. 10V
CTRL Voltage.......................................................... 10V
NB1, NB2 Voltage ................................................... 36V
NE1, NE2 Voltage ................................................... 36V
Maximum Junction Temperature ......................... 125°C
Operating Temperature Range (Note 2) .. –40°C to 85°C
Storage Temperature Range ................ –65°C to 125°C
U W
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
ORDER PART
TOP VIEW
TOP VIEW
NUMBER
CAP
OUT
NB1
NE1
NB2
NE2
1
2
3
4
5
6
12 SW
11
10 SHDN
V
CAP
OUT
CTRL
FB
1
2
3
4
8
7
6
5
SW
IN
LT3473EDD
LT3473AEDE
V
IN
9
13
SHDN
9
8
7
PGOOD
CTRL
FB
PGOOD
DD PART MARKING
LBJJ
DE PART MARKING
3473A
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
DE PACKAGE
12-LEAD (4mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/ W
TJMAX = 125°C, θJA = 43°C/ W
EXPOSED PAD (PIN 13) IS GND
MUST BE SOLDERED TO PCB (NOTE 3)
EXPOSED PAD (PIN 9) IS GND
MUST BE SOLDERED TO PCB (NOTE 3)
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VIN = 3V, SHDN = 3V, CTRL = 2V, unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Minimum Operation Voltage
Maximum Operation Voltage
Supply Current
2.2
V
V
16
1
SHDN = 3V, Not Switching
SHDN = 0V
100
0.1
µA
µA
SHDN Voltage to Enable Chip
SHDN Voltage to Disable Chip
SHDN Pin Bias Current
FB Voltage
●
●
1.4
V
V
0.2
2
1.25
0.01
20
µA
V
●
1.235
1.26
FB Voltage Line Regulation
FB Pin Bias Current
3V < V < 16V
%/V
nA
mV
nA
IN
FB = 1.27V
CTRL = 0.5V
CTRL = 1V
CTRL to FB Offset
5
20
CTRL Pin Bias Current
FB Threshold for PGOOD
50
CTRL = 2V
CTRL = 0.5V
1.15
0.40
V
V
PGOOD Current Capacity
●
100
µA
3473f
2
LT3473/LT3473A
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VIN = 3V, SHDN = 3V, CTRL = 2V, unless otherwise specified.
PARAMETER
CONDITIONS
MIN
0.9
88
TYP
1.2
92
MAX
UNITS
MHz
%
Switching Frequency
Maximum Duty Cycle
Switch Current Limit
1.4
●
●
1.2
A
Switch V
I
= 100mA
= 5V
45
0.1
mV
µA
CESAT
SW
Switch Leakage Current
Schottky Forward Drop
V
5
4
SW
I = 100mA
0.45
V
D
Schottky Leakage Current
Disconnect PNP Voltage Drop
CAP = 36V, SW = 0V
µA
I
I
= 100µA, CAP = 20V
80
250
mV
mV
OUT
OUT
= 50mA, CAP = 20V
Disconnect PNP Quiescent Current
Disconnect PNP Leakage Current
LTC3473A Only
CAP = 20V
1.2
µA
µA
SHDN = OUT = 0V, CAP = 20V
0.01
0.1
NPN1 Voltage Drop
NPN1 Beta
INE1 = 1mA
INE1 = 1mA
INE2 = 1mA
INE2 = 1mA
0.8
0.8
V
V
60
60
NPN2 Voltage Drop
NPN2 Beta
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 3: Failure to correctly solder the Exposed Pad of the package to the
PC board will result in a thermal resistance much higher than 40°C.
Note 2: The LT3473EDD and LT3473AEDE are guaranteed to meet
performance specifications from 0°C to 70°C. Specifications over the
–40°C to 85°C operating temperature range are assured by design,
characterization and correlation with statistical process controls.
U W
TYPICAL PERFOR A CE CHARACTERISTICS T = 25°C unless otherwise noted.
A
Load Regulation (Feedback Taken
from CAP)
Feedback Voltage
PGOOD Threshold Voltage
20.20
20.00
1.4
1.2
1.4
1.2
V
= 3.6V
IN
CAP
OUT
1.0
1.0
0.8
0.6
0.4
0.2
0
19.80
19.60
0.8
0.6
0.4
0.2
19.40
19.20
19.00
0
0
20
40
60
80
100
0
0.6
1
1.2 1.4 1.6 1.8
2
0
0.5
1
1.5
2
0.2 0.4
0.8
LOAD CURRENT (mA)
CTRL VOLTAGE (V)
CTRL VOLTAGE (V)
3473 G01
3473 G02
3473 G03
3473f
3
LT3473/LT3473A
U W
TYPICAL PERFOR A CE CHARACTERISTICS T = 25°C unless otherwise noted.
A
Sleep Mode Quiescent Current
(Not Switching)
Sleep Mode Quiescent Current
SHDN Pin Current
105
100
95
102
100
2.5
2.0
1.5
1.0
0.5
0
SHDN = 3V
IN
SHDN = 3V
IN
V
= 3V
V
= 3V
SHDN = 3V
98
96
94
92
90
SHDN = 1.5V
88
90
4
6
8
10
16
0
50
100
0
2
12 14
–50
–50
0
50
100
TEMPERATURE (°C)
INPUT VOLTAGE, V (V)
TEMPERATURE (°C)
IN
3473 G5
3473 G06
3473 G04
Switch Saturation Voltage
Schottky I-V Characteristic
Switch VCE(SAT)
450
400
350
300
250
200
150
100
50
1000
900
800
700
600
500
400
300
200
100
0
50
49
48
47
I
= 100mA
SW
46
45
44
43
42
0
0
50
200
600
–50
100
0
400
800
1000
0
200
400
600
1200
800 1000
SWITCH CURRENT (mA)
TEMPERATURE (°C)
SCHOTTKY FORWARD DROP (mV)
3473 G08
3473 G09
3473 G07
Output Disconnect Voltage Drop
Schottky Forward Voltage
Switching Frequency
550
500
450
400
350
300
400
350
300
250
200
150
100
50
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
I
= 100mA
90°C
25°C
–45°C
D
0
0
50
TEMPERATURE (°C)
100
0
20
40
60
80
100
–50
5
10
0
15
COLLECTOR CURRENT (mA)
INPUT VOLTAGE, V (V)
IN
3473 G10
3473 G11
3473 G12
3473f
4
LT3473/LT3473A
U W
TYPICAL PERFOR A CE CHARACTERISTICS T = 25°C unless otherwise noted.
A
SHDN Voltage to Turn-On
Disconnect PNP
Disconnect PNP Quiescent Current
Auxiliary NPN VBE
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
1.4
1.2
1.00
0.95
0.90
0.85
0.80
1.0
I
= 1mA
E
0.8
0.6
0.4
0.2
0.75
0.70
0.65
0.60
0.55
0.50
I
= 100µA
E
0
0
10 15 20 25
CAP VOLTAGE (V)
40
0
100
–50
50
TEMPERATURE (°C)
100
0
5
30 35
80
20
40
60
0
OUTPUT CURRENT (mA)
3473 G13
3473 G14
3473 G15
U
U
U
PI FU CTIO S (LT3473/LT3473A)
CAP (Pin 1/Pin 1): Internal Output Voltage. This pin is the
Schottky cathode and disconnect PNP emitter. Connect
output capacitor here.
SHDN (Pin 6/Pin 10): Shutdown Pin. Connect to 1.4V or
highertoenabledevice;0.2Vorlesstodisabledevice.Also
functions as soft-start. Use RC filter as shown in Figure 4.
OUT (Pin 2/Pin 2): Output of Disconnect Circuit. Bypass
this pin with capacitor to ground.
VIN (Pin 7/Pin 11): Input Supply Pin. Must be locally
bypassed with a X5R or X7R type ceramic capacitor.
CTRL (Pin 3/Pin 8): External Reference Pin. This pin sets
the FB voltage externally between 0V and 1.25V. Tie this
pin 1.5V or higher to use the internal 1.25V reference.
SW (Pin 8/Pin 12): Switch Pin. Connect inductor here.
Minimize the metal trace area connected to the pin to
minimize EMI.
FB (Pin 4/Pin 7): Feedback Pin. Pin voltage is regulated to
1.25V if internal reference is used or to the CTRL pin
voltage if the CTRL pin voltage is between 0V and 1.25V.
Connect the feedback resistor divider to this pin. The
output voltage is regulated to:
Exposed Pad (Pin 9/Pin 13): Ground. Solder directly to
PCB ground plane through multiple vias under the pack-
age for optimum thermal performance.
LT3473A Only
NB1 (Pin 3): NPN1 Base.
NE1 (Pin 4): NPN1 Emitter.
NB2 (Pin 5): NPN2 Base.
NE2 (Pin 6): NPN2 Emitter.
R2
R1
⎛
⎜
⎝
⎞
⎠
VOUT = VREF
•
+ 1
⎟
PGOOD (Pin 5/Pin 9): Power Good Output. Open collector
logic output that starts to sink current when FB reaches
within 100mV of the reference voltage.
3473f
5
LT3473/LT3473A
W
BLOCK DIAGRA
7
6
8
SW
V
IN
SHDN
ERROR
AMPLIFIER
CAP
OUT
1
2
–
+
+
FB
4
V
C
Q2
g
m
+
–
ENABLE
CTRL
3
A1
PNP
DRIVER
BTH
V
REF
100mV
+
1.25V
POWER SECTION
– –
+
A4
–
+
A2
R
Q
Q1
PGOOD
S
5
9
DRIVER
Q5
COMPARATOR
–
GND
A3
Σ
+
RAMP
GENERATOR
1.2MHz
OSCILLATOR
3437 F01
Figure 1. LT3473 Block Diagram
11
10
12
SW
V
IN
SHDN
ERROR
AMPLIFIER
CAP
1
2
–
+
+
FB
7
V
C
Q2
g
+
–
m
ENABLE
CTRL
OUT
A1
8
PNP
DRIVER
BTH
V
REF
1.25V
100mV
+
POWER SECTION
– –
+
NB1
NE1
Q3
Q4
3
4
A4
–
+
A2
R
Q
Q1
PGOOD
S
NB2
NE2
9
5
6
DRIVER
Q5
COMPARATOR
–
GND
13
A3
Σ
+
RAMP
GENERATOR
1.2MHz
OSCILLATOR
3437 F02
Figure 2. LT3473A Block Diagram
3473f
6
LT3473/LT3473A
W U U
APPLICATIO S I FOR ATIO
U
Operation
causestheFBvoltagetodecrease,VC increasescausingA1
toenablethepowersectioncircuitry.Thechipstartsswitch-
ing. If the load is light, the output voltage (and FB voltage)
willincreaseuntilA1turnsoffthepowersection.Theoutput
voltage starts to fall again. This cycle repeats and gener-
ates low frequency ripple at the output. This Burst Mode
operation keeps the output regulated and reduces average
current into the IC, resulting in high efficiency at light load.
Iftheoutputloadincreasessufficiently,A1’soutputremains
high, resulting in continuous operation.
The LT3473 combines a current mode, fixed frequency
PWMarchitecturewithBurstModemicropoweroperation
to maintain high efficiency at light loads. Operation can
best be understood by referring to the Block Diagram.
The reference of the part is determined by the lower of the
internal 1.25V bandgap reference and the voltage at the
CTRL pin. The error amplifier compares voltage at the FB
pin with the reference and generates an error signal VC.
When VC is below the Burst Mode threshold voltage, BTH,
the hysteretic comparator, A1, shuts off the power section
leaving only the low power circuitry running. Total current
consumption in this state is minimized. As output loading
At the start of each oscillator cycle, the SR latch is set,
turning on the power switch Q1. A voltage proportional to
the switch current is added to a stabilizing ramp and the
Switching Waveforms
Switching Waveforms
Transient Response
V
OUT
200mV/DIV
I
I
L
L
200mA/DIV
200mA/DIV
I
L
200mA/DIV
V
V
SW
SW
10V/DIV
11mA
10V/DIV
I
LOAD
1mA
3473 AI03
3473 AI02
3473 AI01
500µs/DIV
V
V
= 3.6V
= 20V
0.5µs/DIV
V
V
I
= 3.6V
= 20V
LOAD
0.5µs/DIV
V
V
I
= 3.6V
= 20V
LOAD
IN
OUT
IN
OUT
IN
OUT
= 8mA
= 50mA
Transient Response
Transient Response
Transient Response
V
OUT
V
V
OUT
OUT
500mV/DIV
500mV/DIV
500mV/DIV
I
L
I
I
L
L
500mA/DIV
500mA/DIV
500mA/DIV
51mA
55mA
LOAD
5mA
75mA
I
I
I
LOAD
1mA
LOAD
25mA
3473 AI04
3473 AI05
3473 AI06
500µs/DIV
500µs/DIV
V
OUT
= 3.6V
V
OUT
= 3.6V
200µs/DIV
V
OUT
= 3.6V
IN
IN
IN
V
= 20V
V
= 20V
V
= 20V
Shutdown Waveforms
Start-Up Waveforms
V
OUT
V
OUT
10V/DIV
10V/DIV
CAP
0.5V/DIV
IL
500mA/DIV
SHDN
5V/DIV
SHDN
2V/DIV
3473 AI08
3473 AI07
500µs/DIV
V
V
I
= 3.6V
= 20V
LOAD
SHDN 20k, 100nF
100µs/DIV
V
V
I
= 3.6V
= 20V
LOAD
IN
OUT
IN
OUT
= 30mA
= 60mA
3473f
7
LT3473/LT3473A
W U U
U
APPLICATIO S I FOR ATIO
80
75
70
65
60
55
resulting sum is fed into the positive terminal of the PWM
comparator A2. When this voltage exceeds the level of the
error signal VC, the SR latch is reset, turning off the power
switch Q1. The error amplifier sets the peak current level
to keep the output in regulation. If the error amplifier’s
output increases, more current is delivered to the output;
if it decreases, less current is delivered.
V
V
= 3.6V
OUT
IN
= 20V
TOKO A915AY-6R8M
SUMIDA CDRH4D28-6R8
SUMIDA CDRH5D18-6R2
COILCRAFT ME3220-682
COILCRAFT MSS5131-682
TheLT3473includesaninternalpowerSchottkydiodeand
a PNP transistor, Q2, for output disconnect. Q2 discon-
nects the load from the input during shutdown. The part
also has a power good indication pin, PGOOD. When the
FB voltage reaches within 100mV of the reference voltage,
the comparator A4 turns on Q5, sinking current from
PGOOD pin.
0
20
40
60
80
100
LEAD CURRENT l (mA)
3473 F03
O
Figure 3. Efficiency Comparison of Different Inductors
Capacitor Selection
The small package of ceramic capacitors makes them
suitable for LT3473 applications. X5R and X7R types of
ceramic capacitors are recommended because they retain
their capacitance over wider voltage and temperature
ranges than other types such as Y5V or Z5U. A 4.7µF input
capacitor, a 0.47µF output capacitor and a 2.2µF capacitor
bypassing output disconnect PNP are sufficient for most
LT3473 applications.
The LT3473 has thermal shutdown feature with threshold
at about 145°C.
Inductor Selection
A 6.8µH inductor is recommended for the LT3473. The
minimum inductor size that may be used in a given appli-
cation depends on required efficiency and output current.
Table 2. Recommended Ceramic Capacitor Manufacturers
Inductors with low core losses and small DCR (copper
wire resistance) at 1.2MHz are good choices for LT3473
applications. Some inductors in this category with small
size are listed in Table 1. The efficiency comparison of
different inductors is shown in Figure 3.
MANUFACTURER
Taiyo Yuden
AVX
TELEPHONE
408-573-4150
843-448-9411
814-237-1431
408-986-0424
URL
www.t-yuden.com
www.avxcorp.com
www.murata.com
www.kemet.com
Murata
Kemet
Table 1. Recommended Inductors
DCR
(mΩ)
CURRENT
RATING (A)
DIMENSION
(mm)
PART
MANUFACTURER
DO1605T-682
ME3220-682
MSS6122-682
MSS5131-682
200
270
100
60
1.1
1.0
1.45
1.05
5.4 × 4.2 × 1.8
3.2 × 2.5 × 2.0
6.1 × 6.1 × 2.2
5.1 × 5.1 × 3.1
Coilcraft
800-322-2645
www.coilcraft.com
LQH55DN6R8
74
2.0
5.7 × 5.0 × 4.7
Murata
814-237-1431
www.murata.com
CDRH5D18-6R2
CDRH4D28-6R8
CDRH5D28-6R2
CRD53-4R7
71
81
33
74
1.4
1.12
1.8
5.7 × 5.7 × 2.0
4.7 × 4.7 × 3.0
5.7 × 5.7 × 3.0
6.0 × 5.2 × 3.2
Sumida
847-956-0666
www.sumida.com
1.68
A918CY-6R2M
(TYPE D62LCB)
A915AY-6R8M
(TYPE D53LC)
62
1.49
6.0 × 6.0 × 2.0
Toko
408-432-8281
www.tokoam.com
68
1.51
5.0 × 5.0 × 3.0
3473f
8
LT3473/LT3473A
W U U
APPLICATIO S I FOR ATIO
U
Setting the Output Voltages
Inrush Current
The LT3473 has both an internal 1.25V reference and an
external reference input. This allows the user to select
between using the built-in reference and supplying an
externalreferencevoltage. ThevoltageattheCTRLpincan
beadjustedwhilethedeviceisoperatingtoaltertheoutput
voltage for purposes such as display dimming or contrast
adjustment. To use the internal 1.25V reference, the CTRL
pin must be held higher than 1.5V. When the CTRL pin is
held between 0V and 1.2V, the LT3473 will regulate the
outputsuchthattheFBpinvoltageisequaltotheCTRLpin
voltage.
The LT3473 has an integrated Schottky power diode.
When supply voltage is abruptly applied to the VIN pin
while the output capacitor is discharged, the voltage
difference between VIN and CAP generates inrush current
flowing from the input through the inductor and the
internal Schottky diode to charge the output capacitor at
theCAPpin. ThemaximumcurrenttheLT3473’sSchottky
can sustain is 2A. The selection of inductor and capacitor
values should ensure that the peak inrush current is less
than 2A. Peak inrush current can be calculated as follows:
⎛
⎞
⎛
⎞
ω
⎛ ⎞
⎝ ⎠
α
⎠
V – 0.6
L•ω
α
ω
⎛ ⎞
IN
The CAP pin should be used as the feedback node. To set
the output voltage, select the values of R1 and R2 accord-
ing to the following equation.
IP =
α =
ω =
•exp – •arctan
•sin arctan
⎜ ⎟
⎜ ⎟
⎟
⎜
⎟
⎜
⎝ ⎠
α
ω
⎝
⎠
⎝
r + 1.5
2•L
R2
R1
⎛
⎝
⎞
⎟
⎠
V
INT
= VREF • 1+
⎜
1
–
r
2
L•C
4 •L
where VREF = 1.25V if the internal reference is used, or
VREF = VCTRL if VCTRL is between 0V and 1.2V.
where L is the inductance, r is the resistance of the
inductor and C is the output capacitance. For a low DCR
inductor, which is usually the case for this application, the
peak inrush current can be simplified as follows:
To maintain output voltage accuracy, 1% resistors are
recommended.
Soft-Start
V – 0.6
L • ω
α π
• exp – •
⎜
⎛
⎝
⎞
⎟
⎠
IN
The SHDN pin also functions as soft-start. Use an RC filter
attheSHDNpintolimitthestart-upcurrent.Thesmallbias
current of the SHDN pin allows using a small capacitor for
a large RC time constant.
IP =
ω 2
A large abrupt voltage step at VIN and/or a large capacitor
attheCAPpingeneratelargerinrushcurrent.Table3gives
inrush peak currents for some component selections. An
inductor with low saturation current could generate very
large inrush current. For this case, inrush current should
be measured to ensure safe operation. Note that inrush
current is not a concern if the input voltage rises slowly.
LT3473
20k
ON/OFF
SHDN
100nF
3473 F04
Figure 4. Soft-Start Circuitry
Table 3. Inrush Peak Current
Output Disconnect Considerations
V
IN
(V)
R (Ω)
0.05
0.05
0.05
0.05
L (µH)
6.8
C (µF)
0.47
0.47
0.47
0.47
I (A)
P
The LT3473 has an output disconnect PNP that isolates
the load from the input during shutdown. The drive circuit
maintains the PNP at the edge of saturation, adaptively
according to the load, thus yielding the best compromise
between VCESAT and quiescent current to minimize power
loss. To remain stable, it requires a bypass capacitor
5
0.86
1.83
0.58
0.67
10
3.6
3.6
6.8
6.8
4.7
connected between the OUT pin and the CAP pin or
3473f
9
LT3473/LT3473A
W U U
U
APPLICATIO S I FOR ATIO
connected to the two bases as shown in Figure 5 to
generate buffered voltage at the emitters. When sourcing
high current at low voltage, keep in mind that the NPNs
will be dissipating a fair amount of power, which must be
supplied by the DC/DC converter.
betweentheOUTpinandground.Aceramiccapacitorwith
a value of 1µF is a good choice. The voltage drop (PNP
VCESAT) can be accounted for by setting the output voltage
according to the following formula:
R2
R1
⎛
⎝
⎞
⎟
⎠
VOUT = VINT – VCESAT = VREF • 1+
– V
CESAT
⎜
Thermal Shutdown
TheLT3473hasthermalshutdowncircuitrythatshutsdown
the part when the junction temperature reaches approxi-
mately 145°C to protect the part from abnormal operation
with high power dissipation, such as an output short cir-
cuit or excessive power dissipation in the auxiliary NPNs.
The part will turn back on when the junction cools down to
approximately 125°C. If the abnormal condition remains,
the part will turn on and off while maintaining the junction
temperaturewithinthewindowbetween125°Cand145°C.
Auxiliary NPN Devices (LT3473A Only)
The LT3473A has two auxiliary NPNs as shown in the
Block Diagram that can provide intermediate outputs less
thanOUT. ThecollectorsoftheNPNsareconnectedtothe
OUTpininternally. EachNPNcandissipate100mWsafely
and has a minimum beta of 60. A resistor string can be
2
3
OUT
R
EXT1
Board Layout Consideration
NB1
As with all switching regulators, careful attention must be
paid to the PCB board layout and component placement.
Tomaximizeefficiency, switchriseandfalltimesaremade
as short as possible. To prevent electromagnetic interfer-
ence (EMI) problems, proper layout of the high frequency
switching path is essential. The voltage signal of the SW
pin has sharp rise and fall edges. Minimize the length and
area of all traces connected to the SW pin and always use
a ground plane under the switching regulator to minimize
interplane coupling. Recommended component place-
ment is shown in Figure 6.
4
R
EXT2
NE1
NB2
5
R
EXT3
6
NE2
3473 F05
Figure 5. Auxiliary NPN Transistors in LT3473A. REXT1, REXT2
and REXT3 Set Intermediate Voltage at NE1 and NE2
OUT
1
2
3
4
5
6
12
11
10
9
OUT
1
2
3
4
8
7
6
5
13
8
9
7
3473 F06b
3473 F06a
Figure 6. Recommended Component Placement
3473f
10
LT3473/LT3473A
U
PACKAGE DESCRIPTIO
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115
0.38 ± 0.10
TYP
5
8
0.675 ±0.05
3.5 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
PACKAGE
OUTLINE
(DD8) DFN 1203
4
1
0.25 ± 0.05
0.75 ±0.05
0.200 REF
0.25 ± 0.05
0.50 BSC
0.50
BSC
2.38 ±0.05
(2 SIDES)
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
DE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1708)
0.38 ± 0.10
4.00 ±0.10
(2 SIDES)
R = 0.115
TYP
7
12
0.65 ±0.05
R = 0.20
TYP
3.50 ±0.05
2.20 ±0.05 (2 SIDES)
1.70 ±0.05
3.00 ±0.10 1.70 ± 0.10
(2 SIDES)
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
PIN 1
NOTCH
PACKAGE
OUTLINE
(UE12/DE12) DFN 0603
6
1
0.25 ± 0.05
0.75 ±0.05
0.200 REF
0.25 ± 0.05
0.50
BSC
0.50
BSC
3.30 ±0.10
(2 SIDES)
3.30 ±0.05
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
3473f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
11
LT3473/LT3473A
U
TYPICAL APPLICATIO
Efficiency
OLED Bias
80
75
70
65
60
55
100k
V
OUT
V
IN
= 3.6V
V
= 15V
OUT
25V
PGOOD
CTRL
OUT
C
80mA
OUT
2.2µF
V
= 25V
OUT
L1 6.8µH
LT3473
V
= 20V
OUT
V
IN
SW
3V TO 4.2V
CAP
FB
V
IN
2M
20k
C
INT
0.47µF
SHDN
C
IN
100k
GND
100nF
4.7µF
3473 TA02a
C
C
C
: TAIYO YUDEN JMK107BJ475
IN
INT
OUT
: TAIYO YUDEN GMK212BJ474
0
20
40
60
80
100
: TAIYO YUDEN GMK325BJ225
L1: TOKO A915AY-6R8M (TYPE D53LC)
LOAD CURRENT I (mA)
O
3473 TA02b
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300mA (I ), 1.3MHz/3MHz High Efficiency Step-Up
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IN
Dual Output, Boost/Inverter, 1.3A (I ), 1.2MHz,
V : 2.4V to 16V, V
IN
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Q SD
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High Efficiency Boost-Inverting DC/DC Converter
LT3479
3A (I ), 3.5MHz, 42V Step-Up DC/DC Converter
V : 2.5V to 24V, V
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DFN, TSSOP-16E Packages
ThinSOT is a trademark of Linear Technology Corporation.
3473f
LT/TP 0205 1K • PRINTED IN THE USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
12
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
©LINEAR TECHNOLOGY CORPORATION 2005
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