LT3477 [Linear]
PWM LED Driver and Boost, Flyback and SEPIC Controller; PWM LED驱动器和升压，反激和SEPIC控制器
| 型号： | LT3477 |
| 厂家： | 
Linear |
| 描述： | PWM LED Driver and Boost, Flyback and SEPIC Controller |
| 文件： | 总24页 (文件大小：270K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3783
PWM LED Driver and Boost,
Flyback and SEPIC Controller
U
FEATURES
DESCRIPTIO
The LTC®3783 is a current mode LED driver and boost,
flybackandSEPICcontrollerthatdrivesbothanN-channel
power MOSFET and an N-channel load PWM switch.
When using an external load switch, the PWMIN input not
only drives PWMOUT, but also enables controller GATE
switching and error amplifier operation, allowing the con-
troller to store load current information while PWMIN is
low.Thisfeature(patentpending)providesextremelyfast,
true PWM load switching with no transient overvoltage or
undervoltageissues;LEDdimmingratiosof3000:1canbe
achieved digitally, avoiding the color shift normally asso-
ciated with LED current dimming. The FBP pin allows
analog dimming of load current, further increasing the
effective dimming ratio by 100:1 over PWM alone.
True Color PWMTM Delivers Constant Color with
■
3000:1 Dimming Ratio
■
Fully Integrated Load FET Driver for PWM Dimming
Control of High Power LEDs
■
100:1 Dimming from Analog Inputs
■
Wide FB Voltage Range: 0V to 1.23V
■
Constant Current or Constant Voltage Regulation
■
Low Shutdown Current: IQ = 20µA
■
1% 1.23V Internal Voltage Reference
■
2% RUN Pin Threshold with 100mV Hysteresis
■
Programmable Operating Frequency (20kHz to
1MHz) with One External Resistor
■
Synchronizable to an External Clock Up to 1.3fOSC
■
Internal 7V Low Dropout Voltage Regulator
■
Programmable Output Overvoltage Protection
In applications where output load current must be re-
turned to VIN, optional constant current/constant voltage
regulation controls either output (or input) current or
output voltage and provides a limit for the other. ILIM
provides a 10:1 analog dimming ratio.
■
Programmable Soft-Start
Can be Used in a No RSENSETM Mode for VDS < 36V
■
■
16-Lead DFN and TSSOP Packages
U
APPLICATIO S
For low- to medium-power applications, No RSENSE mode
can utilize the power MOSFET’s on-resistance to eliminate
the current-sense resistor, thereby maximizing efficiency.
■
High Voltage LED Arrays
■
Telecom Power Supplies
■
42V Automotive Systems
■
The IC’s operating frequency can be set with an external
resistor over a 20kHz to 1MHz range and can be synchro-
nized to an external clock using the SYNC pin.
24V Industrial Controls
■
IP Phone Power Supplies
, LTC and LT are registered trademarks of Linear Technology Corporation.
True Color PWM and No R
are trademarks of Linear Technology Corporation.
SENSE
All other trademarks are the property of their respective owners. Patent pending.
The LTC3783 is available in the 16-lead DFN and TSSOP
packages.
U
TYPICAL APPLICATIO
350mA PWM LED Boost Application
Typical Waveforms
V
IN
6V TO 16V
10µF
×2
(< TOTAL V OF LEDs)
F
V
2.2µH
PWMIN
1M
5V/DIV
ZETEX ZLL51000
V
OUT
<25V
LTC3783
RUN
PWMIN OV/FB
PWMOUT
V
OUT
0.2V/DIV
237k
V
IN
AC COUPLED
LED*
STRING
I
TH
SS
I
L
I
LIM
2.5A/DIV
105k
C
OUT
M1
M2
V
GATE
REF
10µF
0.1µF
10µF
FBP
SENSE
I
FBN
FREQ
SYNC
INTV
CC
GND
LED
4.7µF
0.5A/DIV
10k
6k
0.05Ω 12.4k
0.3Ω
3783 TA01b
GND
1µs/DIV
3783 TA01a
M1, M2: SILICONIX Si4470EY *LUMILEDS LHXL-BW02
3783f
1
LTC3783
W W U W
ABSOLUTE AXI U RATI GS (Note 1)
VIN, SENSE, FBP, FBN Voltages ................ –0.3V to 42V
INTVCC Voltage ........................................... –0.3V to 9V
INTVCC Output Current ........................................ 75mA
GATE Output Current ................................ 50mA (RMS)
PWMOUT Output Current ......................... 25mA (RMS)
VREF Ouput Current................................................ 1mA
GATE, PWMOUT Voltages ..... –0.3V to (VINTVCC + 0.3V)
ITH, ILIM, SS Voltages .............................. –0.3V to 2.7V
RUN, SYNC, PWMIN Voltages .................... –0.3V to 7V
FREQ, VREF, OV/FB Voltages .....................–0.3V to 1.5V
Operating Junction Temperature Range
(Note 2) .................................................. –40°C to 85°C
Junction Temperature (Note 3)............ –40°C to 125°C
Storage Temperature Range
DFN Package ................................... –65°C to 125°C
TSSOP Package............................... –65°C to 150°C
Lead Temperature (Soldering, 10sec)
TSSOP Package............................................... 300°C
U W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
TOP VIEW
ORDER PART
NUMBER
ORDER PART
NUMBER
FBN
FBP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RUN
FBN
FBP
1
2
3
4
5
6
7
8
16 RUN
15
I
I
TH
TH
LTC3783EDHD
LTC3783EFE
I
OV/FB
SS
I
14 OV/FB
13 SS
LIM
LIM
V
V
REF
REF
17
17
FREQ
SENSE
FREQ
12 SENSE
SYNC
PWMIN
V
SYNC
PWMIN
11
V
IN
IN
DHD PART MARKING
3783
INTV
CC
10 INTV
CC
GATE
PWMOUT
GATE
PWMOUT
9
FE PACKAGE
DHD PACKAGE
16-LEAD (5mm × 4mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/ W
16-LEAD PLASTIC TSSOP
TJMAX = 125°C, θJA = 38°C/ W
EXPOSED PAD (PIN 17) IS GND
MUST BE SOLDERED TO PCB
EXPOSED PAD (PIN 17) IS GND
MUST BE SOLDERED TO PCB
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are T = 25°C.
A
V
= 12V, V
= 1.5V, V
= 0V, V
= V , R = 20k, unless otherwise specified.
FBP REF T
IN
SYMBOL
Main Control Loop/Whole System
RUN
SYNC
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IN
Input Voltage Range
3
36
V
I
Input Voltage Supply Current
Continuous Mode
Shutdown Mode
(Note 4)
Q
V
V
= 1.5V, V = 0.75V
= 0V
1.5
20
mA
µA
V
V
OV/FB
ITH
RUN
+
–
V
V
V
Rising RUN Input Threshold Voltage
Falling RUN Input Threshold Voltage
RUN Pin Input Threshold Hysteresis
1.348
RUN
1.223
1.248 1.273
100
RUN
mV
RUN(HYST)
3783f
2
LTC3783
ELECTRICAL CHARACTERISTICS
The
IN
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are T = 25°C.
A
V
= 12V, V
= 1.5V, V
= 0V, V
= V , R = 20k, unless otherwise specified.
FBP T
RUN
PARAMETER
RUN Pin Input Current
SYNC
REF
SYMBOL
CONDITIONS
MIN
TYP
5
MAX
UNITS
nA
I
RUN
V
Maximum Current Sense Threshold
SENSE Pin Current (GATE High)
SENSE Pin Current (GATE Low)
Soft-Start Pin Output Current
125
150
70
180
mV
µA
µA
SENSE(MAX)
SENSE(ON)
SENSE(OFF)
SS
I
I
I
V
V
V
= 0V
SENSE
SENSE
= 36V
0.2
–50
= 0V
µA
SS
Voltage/Temperature Reference
V
REF
Reference Voltage
1.218
1.212
1.230 1.242
1.248
V
V
●
I
Max Reference Pin Output Current
Reference Voltage Line Regulation
Reference Voltage Load Regulation
0.5
mA
%/V
REF
∆V /∆V
∆V /∆I
T
3V ≤ V ≤ 36V
0.002
0.2
0.02
1.0
REF
IN
IN
0mA ≤ I ≤ 0.5mA
%/mA
°C
REF REF
REF
Overtemperature SD Threshold
Rising
165
MAX
T
Overtemperature Hysteresis
25
°C
HYST
Error Amplifier
OV/FB Pin Input Current
OV/FB Overvoltage Lockout Threshold V
I
18
7
60
nA
%
V
OV/FB
∆V
– V
in %, V ≤ V
OV/FB(OV)
OV/FB(FB)
OV/FB(OV)
OV/FB(NOM) FBP REF
V
OV/FB Pin Regulation Voltage
Error Amplifier Input Current
2.5V < V
< 36V
1.212
–3
1.230 1.248
FBP
I
, I
0V ≤ V ≤ V
2.5V < V
–0.4
50
µA
µA
mV
mV
mV
FBP FBN
FBP
REF
< 36V
FBP
V
– V
Error Amplifier Offset Voltage
(Note 5)
0V ≤ V ≤ V
3
FBP
m
FBN
FBP
REF
2.5V < V ≤ 36V (V
= V )
REF
= 0.123V)
100
10
FBP
ILIM
ILIM
2.5V < V ≤ 36V (V
V
2.5V < V
FBP
g
Error Amplifier Transconductance
Error Amplifier Open-Loop Gain
≤ V
1.7
14
mmho
mmho
FBP
REF
FBP
< 36V
A
VOL
500
V/V
Oscillator
f
Oscillator Frequency
Oscillator Frequency Range
R
= 20kΩ
FREQ
250
20
300
350
1000
kHz
kHz
OSC
D
Maximum Duty Cycle
85
90
1.25
25
97
%
MAX
f
t
t
/f
Recommended Max SYNC Freq Ratio
SYNC Minimum Input Pulse Width
SYNC Maximum Input Pulse Width
SYNC Input Voltage High Level
SYNC Input Voltage Hysteresis
SYNC Input Pull-Down Resistance
Minimum On-time
f
= 300kHz (Note 6)
OSC
1.3
SYNC OSC
SYNC(MIN)
SYNC(MAX)
V
V
= 0V to 5V
= 0V to 5V
ns
ns
V
SYNC
SYNC
0.8/f
OSC
V
V
1.2
IH(SYNC)
0.5
V
HYST(SYNC)
R
SYNC
100
kΩ
ns
ns
t
With Sense Resistor, 10mV Overdrive
No R Mode
170
300
ON(MIN)
SENSE
3783f
3
LTC3783
ELECTRICAL CHARACTERISTICS
The
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are T = 25°C.
J
V
= 12V, V
= 1.5V, V
= 0V, V
= V , R = 20k, unless otherwise specified.
FBP REF T
IN
SYMBOL
Low Dropout Regulator
INTV Regulator Output Voltage
RUN
SYNC
PARAMETER
CONDITIONS
= 1.5V
MIN
TYP
MAX
UNITS
V
V
OV/FB
●
6.5
1.8
7
7.5
2.5
V
INTVCC
CC
UVLO
INTV Undervoltage Lockout
Rising INTV
2.3
2.1
0.2
V
V
V
CC
CC
Thresholds
Falling INTV
CC
Hysteresis
∆V
∆V
INTV Line Regulation
12V ≤ V ≤ 36V
2
6
mV/V
INTVCC
CC
IN
∆V
IN
INTV Load Regulation
0 ≤ I ≤ 10mA
INTVCC
–1
–0.1
300
%
LDO(LOAD)
DROPOUT
INTVCC(SD)
CC
V
INTV Dropout Voltage
V
IN
= 7V, I = 10mA
INTVCC
500
mV
CC
I
Bootstrap Mode INTV Supply
V
SENSE
V
SENSE
= 0V
= 7V
25
15
µA
µA
CC
Current in Shutdown
GATE/PWMOUT Drivers
t
t
I
I
GATE Driver Output Rise Time
GATE Driver Output Fall Time
C = 3300pF (Note 7)
15
8
ns
ns
A
r(GATE)
L
C = 3300pF (Note 7)
L
f(GATE)
GATE Driver Peak Current Sourcing
GATE Driver Peak Current Sinking
PWMIN Pin Input Threshold Voltages
V
GATE
V
GATE
= 0V
= 7V
0.5
1
PK(GATE,RISE)
PK(GATE,FALL)
A
V
Rising PWMIN
Falling PWMIN
Hysteresis
1.6
0.8
0.8
V
V
V
PWMIN
R
PWMIN Input Pull-Up Resistance
PWMOUT Driver Output Rise Time
PWMOUT Driver Output Fall Time
PWMOUT Driver Peak Current Sourcing
PWMOUT Driver Peak Current Sinking
100
30
kΩ
ns
ns
A
PWMIN
t
t
I
I
C = 3300pF (Note 7)
L
r(PWMOUT)
C = 3300pF (Note 7)
L
16
f(PWMOUT)
V
V
= 0V
= 7V
0.25
0.50
PK(PWMOUT,RISE)
PK(PWMOUT,FALL)
PWMOUT
PWMOUT
A
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 4: The dynamic input supply current is higher due to power MOSFET
gate charging (QG • fOSC). See Operation section.
Note 2: The LTC3783E is guaranteed to meet performance specifications
from 0°C to 85°C junction temperature. Specifications over the –40°C to
85°C operating temperature range are assured by design, characterization
and correlation with statistical process controls.
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
Note 5: The LTC3783 is tested in a feedback loop which servos VFBN to
VFBP = VVREF with the ITH pin forced to the midpoint of its voltage range
(0.3V ≤ VITH ≤ 1.2V; midpoint = 0.75V).
Note 6: In a synchronized application, the internal slope compensation is
increased by 25%. Synchronizing to a significantly higher ratio will reduce
the effective amount of slope compensation, which could result in sub-
harmonic oscillation for duty cycles greater than 50%
TJ = TA + (PD • 43°C/W) for the DFN
TJ = TA + (PD • 38°C/W) for the TSSOP
Note 7: Rise and fall times are measured at 10% and 90% levels.
3783f
4
LTC3783
TYPICAL PERFOR A CE CHARACTERISTICS T = 25°C unless otherwise specified
U W
A
V
vs Temperature
V
Line Regulation
V
Load Regulation
REF
REF
REF
1.235
1.233
1.231
1.229
1.227
1.225
1.25
1.20
1.15
1.10
1.05
1.00
1.235
1.233
1.231
1.229
1.227
1.225
V
IN
= 12V
V
= 2.5V
IN
0
1
2
3
4
5
–50
0
50
100
150
0
10
20
(V)
30
40
I
(mA)
TEMPERATURE (°C)
V
REF
IN
3783 G03
3783 G01
3783 G02
I vs Temperature (PWMIN Low)
I vs V (PWMIN Low)
Dynamic I vs Frequency
Q
Q
Q
IN
30
25
20
15
10
5
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
0
1.6
1.4
1.2
1.0
C
= 3300pF
L
I
= 1.3mA + Q • f
Q(TOT)
G
0.8
0.6
0.4
0.2
0
0
–25
25
TEMPERATURE (°C)
125
–75
175
0
0.5
1
1.5
75
0
40
50
10
20
30
FREQUENCY (MHz)
V
(V)
IN
3783 G04
3783 G06
3783 G05
RUN Thresholds vs V
RUN Thresholds vs Temperature
R vs Frequency
T
IN
1000
100
10
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
1.40
1.38
1.36
1.34
1.32
1.30
1.28
1.26
1.24
1.22
RUN HIGH
RUN HIGH
RUN LOW
RUN LOW
1
0
10
20
(V)
30
40
50
–50
0
100
150
1
10
100
FREQUENCY (kHz)
1000
10000
V
TEMPERATURE (°C)
IN
3783 G09
3783 G07
3783 G08
3783f
5
LTC3783
TYPICAL PERFOR A CE CHARACTERISTICS T = 25°C unless otherwise specified
U W
A
Frequency vs Temperature
Maximum V
vs Temperature
I
vs Temperature
SENSE
SENSE
350
340
330
320
310
300
290
280
270
260
250
75
74
73
72
71
70
69
68
67
66
65
160
158
156
154
152
150
148
146
144
142
140
–50
0
50
100
150
–50
0
50
100
150
–50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3783 G11
3783 G10
3783 G12
INTV Load Regulation
CC
INTV Load Regulation
INTV Line Regulation
CC
Over Temperature
CC
7.05
7.00
6.95
6.90
6.85
6.80
6.75
6.70
6.65
6.60
6.55
7.0
6.8
7.00
6.95
6.90
6.85
6.80
6.75
6.70
6.55
6.50
–50°C, –25°C, 0°C
25°C
75°C
6.6
6.4
6.2
50°C
100°C
125°C
150°C
6.0
5.8
5.6
5.4
5.2
5.0
0
10
20
30
(V)
40
50
0
100
(mA)
150
0
0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16
(mA)
50
I
I
V
INTVCC
INTVCC
IN
3783 G14
3783 G15
3783 G13
I
Soft-Start Current
Gate Rise/Fall Time
vs Capacitance
INTV Line Regulation
SS
CC
vs Temperature
vs Temperature
50.0
49.8
49.6
49.4
49.2
49.0
48.8
48.6
48.4
48.2
48.0
47.8
7.20
7.15
80
70
60
50
40
30
20
10
0
150°C
7.10
7.05
25°C
GATE TR
–50°C
7.00
6.95
6.90
GATE TF
10
CAPACITANCE (nF)
–50
0
50
100
150
0
5
15
20
5
10
15
20
25
(V)
30
35
40
TEMPERATURE (°C)
V
IN
3783 G17
3783 G18
3783 G16
3783f
6
LTC3783
U
U
U
PI FU CTIO S
FBN (Pin 1): Error Amplifier Inverting Input/Negative
Current Sense Pin. In voltage mode (VFBP ≤ VVREF), this
pin senses feedback voltage from either the external
resistor divider across VOUT for output voltage regula-
tion, or the grounded sense resistor under the load for
output current regulation. In constant current/constant
voltage mode (VFBP > 2.5V), connect this pin to the
negative side of the current-regulating resistor. Nominal
PWMIN (Pin 7): PWM Gate Driver Input. Internal 100k
pull-up resistor. While PWMIN is low, PWMOUT is low,
GATE stops switching and the external ITH network is
disconnected, saving the ITH state.
PWMOUT (Pin 8): PWM Gate Driver Output. Used for
constantcurrentdimming(LEDload)orforoutputdiscon-
nect (step-up power supply).
GATE (Pin 9): Main Gate Driver Output for the Boost
Converter.
voltage for this pin in regulation is either VFBP or (VFBP
–
100mV) for VILIM = 1.23V, depending on operational
mode (voltage or constant current/constant voltage) set
INTVCC (Pin 10): Internal 7V Regulator Output. The main
and PWM gate drivers and control circuits are powered
from this voltage. Decouple this pin locally to the IC
ground with a minimum of 4.7µF low ESR ceramic
capacitor.
by the voltage at VFBP
.
FBP (Pin 2): Error Amplifier Noninverting Input/Positive
CurrentSensePin. Thispinvoltagedeterminesthecontrol
loop’s feedback mode (voltage or constant current/con-
stantvoltage), thethresholdofwhichisapproximately2V.
In voltage mode (VFBP ≤ VREF), this pin represents the
desired voltage which the regulated loop will cause FBN to
VIN (Pin 11): Main Supply Pin. Must be closely decoupled
to ground.
SENSE (Pin 12): Current Sense Input for the Control
Loop. Connect this pin to the drain of the main power
MOSFETforVDS sensingandhighestefficiencyforVSENSE
≤ 36V. Alternatively, the SENSE pin may be connected to
a resistor in the source of the main power MOSFET.
Internal leading-edge blanking is provided for both sens-
ing methods.
follow. In constant current/constant voltage mode (VFBP
>
2.5V), connect this pin to the positive side of the load
current-sensing resistor. The acceptable input ranges for
this pin are 0V to 1.23V (voltage mode) and 2.5V to 36V
(constant current/constant voltage mode).
ILIM(Pin 3): Current Limit Pin. Sets current sense resistor
offset voltage (VFBP – VFBN) in constant current mode
regulation (i.e., when VFBP > 2.5V). Offset voltage is
100mV when VILIM = 1.23V and decreases proportionally
with VILIM. Nominal voltage range for this pin is 0.1V to
1.23V.
SS (Pin 13): Soft-Start Pin. Provides a 50µA pull-up
current, enabled and reset by RUN, which charges an
optional external capacitor. This voltage ramp translates
into a corresponding current limit ramp through the main
MOSFET.
VREF (Pin 4): Reference Voltage Pin. Provides a buffered
version of the internal bandgap voltage, which can be
connected to FBP either directly or with attenuation.
Nominalvoltageforthispinis1.23V.Thispinshouldnever
be bypassed by a capacitor to GND. Instead, a 10k resistor
to GND should be used to lower pin impedance in noisy
systems.
OV/FB (Pin 14): Overvoltage Pin/Voltage Feedback Pin. In
voltage mode (VFBP ≤ VREF), this input, connected to VOUT
through a resistor network, sets the output voltage at
which GATE switching is disabled in order to prevent an
overvoltage situation. Nominal threshold voltage for the
OV pin is 1.32V (VREF + 7%) with 20mV hysteresis. In
current/voltage mode (VFBP > 2.5V), this pin senses VOUT
through a resistor divider and brings the loop into voltage
regulation such that pin voltage approaches VREF = 1.23V,
provided the loop is not regulating the load current (e.g.,
[VFBP – VFBN] < 100mV for ILIM = 1.23V).
FREQ (Pin 5): A resistor from the FREQ pin to ground
programs the operating frequency of the chip. The nomi-
nal voltage at the FREQ pin is 0.615V.
SYNC (Pin 6): This input allows for synchronizing the
operating frequency to an external clock and has an
internal 100k pull-down resistor.
3783f
7
LTC3783
U
U
U
PI FU CTIO S
ITH(Pin15):ErrorAmplifierOutput/CompensationPin.The
current comparator input threshold increases with this
control voltage, which is the output of the gm type error
amplifier.Nominalvoltagerangeforthispinis0Vto1.40V.
falling RUN pin threshold is nominally 1.248V and the
comparator has 100mV hysteresis for noise immunity.
WhentheRUNpinisgrounded,theICisshutdownandthe
VIN supply current is kept to a low value (20µA typ).
RUN (Pin 16): The RUN pin provides the user with an
accurate means for sensing the input voltage and pro-
gramming the start-up threshold for the converter. The
Exposed Pad (Pin 17): Ground Pin. Solder to PCB ground
for electrical contact and rated thermal performance.
W
BLOCK DIAGRA
V
REF
4
SLOPE
COMP
BIAS
V
REF
GND
17
FREQ
SYNC
5
6
CLK
V-TO-I
OSC
S
R
SS_RESET
0.615V
Q
GATE
LOGIC
9
1.9V
IVMODE
–
+
TEMP
SENSOR
(165°C)
OT
OV/FB
+
–
OV
I
LIM
SENSE
V
REF
3
EA
+
–
12
ITRIP
FBP
FBN
2
1
A
–
–
+
1
0
S
0.2V
+
–
SLEEP
V
REF
OV/FB
14
+
–
50µA
SS
13
15
+
–
IMAX
0.15V
I
TH
V-TO-I
PWMIN
PWMOUT
RUN
8
7
EN
INTV
CC
LDO
10
V
REF
2.23V
+
–
+
–
16
11
UV
BIAS AND
START-UP
V
REF
V
IN
3738 BD
3783f
8
LTC3783
U
OPERATIO
Main Control Loop
For constant current/constant voltage regulation opera-
tion (defined by VFBP > 2.5V), please refer to the Block
Diagram of the IC and Figure 11. Loop operation is similar
to the voltage feedback, except FBP and FBN now sense
thevoltageacrosssenseresistorRL inserieswiththeload.
The ITH pin now represents the error from the desired
differential set voltage, from 10mV to 100mV, for ILIM
values of 0.123V to 1.23V. That is, with VILIM = 1.23V, the
loop will regulate such that VFBP – VFBN = 100mV; lower
values of ILIM attenuate the difference proportionally.
PWMIN is still functional as above, but will only work
properly if load current can be disconnected by the
PWMOUT signal.
The LTC3783 is a constant frequency, current mode
controller for PWM LED as well as DC/DC boost, SEPIC
and flyback converter applications. In constant current
LED applications, the LTC3783 provides an especially
wide PWM dimming range due to its unique switching
scheme, which allows PWM pulse widths as short as
several converter switching periods.
For voltage feedback circuit operation (defined by VFBP
≤
1.23V), please refer to the Block Diagram of the IC and the
Typical Application on the first page of this data sheet. In
normaloperationwithPWMINhigh, thepowerMOSFETis
turned on (GATE goes high) when the oscillator sets the
PWM latch, and is turned off when the ITRIP current
comparator resets the latch. Based on the error voltage
represented by (VFBP – VFBN), the error amplifier output
signal at the ITH pin sets the ITRIP current comparator
input threshold. When the load current increases, a fall in
the FBN voltage relative to the reference voltage at FBP
causes the ITH pin to rise, causing the ITRIP current com-
parator to trip at a higher peak inductor current value. The
average inductor current will therefore rise until it equals
the load current, thereby maintaining output regulation.
In constant current/constant voltage operation, the OV/FB
pin becomes a voltage feedback pin, which causes the
loop to regulate such that VOV/FB = 1.23V, provided the
above current-sense voltage is not reached. In this way,
the loop regulates either voltage or current, whichever
parameter hits its preset limit first.
The nominal operating frequency of the LTC3783 is pro-
grammed using a resistor from the FREQ pin to ground
and can be controlled over a 20kHz to 1MHz range. In
addition, the internal oscillator can be synchronized to an
external clock applied to the SYNC pin and can be locked
to a frequency between 100% and 130% of its nominal
value. When the SYNC pin is left open, it is pulled low by
an internal 100k resistor. With no load, or an extremely
light one, the controller will skip pulses in order to main-
tain regulation and prevent excessive output ripple.
When PWMIN goes low, PWMOUT goes low, the ITH
switch opens and GATE switching is disabled. Lowering
PWMOUTanddisablingGATEcausestheoutputcapacitor
COUT to hold the output voltage constant in the absence of
load current. Opening the ITH switch stores the correct
load current value on the ITH capacitor CITH. As a result,
when PWMIN goes high again, both ITH and VOUT are
instantly at the appropriate levels.
The RUN pin controls whether the IC is enabled or is in a
low current shutdown state. A micropower 1.248V refer-
ence and RUN comparator allow the user to program the
supply voltage at which the IC turns on and off (the RUN
comparatorhas100mVofhysteresisfornoiseimmunity).
With the RUN pin below 1.248V, the chip is off and the
input supply current is typically only 20µA.
In voltage feedback operation, an overvoltage compara-
tor, OV, senses when the OV/FB pin exceeds the reference
voltage by 7% and provides a reset pulse to the main RS
latch. Because this RS latch is reset-dominant, the power
MOSFET is actively held off for the duration of an output
overvoltage condition.
3783f
9
LTC3783
U
OPERATIO
The SS pin provides a soft-start current to charge an
external capacitor. Enabled by RUN, the soft-start current
is 50µA, which creates a positive voltage ramp on VSS to
which the internal ITH is limited, avoiding high peak
currents on start-up. Once VSS reaches 1.23V, the full ITH
range is established.
2V TO 7V
MODE/
SYNC
t
= 25ns
MIN
0.8T
T
T = 1/f
O
GATE
D = 40%
The LTC3783 can be used either by sensing the voltage
drop across the power MOSFET or by connecting the
SENSE pin to a conventional shunt resistor in the source
of the power MOSFET, as shown in the Typical Application
on the first page of this data sheet. Sensing the voltage
acrossthepowerMOSFETmaximizesconverterefficiency
and minimizes the component count, but limits the output
voltage to the maximum rating for this pin (36V). By
connecting the SENSE pin to a resistor in the source of the
power MOSFET, the user is able to program output volt-
ages significantly greater than 36V, limited only by other
components’ breakdown voltages.
I
L
3783 F01
Figure 1. MODE/SYNC Clock Input and Switching Waveforms
for Synchronized Operation
MOSFET and diode switching losses. However, lower
frequency operation requires more inductance for a given
amount of load current.
Externally Synchronized Operation
The LTC3783 uses a constant frequency architecture that
can be programmed over a 20kHz to 1MHz range with a
single external resistor from the FREQ pin to ground, as
shown in the application on the first page of this data
sheet.ThenominalvoltageontheFREQpinis0.615V,and
thecurrentthatflowsoutoftheFREQpinisusedtocharge
and discharge an internal oscillator capacitor. The oscil-
lator frequency is trimmed to 300kHz with RT = 20k. A
graph for selecting the value of RT for a given operating
frequency is shown in Figure 2.
WhenanexternalclocksignaldrivestheSYNCpinatarate
faster than the chip’s internal oscillator, the oscillator will
synchronize to it. When the oscillator’s internal logic
circuitry detects a synchronizing signal on the SYNC pin,
the internal oscillator ramp is terminated early and the
slope compensation is increased by approximately 25%.
As a result, in applications requiring synchronization, it is
recommendedthatthenominaloperatingfrequencyofthe
IC be programmed to be about 80% of the external clock
frequency. Attempting to synchronize to too high an
external frequency (above 1.3fOSC) can result in inad-
equate slope compensation and possible subharmonic
oscillation (or jitter).
1000
100
10
The external clock signal must exceed 2V for at least 25ns,
and should have a maximum duty cycle of 80%, as shown
in Figure 1. The MOSFET turn-on will synchronize to the
rising edge of the external clock signal.
Programming the Operating Frequency
1
1
10
100
1000
10000
The choice of operating frequency and inductor value is a
tradeoff between efficiency and component size. Low
frequency operation improves efficiency by reducing
FREQUENCY (kHz)
3783 G09
Figure 2. Timing Resistor (R ) Value
T
3783f
10
LTC3783
U
OPERATIO
INTVCC Regulator Bypassing and Operation
In an actual application, most of the IC supply current is
used to drive the gate capacitance of the power MOSFET.
Asaresult, highinputvoltageapplicationsinwhichalarge
power MOSFET is being driven at high frequencies can
cause the LTC3783 to exceed its maximum junction tem-
perature rating. The junction temperature can be esti-
mated using the following equations:
An internal, P-channel low dropout voltage regulator pro-
duces the 7V supply which powers the gate drivers and
logic circuitry within the LTC3783 as shown in Figure 3.
The INTVCC regulator can supply up to 50mA and must be
bypassed to ground immediately adjacent to the IC pins
with a minimum of 4.7µF low ESR or ceramic capacitor.
Good bypassing is necessary to supply the high transient
currents required by the MOSFET gate driver.
IQ(TOT) = IQ + f • QG
PIC = VIN • (IQ + f • QG)
TJ = TA + PIC • θJA
For input voltages that don’t exceed 8V (the absolute
maximum rating for INTVCC is 9V), the internal low drop-
out regulator in the LTC3783 is redundant and the INTVCC
pin can be shorted directly to the VIN pin. With the INTVCC
pin shorted to VIN, however, the divider that programs the
regulated INTVCC voltage will draw 15µA from the input
supply, even in shutdown mode. For applications that
require the lowest shutdown mode input supply current,
do not connect the INTVCC pin to VIN. Regardless of
whethertheINTVCC pinisshortedtoVIN ornot, itisalways
necessary to have the driver circuitry bypassed with a
4.7µF low ESR ceramic capacitor to ground immediately
adjacent to the INTVCC and GND pins.
The total quiescent current IQ(TOT) consists of the static
supply current (IQ) and the current required to charge and
discharge the gate of the power MOSFET. The 16-lead FE
package has a thermal resistance of θJA = 38°C/W and the
DHD package has an θJA = 43°C/W
As an example, consider a power supply with VIN = 12V
and VOUT = 25V at IOUT = 1A. The switching frequency is
300kHz, and the maximum ambient temperature is 70°C.
The power MOSFET chosen is the Si7884DP, which has a
maximum RDS(ON) of 10mΩ (at room temperature) and a
INPUT
V
IN
SUPPLY
6V TO 36V
–
1.230V
P-CH
+
C
IN
R2
R1
INTV
7V
CC
C
VCC
4.7µF
X5R
6V-RATED
POWER
GATE
GND
LOGIC
DRIVER
M1
MOSFET
GND
PLACE AS CLOSE AS
POSSIBLE TO DEVICE PINS
3783 F03
Figure 3. Bypassing the LDO Regulator and Gate Driver Supply
3783f
11
LTC3783
U
OPERATIO
maximum total gate charge of 35nC (the temperature
coefficient of the gate charge is low).
A similar analysis applies to the VFBP resistive divider, if
one is used:
IQ(TOT) = 1.2mA + 35nC • 300kHz = 12mA
PIC = 12V • 12mA = 144mW
R3
R3 + R4
V
FBP
= VREF •
TJ = 70°C + 110°C/W • 144mW = 86°C
where R3 is subject to a similar 500nA bias current.
Thisdemonstrateshowsignificantthegatechargecurrent
can be when compared to the static quiescent current in
the IC.
V
IN
3V TO 36V
LTC3783
RUN
PWMIN OV/FB
V
IN
Topreventthemaximumjunctiontemperaturefrombeing
exceeded, the input supply current must be checked when
operating in a continuous mode at high VIN. A tradeoff
between the operating frequency and the size of the power
MOSFET may need to be made in order to maintain a
reliable IC junction temperature. Prior to lowering the
operating frequency, however, be sure to check with the
power MOSFET manufacturers for the latest low QG, low
RDS(ON) devices. Power MOSFET manufacturing tech-
nologiesarecontinuallyimproving,withnewerandbetter-
performing devices being introduced almost monthly.
I
PWMOUT
V
TH
OUT
SS
V
FBP
FBN
FREQ
SYNC
I
R2
R1
LIM
R4
GATE
SENSE
INTV
CC
GND
REF
R3
GND
3783 F04
Figure 4. LTC3783 Boost Application
Programming Turn-On and Turn-Off Thresholds
with the RUN Pin
Output Voltage Programming
The LTC3783 contains an independent, micropower volt-
age reference and comparator detection circuit that re-
mainsactiveevenwhenthedeviceisshutdown, asshown
in Figure 5. This allows users to accurately program an
input voltage at which the converter will turn on and off.
ThefallingthresholdontheRUNpinisequaltotheinternal
reference voltage of 1.248V. The comparator has 100mV
of hysteresis to increase noise immunity.
In constant voltage mode, in order to regulate the output
voltage, the output voltage is set by a resistor divider
according to the following formula:
R2
R1
⎛
⎝
⎞
VOUT = VFBP • 1+
⎜
⎟
⎠
where 0 ≤ V
≤ 1.23V. The external resistor divider is
FBP
The turn-on and turn-off input voltage thresholds are
programed using a resistor divider according to the fol-
lowing formulas:
connected to the output as shown in Figure 4, allowing
remote voltage sensing. The resistors R1 and R2 are
typically chosen so that the error caused by the 500nA
input bias current flowing out of the FBN pin during
normal operation is less than 1%, which translates to a
R2
R1
⎛
⎞
⎟
⎠
V
= 1.248V • 1+
⎜
IN(OFF)
⎝
maximum R1 value of about 25k at V
= 1.23V. For
FBP
R2
R1
⎛
⎞
⎠
lower FBP voltages, R1 must be reduced accordingly to
maintain accuracy, e.g., R1 < 2k for 1% accuracy when
V
IN(ON)
= 1.348V • 1+
⎜
⎟
⎝
V
=100mV. Moreaccuracycanbeachievedwithlower
FBP
The resistor R1 is typically chosen to be less than 1M.
resistances, at the expense of increased dissipation and
decreased light load efficiency.
3783f
12
LTC3783
U
OPERATIO
V
IN
+
R2
R1
RUN
COMPARATOR
RUN
+
–
BIAS AND
START-UP
CONTROL
6V
INPUT
SUPPLY
OPTIONAL
FILTER
CAPACITOR
1.248V
µPOWER
REFERENCE
GND
–
3783 F05a
Figure 5a. Programming the Turn-On and Turn-Off Thresholds Using the RUN Pin
V
IN
+
R2
1M
RUN
RUN
GND
COMPARATOR
+
–
RUN
COMPARATOR
6V
INPUT
SUPPLY
RUN
+
–
3483 F05c
6V
1.248V
EXTERNAL
LOGIC CONTROL
1.248V
–
3483 F05b
Figure 5b. On/Off Control Using External Logic
Figure 5c. External Pull-Up Resistor on
RUN Pin for “Always On” Operation
assuming 50% ripple current, where RDS(ON)/SENSE repre-
sents either the RDS(ON) of the switching MOSFET or
RSENSE, whichever is used on the SENSE pin. Dimming
ratio is described by 1/DPWM as shown in Figure 6.
For applications where the RUN pin is only to be used as
a logic input, the user should be aware of the 7V Absolute
Maximum Rating for this pin! The RUN pin can be con-
nected to the input voltage through an external 1M resis-
tor, as shown in Figure 5c, for “always on” operation.
Application Circuits
Soft-Start Capacitor Selection
AbasicLTC3783PWM-dimmingLEDapplicationisshown
on the first page of this data sheet.
For proper soft-start operation, the LTC3783 should have
a sufficiently large soft-start capacitor, CSS, attached to
the SS pin. The minimum soft-start capacitor size can be
estimated on the basis of output voltage, capacitor size
and load current. In addition, PWM operation reduces the
effective SS capacitor value by the dimming ratio.
Operating Frequency and PWM Dimming Ratio
The minimum operating frequency, fOSC, required for
proper operation of a PWM dimming application depends
ontheminimumPWMfrequency,fPWM,thedimmingratio
1/DPWM, and N, the number of fOSC cycles per PWM cycle:
2 • dimming ratio • 50µA •COUT • VOUT •RDS(ON)/SENSE
CSS(MIN)
>
150mV •1.2V
N • fPWM
DPWM
fOSC
>
3783f
13
LTC3783
U
OPERATIO
output current needs to be reflected back to the input in
ordertodimensionthepowerMOSFETproperly. Basedon
the fact that, ideally, the output power is equal to the input
power, the maximum average input current is:
Figure 6 illustrates these various quantities in relation to
one another.
Typically, in order to avoid visible flicker, fPWM should be
greater than 120Hz. Assuming inductor and capacitor
sizing which is close to discontinuous operation, 2 fOSC
cycles are sufficient for proper PWM operation. Thus,
within the 1MHz rated maximum fOSC, a dimming ratio of
1/DPWM = 3000 is possible.
IOUT(MAX)
I
=
IN(MAX)
1–DMAX
The peak input current is:
IOUT(MAX)
χ
2
⎛
⎝
⎞
1/f
PWM
I
= 1+
•
⎜
⎟
⎠
IN(PEAK)
D
/f
PWM PWM
1–DMAX
PWMIN
GATE
# = N
The maximum duty cycle, DMAX, should be calculated at
minimum VIN.
3783 F06
1/f
OSC
χ
Boost Converter: Ripple Current ∆IL and the ‘ ’ Factor
Figure 6. PWM Dimming Parameters
χ
The constant ‘ ’ in the equation above represents the
percentage peak-to-peak ripple current in the inductor,
relative to its maximum value. For example, if 30% ripple
Boost Converter: Duty Cycle Considerations
χ
current is chosen, then = 0.3, and the peak current is
For a boost converter operating in a continuous conduc-
tion mode (CCM), the duty cycle of the main switch is:
15% greater than the average.
For a current mode boost regulator operating in CCM,
slope compensation must be added for duty cycles above
50% in order to avoid subharmonic oscillation. For the
LTC3783, this ramp compensation is internal. Having an
internally fixed ramp compensation waveform, however,
does place some constraints on the value of the inductor
and the operating frequency. If too large an inductor is
used, theresultingcurrentramp(∆IL)willbesmallrelative
to the internal ramp compensation (at duty cycles above
50%), and the converter operation will approach voltage
mode(rampcompensationreducesthegainofthecurrent
loop). If too small an inductor is used, but the converter is
still operating in CCM (near critical conduction mode), the
internalrampcompensationmaybeinadequatetoprevent
subharmonic oscillation. To ensure good current mode
gain and to avoid subharmonic oscillation, it is recom-
mended that the ripple current in the inductor fall in the
rangeof20%to40%ofthemaximumaveragecurrent.For
example, if the maximum average input current is 1A,
choosea∆IL between0.2Aand0.4A, andcorrespondingly
VOUT + VD – V
IN
D =
VOUT + VD
where VD is the forward voltage of the boost diode. For
converters where the input voltage is close to the output
voltage, the duty cycle is low, and for converters that
developahighoutputvoltagefromalowinputvoltage, the
duty cycle is high. The maximum output voltage for a
boost converter operating in CCM is:
V
IN(MIN)
VOUT(MAX)
=
– VD
1–DMAX
The maximum duty cycle capability of the LTC3783 is
typically 90%. This allows the user to obtain high output
voltages from low input supply voltages.
Boost Converter: The Peak and Average Input Currents
The control circuit in the LTC3783 is measuring the input
current (either by using the RDS(ON) of the power MOSFET
or by using a sense resistor in the MOSFET source), so the
χ
a value ‘ ’ between 0.2 and 0.4.
3783f
14
LTC3783
U
OPERATIO
Boost Converter: Inductor Selection
OUTPUT
VOLTAGE
200mV/DIV
Givenanoperatinginputvoltagerange,andhavingchosen
the operating frequency and ripple current in the inductor,
the inductor value can be determined using the following
equation:
INDUCTOR
CURRENT
1A/DIV
V
⎛
⎝
⎞
⎠
IN(MIN)
L =
•DMAX
MOSFET
DRAIN
VOLTAGE
20V/DIV
⎜
⎟
∆IL • f
where:
3783 F07
1µs/DIV
χ •IOUT(MAX)
1–DMAX
∆IL =
Figure 7. Discontinuous Mode Waveforms
not been shown to contribute significantly to EMI. Any
attempt to damp it with a snubber will degrade the
efficiency.
Remember that most boost converters are not short-
circuit protected. Under a shorted output condition, the
inductor current is limited only by the input supply capa-
bility.Forapplicationsrequiringastep-upconverterthatis
short-circuit protected, please refer to the applications
section covering SEPIC converters.
Boost Converter: Power MOSFET Selection
ThepowerMOSFETcanservetwopurposesintheLTC3783:
it represents the main switching element in the power
path, and its RDS(ON) can represent the current sensing
element for the control loop. Important parameters for the
power MOSFET include the drain-to-source breakdown
voltage BVDSS, the threshold voltage VGS(TH), the on-
resistance RDS(ON) versus gate-to-source voltage, the
gate-to-source and gate-to-drain charges QGS and QGD,
respectively, the maximum drain current ID(MAX) and the
MOSFET’s thermal resistances θJC and θJA.
The minimum required saturation current of the inductor
can be expressed as a function of the duty cycle and the
load current, as follows:
IOUT(MAX)
χ
2
⎛
⎝
⎞
IL(SAT) > 1+
•
⎜
⎟
⎠
1–DMAX
The saturation current rating for the inductor should be
checkedattheminimuminputvoltage(whichresultsinthe
highest inductor current) and maximum output current.
The gate drive voltage is set by the 7V INTVCC low drop
regulator. Consequently, 6V rated MOSFETs are required
in most high voltage LTC3783 applications. If low input
voltage operation is expected (e.g., supplying power from
alithium-ionbatteryora3.3Vlogicsupply),thensublogic-
level threshold MOSFETs should be used. Pay close atten-
tion to the BVDSS specifications for the MOSFETs relative
to the maximum actual switch voltage in the application.
Manylogic-leveldevicesarelimitedto30Vorless, andthe
switch node can ring during the turn-off of the MOSFET
due to layout parasitics. Check the switching waveforms
of the MOSFET directly across the drain and source
terminals using the actual PC board layout for excessive
ringing.
Boost Converter: Operating in Discontinuous Mode
Discontinuous mode operation occurs when the load
current is low enough to allow the inductor current to run
outduringtheoff-timeoftheswitch, asshowninFigure 7.
Once the inductor current is near zero, the switch and
diode capacitances resonate with the inductance to form
damped ringing at 1MHz to 10MHz. If the off-time is long
enough, the drain voltage will settle to the input voltage.
Depending on the input voltage and the residual energy in
the inductor, this ringing can cause the drain of the power
MOSFET to go below ground where it is clamped by the
body diode. This ringing is not harmful to the IC and it has
3783f
15
LTC3783
U
OPERATIO
Duringtheswitchon-time,theIMAXcomparatorlimitsthe
absolute maximum voltage drop across the power
MOSFET to a nominal 150mV, regardless of duty cycle.
The peak inductor current is therefore limited to
150mV/RDS(ON). The relationship between the maximum
load current, duty cycle, and the RDS(ON) of the power
MOSFET is:
the maximum current drawn from the input supply, and
also to avoid triggering the 150mV IMAX comparator, as
this condition can result in excessive noise.
Calculating Power MOSFET Switching and Conduction
Losses and Junction Temperatures
In order to calculate the junction temperature of the power
MOSFET, the power dissipated by the device must be
known. This power dissipation is a function of the duty
cycle, the load current, and the junction temperature itself
(duetothepositivetemperaturecoefficientofitsRDS(ON)).
As a result, some iterative calculation is normally required
to determine a reasonably accurate value. Since the con-
troller is using the MOSFET as both a switching and a
sensing element, care should be taken to ensure that the
converteriscapableofdeliveringtherequiredloadcurrent
over all operating conditions (line voltage and tempera-
ture),andfortheworst-casespecificationsforVSENSE(MAX)
andtheRDS(ON) oftheMOSFETlistedinthemanufacturer’s
data sheet.
1–DMAX
RDS(ON) < 150mV •
χ
2
⎛
⎞
1+
•IOUT(MAX) •ρT
⎜
⎝
⎟
⎠
TheρT termaccountsforthetemperaturecoefficientofthe
RDS(ON) of the MOSFET, which is typically 0.4%/°C. Fig-
ure 8 illustrates the variation of normalized RDS(ON) over
temperature for a typical power MOSFET.
Another method of choosing which power MOSFET to use
istocheckwhatthemaximumoutputcurrentisforagiven
RDS(ON), since MOSFET on-resistances are available in
discrete values.
The power dissipated by the MOSFET in a boost converter
is:
1–DMAX
IO(MAX) = 150mV •
χ
2
⎛
⎞
1+
•RDS(ON) • ρT
⎜
⎝
⎟
⎠
2
I
⎛
⎞
OUT(MAX)
PFET
=
•RDS(ON) •DMAX • ρT +
⎜
⎝
⎟
⎠
1–D
It is worth noting that the 1 - DMAX relationship between
IO(MAX) and RDS(ON) can cause boost converters with a
wide input range to experience a dramatic range of maxi-
mum input and output currents. This should be taken into
consideration in applications where it is important to limit
MAX
I
⎛
⎞
OUT(MAX)
1.85
k • VOUT
•
•CRSS • f
⎜
⎝
⎟
⎠
1–D
MAX
The first term in the equation above represents the I2R
losses in the device, and the second term, the switching
losses.Theconstantk=1.7isanempiricalfactorinversely
related to the gate drive current and has the dimension of
1/current.
2.0
1.5
1.0
0.5
0
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:
TJ = TA + PFET • θJA
The θJA to be used in this equation normally includes the
θJC for the device plus the thermal resistance from the
casetotheambienttemperature(θCA).ThisvalueofTJ can
then be compared to the original, assumed value used in
50
100
–50
150
0
JUNCTION TEMPERATURE (°C)
3783 F08
Figure 8. Normalized R
vs Temperature
the iterative calculation process.
DS(ON)
3783f
16
LTC3783
U
OPERATIO
Boost Converter: Output Diode Selection
To maximize efficiency, a fast switching diode with low
forward drop and low reverse leakage is desired. The
output diode in a boost converter conducts current during
the switch off-time. The peak reverse voltage that the
diode must withstand is equal to the regulator output
voltage. The average forward current in normal operation
isequaltotheoutputcurrent, andthepeakcurrentisequal
to the peak inductor current.
V
OUT
(AC)
∆V
COUT
3783 F09
∆V
ESR
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
Figure 9. Output Ripple Voltage
ESR step and the charging/discharging ∆V. This percent-
age ripple will change, depending on the requirements of
the application, and the equations provided below can
easily be modified.
IOUT(MAX)
1–DMAX
χ
2
⎛
⎝
⎞
ID(PEAK) = IL(PEAK) = 1+
•
⎜
⎟
⎠
The power dissipated by the diode is:
PD = IOUT(MAX) • VD
For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor can be determined using the
following equation:
and the diode junction temperature is:
TJ = TA + PD • θJA
VOUT
ESRCOUT < 0.01•
The θJA to be used in this equation normally includes the
θJC for the device plus the thermal resistance from the
board to the ambient temperature in the enclosure.
I
IN(PEAK)
where:
I
IOUT(MAX)
1–DMAX
χ
2
⎛
⎝
⎞
= 1+
•
Remember to keep the diode lead lengths short and to
observe proper switch-node layout (see Board Layout
Checklist) to avoid excessive ringing and increased
dissipation.
IN(PEAK)
⎜
⎟
⎠
For the bulk C component, which also contributes 1% to
the total ripple:
Boost Converter: Output Capacitor Selection
IOUT(MAX)
COUT
>
Contributions of ESR (equivalent series resistance), ESL
(equivalent series inductance) and the bulk capacitance
must be considered when choosing the correct compo-
nent for a given output ripple voltage. The effects of these
three parameters (ESR, ESL and bulk C) on the output
voltage ripple waveform are illustrated in Figure 9 for a
typical boost converter.
0.01• VOUT • f
For many designs it is possible to choose a single capaci-
tor type that satisfies both the ESR and bulk C require-
ments for the design. In certain demanding applications,
however, the ripple voltage can be improved significantly
by connecting two or more types of capacitors in parallel.
For example, using a low ESR ceramic capacitor can
minimize the ESR setup, while an electrolytic capacitor
can be used to supply the required bulk C.
The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step and the charging/discharging ∆V.
For the purpose of simplicity we will choose 2% for the
maximum output ripple, to be divided equally between the
Once the output capacitor ESR and bulk capacitance have
been determined, the overall ripple voltage waveform
should be verified on a dedicated PC board (see Board
3783f
17
LTC3783
U
OPERATIO
Layout section for more information on component place-
ment). Lab breadboards generally suffer from excessive
series inductance (due to inter-component wiring), and
these parasitics can make the switching waveforms look
significantly worse than they would be on a properly
designed PC board.
Please note that the input capacitor can see a very high
surge current when a battery is suddenly connected to the
input of the converter, and solid tantalum capacitors can
fail catastrophically under these conditions. Be sure to
specify surge-tested capacitors!
Boost Converter Design Example
Theoutputcapacitorinaboostregulatorexperienceshigh
RMS ripple currents. The RMS output capacitor ripple
current is:
Thedesignexamplegivenherewillbeforthecircuitshown
inFigure1.Theinputvoltageis12V,andtheoutputvoltage
is 25V at a maximum load current of 0.7A (1A peak).
VOUT – V
1. The duty cycle is:
IN(MIN)
IRMS(COUT) ꢀIOUT(MAX) •
V
IN(MIN)
VOUT + VD – V
25 + 0.4 – 12
25 + 0.4
IN
D =
=
= 53%
VOUT + VD
Note that the ripple current ratings from capacitor manu-
facturers are often based on only 2000 hours of life. This
makes it advisable to further derate the capacitor or to
choose a capacitor rated at a higher temperature than
required. Several capacitors may also be placed in parallel
to meet size or height requirements in the design.
2. The operating frequency is chosen to be 1MHz to
maximize the PWM dimming range. From Figure 2, the
resistor from the FREQ pin to ground is 6k.
3. An inductor ripple current of 40% of the maximum load
current is chosen, so the peak input current (which is also
the minimum saturation current) is:
Boost Converter: Input Capacitor Selection
Theinputcapacitorofaboostconverterislesscriticalthan
the output capacitor, due to the fact that the inductor is in
series with the input, and hence, the input current wave-
form is continuous (see Figure 10). The input voltage
source impedance determines the size of the input capaci-
tor, which is typically in the range of 10µF to 100µF. A low
ESR capacitor is recommended, although it is not as
critical as for the output capacitor.
IOUT(MAX)
1–DMAX
χ
2
0.7
1– 0.53
⎛
⎝
⎞
I
= 1+
•
= 1.2 •
= 1.8A
IN(PEAK)
⎜
⎟
⎠
The inductor ripple current is:
IOUT(MAX)
0.7
1− 0.53
∆IL = χ •
= 0.4 •
= 0.6A
1−DMAX
And so the inductor value is:
The RMS input capacitor ripple current for a boost con-
verter is:
V
12V
IN(MIN)
L =
•DMAX
=
• 0.53 = 11µH
V
I
RMS(CIN) ꢀ 0.3• IN(MIN) •DMAX
∆IL • f
4. RSENSE should be:
0.5 • VSENSE(MAX)
0.6A •1MHz
L • f
I
IN
I
L
0.5 •150mV
RSENSE
=
=
= 42mΩ
I
1.8A
IN(PEAK)
Figure 10. Inductor and Input Currents
3783f
18
LTC3783
U
OPERATIO
5. The diode for this design must handle a maximum DC
output current of 0.7A and be rated for a minimum reverse
voltage of VOUT, or 25V. A 1A, 40V diode from Zetex was
chosen for its specifications, especially low leakage at
higher temperatures, which is important for maintaining
dimming range.
the INTVCC decoupling capacitor, 2) the negative terminal
of the output decoupling capacitors, 3) the bottom termi-
nals of the sense resistors or the source of the power
MOSFET, 4) the negative terminal of the input capacitor,
and 5) at least one via to the ground plane immediately
under the exposed pad. The ground trace on the top layer
of the PC board should be as wide and short as possible
to minimize series resistance and inductance.
6. Voltage and value permitting, the output capacitor
usually consists of some combination of low ESR ceram-
ics. Based on a maximum output ripple voltage of 1%, or
250mV, the bulk C needs to be greater than:
2. Beware of ground loops in multiple layer PC boards. Try
to maintain one central ground node on the board and use
the input capacitor to avoid excess input ripple for high
output current power supplies. If the ground plane is to be
used for high DC currents, choose a path away from the
small-signal components.
IOUT(MAX)
0.01• VOUT • f 0.01• 25V •1MHz
0.7A
COUT
>
=
= 3µF
The RMS ripple current rating for this capacitor needs to
exceed:
3. Place the CVCC capacitor immediately adjacent to the
INTVCC and GND pins on the IC package. This capacitor
carries high di/dt MOSFET gate-drive currents. A low ESR
and ESL 4.7µF ceramic capacitor works well here.
VOUT – V
IN(MIN)
IRMS(COUT) = IOUT(MAX)
•
V
IN(MIN)
4. The high di/dt loop from the bottom terminal of the
outputcapacitor,throughthepowerMOSFET,throughthe
boostdiodeandbackthroughtheoutputcapacitorsshould
be kept as tight as possible to reduce inductive ringing.
Excess inductance can cause increased stress on the
powerMOSFETandincreaseHFnoiseontheoutput. Iflow
ESR ceramic capacitors are used on the output to reduce
output noise, place these capacitors close to the boost
diodeinordertokeeptheseriesinductancetoaminimum.
25V – 12V
= 0.7A •
= 0.7A
12V
Based on value and ripple current, and taking physical size
into account, a surface mount ceramic capacitor is a good
choice. A 4.7µF TDK C5750X7R1H475M will satisfy all
requirements in a compact package.
7. The soft-start capacitor should be:
5. Check the stress on the power MOSFET by measuring
its drain-to-source voltage directly across the device ter-
minals (reference the ground of a single scope probe
directly to the source pad on the PC board). Beware of
inductive ringing which can exceed the maximum speci-
fied voltage rating of the MOSFET. If this ringing cannot be
avoided and exceeds the maximum rating of the device,
either choose a higher voltage device or specify an ava-
lanche-rated power MOSFET.
2 • dimming ratio • 50µA •COUT • VOUT •RDS(ON)/SENSE
CSS(MIN)
>
>
150mV •1.2V
2 • 3000 • 50µA • 4.7µF • 25V • 42mΩ
= 8µF
150mV •1.2V
8. The choice of an input capacitor for a boost converter
depends on the impedance of the source supply and the
amount of input ripple the converter will safely tolerate.
Forthisparticulardesignandlabsetup, 20µFwasfoundto
be satisfactory.
6. Place the small-signal components away from high
frequencyswitchingnodes. Allofthesmall-signalcompo-
nents should be placed on one side of the IC and all of the
power components should be placed on the other. This
also allows the use of a pseudo-Kelvin connection for the
signal ground, where high di/dt gate driver currents flow
PC Board Layout Checklist
1. In order to minimize switching noise and improve
output load regulation, the GND pad of the LTC3783
should be connected directly to 1) the negative terminal of
3783f
19
LTC3783
U
OPERATIO
out of the IC ground pad in one direction (to bottom plate
of the INTVCC decoupling capacitor) and small-signal
currents flow in the other direction.
Returning the Load to VIN: A Single Inductor
Buck-Boost Application
As shown in Figure 11, due to its available high side
current sensing mode, the LTC3783 is also well-suited to
a boost converter in which the load current is returned to
VIN, hence providing a load voltage (VOUT – VIN) which can
be greater or less than the input voltage VIN. This configu-
ration allows for complete overlap of input and output
voltages, with the disadvantages that only the load cur-
rent, andnottheloadvoltage, canbetightlyregulated. The
7. If a sense resistor is used in the source of the power
MOSFET, minimize the capacitance between the SENSE
pin trace and any high frequency switching nodes. The
LTC3783 contains an internal leading-edge blanking time
of approximately 160ns, which should be adequate for
most applications.
8. For optimum load regulation and true remote sensing,
the top of the output resistor should connect indepen-
dently to the top of the output capacitor (Kelvin connec-
tion), staying away from any high dV/dt traces. Place the
divider resistors near the LTC3783 in order to keep the
high impedance FBN node short.
switch must be rated for a VDS(MAX) equal to VIN + VLOAD
.
The design of this circuit resembles that of the boost
converter above, and the procedure is much the same,
except VOUT is now (VIN + VLOAD), and the duty cycles and
voltages must be adjusted accordingly.
9. Forapplicationswithmultipleswitchingpowerconvert-
ersconnectedtothesameinputsupply,makesurethatthe
input filter capacitor for the LTC3783 is not shared with
any other converters. AC input current from another
convertercouldcausesubstantialinputvoltageripple,and
this could interfere with the operation of the LTC3783. A
fewinchesofPCtraceorwire(L~100nH)betweentheCIN
of the LTC3783 and the actual source VIN should be
sufficient to prevent current-sharing problems.
Similar to the boost converter, which can be dimmed via
the digital PWMIN input or the analog FBP pin, the buck-
boost can be dimmed via the PWMIN pin or the analog
ILIM pin, which adjusts the offset voltage to which the
loop will drive (VFBP – VFBN). In the case of the buck-
boost, however, the dimming ratio cannot be as high as
in the boost converter, since there is no load switch to
preserve the VOUT level while PWMIN is low.
V
IN
9V TO 26V
10µF, 50V
×2
UMK432C106MM
10µH
R
L
1M
SUMIDA
0.28Ω
LED STRING 1-4 EA
CDRH8D28-100
LUMILEDS LHXL-BW02
EACH LED IS 3V TO 4.2V
AT 350mA
PMEG6010
40.2k
LTC3783
V
OUT
RUN
PWMIN OV/FB
PWMOUT
V
IN
PWM
5V AT 0Hz TO 10Hz
I
SS
V
TH
0V TO
1.23V
I
LIM
100k
FAIRCHILD
FDN5630
10µF, 50V
C5750X7R1H106M
CERAMIC
GATE
REF
FBP
SENSE
1µF
FBN
INTV
CC
4.7µF
4.7µF
FREQ
SYNC
GND
0.05Ω
1k
20k
GND
3783 F11
Figure 11. Single Inductor Buck-Boost Application with Analog Dimming and Low Frequency PWM Dimming
3783f
20
LTC3783
U
OPERATIO
Using the LTC3783 for Buck Applications
VIN. In this scheme the input voltage to the inductor is
lowered by the load voltage. The boost converter now
sees a VIN’ = VIN – VLOAD, meaning the controller is now
boosting from (VIN – VLOAD) to VIN.
As shown in Figure 12, high side current sensing also
allows the LTC3783 to control a functional buck con-
verter when load voltage is always sufficiently less than
V
IN
6V TO 36V
LED STRING
LTC3783
RUN
PWMIN OV/FB
PWMOUT
V
IN
I
TH
SS
I
LIM
V
GATE
REF
FBP
SENSE
FBN
FREQ
SYNC
INTV
CC
GND
GND
3783 F12
Figure 12. LED Buck Application
3783f
21
LTC3783
U
PACKAGE DESCRIPTIO
DHD Package
16-Lead Plastic DFN (5mm × 4mm)
(Reference LTC DWG # 05-08-1707)
0.70 ±0.05
4.50 ±0.05
3.10 ±0.05
2.44 ±0.05
(2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
4.34 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
0.40 ± 0.10
5.00 ±0.10
(2 SIDES)
9
16
R = 0.20
TYP
4.00 ±0.10 2.44 ± 0.10
(2 SIDES)
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
PIN 1
NOTCH
(DHD16) DFN 0504
8
1
0.25 ± 0.05
0.75 ±0.05
0.200 REF
0.50 BSC
4.34 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJGD-2) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3783f
22
LTC3783
U
PACKAGE DESCRIPTIO
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BC
4.90 – 5.10*
(.193 – .201)
3.58
(.141)
3.58
(.141)
16 1514 13 12 1110
9
6.60 ±0.10
4.50 ±0.10
2.94
(.116)
6.40
(.252)
BSC
SEE NOTE 4
2.94
(.116)
0.45 ±0.05
1.05 ±0.10
0.65 BSC
5
7
8
1
2
3
4
6
RECOMMENDED SOLDER PAD LAYOUT
1.10
(.0433)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE16 (BC) TSSOP 0204
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
3783f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
23
LTC3783
RELATED PARTS
PART NUMBER
LT®1618
DESCRIPTION
COMMENTS
Monolithic 1.4MHz Boost Regulator
Boost, Flyback, SEPIC Controller
3A DC/DC LED Driver with Rail-to-Rail Current Sense
High Power Buck-Boost Controller
2-Phase Boost Controller
Constant-Current/Constant-Voltage, 1A Switch
LTC1871
LT3477
No R , 2.5V ≤ V ≤ 36V, 92% Duty Cycle
SENSE IN
2.5V ≤ V ≤ 25V: Buck, Buck-Boost and Boost Topologies
IN
LTC3780
LTC3782
4-Switch, 4V ≤ V ≤ 36V, 0.8V ≤ V
≤ 30V
OUT
IN
High Power, 6V ≤ V ≤ 40V, 150kHz to 500kHz
IN
LTC3827/LTC3827-1 Low I Current Dual Controllers
2-Phase, 80µA I , 0.8V ≤ V
≤ 10V, 4V ≤ V ≤ 36V
OUT IN
Q
Q
LTC4002
Standalone 2A Li-Ion Battery Charger
1- and 2-Cell, 4.7V ≤ V ≤ 22V, 3 Hour Timer
IN
3783f
LT 1105 • PRINTED IN THE USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005
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