LT3501 [Linear]
Monolithic Dual Tracking 3A Step-Down Switching Regulator; 单片双通道跟踪3A降压型开关稳压器
| 型号： | LT3501 |
| 厂家： | 
Linear |
| 描述： | Monolithic Dual Tracking 3A Step-Down Switching Regulator |
| 文件： | 总28页 (文件大小：438K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3501
Monolithic Dual Tracking
3A Step-Down Switching
Regulator
FEATURES
DESCRIPTION
■
Wide Input Range: 3.1V to 25V
The LT®3501 is a dual current mode PWM step-down
DC/DC converter with two internal 3.5A switches. Inde-
pendent input voltage, feedback, soft-start and power
good pins for each channel simplify complex power
supply tracking/sequencing requirements.
■
Two Switching Regulators with 3A Output Capability
■
Independent Supply to Each Regulator
■
Adjustable/Synchronizable Fixed Frequency
Operation from 250kHz to 1.5MHz
■
Antiphase Switching
Outputs Can be Paralleled
Both converters are synchronized to either a common
external clock input or a resistor programmable fixed
250kHz to 1.5MHz internal oscillator. At all frequencies, a
180° phase relationship between channels is maintained,
reducingvoltagerippleandcomponentsize.Programmable
frequency allows for optimization between efficiency and
external component size.
■
■
Independent, Sequential, Ratiometric or Absolute
Tracking Between Outputs
■
Independent Soft-Start and Power Good Pins
■
Enhanced Short-Circuit Protection
■
Low Dropout: 95% Maximum Duty Cycle
■
Low Shutdown Current: <10µA
■
Minimum input-to-output voltage ratios are improved
by allowing the switch to stay on through multiple clock
cycles, only switching off when the boost capacitor needs
recharging, resulting in ~95% maximum duty cycle.
20-Lead TSSOP Package with Exposed Leadframe
APPLICATIONS
■
DSP Power Supplies
Each output can be independently disabled using its own
soft-start pin, or by using the SHDN pin the entire part can
be placed in a low quiescent current shutdown mode.
■
Disc Drives
■
DSL/Cable Modems
■
Wall Transformer Regulation
■
The LT3501 is available in a 20-lead TSSOP package with
exposed leadframe for low thermal resistance.
Distributed Power Regulation
, LT, LTC, and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
3.3V and 1.8V Dual 3A Step-Down Converter with Output Tracking
V
IN
12V
Efficiency
4.7µF
100
V
V
IN2
R /SYNC
T
IN1
61.9k
V
= 3.3V
= 2.5V
OUT1
V
= 5V
OUT1
SHDN
90
80
70
60
50
40
30
20
10
0
BST1
SW1
BST2
SW2
3.3µH
4.7µH
0.47µF
B360A
0.47µF
V
= 1.8V
OUT1
V
OUT1
B360A
PMEG4005
PMEG4005
LT3501
IND1
IND2
V
OUT2
V
V
1.8V
3A
OUT1
3.3V
3A
OUT2
V
OUT1
47µF
100µF
10k
24.9k
PG1
FB1
PG2
FB2
V
C2
V
= 12V
OUT2
FREQUENCY = 500kHz
IN
I
= 0A
V
C1
470pF
40.2k
470pF
40.2k
SS/TRACK1 SS/TRACK2
GND
0
0.5
1.5
2
2.5
3
1
8.06k
10pF
47pF
8.06k
LOAD CURRENT (A)
3501 TA01b
0.1µF
3501 TA01a
3501fb
1
LT3501
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
(Note 1)
TOP VIEW
V
, SHDN, PG1/2...................................... 25V/–0.3V
IN1/2
V
1
2
20
19
18
17
16
15
14
13
12
11
BST1
SW1/2....................................................................V
IN1
IN1/2
SW1
IND1
SS/TRACK1
BST1/2........................................................... 35V/–0.3V
BST1/2 Pins Above SW1/2........................................25V
IND1/2 ..................................................................... 5A
3
V
C1
V
4
FB1
OUT1
PG1
5
R /SYNC
T
V
........................................................ V
/–0.3V
IN1/2
21
OUT1/2
PG2
6
SHDN
FB2
FB1/2, SS1/2, R /SYNC............................................5.5V
T
V
7
OUT2
V
...................................................................... 1mA
C1/2
IND2
SW2
8
V
C2
Operating Junction Temperature Range
9
SS/TRACK2
BST2
LT3501EFE (Notes 2, 8)..................... –40°C to 125°C
LT3501IFE (Notes 2, 8)...................... –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
V
10
IN2
FE PACKAGE
20-LEAD PLASTIC TSSOP
= 125°C, θ = 45°C/W, θ = 10°C/W
JC(PAD)
T
JMAX
JA
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
ORDER PART NUMBER
LT3501EFE
LT3501IFE
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
unless otherwise specified.
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V
= 15V, V
= open, V
= 2V, V
= open,
VOUT1/2
J
VIN1/2
BST1/2
RT/SYNC
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
●
SHDN Threshold
SHDN Input Current
V
= 0V, R /SYNC = 133k
1.23
1.28
1.37
V
OUT1/2
T
V
SHDN
V
SHDN
= 1.375V
= 1.225V
7
2
10
3
13
5
µA
µA
Minimum Input Voltage Ch 1 (Note 3)
Minimum Input Voltage Ch 2
Supply Shutdown Current Ch 1
Supply Shutdown Current Ch 2
Supply Quiescent Current Ch 1
Supply Quiescent Current Ch 2
Feedback Voltage Ch 1/2
V
FB1/2
V
FB1/2
V
SHDN
V
SHDN
V
FB1/2
V
FB1/2
V
VC1/2
V
VIN1/2
V
VC1/2
V
FB1/2
V
VC1/2
= 0V, V
= 0V, V
= 0V
= 0V, V
= 0V, V
= 0V, R /SYNC = 133k
2.8
2.8
9
3
3
V
V
VOUT1/2
VOUT1/2
IND1/2
IND1/2
T
= 0V
●
30
µA
= 0V
0
5
µA
= 0.9V
= 0.9V
= 1V
3.5
200
0.8
0
5
mA
µA
500
0.816
1
●
●
●
●
●
0.784
–1
V
Feedback Voltage Line Regulation
Feedback Voltage Offset Ch 1 to Ch 2
Feedback Bias Current Ch 1/2
= 3V to 25V
= 1V
%
–16
0
16
mV
nA
= 0.8V, V
= 1V
5µA
–250
150
75
250
450
VC1/2
Error Amplifier g Ch 1/2
= 1V, I
=
275
1000
3.3
µmho
V/V
A/V
m
VC1/2
Error Amplifier Gain Ch 1/2
Error Amplifier to Switch Gain Ch 1/2
3501fb
2
LT3501
ELECTRICAL CHARACTERISTICS
unless otherwise specified.
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V
= 15V, V
= open, V
= 2V, V
= open,
VOUT1/2
J
VIN1/2
BST1/2
RT/SYNC
PARAMETER
CONDITIONS
MIN
10
TYP
15
MAX
UNITS
µA
µA
V
Error Amplifier Source Current Ch 1/2
Error Amplifier Sink Current Ch 1/2
Error Amplifier High Clamp Ch 1/2
Error Amplifier Switching Threshold Ch 1/2
Soft-Start Source Current Ch 1/2
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 0.6V, V
= 1V
25
30
FB1/2
FB1/2
FB1/2
OUT1/2
VC1/2
= 1V, V
= 0.7V
= 1V
15
20
VC1/2
1.75
0.5
2.5
1.9
200
50
2.0
0.7
3.25
2
2.25
1.0
4
= 5V, R /SYNC = 133k
V
T
●
●
= 0.6V, V
= 0.4V
µA
V
FB1/2
FB1/2
FB1/2
FB1/2
VC1/2
SS1/2
FB1/2
FB1/2
FB1/2
FB1/2
FB1/2
FB1/2
VIN1/2
FB1/2
SS1/2
Soft-Start V Ch 1/2
= 0.9V
= 0.6V, V
= 0V
2.4
1000
125
16
OH
Soft-Start Sink Current Ch 1/2
= 1V
600
80
µA
mV
mV
mA
mV
mV
µA
%
SS1/2
Soft-Start V Ch 1/2
OL
Soft-Start to Feedback Offset Ch 1/2
Soft-Start Sink Current Ch 1/2 POR
Soft-Start POR Threshold Ch 1/2
Soft-Start Switching Threshold Ch 1/2
Power Good Leakage Ch 1/2
= 1V, V
= 0.4V
–16
0.5
55
0
SS1/2
= 0.4V (Note 4), V = 1V
1.5
80
2
VC
= 0V (Note 4)
= 0V
105
70
30
50
= 0.9V, V
= 25V, V
= 25V
VIN1/2
0
1
PG1/2
●
Power Good Threshold Ch 1/2
Rising, PG1/2 = 20k to 5V
Falling, PG1/2 = 20k to 5V
87
20
90
93
Power Good Hysteresis Ch 1/2
30
50
mV
µA
µA
V
Power Good Sink Current Ch 1/2
Power Good Shutdown Sink Current Ch 1/2
= 0.65V, V
= 0.4V
400
10
800
50
1200
100
1
PG1/2
= 2V, V
= 0V, V
= 0.4V
FB1/2
PG1/2
R /SYNC Reference Voltage
T
= 0.9V, I
= –40µA
0.93
0.975
RT/SYNC
Switching Frequency
R /SYNC = 133k, V
T
= 0.6V, V
FB1/2
= V + 3V
200
1.2
250
1.5
300
1.8
kHz
MHz
T
FB1/2
BST1/2
SW
R /SYNC = 15.4k, V
= 0.6V, V
= V + 3V
BST1/2
SW
Switching Phase Angle Ch A to Ch B
Minimum Boost for 100% Duty Cycle Ch 1/2
SYNC Frequency Range
R /SYNC = 133k, V
= 0.6V, V
= V + 3V
120
180
1.7
210
2
Deg
V
T
FB1/2
BST1/2
SW
V
V
= 0.7V, I
= –35µA (Note 5), V
= 0V
FB1/2
RT/SYNC
OUT
= V + 3V
250
120
40
1500
210
kHz
Deg
BST1/2
SW
SYNC Switching Phase Angle Ch A to Ch B
SYNC Frequency = 250kHz, V
= V + 3V
180
BST1/2
SW
IND + V
Current Ch 1/2
V
V
= 0V, V
= 5V
= 0.9V
FB1/2
70
0
100
1
µA
µA
OUT
VOUT1/2
VOUT1/2
IND to V
Maximum Current Ch 1/2
V
V
= 0.5V (Note 6), V
= 0.7V, V = 20V
BST1/2
3.25
3.5
4
4
5
5
A
A
OUT
VOUT1/2
VOUT1/2
FB1/2
= 5V (Note 6), R /SYNC = 133k, V
= 20V
T
BST1/2
●
●
Switch Leakage Current Ch 1/2
Switch Saturation Voltage Ch 1/2
Boost Current Ch 1/2
V
= 0V, V
= 25V
0
50
µA
mV
mA
V
SW1/2
SW1/2
SW1/2
SW1/2
VIN1/2
BST1/2
BST1/2
BST1/2
I
I
I
= 3A, V
= 3A, V
= 3A, V
= 20V, V
= 20V, V
= 20V, V
= 0.7V
= 0.7V
= 0.7V
250
60
600
100
2.5
FB1/2
FB1/2
FB1/2
25
Minimum Boost Voltage Ch 1/2
1.4
constant. Actual minimum input voltage to maintain a regulated output
will depend upon output voltage and load current. See Applications
Information.
Note 4: An internal power-on reset (POR) latch is set on the positive
transition of the SHDN pin through its threshold. The output of the latch
activates current sources on each SS pin which typically sink 1.5mA,
discharging the SS capacitor. The latch is reset when both SS pins are
driven below the soft-start POR threshold or the SHDN pin is taken below
its threshold.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3501EFE is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3501IFE is guaranteed and tested over the full –40°C to 125°C operating
junction temperature range.
Note 5: To enhance dropout operation, the output switch will be turned off
for the minimum off time only when the voltage across the boost capacitor
drops below the minimum boost for 100% duty cycle threshold.
3501fb
Note 3: Minimum input voltage is defined as the voltage where internal
bias lines are regulated so that the reference voltage and oscillator remain
3
LT3501
ELECTRICAL CHARACTERISTICS
Note 6: The IND to V
maximum current is defined as the value of
Note 8: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
OUT
current flowing from the IND pin to the V
pin which resets the switch
OUT
latch when the V pin is at its high clamp.
C
Note 7: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.
TYPICAL PERFORMANCE CHARACTERISTICS
Shutdown Threshold and Minimum
Input Voltage vs Temperature
Feedback Voltage vs Temperature
R /SYNC Voltage vs Temperature
T
1.05
1.03
1.01
0.99
0.97
0.95
0.816
0.811
0.806
0.801
3.0
2.5
2.0
1.5
MINIMUM INPUT
VOLTAGE
SHUTDOWN
THRESHOLD
VOLTAGE
0.796
0.791
0.786
1.0
0.5
0
–50 –25
0
25
50
75 100 125
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
TEMPERATURE (°C)
3501 G03
3501 G02
3501 G04
Shutdown Quiescent Current
vs Temperature
Soft-Start Source Current
vs Temperature
IND to V
Maximum Current
OUT
vs Temperature
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
16
14
12
V
VIN1
10
8
V
= 5V
OUT
V
= 0V
OUT
6
4
2
V
VIN2
0
–50
0
25
50
75 100 125
50
TEMPERATURE (°C)
125
–25
–50
0
25
75 100
–25
–25
0
50
75 100 125
–50
25
TEMPERATURE (°C)
TEMPERATURE (°C)
3501 G07
3501 G30
3501 G05
3501fb
4
LT3501
TYPICAL PERFORMANCE CHARACTERISTICS
Soft-Start to Feedback Offset
Voltage vs Temperature
V Switching Threshold Voltage
Power Good Threshold Voltage
vs Temperature
C
vs Temperature
800
780
760
740
720
700
680
660
640
620
600
1000
900
800
700
4
3
2
RISING
FALLING
1
0
V
= 5V
OUT
V
0
= 0V
OUT
–1
–2
–3
600
500
400
–4
50
100 125
–50
–25
0
25
50
75 100 125
–25
0
50
75 100 125
–50 –25
25
75
–50
25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3501 G09
3501 G10
3501 G08
Switching Frequency and Channel
Phase vs Temperature
Power Good Sink Current
vs Temperature
Minimum Switching Times
vs Temperature
300
290
280
270
260
250
240
230
220
210
200
200
190
180
170
160
150
140
130
120
110
100
1000
950
900
850
800
750
700
650
600
550
500
250
230
210
190
170
150
130
110
90
R /SYNC = 133kΩ
T
MINIMUM ON TIME
PHASE
FREQUENCY
MINIMUM OFF TIME
70
50
–50
–25
0
25
50
75 100 125
–50
0
25
50
75 100 125
–50
0
25
50
75 100 125
–25
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3501 G13
3501 G11
3501 G12
Switching Frequency and Channel
Phase vs Temperature
Syncronization Clock Frequency
Range vs Temperature
Channel Phase vs Temperature
with External Synchronization
188
2500
1650
1600
1550
1500
200
195
190
185
180
175
170
165
160
155
150
R
/SYNC = 15.4k
RT
186
164
182
180
178
176
174
172
170
168
2000
1500
1000
500
0
PHASE
MAXIMUM
SYNCHRONIZATION
FREQUENCY
SYNCHRONIZATION
FREQUENCY = 250kHz
FREQUENCY
1450
1400
1350
MINIMUM
SYNCHRONIZATION
FREQUENCY
SYNCHRONIZATION
FREQUENCY = 1500kHz
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
125
–50
0
25
50
75
125
–50 –25
0
25
75
–50 –25
0
25
75
–25
100
100
TEMPERATURE (°C)
3501 G14
3501 G15
3501 G16
3501fb
5
LT3501
TYPICAL PERFORMANCE CHARACTERISTICS
External Sync Duty Cycle Range
vs External Sync Frequency
Switch Saturation Voltage
vs Switch Current
Frequency and Phase vs R /SYNC
T
Pin Resistance
100
90
80
70
60
50
40
30
20
10
0
450
400
350
300
250
200
150
100
50
1600
1400
1200
1000
800
190
185
180
175
170
165
160
155
150
125°C
MAXIMUM CLOCK
DUTY CYCLE
FREQUENCY
25°C
–50°C
PHASE
600
MINIMUM CLOCK
DUTY CYCLE
400
200
100
0
250
500
750
1000
1250
1500
0
20
40
60
80 100 120 140
0.5
1
1.5
2
2.5
3
3.5
FREQUENCY (kHz)
RESISTANCE (kΩ)
CURRENT (A)
3501 G17
1344 G18
3501 G19
V
+ IND Current
Minimum Boost Voltage
vs Temperature
V
+ IND Current
OUT
OUT
vs Voltage
vs Temperature
2.5
2.0
1.5
1.0
0.5
0
100
95
90
85
80
75
70
65
60
55
50
100
90
80
70
60
50
40
30
20
10
0
–50 –25
0
25
50
75 100 125
–50
0
25
50
75 100 125
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
VOLTAGE (V)
3501 G21
3501 G22
3501 G23
Minimum Input Voltage
vs Load Current
Minimum Input Voltage
vs Load Current
Minimum Input Voltage
vs Load Current
7.5
7.0
6.0
5.5
5.0
4.5
V
= 5V
V
OUT
= 3.3V
V
= 2.5V
OUT
OUT
6.5
6.0
5.0
4.5
4.0
3.5
5.5
5.0
4.5
4.0
3.5
3.0
3.0
2.5
2.0
RUNNING
RUNNING
RUNNING
1000
1
10
100
1000
10000
1
10
100
1000
10000
1
10
100
10000
CURRENT (mA)
CURRENT (mA)
CURRENT (mA)
3501 G26
3501 G25
3501 G24
3501fb
6
LT3501
TYPICAL PERFORMANCE CHARACTERISTICS
Inductor Value vs Frequency for
3A Maximum Load Current
Inductor Value vs Frequency for
3A Maximum Load Current
Dropout Operation
6
5
4
3
2
1
0
1500
1250
1500
1250
1000
750
V
= 3.3V
LOAD = 1A
OUT
V
I
= 5V
OUT
RIPPLE
I
= 1A
RIPPLE
= 1A
L = 2.2µH
L = 2.2µH
L = 3.3µH
V
= 5V
OUT
L = 3.3µH
L = 4.7µH
1000
V
= 3.3V
OUT
750
500
250
L = 4.7µH
L = 6.8µH
500
250
FREQUENCY
1.5MHz
L = 6.8µH
L = 10µH
250kHz
4.5
3.5
INPUT VOLTAGE (V)
5
2
2.5
3
4
5.5
6
7
9
11 13 15 17 19 21 23 25
INPUT VOLTAGE (V)
10
15
17.5
20
22.5
25
12.5
INPUT VOLTAGE (V)
3501 G27
3501 G28
3501 G29
PIN FUNCTIONS
PG1/PG2 (Pins 5, 6): The power good pin is an open-col-
V
(Pin 1): The V pin powers the internal control
IN1
IN1
lector output that sinks current when the feedback falls
circuitry for both channels and is monitored by the
below 90% of its nominal regulating voltage. For V
undervoltage lockout comparator. The V
pin is also
IN1
IN1
above 1V, its output state remains true, although during
connected to the collector of channel 1’s on-chip power
shutdown,V undervoltagelockoutorthermalshutdown,
NPN switch. The V pin has high dI/dt edges and must
IN1
IN1
its current sink capability is reduced. The PG pins can be
left open circuit or tied together to form a single power
good signal.
be decoupled to ground close to the pin of the device.
SW1/SW2 (Pins 2, 9): The SW pin is the emitter of the on-
chip power NPN. At switch off, the inductor will drive this
pin below ground with a high dV/dt. An external Schottky
catch diode to ground, close to the SW pin and respective
V
(Pin 10): The V pin is the collector of channel 2’s
IN2
IN2
on-chippowerNPNswitch. ThispinisindependentofV
IN1
and may be connected to the same or a separate supply. In
either case, high dI/dt edges are present and decoupling
to ground must be used close to this pin.
V decouplingcapacitor’sground,mustbeusedtoprevent
IN
this pin from excessive negative voltages.
IND1/IND2 (Pins 3, 8): The IND pin is the input to the
on-chip sense resistor that measures current flowing in
the inductor. When the current in the resistor exceeds
SS1/SS2 (Pins 19, 12): The SS1/2 pins control the soft-
start and sequence of their respective outputs. A single
capacitor from the SS pin to ground determines the outpt
ramp rate. For soft-start and output tracking/sequencing
details, see the Applications Information section.
the current dictated by the V pin, the SW latch is held in
C
reset, disabling the output switch. Bias current flows out
of the IND pin when IND is less than 1.6V.
V /V (Pins 18, 13): The V pin is the output of the
V
/V
(Pins 4, 7): The V
pin is the output to
C1 C2
C
OUT1 OUT2
OUT
error amplifier and the input to the peak switch current
comparator. It is normally used for frequency compensa-
tion, but can also be used as a current clamp or control
the on-chip sense resistor that measures current flowing
in the inductor. When the current in the resistor exceeds
the current dictated by the V pin, the SW latch is held in
C
loop override. If the error amplifier drives V above the
reset, disabling the output switch. Bias current flows out
C
maximum switch current level, a voltage clamp activates.
of the V
pin when V
is less than 1.6V.
OUT
OUT
3501fb
7
LT3501
PIN FUNCTIONS
This indicates that the output is overloaded and current is
pulled from the SS pin, reducing the regulation point.
the clock signal is detected, with switch 1 in phase with
thesynchronizationsignal. Eachrisingclockedgeinitiates
an oscillator ramp reset. A gain control loop servos the
oscillatorchargingcurrenttomaintainaconstantoscillator
amplitude. Hence, the slope compensation and channel
phase relationship remain unchanged. If the clock signal
is removed, the oscillator reverts to resistor mode and
FB1/FB2 (Pins 17, 14): The FB pin is the negative input
to the error amplifier. The output switches regulate this
pin to 0.8V, with respect to the exposed ground pad. Bias
current flows out of the FB pin.
SHDN (Pin 15): The shutdown pin is used to turn off both
channels and control circuitry to reduce quiescent current
toatypicalvalueof9µA. Theaccurate1.28Vthresholdand
input current hysteresis can be used as an undervoltage
lockout, preventing the regulator from operating until the
input voltage has reached a predetermined level. Force
the SHDN pin above its threshold or let it float for normal
operation.
reapplies the 0.975V bias to the R /SYNC pin after the
T
synchronization detection circuitry times out. The clock
source impedance should be set such that the current out
oftheR /SYNCpininresistormodegeneratesafrequency
T
roughly equivalent to the synchronization frequency.
BST1/BST2 (Pins 20, 11): The BST pin provides a higher
than V base drive to the power NPN to ensure a low
IN
switch drop. A comparator to V imposes a minimum
IN
R /SYNC (Pin 16): This R /SYNC pin provides two modes
off time on the SW pin if the BST pin voltage drops too
low. Forcing a SW off time allows the boost capacitor to
recharge.
T
T
of setting the constant switch frequency.
Connecting a resistor from the R /SYNC pin to ground
T
will set the R /SYNC pin to a typical value of 0.975V. The
Exposed Pad (Pin 21): GND. The Exposed Pad GND pin is
the only ground connection for the device. The Exposed
Pad should be soldered to a large copper area to reduce
thermal resistance. The GND pin is common to both chan-
nels and also serves as small-signal ground. For ideal
operation all small-signal ground paths should connect
to the GND pin at a single point, avoiding any high current
ground returns.
T
resultant switching frequency will be set by the resistor
value. Theminimumvalueof15.4kandmaximumvalueof
133k sets the switching frequency to 1.5MHz and 250kHz
respectively.
Driving the R /SYNC pin with an external clock signal will
T
synchronize the switch to the applied frequency. Synchro-
nization occurs on the rising edge of the clock signal after
3501fb
8
LT3501
BLOCK DIAGRAM
V
R /SYNC
T
IN
ONE CHANNEL
R3
C
V
CLK1
CLK2
IN1
INTERNAL
REGULATOR
AND
OSCILLATOR
AND
AGC
BST
DROPOUT
ENHANCEMENT
REFERENCE
3µA
7µA
SLOPE
COMPENSATION
C3
PRE
S
R
–
+
DRIVER
CIRCUITRY
Q
Σ
SHDN
SW
IND
+
–
D
+
L1
SHUTDOWN
COMPARATOR
1.28V
+
–
POR
UNDERVOLTAGE
TSD
D
V
OUT
FB
+
0.8V
C
+
–
R1
LOWEST
VOLTAGE
R2
V
CLAMP
C
S
R
Q
POWER GOOD
COMPARATOR
3.25µA
PGOOD
–
+
–
+
SS CLAMP
+
+
SOFT-START
RESET
COMPARATOR
80mV
0.72V
GND
3501 BD
SS
V
C
C
Figure 1. Block Diagram (One of Two Switching Regulators Shown)
The LT3501 is dual channel, constant frequency, current
mode buck converter with internal 3A switches. Each
channelisidenticalwithacommonshutdownpin, internal
regulator,oscillator,undervoltagedetect,thermalshutdown
and power-on reset.
When the SHDN pin is opened or driven above 1.28V,
the internal bias circuits turn on generating an internal
regulated voltage, 0.8V , 0.975V R /SYNC references,
FB
T
and a POR signal which sets the soft-start latch.
As the R /SYNC pin reaches its 0.975V regulation point,
T
If the SHDN pin is taken below its 1.28V threshold the
LT3501 will be placed in a low quiescent current mode.
theinternaloscillatorwillstartgeneratingtwoclocksignals
180° out of phase for each regulator at a frequency deter-
In this mode the LT3501 typically draws 9µA from V
mined by the resistor from the R /SYNC pin to ground.
IN1
T
and <1µA from V . In shutdown mode the PG is active
Alternatively, if a synchronization signal is detected by the
IN2
with a typical sink capability of 50µA for V
voltage
LT3501attheR /SYNCpin,clocksignals180°outofphase
IN1
T
greater than 2V.
3501fb
9
LT3501
BLOCK DIAGRAM
is turned off. Once the switch is turned off the inductor
will drive the voltage at the SW pin low until the external
Schottky diode starts to conduct, decreasing the current
in the inductor. The cycle is repeated with the start of each
clock cycle. However, if the internal sense resistor voltage
exceedsthepredeterminedlevelatthestartofaclockcycle,
theflip-flopwillnotbesetresultinginafurtherdecreasein
inductor current. Since the output current is controlled by
will be generated at the incoming frequency on the rising
edge of the synchronization pulse with switch 1 in phase
with the synchronization signal. In addition, the internal
slope compensation will be automatically adjusted to pre-
vent subharmonic oscillation during synchronization.
The two regulators are constant frequency, current mode
step-down converters. Current mode regulators are con-
trolled by an internal clock and two feedback loops that
control the duty cycle of the power switch. In addition to
thenormalerroramplifier,thereisacurrentsenseamplifier
that monitors switch current on a cycle-by-cycle basis.
This technique means that the error amplifier commands
current to be delivered to the output rather than voltage.
A voltage fed system will have low phase shift up to the
resonant frequency of the inductor and output capacitor,
then an abrupt 180°, shift will occur. The current fed sys-
tem will have 90° phase shift at a much lower frequency,
but will not have the additional 90° shift until well beyond
the LC resonant frequency. This makes it much easier to
frequency compensate the feedback loop and also gives
much quicker transient response.
the V voltage, output regulation is achieved by the error
C
amplifier continually adjusting the V pin voltage.
C
The error amplifier is a transconductance amplifier that
compares the FB voltage to the lowest voltage present at
either the SS pin or an internal 0.8V reference. Compensa-
tion of the loop is easily achieved with a simple capacitor
or series resistor/capacitor from the V pin to ground.
C
Since the SS pin is driven by a constant current source, a
singlecapacitoronthesoft-startpinwillgeneratecontrolled
linear ramp on the output voltage.
If the current demanded by the output exceeds the maxi-
mum current dictated by the V pin clamp, the SS pin
C
will be discharged, lowering the regulation point until the
outputvoltagecanbesupportedbythemaximumcurrent.
When overload is removed, the output will soft-start from
the overload regulation point.
The Block Diagram in Figure 1 shows only one of the
switching regulators whose operation will be discussed
below. The additional regulator will operate in a similar
manner with the exception that its clock will be 180° out
of phase with the other regulator.
V
IN1
undervoltage detection or thermal shutdown will
set the soft-start latch, resulting in a complete soft-start
sequence.
When, during power up, the POR signal sets the soft-start
latch, both SS pins will be discharged to ground to ensure
proper start-up operation. When the SS pin voltage drops
The switch driver operates from either the V or BST volt-
IN
age. An external diode and capacitor are used to generate
below 80mV, the V pin is driven low disabling switching
C
a drive voltage higher than V to saturate the output NPN
IN
and the soft-start latch is reset. Once the latch is reset the
soft-start capacitor starts to charge with a typical value
of 3.25µA.
and maintain high efficiency. If the BST capacitor voltage
is sufficient, the switch is allowed to operate to 100% duty
cycle. If the boost capacitor discharges towards a level
insufficient to drive the output NPN, a BST pin compara-
tor forces a minimum cycle off time, allowing the boost
capacitor to recharge.
As the voltage rises above 80mV on the SS pin, the V pin
C
will be driven high by the error amplifier. When the volt-
age on the V pin exceeds 0.7V, the clock set-pulse sets
C
the driver flip-flop which turns on the internal power NPN
A power good comparator with 30mV of hysteresis trips
at 90% of regulated output voltage. The PG output is an
open-collector NPN that is off when the output is in regu-
lation allowing a resistor to pull the PG pin to a desired
voltage.
switch. This causes current from V , through the NPN
IN
switch, inductor and internal sense resistor, to increase.
When the voltage drop across the internal sense resistor
exceeds a predetermined level set by the voltage on the
V pin, the flip-flop is reset and the internal NPN switch
C
3501fb
10
LT3501
APPLICATIONS INFORMATION
Choosing the Output Voltage
1600
1400
1200
1000
800
190
185
180
175
170
165
160
155
150
The output voltage is programmed with a resistor divider
between the output and the FB pin. Choose the 1% resis-
tors according to:
FREQUENCY
PHASE
V
0.8V
⎛
⎞
⎠
OUT
R1= R2 •
– 1
600
⎜
⎝
⎟
400
R2shouldbe10korlesstoavoidbiascurrenterrors.Refer-
ence designators refer to the Block Diagram in Figure 1.
200
100
0
20
40
60
80 100 120 140
RESISTANCE (kΩ)
Choosing the Switching Frequency
3501 F02
The LT3501 switching frequecy is set by resistor R3 in
Figure 2. Frequency and Phase vs R /SYNC Resistance
T
Figure1.TheR /SYNCpinisinternallyregulatedat0.975V.
T
Setting resistor R3 sets the current in the R /SYNC pin
The following example along with the data in Table 1
illustrates the tradeoffs of switch frequency selection.
T
which determines the oscillator frequency as illustrated
in Figure 2.
Example.
The switching frequency is typically set as high as pos-
sible to reduce overall solution size. The LT3501 employs
techniques to enhance dropout at high frequencies but
efficiency and maximum input voltage decrease due to
switching losses and minimum switch on times. The
maximum recommended frequency can be approximated
by the equation:
V = 25V, V
= 3.3V, I
= 2.5A,
OUT
IN
OUT
Temperature = 0°C to 85°C
t
= 200ns (85°C from Typical Characteristics
D
ON(MIN)
graph), V = 0.6V, V = 0.4V (85°C)
SW
3.3+ 0.6
25 – 0.4+ 0.6 200e-9
1
Max Frequency =
•
~ 750kHz
RT/SYNC ~ 42k (Figure 2)
VOUT + VD
1
Frequency (Hz) =
•
V – VSW + VD tON(MIN)
IN
Input Voltage Range
whereV istheforwardvoltagedropofthecatchdiode(D1
D
Once the switching frequency has been determined, the
input voltage range of the regulator can be determined.
The minimum input voltage is determined by either the
LT3501’s minimum operating voltage of ~2.8V, or by its
Figure 2), V is the voltage drop of the internal switch,
SW
ON(MIN)
and t
in the minimum on time of the switch, all at
maximum load current.
Table 1. Efficiency and Size Comparisons for Different R
Values. 3.3V Output
RT/SYNC
EFFICIENCY
VIN1/2
79.0%
80.9%
81.2%
82.0%
83.9%
†
FREQUENCY
1.2MHz
1.0MHz
750kHz
500kHz
250kHz
R /SYNC
V
= 12V
V
L*
C*
C + L
63mm
66mm
66mm
66mm
T
IN(MAX)
16
18
22
24
24
2
2
2
2
20.5k
26.7k
38.3k
61.9k
133k
1.5µH
2.2µH
3.3µH
4.7µH
10µH
22µH
47µH
47µF
47µF
100µF
2
172mm
†
V
is defined as the highest input voltage that maintains constant output voltage ripple.
IN(MAX)
*Inductor and capacitor values chosen for stability and constant ripple current.
3501fb
11
LT3501
APPLICATIONS INFORMATION
6.0
5.5
maximum duty cycle. The duty cycle is the fraction of time
that the internal switch is on during a clock cycle. Unlike
mostfixedfrequencyregulators,theLT3501willnotswitch
off at the end of each clock cycle if there is sufficient volt-
age across the boost capacitor (C3 in Figure 1) to fully
saturatetheoutputswitch.Forcedswitchoffforaminimum
time will only occur at the end of a clock cycle when the
boost capacitor needs to be recharged. This operation
has the same effect as lowering the clock frequency for a
fixed off time, resulting in a higher duty cycle and lower
minimum input voltage. The resultant duty cycle depends
on the charging times of the boost capacitor and can be
approximated by the following equation:
V
= 3.3V
OUT
5.0
4.5
START-UP
RUNNING
4.0
3.5
3.0
1
10
100
1000
10000
CURRENT (mA)
3501 F03
Figure 3. Minimum Input Voltage vs Load Current
1
Example:
= 3.3V, I
DCMAX
=
1
B
1+
V
= 1A, Frequency = 1MHz, Temperature
OUT
OUT
= 25°C
where B is 3A divided by the typical boost current from
the Electrical Characteristics table.
V
= 0.1V, B = 50 (from from boost characteristics
SW
specification), V = 0.4V, t
= 200ns
D
ON(MIN)
This leads to a minimum input voltage of:
1
DCMAX
=
= 98%
VOUT + VD
DCMAX
1
V
=
– VD + VSW
1+
IN(MIN)
50
where V is the voltage drop of the internal switch.
3.3+ 0.4
0.98
SW
V
=
– 0.4+ 0.1= 3.48V
IN(MIN)
Figure 3 shows a typical graph of minimum input voltage
vs load current for the 3.3V and 1.8V application on the
first page of this data sheet. The maximum input voltage
DCMIN = tMIN(ON) • f = 0.200
3.3+ 0.4
is determined by the absolute maximum ratings of the V
IN
V
=
– 0.4+ 0.1= 18.2V
IN(MAX)
and BST pins and by the frequency and minimum duty
0.200
cycle. The minimum duty cycle is defined as :
Inductor Selection and Maximum Output Current
DC
= t
• Frequency
ON(MIN)
MIN
A good first choice for the inductor value is:
Maximum input voltage as:
V – V
• V
OUT
(
)
IN
OUT
VOUT + VD
DCMIN
L =
V
=
– VD + VSW
IN(MAX)
V • f
IN
where f is frequency in MHz and L is in µH.
Note that the LT3501 will regulate if the input voltage is
taken above the calculated maximum voltage as long as
With this value the maximum load current will be ~3A,
independent of input voltage. The inductor’s RMS current
rating must be greater than your maximum load current
maximum ratings of the V and BST pins are not violated.
IN
Howeveroperationinthisregionofinputvoltagewillexhibit
pulse skipping behavior.
3501fb
12
LT3501
APPLICATIONS INFORMATION
and its saturation current should be about 30% higher. To
keep efficiency high, the series resistance (DCR) should
be less than 0.05Ω.
3.5Aovertheentiredutycyclerange.Themaximumoutput
current is a function of the chosen inductor value:
∆IL
2
∆IL
2
IOUT(MAX) = ILIM
–
= 3.5 –
Forapplicationswithadutycycleofabout50%, theinduc-
tor value should be chosen to obtain an inductor ripple
current less than 40% of peak switch current.
If the inductor value is chosen so that the ripple current
is small, then the available output current will be near the
switch current limit.
Ofcourse,suchasimpledesignguidewillnotalwaysresult
intheoptimuminductorforyourapplication.Alargervalue
provides a slightly higher maximum load current, and will
reduce the output voltage ripple. If your load is lower than
2.5A, then you can decrease the value of the inductor and
operate with higher ripple current. This allows you to use
a physically smaller inductor, or one with a lower DCR
resulting in higher efficiency.
One approach to choosing the inductor is to start with the
simple rule given above, look at the available inductors
and choose one to meet cost or space goals. Then use
these equations to check that the LT3501 will be able to
deliver the required output current. Note again that these
equations assume that the inductor current is continuous.
Discontinuous operation occurs when I
L
is less than
OUT
The current in the inductor is a triangle wave with an
average value equal to the load current. The peak switch
current is equal to the output current plus half the peak-to-
peak inductor ripple current. The LT3501 limits its switch
current in order to protect itself and the system from
overload faults. Therefore, the maximum output current
that the LT3501 will deliver depends on the current limit,
the inductor value, switch frequency, and the input and
output voltages. The inductor is chosen based on output
currentrequirements, outputvoltageripplerequirements,
size restrictions and efficiency goals.
I /2 as calculated above.
Figure 4 illustrates the inductance value needed for a 3.3V
output with a maximum load capability of 3A. Referring
to Figure 4, an inductor value between 3.3µH and 4.7µH
will be sufficient for a 15V input voltage and a switch
frequency of 750kHz. There are several graphs in the
Typical Performance Characteristics section of this data
sheet that show inductor selection as a function of input
voltage and switch frequency for several popular output
voltages and output ripple currents. Also, low inductance
1500
When the switch is off, the inductor sees the output volt-
age plus the catch diode drop. This gives the peak-to-peak
ripple current in the inductor:
V
= 3.3V
OUT
I
= 1A
RIPPLE
1250
1000
L = 2.2µH
L = 3.3µH
1–DC VOUT + VD
(
)(
)
∆IL =
L • f
750
500
250
L = 4.7µH
where f is the switching frequency of the LT3501 and L
is the value of the inductor. The peak inductor and switch
current is
L = 6.8µH
∆IL
2
7
9
11 13 15 17 19 21 23 25
INPUT VOLTAGE (V)
ISW PK = ILPK = IOUT
+
(
)
3501 F04
To maintain output regulation, this peak current must be
less than the LT3501’s switch current limit I . I is
Figure 4. Inductor Values for 3A Maximum Load Current
vs Frequency and Input Voltage
LIM LIM
3501fb
13
LT3501
APPLICATIONS INFORMATION
may result in discontinuous mode operation, which is
okay, but further reduces maximum load current. For
details of maximum output current and discontinuous
mode operation, see Linear Technology Application Note
ments of the input capacitor. Determine the worst-case
condition for input ripple current and then size the input
capacitor such that it reduces input voltage ripple to an
acceptable level. Typical values for input capacitors run
from 10µF at low frequencies to 2.2µF at higher frequen-
cies. The combination of small size and low impedance
(low equivalent series resistance or ESR) of ceramic
capacitors make them the preferred choice. The low ESR
results in very low voltage ripple and the capacitors can
handleplentyofripplecurrent.Theyarealsocomparatively
robust and can be used in this application at their rated
voltage. X5R and X7R types are stable over temperature
and applied voltage, and give dependable service. Other
types (Y5V and Z5U) have very large temperature and
voltage coefficients of capacitance, so they may have
only a small fraction of their nominal capacitance in your
application. While they will still handle the RMS ripple
current, the input voltage ripple may become fairly large,
and the ripple current may end up flowing from your input
supply or from other bypass capacitors in your system,
as opposed to being fully sourced from the local input
capacitor. An alternative to a high value ceramic capacitor
is a lower value along with a larger electrolytic capacitor,
for example a 1µF ceramic capacitor in parallel with a low
ESR tantalum capacitor. For the electrolytic capacitor, a
valuelargerthan10µFwillberequiredtomeettheESRand
ripple current requirements. Because the input capacitor
is likely to see high surge currents when the input source
is applied, tantalum capacitors should be surge rated. The
manufacturer may also recommend operation below the
rated voltage of the capacitor. Be sure to place the 1µF
44. Finally, for duty cycles greater than 50% (V /V
OUT IN
> 0.5), there is a minimum inductance required to avoid
subharmonic oscillations. See Application Note 19 for
more information.
Input Capacitor Selection
Bypass the inputs of the LT3501 circuit with a 4.7µF or
higher ceramic capacitor of X7R or X5R type. A lower
value or a less expensive Y5V type can be used if there
is additional bypassing provided by bulk electrolytic or
tantalum capacitors. The following paragraphs describe
the input capacitor considerations in more detail.
Step-downregulatorsdrawcurrentfromtheinputsupplyin
pulses with very fast rise and fall times. The input capaci-
tor is required to reduce the resulting voltage ripple at the
LT3501 and to force this very high frequency switching
current into a tight local loop, minimizing EMI. The input
capacitor must have low impedance at the switching fre-
quency to do this effectively, and it must have an adequate
ripple current rating. With two switchers operating at the
same frequency but with different phases and duty cycles,
calculating the input capacitor RMS current is not simple.
However, aconservativevalueistheRMSinputcurrentfor
the channel that is delivering most power (V • I ).
OUT OUT
This is given by:
IOUT VOUT • V – V
(
)
<
IOUT
2
IN
OUT
ICIN(RMS)
=
ceramic as close as possible to the V and GND pins on
IN
V
IN
the IC for optimal noise immunity.
and is largest when V = 2V
(50% duty cycle). As
IN
OUT
WhentheLT3501’sinputsuppliesareoperatedatdifferent
input voltages, an input capacitor sized for that channel
should be placed as close as possible to the respective
the second, lower power channel draws input current,
the input capacitor’s RMS current actually decreases as
the out-of-phase current cancels the current drawn by the
higherpowerchannel.Consideringthatthemaximumload
current from a single channel is ~3A, RMS ripple current
will always be less than 1.5A.
V pins.
IN
A final caution regarding the use of ceramic capacitors
at the input. A ceramic input capacitor can combine with
stray inductance to form a resonant tank circuit. If power
is applied quickly (for example by plugging the circuit
into a live power source) this tank can ring, doubling the
input voltage and damaging the LT3501. The solution is to
The frequency, V to V
ratio, and maximum load cur-
OUT
IN
rentrequirementoftheLT3501alongwiththeinputsupply
source impedance, determine the energy storage require-
3501fb
14
LT3501
APPLICATIONS INFORMATION
either clamp the input voltage or dampen the tank circuit
by adding a lossy capacitor in parallel with the ceramic
capacitor. For details, see Application Note 88.
The RMS content of this ripple is very low, and the RMS
current rating of the output capacitor is usually not of
concern.
Another constraint on the output capacitor is that it must
havegreaterenergystoragethantheinductor;ifthestored
energy in the inductor is transferred to the output, you
would like the resulting voltage step to be small compared
totheregulationvoltage. Fora5%overshoot, thisrequire-
Output Capacitor Selection
Typicallystep-downregulatorsareeasilycompensatedwith
an output crossover frequency that is 1/10 of the switch-
ing frequency. This means that the time that the output
capacitor must supply the output load during a transient
step is ~2 or 3 switching periods. With an allowable 5%
drop in output voltage during the step, a good starting
value for the output capacitor can be expressed by:
ment becomes
2
⎛
⎜
⎝
⎞
⎟
⎠
ILIM
COUT > 10 L
V
OUT
Finally,theremustbeenoughcapacitanceforgoodtransient
performance.Thelastequationgivesagoodstartingpoint.
Alternatively, you can start with one of the designs in this
datasheetandexperimenttogetthedesiredperformance.
This topic is covered more thoroughly in the section on
loop compensation.
Max Load Step
Frequency • 0.05 • VOUT
CVOUT
=
Example:
V
= 3.3V, Frequency = 1MHz, Max Load Step = 3A
OUT
2
CVOUT
=
= 12µF
Thehighperformance(lowESR),smallsizeandrobustness
of ceramic capacitors make them the preferred type for
LT3501 applications. However, all ceramic capacitors are
not the same. As mentioned above, many of the high value
capacitors use poor dielectrics with high temperature and
voltage coefficients. In particular, Y5V and Z5U types lose
a large fraction of their capacitance with applied voltage
and temperature extremes. Because the loop stability and
1e6 • 0.05 • 3.3V
The calculated value is only a suggested starting value.
Increasethevalueiftransientresponseneedsimprovement
or reduce the capacitance if size is a priority.
Theoutputcapacitorfilterstheinductorcurrenttogenerate
an output with low voltage ripple. It also stores energy in
ordertosatisfytransientloadsandtostabilizetheLT3501’s
controlloop.TheswitchingfrequencyoftheLT3501deter-
mines the value of output capacitance required. Also, the
current mode control loop doesn’t require the presence
of output capacitor series resistance (ESR). For these
reasons, you are free to use ceramic capacitors to achieve
very low output ripple and small circuit size.
transient response depend on the value of C , you may
OUT
not be able to tolerate this loss. Use X7R and X5R types.
Youcanalsouseelectrolyticcapacitors. TheESRsofmost
aluminum electrolytics are too large to deliver low output
ripple. Tantalumandnewer, lowerESRorganicelectrolytic
capacitors intended for power supply use, are suitable
and the manufacturers will specify the ESR. The choice of
capacitor value will be based on the ESR required for low
ripple. Because the volume of the capacitor determines
its ESR, both the size and the value will be larger than a
ceramic capacitor that would give you similar ripple per-
formance. One benefit is that the larger capacitance may
give better transient response for large changes in load
current. Table 2 lists several capacitor vendors.
Estimate output ripple with the following equations:
V
= ∆I /(8f C ) for ceramic capacitors,
L OUT
RIPPLE
and
V
= ∆I ESR for electrolytic capacitors (tantalum
L
and aluminum)
RIPPLE
where ∆I is the peak-to-peak ripple current in the
L
inductor.
3501fb
15
LT3501
APPLICATIONS INFORMATION
where I
BST(MIN)
the switch.
is the maximum load current, and
Table 2
OUT(MAX)
V is the minimum boost voltage to fully saturate
VENDOR
Taiyo Yuden
AVX
TYPE
SERIES
Ceramic X5R, X7R
Ceramic X5R, X7R
Tantalum
Figure 5 shows four ways to arrange the boost circuit. The
BST pin must be more than 1.4V above the SW pin for
full efficiency. Generally, for outputs of 3.3V and higher
the standard circuit (Figure 5a) is the best. For outputs
between 2.8V and 3.3V, replace the D2 with a small
Schottky diode such as the PMEG4005. For lower output
voltages the boost diode can be tied to the input (Figure
5b). The circuit in Figure 5a is more efficient because the
BST pin current comes from a lower voltage source. Fig-
ure 5c shows the boost voltage source from available DC
sources that are greater than 3V. The highest efficiency is
attained by choosing the lowest boost voltage above 3V.
For example, if you are generating 3.3V and 1.8V and the
3.3V is on whenever the 1.8V is on, the 1.8V boost diode
can be connected to the 3.3V output. In any case, you
must also be sure that the maximum voltage at the BST
pin is less than the maximum specified in the Absolute
Maximum Ratings section.
Kemet
Tantalum
TA Organic
AL Organic
T491, T494, T495
T520
A700
Sanyo
Panasonic
TDK
TA/AL Organic
AL Organic
POSCAP
SP CAP
Ceramic X5R, X7R
Catch Diode
The diode D1 conducts current only during switch off
time. Use a Schottky diode to limit forward voltage drop to
increase efficiency. The Schottky diode must have a peak
reverse voltage that is equal to regulator input voltage and
sized for average forward current in normal operation.
Average forward current can be calculated from:
IOUT
ID(AVG)
=
• V – V
IN OUT
(
)
V
IN
The boost circuit can also run directly from a DC voltage
that is higher than the input voltage by more than 3V, as
in Figure 5d. The diode is used to prevent damage to the
The only reason to consider a larger diode is the worst-
case condition of a high input voltage and shorted output.
With a shorted condition, diode current will increase to a
typical value of 4A, determined by the peak switch current
limit of the LT3501. This is safe for short periods of time,
but it would be prudent to check with the diode manu-
facturer if continuous operation under these conditions
can be tolerated.
LT3501 in case V is held low while V is present. The
X
IN
circuit saves several components (both BST pins can be
tied to D2). However, efficiency may be lower and dissipa-
tion in the LT3501 may be higher. Also, if V is absent, the
X
LT3501 will still attempt to regulate the output, but will do
so with very low efficiency and high dissipation because
the switch will not be able to saturate, dropping 1.5V to
2V in conduction.
BST Pin Considerations
The capacitor and diode tied to the BST pin generate
a voltage that is higher than the input voltage. In most
cases a 0.47µF capacitor and fast switching diode (such
as the CMDSH-3 or FMMD914) will work well. Almost
any type of film or ceramic capacitor is suitable, but the
ESR should be <1Ω to ensure it can be fully recharged
during the off time of the switch. The capacitor value can
be approximated by:
The minimum input voltage of an LT3501 application is
limited by the minimum operating voltage (<3V) and by
the maximum duty cycle as outlined above. For proper
start-up, the minimum input voltage is also limited by
the boost circuit. If the input voltage is ramped slowly, or
the LT3501 is turned on with its SS pin when the output
is already in regulation, then the boost capacitor may not
be fully charged. Because the boost capacitor is charged
with the energy stored in the inductor, the circuit will rely
on some minimum load current to get the boost circuit
running properly. This minimum load will depend on
IOUT(MAX) •DC
CBST
=
B • VOUT – VBST(MIN) • f
(
)
3501fb
16
LT3501
APPLICATIONS INFORMATION
D2
C3
C3
D2
V
BST
BST
V
V
SW
V
V
IN
SW
IN
IN
IN
LT3501
LT3501
IND
OUT
IND
OUT
V
< 3V
OUT
V
V
OUT
GND
GND
V
V
– V = V
V
V
– V = V
SW IN
BST
SW
OUT
BST
BST(MAX)
= V + V
= 2 • V
IN
BST(MAX)
IN
OUT
D2
(5a)
(5b)
D2
V
X
= LOWEST V
IN
OR V
V
> V + 3V
IN
X
> 3V
OUT
C3
BST
BST
V
V
SW
V
V
IN
SW
IN
IN
IN
LT3501
LT3501
IND
OUT
IND
OUT
V
< 3V
V
OUT
< 3V
V
V
OUT
GND
GND
V
V
V
– V = V
V
V
V
– V = V
SW X
BST
SW
X
BST
BST(MAX)
3501 F05
= V + V
= V
X
BST(MAX)
IN
X
= 3V
= V + 3V
IN
X(MIN)
X(MIN)
(5c)
(5d)
Figure 5. BST Pin Considerations
input and output voltages, and on the arrangement of the
boost circuit. The Typical Performance Characteristics
section shows plots of the minimum load current to start
and to run as a function of input voltage for 3.3V and 5V
outputs. In many cases the discharged output capacitor
will present a load to the switcher which will allow it to
part of the loop compensation but is used to filter noise
at the switching frequency.
Loop compensation determines the stability and transient
performance.Designingthecompensationnetworkisabit
complicatedandthebestvaluesdependontheapplication
and in particular the type of output capacitor. A practical
approach is to start with one of the circuits in this data
sheet that is similar to your application and tune the com-
pensation network to optimize the performance. Stability
should then be checked across all operating conditions,
including load current, input voltage and temperature.
start. Theplotsshowtheworst-casesituationwhereV is
IN
ramping very slowly. Use a Schottky diode for the lowest
start-up voltage.
Frequency Compensation
The LT3501 uses current mode control to regulate the
output.Thissimplifiesloopcompensation.Inparticular,the
LT3501 does not require the ESR of the output capacitor
for stability so you are free to use ceramic capacitors to
achieve low output ripple and small circuit size.
The LT1375 data sheet contains a more thorough discus-
sion of loop compensation and describes how to test the
stability using a transient load.
Figure6showsanequivalentcircuitfortheLT3501control
loop. The error amp is a transconductance amplifier with
finite output impedance. The power section, consisting of
the modulator, power switch and inductor, is modeled as
a transconductance amplifier generating an output cur-
Frequency compensation is provided by the components
tied to the V pin. Generally a capacitor and a resistor in
C
series to ground determine loop gain. In addition, there
is a lower value capacitor in parallel. This capacitor is not
rent proportional to the voltage at the V pin. Note that
C
3501fb
17
LT3501
APPLICATIONS INFORMATION
LT3501
CURRENT MODE
POWER STAGE
SW
OUTPUT
ESR
g
= 3mho
m
C
R1
PL
g
m
= 275µmho
FB
–
V
C
C1
C1
CERAMIC
+
+
3.6M
R
C
ERROR
AMP
TANTALUM
OR
POLYMER
R2
0.8V
C
F
C
C
3501 F06
Figure 6. Model for Loop Response
the output capacitor integrates this current, and that the
capacitor on the V pin (C ) integrates the error ampli-
V
V
CC
OUT1
C
C
LT3501
R /SYNC
SYNCHRONIZATION
CIRCUITRY
fier output current, resulting in two poles in the loop. In
PG1
T
CLK
most cases a zero is required and comes from either the
3501 F07
output capacitor ESR or from a resistor in series with C .
C
This simple model works well as long as the value of the
inductor is not too high and the loop crossover frequency
is much lower than the switching frequency. A phase lead
Figure 7. Synchronous Signal Powered from Regulator’s Output
capacitor (C ) across the feedback divider may improve
PL
time the LT3501 reverts to the free-running frequency
the transient response.
based on the current through R /SYNC. If the R /SYNC
T
T
resistor is held above 1.6V at any time, switching will be
Synchronization
disabled.
TheR /SYNCpincanbeusedtosynchronizetheregulators
T
If the synchronization signal is not present during regula-
tor start-up (for example, the synchronization circuitry is
to an external clock source. Driving the R /SYNC resistor
T
with a clock source triggers the synchronization detection
circuitry.Oncesynchronizationisdetected,therisingedge
of SW1 will be synchronized to the rising edge of the
poweredfromtheregulatoroutput)theR /SYNCpinmust
T
see an equivalent resistance to ground between 15.4k and
133kuntilthesynchronizationcircuitryisactiveforproper
start-up operation.
R /SYNC pin signal. An AGC loop will adjust the internal
T
oscillators to maintain a 180 degree phase between SW1
and SW2, and also adjust slope compensation to avoid
subharmonic oscillation.
Ifthesynchronizationsignalpowersupinanundetermined
state (V , V , Hi-Z), connect the synchronization clock
OL OH
to the LT3501 as shown in Figure 7. The circuit as shown
will isolate the synchronization signal when the output
voltage is below 90% of the regulated output. The LT3501
will start-up with a switching frequency determined by the
The synchronizing clock signal input to the LT3501 must
have a frequency between 250kHz and 1.5MHz, a duty
cycle between 20% and 80%, a low state below 0.5V and
a high state above 1.6V. Synchronization signals outside
of these parameters will cause erratic switching behavior.
resistor from the R /SYNC pin to ground.
T
The R /SYNC resistor should be set such that the free
T
Ifthesynchronizationsignalpowersupinalowimpedance
running frequency ((V
– V
)/R
) is
RT/SYNC
RT/SYNC
SYNCLO
state (V ), connect a resistor between the R /SYNC pin
OL T
approximately equal to the synchronization frequency. If
the synchronization signal is halted, the synchronization
detection circuitry will timeout in typically 10µs at which
and the synchronizing clock. The equivalent resistance
seen from the R /SYNC pin to ground will set the start-up
T
frequency.
3501fb
18
LT3501
APPLICATIONS INFORMATION
Ifthesynchronizationsignalpowersupinahighimpedance
defaultstheopen-pinconditiontobeoperating(seeTypical
PerformanceCharacteristics).Currenthysteresisisadded
above the SHDN threshold. This can be used to set voltage
hysteresis of the UVLO using the following:
state (Hi-Z), connect a resistor from the R /SYNC pin to
T
ground. The equivalent resistance seen from the R /SYNC
T
pin to ground will set the start-up frequency.
If the synchronization signal changes between high and
VH – V
7µA
L
R1=
R2 =
lowimpedancestatesduringpowerup(V ,Hi-Z),connect
OL
the synchronization circuitry to the LT3501 as shown in
theTypicalApplicationssection.ThiswillallowtheLT3501
to start-up with a switching frequency determined by the
1.28
VH – 1.28
+ 3µA
equivalent resistance from the R /SYNC pin to ground.
R1
T
Shutdown and Undervoltage Lockout
V = Turn-on threshold
H
Figure 8 shows how to add undervoltage lockout (UVLO)
to the LT3501. Typically, UVLO is used in situations where
the input supply is current limited, or has a relatively high
source resistance. A switching regulator draws constant
power from the source, so source current increases as
source voltage drops. This looks like a negative resistance
loadtothesourceandcancausethesourcetocurrentlimit
or latch low under low source voltage conditions. UVLO
prevents the regulator from operating at source voltages
where these problems might occur.
V = Turn-off threshold
L
Example:switchingshouldnotstartuntiltheinputisabove
4.75V and is to stop if the input falls below 3.75V.
V = 4.75V
H
V = 3.75V
L
4.75 – 3.75
R1=
R2 =
≅ 143k
+ 3µA
7µA
1.28
4.75 – 1.28
143k
An internal comparator will force the part into shutdown
≅ 47k
below the minimum V
of 2.8V. This feature can be
IN1
used to prevent excessive discharge of battery-operated
systems.
Keep the connections from the resistors to the SHDN
pin short and make sure that the interplane or surface
capacitance to switching nodes is minimized. If high re-
sistor values are used, the SHDN pin should be bypassed
with a 1nF capacitor to prevent coupling problems from
the switch node.
Since V supplies the output stage of channel 2 and is
IN2
not monitored, care must be taken to insure that V is
IN2
present before channel 2 is allowed to switch.
If an adjustable UVLO threshold is required, the SHDN
pin can be used. The threshold voltage of the SHDN
pin comparator is 1.28V. A 3µA internal current source
Soft-Start
The output of the LT3501 regulates to the lowest voltage
present at either the SS pin or an internal 0.8V reference.
A capacitor from the SS pin to ground is charged by an
internal 3.25µA current source resulting in a linear output
ramp from 0V to the regulated output whose duration is
given by:
LT3501
V
IN1
V
> 2.8V
IN1
–
+
+
V
OR V
IN2
IN1
3µA
7µA
1.28V
R1
INTERNAL
REGULATOR
SHDN
3501 F08
C1 R2
CSS • 0.8V
3.25µA
tRAMP
=
Figure 8. Undervoltage Lockout
3501fb
19
LT3501
APPLICATIONS INFORMATION
At power-up, a reset signal sets the soft-start latch and
discharges both SS pins to approximately 0V to ensure
proper start-up. When both SS pins are fully discharged
the latch is reset and the internal 3.25µA current source
starts to charge the SS pin.
threshold is exceeded. The PG pin is active (sink capability
is reduced in shutdown and undervoltage lockout mode)
as long as the V pin voltage exceeds 1V.
IN1
Output Tracking/Sequencing
Complex output tracking and sequencing between chan-
nels can be implemented using the LT3501’s SS and PG
pins. Figure 9 shows several configurations for output
tracking/sequencing for a 3.3V and 1.8V application.
WhentheSSpinvoltageisbelow50mV,theV pinispulled
C
low which disables switching. This allows the SS pin to be
used as an individual shutdown for each channel.
As the SS pin voltage rises above 50mV, the V pin is re-
C
Independent soft-start for each channel is shown in
Figure 9a. The output ramp time for each channel is set
by the soft-start capacitor as described in the soft-start
section.
leased and the output is regulated to the SS voltage. When
the SS pin voltage exceeds the internal 0.8V reference, the
output is regulated to the reference. The SS pin voltage
will continue to rise until it is clamped at 2V.
RatiometrictrackingisachievedinFigure9bbyconnecting
both SS pins together. In this configuration, the SS pin
source current is doubled (6.5µA) which must be taken
into account when calculating the output rise time.
In the event of a V undervoltage lockout, the SHDN
IN1
pin driven below 1.28V, or the internal die temperature
exceedingitsmaximumratingduringnormaloperation,the
soft-start latch is set, triggering a start-up sequence.
By connecting a feedback network from V
to the SS2
Inaddition,iftheloadexceedsthemaximumoutputswitch
OUT1
voltage, absolute
pin with the same ratio that sets V
current, the output will start to drop causing the V pin
OUT2
C
trackingshowninFigure9cisimplemented.Theminimum
value of the top feedback resistor (R1) should be set such
that the SS pin can be driven all the way to ground with
clamp to be activated. As long as the V pin is clamped,
C
the SS pin will be discharged. As a result, the output will
be regulated to the highest voltage that the maximum
output current can support. For example, if a 6V output
is loaded by 1Ω the SS pin will drop to 0.53V, regulating
the output at 4V ( 4A • 1Ω ). Once the overload condition
is removed, the output will soft-start from the temporary
voltage level to the normal regulation point.
700µAofsinkcurrentwhenV
isatitsregulatedvoltage.
OUT1
In addition, a small V
voltage offset will be present
OUT2
due to the SS2 3.25µA source current. This offset can be
corrected for by slightly reducing the value of R2.
Figure 9d illustrates output sequencing. When V
is
OUT1
within 10% of its regulated voltage, PG1 releases the SS2
soft-start pin allowing V to soft-start. In this case PG1
Since the SS pin is clamped at 2V and has to discharge
to 0.8V before taking control of regulation, momentary
overload conditions will be tolerated without a soft-start
recovery. The typical time before the SS pin takes control
is:
OUT2
will be pulled up to 2V by the SS pin. If a greater voltage
is needed for PG1 logic, a pull-up resistor to V can
OUT1
be used. This will decrease the soft-start ramp time and
increase tolerance to momentary shorts.
CSS •1.2V
700µA
tSS(CONTROL)
=
If precise output ramp up and down is required, drive the
SS pins as shown in Figure 9e. The minimum value of
resistor (R3) should be set such that the SS pin can be
driven all the way to ground with 700µA of sink current
during power-up and fault conditions.
Power Good Indicators
The PG pin is the open-collector output of an internal
comparator. The comparator compares the FB pin voltage
to 90% of the reference voltage with 30mV of hysterisis.
The PG pin has a sink capability of 800µA when the FB pin
is below the threshold and can withstand 25V when the
Multiple Input Voltages
For applications requiring large inductors due to high V
IN
to V
ratios, a 2-stage step-down approach may reduce
OUT
3501fb
20
LT3501
APPLICATIONS INFORMATION
Independent Start-Up
Ratiometric Start-Up
Absolute Start-Up
V
V
V
OUT1
0.5V/DIV
OUT1
OUT1
0.5V/DIV
0.5V/DIV
PG1
PG1
PG2
PG1
V
V
V
OUT2
0.5V/DIV
OUT2
OUT2
0.5V/DIV
0.5V/DIV
PG2
PG2
5ms/DIV
10ms/DIV
10ms/DIV
3.3V
3.3V
3.3V
1.8V
SS1
SS2
V
SS1
SS2
V
SS1
SS2
V
OUT1
PG1
OUT2
OUT1
PG1
OUT2
OUT1
PG1
OUT2
0.1µF
0.1µF
0.22µF
LT3501
LT3501
LT3501
1.8V
1.8V
V
V
V
0.22µF
PG2
PG2
PG2
R1
13.7k
R2
8.08k
(9a)
(9b)
(9c)
Output Sequencing
Controlled Power Up and Down
V
V
OUT1
0.5V/DIV
OUT1
0.5V/DIV
PG1
V
V
OUT2
0.5V/DIV
OUT2
0.5V/DIV
PG1
PG2
SS1/2
10ms/DIV
10ms/DIV
R3
25k
3.3V
1.8V
3.3V
1.8V
SS1
SS2
V
SS1
SS2
V
OUT1
PG1
OUT2
OUT1
PG1
OUT2
0.1µF
0.1µF
EXTERNAL
SOURCE
LT3501
+
–
LT3501
V
V
PG2
PG2
(9d)
(9e)
Figure 9
3501fb
21
LT3501
APPLICATIONS INFORMATION
V
IN
6V TO 24V
4.7µF
PMEG4005
26.7k
V
V
IN2
IN1
SHDN
BST1
FSET
BST2
SW2
1µH
3.3µH
0.47µF
0.47µF
B360A
SW1
PMEG4005
B360A
LT3501
IND1
IND2
V
OUT2
V
V
OUT2
1.2V
OUT1
5V
V
OUT1
47µF
×2
47µF
42.3k
100k
4k
PG1
FB1
PG2
FB2
V
V
8.06k
C1
C2
8.06k
SS/TRACK1 SS/TRACK2
GND
470pF
470pF
32.4k
40.2k
10pF
0.1µF
0.1µF
10pF
3501 F10
Figure 10. 5V and 1.2V 2-Stage Step-Down Converter with Output Sequencing
inductor size by allowing an increase in frequency. A dual
step down application (Figure 10) steps down the input
Single Step Down:
1.2+ 0.6
voltage (V ) to the highest output voltage then uses that
IN1
24 – 0.4+ 0.6
Frequency (Hz) ≤
= 392kHz
voltage to power the second output (V ). V
must be
IN2
OUT1
190ns
able to provide enough current for its output plus V
OUT2
24 – 5 • 5
24 • 392kHz
(
)
maximum load. Note that the V
must be above V
OUT1
IN2
L1=
L2 =
≥ 10µH
minimum input voltage (2V) when the second channel
starts to switch. Delaying channel 2 can be accomplished
by either independent soft-start capacitors or sequencing
with the PG1 output.
24 – 1.2 •1.2
(
)
≥ 2.7µH
24 • 392kHz
For example, assume a maximum input of 24V:
2-Stage Step-Down:
V = 24V, V
= 5V at 1.5A and V
= 1.2V at 1.5A
5+ 0.6
IN
OUT1
OUT2
24 – 0.4+ 0.6
Frequency ≤
= 1.2MHz
VOUT + VD
190ns
V – VSW + VD
IN
Frequency (Hz) ≤
V – V
Max Frequency = 1.2MHz
tMIN(ON)
24 – 5 • 5
24 •1.2MHz
(
)
• V
(
)
IN
OUT
OUT
L1=
L2 =
≥ 3.3µH
L ≥
V • f
IN
5 – 1.2 •1.2
(
)
≥ 0.76µH
5 •1.2MHz
3501fb
22
LT3501
APPLICATIONS INFORMATION
LT3501
LT3501
GND
LT3501
GND
V
V
V
IN
SW
SW
SW
IN
IN
GND
(11a)
(11b)
(11c)
Figure 11. Subtracting the Current when the Switch is On (11a) from the Current when the Switch is Off (11b) Reveals the Path of the
High Frequency Switching Current (11c). Keep this Loop Small. The Voltage on the SW and BST Traces will Also Be Switched; Keep
These Traces as Short as Possible. Finally, Make Sure the Circuit is Shielded with a Local Ground Plane
PCB Layout
at one location, ideally at the ground terminal of the output
capacitor C2. Additionally, the SW and BST traces should
be kept as short as possible. The topside metal from the
DC964AdemonstrationboardinFigure12illustratesproper
component placement and trace routing.
ForproperoperationandminimumEMI,caremustbetaken
duringprintedcircuitboard(PCB)layout. Figure11shows
the high di/dt paths in the buck regulator circuit.
Notethatlargeswitchedcurrentsflowinthepowerswitch,
the catch diode and the input capacitor. The loop formed
by these components should be as small as possible.
These components, along with the inductor and output
capacitor, should be placed on the same side of the cir-
cuit board and their connections should be made on that
layer. Place a local, unbroken ground plane below these
components, and tie this ground plane to system ground
Thermal Considerations
The PCB must also provide heat sinking to keep the
LT3501 cool. The exposed metal on the bottom of the
package must be soldered to a ground plane. This ground
should be tied to other copper layers below with thermal
vias; these layers will spread the heat dissipated by the
Figure 12. Topside PCB Layout DC964A
3501fb
23
LT3501
APPLICATIONS INFORMATION
LT3501. Place additional vias near the catch diodes.
Adding more copper to the top and bottom layers and
tying this copper to the internal planes with vias can
further reduce thermal resistance. With these steps, the
thermal resistance from die (or junction) to ambient can
be reduced to θJA = 45°C/W.
There is one special consideration regarding the 2-phase
circuit. When the difference between the input voltage and
outputvoltageislessthan2.5V,thentheboostcircuitsmay
prevent the two channels from properly sharing current.
If, for example, channel 1 gets started first, it can supply
the load current, while channel 2 never switches enough
current to get its boost capacitor charged.
The power dissipation in the other power components
such as catch diodes, boost diodes and inductors, cause
additional copper heating and can further increase what
the IC sees as ambient temperature. See the LT1767 data
sheet’s Thermal Considerations section.
In this case, channel 1 will supply the load until it reaches
current limit, the output voltage drops, and channel 2 gets
started. Two solutions to this problem are shown in the
Typical Applications section.
Thesingle3.3V/6Aoutputconvertergeneratesaboostsup-
ply from either SW that will service both switch pins.
Single, Low Ripple 6A Output
The LT3501 can generate a single, low ripple 6A output
if the outputs of the two switching regulators are tied
together and share a single output capacitor. By tying the
The synchronized 3.3V/12A output converter utilizes
undervoltage lockout to prevent the start-up condition.
two FB pins together and the two V pins together, the
C
Other Linear Technology Publications
two channels will share the load current. There are several
advantagestothis2-phasebuckregulator.Ripplecurrents
attheinputandoutputarereduced,reducingvoltageripple
andallowingtheuseofsmaller, lessexpensivecapacitors.
Although two inductors are required, each will be smaller
than the inductor required for a single-phase regulator.
This may be important when there are tight height restric-
tions on the circuit.
Application notes AN19, AN35 and AN44 contain more
detailed descriptions and design information for buck
regulators and other switching regulators. The LT1376
data sheet has a more extensive discussion of output
ripple, loop compensation and stability testing. Design
Note DN100 shows how to generate a dual (+ and –)
output supply using a buck regulator.
3501fb
24
LT3501
TYPICAL APPLICATIONS
5V and 2.5V with Absolute Tracking
V
IN
12V
4.7µF
V
V
IN2
R /SYNC
T
IN1
26.7k
SHDN
BST1
SW1
BST2
SW2
2.2µH
3.3µH
0.47µF
B360A
0.47µF
PMEG4005
B360A
PMEG4005
LT3501
IND1
IND2
V
OUT2
V
V
OUT1
5V
OUT2
V
OUT1
2.5V
47µF
47µF
100k
100k
16.9k
42.3k
PG1
FB1
PG2
FB2
V
V
C2
C1
470pF
40.2k
470pF
40.2k
SS/TRACK1 SS/TRACK2
GND
8.06k
10pF
10pF
8.06k
0.1µF
16.9k
7.68k
3501 TA02
1.25MHz Single 3.3V/6A Low Ripple Output
V
6V TO 25V
IN
4.7µF
V
V
IN2
IN1
20.5k
SHDN
R /SYNC
T
BST1
SW1
BST2
SW2
1.5µH
1.5µH
0.47µF
B360A
0.47µF
B360A
PMEG4005
PMEG4005
LT3501
IND1
IND2
V
OUT2
V
OUT1
3.3V
6A
V
OUT1
47µF
×2
24.9k
100k
PG1
FB1
PG2
FB2
V
V
C2
8.06k
C1
SS/TRACK1 SS/TRACK2
GND
1000pF
17.8k
22pF
0.1µF
3501 TA03
3501fb
25
LT3501
TYPICAL APPLICATIONS
1.25MHz Single 3.3V/6A Low Ripple Output
V
IN
4.5V TO 6V
4.7µF
1µF*
V
V
IN2
IN1
20.5k
PMEG4005*
SHDN
R /SYNC
T
PMEG4005*
BST1
SW1
BST2
SW2
1.5µH
1.5µH
0.47µF
B360A
0.47µF
B360A
PMEG4005
PMEG4005
LT3501
IND1
IND2
V
OUT2
V
OUT1
3.3V
6A
V
OUT1
47µF
×2
24.9k
100k
PG1
FB1
PG2
FB2
V
C1
V
C2
8.06k
SS/TRACK1 SS/TRACK2
GND
1000pF
17.8k
22pF
0.1µF
3501 TA03
*ADDITIONAL COMPONENTS ADDED TO SHOW THE BOOST VOLTAGE WHEN V <6V.
IN
THIS IS REQUIRED TO ENSURE LOAD SHARING BETWEEN THE TWO CHANNELS.
Dual LT3501 Synchronized 3.3V/12A Output, 3MHz Effective Switch Frequency
V
IN
5.5V TO 24V
10µF
143k
V
V
IN2
R /SYNC
T
IN1
36.5k
SHDN
BST1
SW1
BST2
SW2
3.3µH
3.3µH
0.47µF
B360A
0.47µF
PMEG4005
B360A
PMEG4005
LT3501
IND1
IND2
V
OUT2
V
OUT1
3.3V
V
OUT1
47µF
×4
49.9k
24.9k
PG1
FB1
PG2
FB2
49.9k
49.9k
V
V
C2
C1
8.06k
V+ OUT1
SS/TRACK1 SS/TRACK2
GND
LTC6908-1
SET
3300pF
47pF 15.3k
133k
MOD
0.1µF
GND OUT2
PMEG4005
PMEG4005
V
IN1
V
IN2
SHDN
R /SYNC
T
BST1
SW1
BST2
SW2
3.3µH
3.3µH
0.47µF
B360A
0.47µF
B360A
LT3501
IND1
IND2
V
V
OUT1
OUT2
PG2
FB2
49.9k
PG1
FB1
V
C1
V
C2
SS/TRACK1 SS/TRACK2
GND
3501 TA04
3501fb
26
LT3501
PACKAGE DESCRIPTION
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation CA
6.40 – 6.60*
(.252 – .260)
4.95
(.195)
4.95
(.195)
20 1918 17 16 15 14 1312 11
6.60 0.10
2.74
(.108)
4.50 0.10
SEE NOTE 4
6.40
(.252)
BSC
2.74
(.108)
0.45 0.05
1.05 0.10
0.65 BSC
5
7
8
1
2
3
4
6
9 10
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
FE20 (CA) TSSOP 0204
0.195 – 0.30
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
3501fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LT3501
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
V : 5.5V to 60V, V
LT1766
60V, 1.2A (I ), 200kHz High Efficiency Step-Down DC/DC
Converter
= 1.20V, I = 2.5mA, I = 25µA,
OUT(MIN) Q SD
OUT
IN
16-Lead TSSOPE Package
V : 3.6V to 36V, V = 1.2V, I = 1.6mA, I <1µA,
OUT(MIN) Q SD
LT1933
500mA (I ), 500kHz Step-Down Switching Regulator in
OUT
IN
SOT-23
ThinSOTTM Package
V : 3.6V to 36V, V
LT1936
36V, 1.4A (I ), 500kHz High Efficiency Step-Down DC/DC
Converter
= 1.2V, I = 1.9mA, I <1µA,
OUT(MIN) Q SD
OUT
IN
8-Lead MS8E Package
LT1940
Dual 25V, 1.4A (I ), 1.1MHz High Efficiency Step-Down
V : 3.6V to 25V, V
= 1.20V, I = 3.8mA, I <30µA,
OUT(MIN) Q SD
OUT
IN
DC/DC Converter
16-Lead TSSOPE Package
LT1976/LT1977
60V, 1.2A (I ), 200kHz/500kHz High Efficiency Step-Down V : 3.3V to 60V, V
= 1.20V, I = 100µA, I <1µA,
OUT(MIN) Q SD
OUT
IN
DC/DC Converters with Burst Mode® Operation
16-Lead TSSOPE Package
LTC®3407/LTC3407-2 Dual 600mA/800mA, 1.5MHz/2.25MHz Synchronous
V : 2.5V to 5.5V, V
= 0.6V, I = 40µA, I <1µA,
Q SD
IN
OUT(MIN)
Step-Down DC/DC Converters
3mm × 3mm DFN and 10-Lead MSE Packages
60V, 2.4A (I ), 200kHz/500kHz High Efficiency Step-Down V : 3.3V to 60V, V = 1.20V, I = 100µA, I <1µA,
OUT IN OUT(MIN)
LT3434/LT3435
LT3437
Q
SD
DC/DC Converters with Burst Mode Operation
16-Lead TSSOPE Package
60V, 400mA (I ), Micropower Step-Down DC/DC Converter V : 3.3V to 60V, V
= 1.25V, I = 100µA, I <1µA,
Q SD
OUT
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
with Burst Mode Operation
DFN Package
LT3493
36V, 1.4A (I ), 750kHz High Efficiency Step-Down DC/DC
V : 3.6V to 36V, V
= 0.8V, I = 1.9mA, I <1µA,
Q SD
OUT
IN
Converter
DFN Package
LT3505
36V, 1.2A (I ), 3MHz High Efficiency Step-Down DC/DC
V : 3.6V to 36V, V
= 0.78V, I = 2mA, I <2µA,
Q SD
OUT
IN
Converter
3mm × 3mm DFN and 8-Lead MSE Packages
LT3506/LT3506A
LT3510
Dual 25V, 1.6A (I ), 575kHz/1.1MHz High Efficiency
V : 3.6V to 25V, V = 0.8V, I = 3.8mA, I <30µA,
OUT
IN
OUT(MIN)
Q
SD
Step-Down DC/DC Converters
4mm × 5mm DFN Package
Dual 25V, 3A (I ), 1.5MHz High Efficiency Step-Down
V : 3.3V to 25V, V
= 0.8V, I = 3.5mA, I <1µA,
Q SD
OUT
IN
OUT(MIN)
DC/DC Converter
20-Lead TSSOPE Package
V : 2.5V to 5.5V, V = 0.6V, I = 40µA, I <1µA,
OUT(MIN) Q SD
LTC3548
Dual 400mA/800mA, 2.25MHz Synchronous Step-Down
DC/DC Converters
IN
3mm × 3mm DFN and 10-Lead MSE Packages
Burst Mode is a registered trademark of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation.
3501fb
LT 0507 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
© LINEAR TECHNOLOGY CORPORATION 2006
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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