LT3641EUFD#TRPBF [Linear]
LT3641 - Dual Monolithic Buck Regulator with Power-On Reset and Watchdog Timer; Package: QFN; Pins: 28; Temperature Range: -40°C to 85°C;
| 型号： | LT3641EUFD#TRPBF |
| 厂家： | 
Linear |
| 描述： | LT3641 - Dual Monolithic Buck Regulator with Power-On Reset and Watchdog Timer; Package: QFN; Pins: 28; Temperature Range: -40°C to 85°C 开关 |
| 文件： | 总28页 (文件大小：451K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3641
Dual Monolithic Buck
Regulator with Power-On
Reset and Watchdog Timer
FEATURES
DESCRIPTION
TheLT®3641isadualchannel,currentmodemonolithicbuck
switching regulator with a power-on reset and a watchdog
timer.Bothregulatorsaresynchronizedtoasingleoscillator
with an adjustable frequency (350kHz to 2.5MHz). At light
loads, both regulators operate in low ripple Burst Mode®
to maintain high efficiency and low output ripple.
n
High Voltage Buck Regulator:
4V to 42V Operating Range
1.3A Output Current
n
Input Transient Protection to 55V
n
Low Voltage Synchronous Buck Regulator:
2.5V to 5.5V Input Voltage Range
1.1A Output Current
The high voltage channel is a nonsynchronous buck with
an internal 2.4A top switch that operates from an input
of 4V to 42V and input transient protection to 55V. The
low voltage channel operates from an input of 2.5V to
5.5V. Internal synchronous power switches provide high
efficiency without the need of external Schottky diode.
Bothchannelshavecycle-by-cyclecurrentlimit,providing
protection against shorted outputs.
n
Synchronizable, Adjustable 350kHz to 2.5MHz
Switching Frequency
Programmable Power-On Reset Timer
Programmable Window Mode Watchdog Timer
Typical Quiescent Current: 290μA
Short-Circuit Robust
Programmable Soft-Start
Low Shutdown Current: I < 1μA
Thermal Shutdown
Available in Thermally Enhanced 28-Lead
(4mm × 5mm) QFN and 28-Lead TSSOP Packages
n
n
n
n
n
n
Q
n
n
The power-on reset and watchdog timeout periods are
both adjustable using external capacitors. The window
mode watchdog timer flags when the μP pulses group
too close together or too far apart.
APPLICATIONS
The LT3641 is available in a 28-pin 4mm × 5mm QFN
package and 28-pin TSSOP package. Both packages have
an exposed pad for low thermal resistance.
n
Industrial Power Supplies
n
Automotive Electronic Control Units
L, LT, LTC, LTM, Linear Technology, Burst Mode and the Linear logo are registered trademarks
and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
TYPICAL APPLICATION
2MHz 5V/0.8A and 3.3V/0.5A Step Down Regulators
HV Channel Efficiency,
2MHz, VOUT1 = 5V
LV Channel Efficiency,
2MHz, VOUT2 = 3.3V
0.22μF
V
IN
7V TO 42V*
10μF
4.7μH
301k
V
OUT1
90
85
80
75
70
95
90
85
80
75
70
EN/UVLO
V
SW
BST SW1
IN
5V/0.8A
SYNC
WDE
PGOOD2
22μF
DA
FB1
V
IN
= 12V
V
IN2
= 5V
100k
V
OUT1
100k
100k
LT3641
V
IN2
RST1
RST2
WDO
WDI
EN2
2.2μH
μP
V
OUT2
SW2
3.3V/0.5A
226k
22μF
CWDT
CPOR
FB2
RT GND SS2 SS1
49.9k
1nF
1.5nF
1.5nF
32.4k
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4
CURRENT (A)
0
0.2
0.4
0.6
0.8
1.0
1.2
1nF
V
V
OUT2
CURRENT (A)
OUT1
3641 TA01a
3641 TA01b
3641 TA01c
* FOR INPUT VOLTAGES ABOVE 42V RESTRICTIONS APPLY
3641fa
1
LT3641
(Note 1)
ABSOLUTE MAXIMUM RATINGS
V , EN/UVLO Voltage (Note 7).................................55V
SW2 Voltage ................................–0.3V to (V + 0.3V)
IN
IN2
WDE Voltage.............................................................30V
BST Above SW, SW1 Voltage....................... –0.3V to 6V
SW1 Above SW Voltage............................... –0.3V to 6V
Operating Junction Temperature Range (Note 2)
LT3641E................................................. –40°C to 125°C
LT3641I.................................................. –40°C to 125°C
LT3641H................................................. –40°C to 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature, FE Only (Soldering, 10 sec) .... 300°C
V , SYNC, EN2, PGOOD2, WDI,
IN2
WDO, RST1, RST2, Voltages ....................... –0.3V to 6V
SS1, SS2, FB1, FB2, RT, CWDT,
CPOR Voltages……….............................. –0.3V to 2.5V
PIN CONFIGURATION
TOP VIEW
TOP VIEW
1
2
SS2
EN2
GND
SW2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
FB2
PGOOD2
EN/UVLO
SYNC
SS1
3
28 27 26 25 24 23
4
SYNC
SS1
1
2
3
4
5
6
7
8
22
21
20
19
18
17
16
15
SW2
5
V
IN2
V
IN2
6
GND
FB1
FB1
GND
7
V
RT
IN
29
GND
RT
V
29
GND
IN
8
BST
SW
RST2
RST1
WDO
RST2
RST1
WDO
CWDT
BST
SW
SW1
DA
9
10
11
12
13
14
SW1
DA
CWDT
CPOR
WDE
9
10 11 12 13 14
UFD PACKAGE
NC
GND
GND
WDI
28-LEAD (4mm × 5mm) PLASTIC QFN
= 43°C/W, θ = 3.4°C/W
FE PACKAGE
θ
28-LEAD PLASTIC TSSOP
JA
JC
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
θ
= 30°C/W, θ = 8°C/W
JA
JC
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LT3641EFE#PBF
LT3641IFE#PBF
LT3641HFE#PBF
LT3641EUFD#PBF
LT3641IUFD#PBF
TAPE AND REEL
PART MARKING*
LT3641FE
LT3641FE
LT3641FE
3641
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3641EFE#TRPBF
LT3641IFE#TRPBF
LT3641HFE#TRPBF
LT3641EUFD#TRPBF
LT3641IUFD#TRPBF
28-Lead Plastic TSSOP
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–40°C to 125°C
–40°C to 125°C
28-Lead Plastic TSSOP
28-Lead Plastic TSSOP
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
3641
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3641fa
2
LT3641
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VIN2 = 3.3V, EN/UVLO = 12V, EN2 = 3.3V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
3.6
3.8
MAX
4
UNITS
l
l
V
IN
V
IN
Undervoltage Lockout Threshold
Undervoltage Release Threshold
V
V
4.2
Quiescent Current from V
EN/UVLO = 0.3V
Not Switching
0.1
275
1
375
μA
μA
IN
EN/UVLO Threshold Voltage
EN/UVLO High Bias Current
EN/UVLO Low Bias Current
SYNC Input Frequency
1.2
1.26
2
1.3
V
μA
EN/UVLO = Threshold + 60mV
EN/UVLO = Threshold – 60mV
0.1
μA
0.35
0.4
2.5
1
MHz
V
SYNC Threshold Voltage
Switching Frequency
0.8
l
l
RT = 32.4k
RT = 182k
1.75
450
2
500
2.35
550
MHz
kHz
l
FB1 Voltage
1.24
1.265
30
1.29
100
V
nA
FB1 Bias Current
FB1 Line Regulation
SW1 Minimum Off-Time
FB1 = 1.265V
5V < V < 30V
0.001
70
%/V
ns
IN
100
SW1 V
I
= 800mA
SW1
400
0.1
mV
μA
CESAT
SW1 Leakage Current
SW1 Current Limit
1
l
l
FB1 = 1V (Note 3)
FB1 = 0.1V
2.2
2.8
1.8
3.4
A
A
DA Current limit
FB1 = 1V (Note 4)
FB1 = 0.1V
1.35
1.7
1
2.2
A
A
BST Pin Current
I
= 800mA
30
2
50
2.7
mA
V
SW1
Minimum BST-SW Voltage
l
l
l
V
V
Minimum Operating Voltage
Maximum Operating Voltage
2.3
2.5
V
IN2
IN2
5.5
V
EN2 Threshold
Rising
1.13
50
1.18
80
1.23
110
500
615
100
V
EN2 Hysteresis
mV
nA
mV
nA
%/V
A
EN2 Bias Current
FB2 Voltage
EN2 = EN2 Threshold
FB2 = 0.6V
50
l
585
600
0
FB2 Bias Current
FB2 Line Regulation
SW2 PMOS Current Limit
SW2 NMOS Current Limit
2.5V < V < 5.5V
0.01
1.9
1.6
275
200
40
IN2
l
l
(Note 5)
(Note 5)
1.5
1.2
2.2
2
A
SW2 PMOS R
SW2 NMOS R
I
I
= 0.5A (Note 6)
= 0.5A (Note 6)
mΩ
mΩ
mV
mV
mV
DS(ON)
DS(ON)
SW2
SW2
ΔFB2 to Enable PGOOD2
ΔFB2 Hysteresis to Disable PGOOD2
PGOOD2 Voltage
20
20
80
80
40
FB2 = 0.6V, I
= 1mA
200
320
PGOOD2
3641fa
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LT3641
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VIN2 = 3.3V, EN/UVLO = 12V, EN2 = 3.3V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
2.0
5
MAX
2.7
30
UNITS
μA
mV
mV
%
SS1, SS2 Charge Current
SS1 = 0.5V, SS2 = 0.5V
SS1 = 0.6V
1.3
SS1 to FB1 Offset Voltage
SS2 to FB2 Offset Voltage
SS2 = 0.3V
5
30
l
l
RST1 Threshold as Percentage of V
RST2 Threshold as Percentage of V
Undervoltage to RST Assert Time
RST1, RST2, WDO Pull-Up Current
RST1, RST2, WDO Output Voltage
90
88
92
91
20
15
150
9.5
16
32
2
94
FB1
94
%
FB1
μs
RST1, RST2, WDO = 0V
5
30
250
11
μA
mV
ms
ms
ms
ms
μA
V
I
, I
, I
= 2mA
RST1 RST2 WDO
l
RST1, RST2 Timeout Period (t
)
CPOR = 220pF
CWDT = 820pF
CWDT = 820pF
CWDT = 820pF
WDI = 1.2V
8
14
RST
Watchdog Start Delay Time (t
Watchdog Upper Boundary (t
Watchdog Lower Boundary (t
WDI Pull-Up Current
)
18
DLY
l
l
)
27
35
WDU
)
1.68
2.2
WDL
4
WDI Voltage Threshold
0.55
300
300
0.85
1.15
0.9
WDI Low Minimum Pulse Width
WDI High Minimum Pulse Width
WDE Pull-Down Current
WDE Threshold
ns
ns
WDE = 2V
1
μA
V
l
0.5
0.7
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: The oscillator cycle is extended when DA current exceeds its limit.
DA current limit is flat over duty cycle.
Note 5: If the SW2 NMOS current exceeds its limit at the start of an
oscillator cycle, the PMOS will not be turned on in the cycle.
Note 2: The LT3641E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3641I is guaranteed and tested over the full –40°C to 125°C operating
junction temperature range. The LT3641H is guaranteed and tested over
the full –40°C to 150°C operating junction temperature range.
Note 3: SW1, SW2 current limit is guaranteed by design and/or correlation
to static test. Slope compensation reduces current limit at higher duty
cycle.
Note 6: The QFN switch R
measurement.
Note 7: Absolute Maximum Voltage at V and EN/UVLO pins is 55V for
nonrepetitive 1 second transients, and 42V for continuous operation.
Note 8: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed the maximum operating junction temperature
when overtemperature protection is active. Continuous operation above
the specified maximum operating junction temperature may impair device
reliability.
is guaranteed by correlation to wafer level
DS(ON)
IN
3641fa
4
LT3641
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
HV Channel Efficiency
(2MHz, VOUT1 = 5V)
LV Channel Efficiency
(2MHz, VOUT2 = 1.2V)
HV Channel Efficiency
(2MHz, VOUT1 = 3.3V)
90
85
80
75
70
95
90
85
80
75
70
65
90
85
80
75
70
V
= 12V
IN
V
= 3.3V
V
= 16V
= 24V
IN2
IN
V
= 5V
IN2
V
IN
V
V
V
V
= 12V
= 24V
= 36V
= 48V
IN
IN
IN
IN
0
0.2
0.4
0.6
0.8
1.0
1.2
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
CURRENT (A)
0
0.2
0.4
0.6
0.8
1.0
V
CURRENT (A)
V
V
OUT2
CURRENT (A)
OUT1
OUT1
3641 G01
3641 G02
3641 G03
LV Channel Efficiency
(2MHz, VOUT2 = 1.8V)
Quiescent Current vs VIN
Quiescent Current vs Temperature
0.35
0.30
350
300
90
85
80
75
70
V
= 3.3V
IN2
0.25
250
V
= 5V
IN2
0.20
0.15
0.10
0.05
200
150
100
50
0.00
0
20
30
40
50
100
150
0
10
–50
0
0
0.2
0.4
0.6
0.8
1.0
V
CURRENT (A)
V
VOLTAGE (V)
IN
TEMPERATURE (°C)
OUT2
3641 G05
3641 G06
3641 G04
FB1 Voltage vs SS1
FB1 Voltage vs Temperature
FB2 Voltage vs Temperature
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.70
0.65
0.60
0.55
0.50
0.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
REGULATION
REGULATION
RST1 THRESHOLD
RST2 THRESHOLD
0
1.0
1.5
2.0
50
100
150
0.5
–50
0
50
100
150
–50
0
SS1 VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
3641 G08
3641 G09
3641 G07
3641fa
5
LT3641
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Switching Frequency
vs Temperature
HV Channel Current Limit
vs Duty Cycle
FB2 Voltage vs SS2
0.52
0.51
0.50
0.49
0.48
2.5
2.0
1.5
1.0
0.5
0.0
700
600
500
400
300
200
100
0
R
= 182k
T
0
40
60
80
100
0
400
6000
800
1000
–50
0
50
100
150
20
200
TEMPERATURE (°C)
DUTY CYCLE (%)
SS2 VOLTAGE (mV)
3641 G11
3641 G12
3641 G10
LV Channel Peak Current Limit
vs Duty Cycle
LV Channel Switch Voltage
Drop vs Current (VIN2 = 3.3V)
VOUT1 Minimum Load to Run at
Full Frequency (VOUT1 = 3.3V)
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
450
400
350
300
250
200
150
100
50
2.0
1.5
1.0
0.5
0.0
2.5MHz
2MHz
PMOS
NMOS
0
0
5
10
V
15
20
25
30
0.5
1
1.5
0
0
40
60
80
100
20
VOLTAGE (V)
SW2 CURRENT (A)
DUTY CYCLE (%)
IN
3641 G15
3641 G14
3641 G13
HV Channel Switching Frequency
(VOUT1 = 3.3V)
LV Channel Switching Frequency
(VOUT2 = 1.8V)
EN2 Current vs Voltage
2.5
2.0
1.5
1.0
0.5
0
2.5
2.0
1.5
1.0
0.5
0
30
25
20
15
10
5
R
= 32.4k
= 12V
T
V
= 3.3V
V
IN2
IN
V
= 16V
V
= 5V
IN
IN2
V
= 24V
IN
0
0
0.4
0.6
0.8
1.0
0.2
0
0.4
0.6
0.8
1.0
1.2
0
4
6
0.2
2
V
CURRENT (A)
V
CURRENT (A)
OUT2
EN2 VOLTAGE (V)
OUT1
3641 G17
3641 G16
3641 G17a
3641fa
6
LT3641
T = 25°C, unless otherwise noted.
A
TYPICAL PERFORMANCE CHARACTERISTICS
Watchdog Upper Boundary
Period vs CWDT
Full Frequency Waveforms
Light Load Operation Waveforms
180
160
140
120
100
80
SW1
10V/DIV
SW1
10V/DIV
I
L1
I
L1
0.5A/DIV
0.5A/DIV
SW2
5V/DIV
SW2
5V/DIV
60
40
I
L2
I
L2
20
0.5A/DIV
0.5A/DIV
0
3641 G19
3641 G18
0
1000
2000
3000
4000
5000
500ns/DIV
200ns/DIV
C
CAPACITANCE (pF)
WDT
V
V
= 12V
OUT1
V = V
IN2 OUT1
V
V
= 12V
OUT1
V
V
= V
OUT2
IN1
IN1
IN2 OUT1
3641 G20
= 3.3V/25mA
V
= 1.8V/30mA
= 3.3V/0.5A
= 1.8V/0.5A
OUT2
Watchdog Upper Boundary
Period vs Temperature
RST/WDO Pull-Up Current
35
30
20
15
10
5
25
20
15
10
5
0
0
50
100
150
–50
0
1
1.5
2
0
0.5
TEMPERATURE (°C)
RST/WDO VOLTAGE (V)
3641 G21
3641 G22
3641fa
7
LT3641
PIN FUNCTIONS (FE/QFN)
FB2(Pin1/Pin26):Thelowvoltageconverterregulatesthe
FB2 pin to 600mV. Connect the feedback resistor divider
tap to this pin to set output voltage.
WDE (Pin 13/Pin 10): Watchdog Enable Pin.
WDI (Pin 14/Pin 11): The WDI pin receives watchdog
signals from a microprocessor.
PGOOD2(Pin2/Pin27):Open-drainlogicoutputthatstarts
to sink current when FB2 is in regulation.
GND (Pins 15, 16, 23, 26, Exposed Pad Pin 29/Pins 12,
13, 20, 23, Exposed Pad Pin 29): Ground. These pins
must be soldered to PCB ground.
EN/UVLO (Pin 3/Pin 28): Pull this pin below 0.3V to shut
down the LT3641. The 1.26V threshold can function as an
accurateundervoltagelockout,preventingtheLT3641from
NC (Pin 17/Pin 14): Not Connected. This pin can be con-
nected to ground.
operating until V voltage has reached the programmed
IN
DA (Pin 18/Pin 15): The DA pin is used to sense the catch
diodecurrentforcurrentlimitandprotection.Connectthis
pin to catch diode anode.
level.
SYNC (Pin 4/Pin 1): Driving the SYNC pin with an external
clock signal synchronizes both converters to the applied
frequency. The lowest external clock frequency should be
20% higher than the internal oscillator frequency.
SW1 (Pin 19/Pin 16): Output of the High Voltage Internal
Power Switch. Connect this pin to the inductor and catch
diode cathode.
SS1 (Pin 5/Pin 2): The SS1 pin sets the FB1 voltage ex-
ternally between 0V and 1.265V, providing soft-start and
tracking. Tie this pin 1.5V or higher to use the internal
1.265Vreference. Acapacitortogroundatthispinsetsthe
ramp time to regulated output voltage for the high voltage
converter. Use a resistor divider to track another supply.
SW (Pin 20/Pin 17): The SW pin is used to charge the
boost capacitor. Connect this pin to the boost capacitor.
BST(Pin21/Pin18):TheBSTpinisusedtoprovideadrive
pin voltage, to the high voltage
voltage, higher than V
IN
channel internal power switch. Connect an external boost
diode to this pin.
FB1(Pin6/Pin3):Thehighvoltageconverterregulatesthe
FB1 pin to 1.265V. Connect the feedback resistor divider
tap to this pin to set output voltage.
V
(Pin 22/Pin 19): The V pin supplies current to
IN
IN
the LT3641’s internal circuitry and to the high voltage
channel internal power switch. This pin must be locally
bypassed.
RT (Pin 7/Pin 4): Oscillator Resistor Input. Connecting a
resistor to ground from this pin sets the internal oscillator
frequency.
V
(Pin 24/Pin 21): The V pin supplies current to the
IN2
IN2
internal power MOSFET of the low voltage converter and
RST2 (Pin 8/Pin 5): Open-drain logic output that remains
asserted for the period set by the CPOR pin capacitor after
FB2 goes above 550mV.
to the LT3641’s internal circuitry when V is above 3V.
IN2
SW2 (Pin 25/Pin 22): Switch Node of the Low Voltage
Converter. Connect this pin to an inductor.
RST1 (Pin 9/Pin 6): Open-drain logic output that remains
asserted for the period set by the CPOR pin capacitor after
FB1 goes above 1.165V.
EN2 (Pin 27/Pin 24): Low Voltage Converter Enable Pin. The
enable threshold is 100mV below FB1 target voltage. The
disablethresholdhas50mVhysteresis.Theaccuratethreshold
can function as an accurate undervoltage lockout.
WDO(Pin10/Pin7):Open-drainlogicoutputthatremains
asserted for the period set by the CPOR pin capacitor if
WDE is enabled and WDI pin is not driven by an appropri-
ate signal.
SS2 (Pin 28/Pin 25): The SS2 pin sets the FB2 voltage
externally between 0V and 0.6V, providing soft-start and
tracking. Tie this pin 0.8V or higher to use the internal
0.6V reference. A capacitor to ground at this pin sets the
ramp time to regulated output voltage for the low voltage
converter. Use a resistor divider to track another supply.
CWDT (Pin 11/Pin 8): Connect a capacitor to ground at
this pin to set watchdog timer.
CPOR (Pin 12/Pin 9): Connect a capacitor to ground at this
pin to set the power-on reset timer and WDO output timer.
3641fa
8
LT3641
BLOCK DIAGRAM
C
IN
V
IN
2μA
D
BST
BST
SW
EN/
UVLO
100k
C
BST
+
–
ENABLE
–
+
Q1
R
Q
A4
A3
S
5.5V
DRIVER
+
–
V
REF
A1
A2
1.265V
L1
V
OUT1
C
2μA
SW1
DA
g
D1
m1
SS1
VC1
+
–
+
–
+
RAMP
GENERATOR
OUT1
OSCILLATOR
Σ
R2
FB1
V
OUT1
+
–
R1
RT
SYNC
+
–
A8
V
IN2
+
–
A5
Σ
C
IN2
2μA
g
m2
+
–
S
L2
SS2
FB2
V
OUT2
C
SW2
+
LOGIC
CIRCUIT
VC2
A7
R
Q
–
+
R4
OUT2
V
OUT2
+
–
V
REF
50mV
R3
–
+
600mV
A6
+
–
PGOOD2
A9
+
–
EN2
2μA
2μA
1.165V
CWDT
CPOR
WATCHDOG
TIMER
POR TIMER
RST1
RST2
WDE
WDI
WDO
3641 BD
3641fa
9
LT3641
TIMING DIAGRAMS
Power-On Reset Timing
FB
t
t
RST
UV
RST
Watchdog Timing
WDI
WDO
t < t
WDU
t
t
WDU
DLY
t < t
t
t
< t < t
t
RST
WDL RST
WDL
WDU
3641 TD
OPERATION
The LT3641 is a dual channel, constant-frequency, current
mode monolithic buck switching regulator with power-on
resetandwatchdogtimer.Bothchannelsaresynchronized
to a single oscillator with frequency set by RT. Operation
can be best understood by referring to the Block Diagram.
An active clamp (not shown) on the VC1 node provides
peak current limit. A DA pin current comparator extends
the oscillator cycle until the catch diode current is below
the valley current limit. Both the peak and valley current
limits help to control the inductor current in fault condi-
tions such as shorted output with high V . Both current
IN
Buck Regulators
limits are reduced when the voltage at the FB1 pin is below
0.2V. This current foldback helps to control the inductor
current during start-up and overload.
The high voltage channel is a nonsynchronous buck
regulator that operates from the V pin. The start of each
IN
oscillator cycle sets an SR latch and turns on the internal
The NPN power switch driver operates from either the V
IN
NPN power switch. An amplifier and comparator monitor
pin or the BST pin. An external capacitor and diode are
used to generate a voltage between the BST and SW pins.
Duringthepower-upoftheLT3641,aninternal5mAcurrent
source charges the external BST capacitor. The regulator
starts switching when the (BST-SW) voltage reaches the
2V threshold. The internal NPN power switch can be fully
saturatedforefficientoperationwhenthe(BST-SW)voltage
is between 2.3V and 5.5V.
thecurrentflowingbetweentheV andSW1pins, turning
IN
theswitchoffwhenthiscurrentreachesaleveldetermined
by the voltage at VC1 node. An error amplifier measures
the output voltage through an external resistor divider tied
to the FB1 pin and servos the VC1 node. The reference
of the error amplifier is determined by the lower of the
internalreferenceandthevoltageattheSS1pin.Iftheerror
amplifier’s output increases, more current is delivered to
the output; if it decreases, less current is delivered.
The low voltage channel is a synchronous buck regulator
that operates from the V pin. It starts switching only
IN2
3641fa
10
LT3641
OPERATION
when the V pin voltage is above 2.3V, and the EN2 pin
undervoltage condition on the V pin triggers an internal
IN2
IN
is above its threshold. The internal top power MOSFET is
turned on each cycle at the beginning of each oscillator
cycle, and turned off when the current flowing through
the top MOSFET reaches a level determined by the voltage
at the VC2 node. An error amplifier measures the output
voltage through an external resistor divider tied to the FB2
pin and servos the VC2 node. The reference of the error
amplifier is determined by the lower of the internal 600mV
reference and the voltage at the SS2 pin.
latch that discharges the SS1 pin to below 100mV before
it is released. If the EN2 pin goes below its threshold,
or the V voltage falls below 2.2V, the SS2 pin will be
IN2
discharged to below 100mV before it is released.
To optimize efficiency, the LT3641 switches to low ripple
Burst Mode operation in light load situations. Between
switching pulses, control-circuitry current is minimized.
A power good comparator with 40mV of hysteresis trips
when the low voltage channel is enabled and the FB2 pin
is above 550mV. The PGOOD2 pin is an open-drain output
that is pulled low when both the outputs are in regulation.
While the top MOSFET is off, the bottom MOSFET is
turned on in an oscillator cycle until the inductor current
starts to reverse. If the inductor current is higher than the
valley current limit at the beginning of an oscillator cycle,
the bottom MOSFET will remain on and prevent the top
MOSFET from turning on until the overcurrent situation
clears, limiting inductor current in shorted output fault.
Power-On Reset and Watchdog Timer
The LT3641 includes one power-on reset timer for each
buck regulator and one common watchdog timer. Power-
on reset and watchdog timers are both adjustable using
external capacitors. Operation can be best understood by
referring to the Timing Diagram.
Aninternalregulatorprovidespowertothecontrolcircuitry.
The regulator draws most power from the V pin and a
IN2
small portion of power from the V pin when the V pin
IN
IN2
The RST1, RST2 and WDO pins are all open-drain outputs
withweakinternalpull-upstoabout2V.TheRST1andRST2
voltage is higher than 3V. If the voltage at V pin is lower
IN2
than 3V, the regulator draws all power from the V pin.
IN
pins are pulled low when the LT3641 is enabled and V is
IN
The EN/UVLO pin is used to put the LT3641 in shutdown,
reducing the input current to less than 1μA. The accurate
1.26V threshold of the EN/UVLO pin provides a program-
above 3.6V. Once the FB1 pin rises above 1.165V, the high
voltagechannelresettimerisstartedandRST1isreleased
aftertheresettimeoutperiod.Thelowvoltagechannelreset
timer is started once the FB2 pin rises above 550mV, and
releases RST2 after the reset timeout period.
mableV undervoltagelockoutthroughanexternalresistor
IN
divider tied to the EN/UVLO pin. A 2μA hysteresis current
on the EN/UVLO pin prevents switching noise from shut-
ting down the LT3641.
The watchdog circuit monitors a μP’s activity. As soon as
RST2 is released, a delay timer is started. The watchdog
timer is started after the delay timer times out. The LT3641
implements windowed watchdog function for higher sys-
tem reliability. The watchdog timer detects falling edges
on the WDI pin. If the falling edges are grouped too close
together or too far apart, the WDO pin is pulled down and
the reset timer is started. When the reset timer times out,
WDO is released and the watchdog timer is again started
after the delay period.
The LT3641 has an overtemperature protection feature
which disables switching in both channels when the junc-
tion temperature exceeds the overtemperature threshold.
Junction temperature will exceed the maximum operating
junction when overtemperature protection is active.
Internal2μAcurrentsourceschargetheSS1pinandtheSS2
pin up to about 2V. Soft-start or output voltage tracking of
the two channels can be independently implemented with
capacitorsfromtheSS1pinandtheSS2pintoground.Any
3641fa
11
LT3641
APPLICATIONS INFORMATION
Setting the Output Voltages
The high switching frequency also decreases the duty
cycle range. The reason is that the LT3641 switches have
finite minimum on- and off-times independent of the
switching frequency. The top switch in the high voltage
channel can turn on for a minimum of ~60ns and turn off
for a minimum of ~70ns. The top switch in the low voltage
channel can turn on for a minimum of ~110ns and turn
off for a minimum of ~70ns. The minimum and maximum
duty cycles are:
The internal reference voltage is 1.265V for the high
voltage channel, and 600mV for the low voltage channel.
The output voltages are set by resistor dividers according
to the following formulas:
VOUT1
1.265V
⎛
⎞
R2 = R1•
− 1
⎟
⎜
⎝
⎠
V
0.6V
⎛
⎞
OUT2
DC
DC
= f • t
S ON(MIN)
R4 = R3 •
− 1
MIN
⎜
⎟
⎝
⎠
= 1 – f • t
OFF(MIN)
MAX
S
Use 1% resistors in the resistor dividers. To avoid noise
problems, R1 should be 100k or less, and R3 should
be 50k or less. Reference designators refer to the Block
Diagram.
wheref istheswitchingfrequency,t
istheminimum
S
ON(MIN)
is the minimum switch
switch on-time, and t
OFF(MIN)
off-time. These equations illustrate how duty cycle range
increases when switching frequency decreases.
Switching Frequency
The internal oscillator of the LT3641 can be synchronized
to an external 350kHz to 2.5MHz positive clock signal on
The LT3641 uses a constant-frequency PWM architecture
thatcanbeprogrammedtoswitchfrom350kHzto2.2MHz
by using a resistor tied from the RT pin to ground. Table
1 shows the necessary R value for a desired switching
frequency.
the SYNC pin. The R value should be chosen such that
T
the internal oscillator’s frequency is 20% lower than the
lowest SYNC clock frequency (refer to Table 1). To avoid
erratic operation, the LT3641 ignores the SYNC signal
until the FB1 pin voltage is above 1.165V. When applying
a SYNC signal, the rising edges reset the LT3641’s internal
clock and initiate a switch cycle. The amplitude of the
SYNC signal must be at least 2V. The SYNC pulse width
must be at least 40ns.
T
Table 1. Switching Frequency vs RT Value
SWITCHING FREQUENCY (MHz)
R (k)
T
0.35
0.5
1
267
182
82.5
32.4
27.4
V Voltage Range
IN
2
2.2
The LT3641’s minimum operating voltage is 3.6V typical.
A higher minimum operating voltage can be accurately
Selection of the operating frequency is mainly a trade-off
between efficiency and component size. The advantage
of high frequency operation is that smaller inductor and
capacitor values may be used. The disadvantage is lower
efficiency.
programmed with a resistor divider between the V pin
IN
and the EN/UVLO pin. The EN/UVLO threshold is 1.26V.
WhentheLT3641isenabled, a2μAcurrentflowsoutofthe
EN/UVLOpingeneratinghysteresistopreventtheswitching
actionfromfalselydisablingtheLT3641.Choosethedivider
resistances for appropriate hysteresis voltage.
3641fa
12
LT3641
APPLICATIONS INFORMATION
The high voltage nonsynchronous channel operates from
V
Voltage Range
IN2
the V pin. The minimum V voltage to regulate output
IN
IN
The low voltage synchronous channel operates from
voltage is:
the V pin. The V pin can be connected to either an
IN2
IN2
independent voltage supply or the high voltage channel
⎛
⎜
⎞
VOUT1 + VD
⎝ DCMAX
VIN(MIN)
=
− VD + VCE
output for a two-stage power regulator. The V voltage
⎟
⎠
IN2
range is 2.3V ~ 5.5V
WhereV istheforwardvoltagedropofthecatchdiode,V
D
CE
The minimum V voltage to regulate output voltage at
IN2
is the voltage drop of the internal NPN power switch, and
full frequency is:
DC
is the maximum duty cycle (refer to the Switching
MAX
VOUT2
Frequencysection).IfV isbelowthecalculatedminimum
V
≈
IN
IN2(MIN)
DCMAX
voltage, output will lose regulation.
The maximum V should not exceed the absolute
WhereDC
isthemaximumdutycycle(refertoSwitching
IN
MAX
maximum rating. For fixed frequency operation, the
Frequencysection).IfV isbelowthecalculatedminimum
IN2
maximum V is:
voltage, the low voltage channel starts to skip oscillator
clock. In this case, the low voltage channel switching
frequency will no longer be the programmed frequency.
IN
⎛
⎜
⎞
VOUT1 + VD
⎝ DCMIN
V
=
− VD + VCE
IN(MAX)
⎟
⎠
As the V voltage further decreases, the top MOSFET
IN2
will remain on 100% duty cycle. In the case, the output
Note that the high voltage buck will still regulate at an
input voltage that exceeds V (up to 42V). It will
starts to fall out of regulation.
IN(MAX)
The maximum V for fixed frequency operation is:
continue to regulate through transients up to 55V for one
second. Note that the switching frequency will be reduced
once the on-time required to satisfy the above equation is
below 50ns (Figure 1).
IN2
VOUT2
DCMIN
V
≈
IN2(MAX)
Where DC
is the minimum duty cycle (refer to the
MIN
Switching Frequency section). For voltage that exceeds
(up to 5.5V), the low voltage channel exhi-
V
IN2(MAX)
bits pulse-skipping behavior, and the output ripple will
increase.
SW1
10V/DIV
Inductor Selection
I
L1
0.5A/DIV
Inductorselectioninvolvesinductance,saturationcurrent,
series resistance (DCR) and magnetic loss.
3641 F01
200ns/DIV
SET = 2MHz
V
V
= 30V
R
T
IN
OUT1
= 3.3V/0.2A
The inductance for the high voltage channel is:
Figure 1. Lower Switching Frequency Occurs in High
Voltage Channel When Required On-Time Is Below 50ns
VOUT1 + VD
L1= 1.7 •
fS
3641fa
13
LT3641
APPLICATIONS INFORMATION
where V
is high voltage channel output voltage, V is
OUT1
D
Table 2. Inductor Vendors
VENDOR
Murata
the forward voltage drop of the catch diode, and f is the
S
WEBSITE
www.murata.com
switching frequency. For example, 3.3μH is a reasonable
inductance for a 3.3V output with 2MHz switching
frequency.
TDK
www.tdk.com
TOKO
www.toko.com
Oncetheinductanceisselected,theinductorcurrentripple
and peak current can be calculated:
Sumida
www.sumida.com
www.cooperindustries.com
www.coilcraft.com
www.vishay.com
Cooper/Coiltronics
Coilcraft
Vishay
⎛
⎞
(VOUT1 + VD)
VOUT1 + VD
ΔIL1 =
• 1–
⎜
⎝
⎟
⎠
L1• fS
V
IN
NIC
www.niccomp.com
www.we-online.com
Würth Elektronik
ΔIL
2
IL(PEAK) = IOUT(MAX)
+
Of course, such a simple design guide will not always
result in the optimum inductors for the applications. A
larger value inductor provides a slightly higher maximum
load current and will reduce the output voltage ripple. A
largervalueinductoralsoresultsinhigherefficiencyinthe
condition of same DCR and same magnetic loss. However,
for a same series of inductors, a larger value inductor has
higher DCR. The trade-off between inductance and DCR
is not always obvious. Use experiments to find optimum
inductors.
To guarantee sufficient output current, peak inductor
current must be lower than the switch current limit (I ).
LIM
The largest inductor current ripple occurs at the highest
V . To guarantee current capacity, use V
in the
IN
IN(MAX)
above formula.
The inductance for the low voltage channel is:
VOUT2
L2 = 1.5
fS
Low inductance may result in discontinuous mode oper-
ation, which is okay, but reduces maximum load current.
For details of maximum output current and discontinuous
modeoperation,seetheLinearTechnologyApplicationNote
44. For duty cycles greater than 50%, there is a minimum
inductance required to avoid subharmonic oscillations.
See the Linear Technology Application Note 19.
For a selected inductance, the inductor current ripple can
be calculated:
⎛
⎞
VOUT2
L2 • fS
VOUT2
V
IN2
ΔIL2
=
• 1–
⎜
⎝
⎟
⎠
For robust operation in fault conditions, the inductor
saturation current should be higher than the upper limit
of the corresponding top switch current limit.
Input Capacitor
Bypass the V pin of the LT3641 with a ceramic capacitor
IN
To keep the efficiency high, the inductor series resistance
(DCR) should be as small as possible (must be < 0.1Ω),
and the core material should be intended for the chosen
operation frequency. High efficiency converters generally
cannot afford the core loss found in low cost powdered
iron cores; instead use ferrite, molypermalloy or Kool Mμ
cores. Table 2 lists several vendors and suitable inductor
series.
of X7R (–55°C to 125°C) or X5R (–55°C to 85°C) type.
Buckconvertersdrawpulsecurrentfromtheinputsupply.
The input capacitor is required to reduce the resulting
voltage ripple. Use a ceramic capacitor with:
10μF
fS
CIN ≥
where f in the switching frequency in MHz.
S
3641fa
14
LT3641
APPLICATIONS INFORMATION
Asecondprecautionregardingtheceramicinputcapacitor
concernsthemaximuminputvoltageratingoftheLT3641.
A ceramic input capacitor combined with trace or cable
inductanceformsaunderdampedtankcircuit.IftheLT3641
circuit is plugged into a live supply, the input voltage can
ring to twice its nominal value, possibly exceeding the
LT3641’svoltagerating.Thissituationcanbeeasilyavoided
(see the Linear Technology Application Note 80).
When choosing a capacitor, look carefully through the
data sheet to find out what the actual capacitance is under
operating conditions (applied voltage and temperature).
A physically larger capacitor or one with a higher voltage
rating may be required. High performance tantalum or
electrolyticcapacitorscanbeusedfortheoutputcapacitor.
Low ESR is important, so choose one that is intended for
use in switching regulators. Table 3 lists several capacitor
vendors.
Output Capacitors and Output Ripple
Table 3. Capacitor Vendors
Theoutputcapacitorhastwoessentialfunctions.Insteady
state, it determines the output voltage ripple. In transient,
it stores energy in order to satisfy transient loads and
stabilize the control loop. Ceramic capacitors have low
equivalent series resistance (ESR) and provide the best
ripple performance. A good starting value is:
PART SERIES
VENDOR
Ceramic, Polymer, Tantalum Panasonic/Sanyo
www.panasonic.com
Ceramic, Tantalum
Kemet
www.kemet.com
Ceramic
Murata
www.murata.com
150
VOUT • fS
Ceramic, Tantalum
Ceramic
AVX
COUT1
=
www.avxcorp.com
Taiyo Yuden
www.taiyo-yuden.com
where f is in MHz, and C
is the recommended output
OUT
S
capacitance in μF. Use X5R or X7R types. This choice will
Catch Diode
provide low output ripple and good transient response.
The high voltage channel requires an external catch diode
toconductcurrentduringswitchoff-time.Averageforward
current in normal operation can be calculated from:
A good starting value for the low voltage channel output
capacitor is:
100
VOUT2 • fS
COUT2
=
IOUT (VIN − VOUT
)
ID(AVG)
where I
=
V
IN
In the case where V is connected to the high voltage
IN2
is the output load current. Use a 1A or 2A
OUT
channel output, the high voltage channel output capacitor
rated Schottky diode. Peak reverse voltage is equal to
the regulator input voltage. Use a diode with a reverse
voltage rating greater than the input voltage. Table 4 lists
several Schottky diodes and their manufacturers. Diodes
Inc. PDS360 is recommended for high current, H-grade
applications. DiodesInc. DFLS260canbeusedforsmaller
circuit footprint in non-H-grade applications.
can be used as the low voltage channel input capacitor.
The required V input capacitor value is usually smaller
IN2
than the high voltage output capacitor.
Low ESR ceramic capacitors for V input and high volt-
IN2
age channel output could form resonant tank and cause
jitter in certain operating area. Avoid V input capacitor
IN2
if possible.
3641fa
15
LT3641
APPLICATIONS INFORMATION
Table 4. Diode Vendors
capacitor charging scheme solves this start-up issue.
Figure 2 shows that the minimum input voltage to start
the high voltage channel nonsynchronous buck regulator
of the LT3641 is very close to the minimum input voltage
to regulate the output voltage for most of the load range.
V
I
V AT 1A V AT 2A V AT 3A
F F F
R
AVE
PART NUMBER
(V)
(A)
(MV)
(MV)
(MV)
On Semiconductor
MBRM120E
MBRM140
20
40
1
1
530
595
5
Diodes Inc.
START
B120
20
30
20
30
40
60
60
100
1
1
2
2
2
2
3
3
500
500
4
B130
RUN
B220
B230
DFLS240L
DFLS260
PDS360
PDS3100
500
500
500
620
3
2
1
0
650
620
760
International Rectifier
10BQ030
20BQ030
30
30
1
2
420
470
470
0.001
0.01
0.1
1
V
CURRENT (A)
OUT
3641 F03a
BST and SW Pin Considerations
(2a) FS = 2MHz
The high voltage channel requires an external capacitor
between the BST and SW pins and an external boost diode
from a voltage source to the BST pin. In most cases, a
0.22μF capacitor will work well. Use a Schottky with fast
reverse recovery for BST diode. The (BST-SW) voltage
cannot exceed 5.5V, and must be more than 2.3V for best
efficiency.Connecttheboostdiodetoanyvoltagebetween
5
4
3
2
1
START
RUN
2.7V and 5.5V. The V pin is the best choice if the low
IN2
voltage channel is used.
The high voltage channel will not start until the (BST-SW)
voltage is 2V or above. When the LT3641 is enabled, an
internal ~5mA current source from V flows out of the
0
IN
0.001
0.01
0.1
1
BST pin. The SW pin is disconnected from the SW1 pin,
andispulleddownbyaninternalcurrentsourcetoground.
The external boost capacitor can be charged up regard-
less of the output. When the (BST-SW) voltage reaches
2V, the SW pin is connected to the SW1 pin, and the high
voltage channel starts switching. However, the internal
bipolar power switch cannot be fully saturated until the
(BST-SW)voltageisfurtherchargedtoabove2.3V.Tostart
up a traditional nonsynchronous buck regulator with very
light load, the input voltage needs to be a couple of volts
higherthantheminimumrunninginputvoltageiftheinput
voltage is ramping up slowly. The LT3641’s unique boost
V
CURRENT (A)
OUT
3641 F03b
(2b) FS = 500kHz
Figure 2. High Voltage Channel Minimum
Input Voltage for VOUT1 = 3.3V
3641fa
16
LT3641
APPLICATIONS INFORMATION
Soft-Start
EN/UVLO
2V/DIV
The LT3641 has a soft-start pin for each channel. The
feedback pin voltage is regulated to the lower of the
corresponding SS pin and the internal references, which
is 1.265V for the high voltage channel, and 600mV for the
lowvoltagechannel.AcapacitorfromtheSSpintoground
ischargedbyaninternal2μAcurrentsourceresultinginan
output ramping linearly from 0V to the regulated voltage.
The duration of the ramp is:
V
OUT1
2V/DIV
V
OUT2
1V/DIV
PGOOD2
2V/DIV
3641 F04
500μs/DIV
V
= 12V
IN
T
R
SET = 2MHz
EN2 TIED TO FB2
1.265V
2μA
tSS1 = CSS1
•
Figure 3. Soft-Start of LT3641
600mV
2μA
tSS2 = CSS2
where t
•
Shorted-Output Protection
If an inductor is chosen that will not saturate excessively,
the LT3641 will tolerate a shorted output. For the high
voltage channel, the DA current comparator extends the
internal oscillator period until the catch diode current is
below its limit. Both the top switch and the DA comparator
have current foldback to help limit load current when the
output is shorted to ground. The DA current limit is 1.7A
when the FB1 voltage is above 0.2V, and is 1A when the
FB1 voltage is below 0.2V. Figure 4 shows the high voltage
channel operation under shorted output.
is the ramping time for the SS1 pin, t
the ramping time for the SS2 pin, C
from the SS1 pin to ground, and C
from the SS2 pin to ground.
is
SS1
SS2
is the capacitance
is the capacitance
SS1
SS2
At power-up, a latch is set to discharge the SS1 pin.
After the SS1 pin is discharged to below 100mV, the latch
is reset. The internal 2μA current source starts to charge
the SS1 pin when the (BST-SW) voltage is charged to
above 2V.
In the event of V undervoltage lockout, or the EN/UVLO
IN
Because of the low V voltage, the low voltage channel
IN2
pin being driven below 1.26V, the soft-start latch is set,
does not have current foldback. The low voltage channel
does not extend the internal oscillator in shorted output
condition allowing the high voltage channel to operate
in constant frequency. If the bottom MOSFET current
exceeds the NMOS current limit at the start of a clock
cycle, the top MOSFET is kept off until the overcurrent
situation clears. The inductor valley current is kept below
the NMOS current limit to ensure robustness in shorted
output condition (Figure 5).
triggering a start-up sequence.
A latch is set to discharge the SS2 pin at power-up. After
EN/UVLO is enabled, the V voltage is above 2.3V, the
IN2
EN2 pin is enabled, and the SS2 pin is below 100mV, the
latch is reset. The internal 2μA current source starts to
charge the SS2 pin.
In the event of the V pin falling below 2.2V, or the EN2
IN2
pin going below its threshold, the SS2 discharging latch
is set, triggering a start-up sequence.
The SS pins can also be pulled up by external current
sources or resistors for output tracking. The external pull-
up current should not exceed 100μA for either SS pin.
Figure 3 shows the soft-start for a 3.3V and 1.8V
application.
3641fa
17
LT3641
APPLICATIONS INFORMATION
Reverse Protection
In battery charging applications or in battery back-up
systems, the output will be held high when the input to the
SW1
20V/DIV
LT3641 is absent. If the V pin is floated and the LT3641
IN
is enabled, the LT3641’s internal circuitry will pull its qui-
escent current through the SW1 pin or the SW2 pin. This
is fine if the system can tolerate a few mA in this state.
If the LT3641 is disabled, the SW1 pin and the SW2 pin
I
L1
1A/DIV
3641 F05
1μs/DIV
current will drop to essentially zero. However, if the V
IN
V
V
= 55V
IN
OUT1
= SHORT
pin is grounded while the high voltage channel output is
held high, an external diode is required at the V pin to
IN
Figure 4. The High Voltage Channel Reduces Frequency
to Protect Against Shorted Output with 55V Input
prevent current being pulled out of the V pin. If the V
IN
IN2
pin is grounded while the low voltage channel output is
held high, an external diode is required at the V pin to
IN2
SW1
20V/DIV
prevent current being pulled out of the V pin (Figure 6).
IN2
PFM Operation
SW2
2V/DIV
Toimproveefficiencyatlightloads,theLT3641automatically
switches to pulse frequency modulation (PFM) operation
which minimizes the switching loss and keeps the output
voltage ripples small.
I
L2
1A/DIV
3641 F06
1μs/DIV
Because the two channels of the LT3641 may have differ-
ent loads, the two channels can have different switching
frequency (Figure 7).
V
V
= 5V
OUT2
IN2
= SHORT
Figure 5. The Low Voltage Channel Operates in Valley
Current Limit Mode to Protect Against Shorted Output
IN
V
SW BST SW1
OUT1
OUT2
IN
+
–
DA
FB1
EN/UVLO
LT3641
SW2
FB2
IN2
V
IN2
+
–
GND
3641 F07
Figure 6. Diodes Prevent Shorted Inputs from
Discharging a Battery Tied to the Outputs
3641fa
18
LT3641
APPLICATIONS INFORMATION
Power-On Reset Timer
SW1
10V/DIV
Each channel of the LT3641 has a power-on comparator.
BothcomparatorsareenabledwhentheLT3641ispowered
up and starts monitoring their corresponding feedback
voltages. The threshold of power-on comparator is 1.15V
for the high voltage channel, and 550mV for the low
voltage channel.
I
L1
0.5A/DIV
SW2
5V/DIV
I
L2
0.5A/DIV
3641 F08a
500ns/DIV
Both RST1 and RST2 are open-drain outputs with weak
internal pull-ups (100k to ~2V). The DC characteristics of
the RST1 and RST2 pull-down strength are shown in the
Typical Performance Characteristics section. The weak
pull-ups eliminate the need for external pull-ups when
the rise time of these pins is not critical. The open-drain
configuration allows wired-OR connections.
V
V
= 12V
IN
OUT1
V
OUT2
= V
IN2 OUT1
= 3.3V/25mA
V
= 1.8V/30mA
(7a)
SW1
10V/DIV
I
L1
The two power-on reset timers share one oscillator. The
0.5A/DIV
power-on reset timeout period, t
(64 cycles on the
RST
SW2
5V/DIV
CPOR pin), which is the same for the two channels, can
be programmed by connecting a capacitor, C , between
POR
I
L2
0.5A/DIV
the CPOR pin and ground:
3641 F08b
2μs/DIV
s
⎝ ⎠
F
⎛ ⎞
tRST = CPOR • 37 • 106
V
V
= 12V
OUT1
V = V
IN2 OUT1
IN
⎜ ⎟
= 3.3V/25mA
V
= 1.8V/20mA
OUT2
(7b)
For example, using a capacitor value of 8.2nF gives a
303ms reset timeout period. The accuracy of t will be
RST
SW1
limited by the accuracy and temperature coefficient of the
capacitor CPOR. Extra parasitic capacitance on the CPOR
10V/DIV
I
L1
pin, such as probe capacitance, can affect t
.
RST
0.5A/DIV
SW2
5V/DIV
Watchdog
TheWDEpinistheenablepinforthewatchdog.Assoonas
RST2 is released, the watchdog starts a delay period, t
during which the input signal at the WDI pin is ignored for
higherreliability.Afterthedelayperiod,thewatchdogstarts
detecting falling edges on the WDI pin. If the time between
any two WDI falling edges is shorter than the watchdog
I
L2
0.5A/DIV
,
DLY
3641 F08c
2μs/DIV
V
V
= 12V
OUT1
V
OUT2
= V
IN
IN2 OUT1
= 3.3V/0mA
V
= 1.8V/30mA
(7c)
Figure 7. PFM Operation
lower boundary, t
, or longer than the watchdog upper
WDL
boundary, t
, the WDO pin is pulled down for a period
WDU
of t , which is the same as the power-on reset timeout
RST
period.WhentheWDOpinisreleased,thewatchdogagain
starts the delay period.
3641fa
19
LT3641
APPLICATIONS INFORMATION
The WDO is open-drain output with weak internal pull-up,
CWDT
CPOR
similar to the RST pins.
WD STARTS
The delay period corresponding to 33 cycles on CWDT, the
watchdog lower boundary (4 cycles on CWDT), and the
watchdog upper boundary (64 cycles on CWDT) are all
64 CYCLES 64 CYCLES
FB2
FB1
RST2
RST1
related and set by a capacitor, C
pin and ground:
, between the CWDT
WDT
3641 F09a
33
64
⎛
⎞
20ms/DIV
tDLY = tWDU ⎜
•
⎟
⎠
⎝
(8a)
tWDU
16
tWDL
=
s
⎝ ⎠
F
CWDT
CPOR
⎛ ⎞
tWDU = CWDT • 37 • 106
⎜ ⎟
The accuracy of the watchdog timer will be limited by
the accuracy and temperature coefficient of the capacitor
WDT
WDI
C
. Extra parasitic capacitance on the CWDT pin, such
WDO
as probe capacitance, can affect the watchdog timer.
3641 F09b
1ms/DIV
Figure 8a shows the power-on reset timing. Having FB1
(8b)
or FB2 high starts the CPOR oscillator. After t , the cor-
RST
responding RST is released. When both RST1 and RST2
are released, the CWDT oscillator starts. Figure 8b shows
thewatchdogwaveformwiththeWDIperiodbetweent
WDL
CWDT
CPOR
andt
.TheWDIfallingedgeresetstheCWDToscillator.
WDU
The CPOR oscillator is disabled and WDO remains high.
Figure 8c shows the watchdog waveform with the WDI
period longer than t
RST
. WDO is asserted for a period of
WDU
WDI
t
when the watchdog upper boundary, t
, expires.
WDU
WDO
The watchdog function can be disabled by tying WDE
above its threshold. In this case, the CWDT pin can be left
floating. If neither the watchdog function nor the power-
on reset function is used, both the CWDT and CPOR pin
can be left floating.
3640 F09c
50ms/DIV
(8c)
Figure 8. Power-On Reset and Watchdog Timing
TheaccuracyoftheCPORandCWDTcapacitorsdetermine
the accuracy of the power-on reset timer and watchdog
timer. The COG or NPO type of ceramic capacitors have
zero temperature coefficient and good aging characteris-
tics. Use COG or NPO type of capacitors with flat DC bias
characteristic up to 1.5V on the CPOR and CWDT pins.
3641fa
20
LT3641
APPLICATIONS INFORMATION
PCB Layout
For proper operation and minimum EMI, care must be
takenduringtheprintedcircuitboard(PCB)layout.Figure9
shows the recommended component placement with
trace, ground plane and via locations. The input loop
of the high voltage channel, which is formed by the V
IN
C
OUT2
and SW1 pins, the external catch diode (D1), the input
L2
capacitor (C ) and the ground, should be as small as
IN
possible. These external components should be placed
on the same side of the circuit board as the LT3641, and
their connections should be made on that layer. Place a
local, unbroken ground plane below these components.
The BST and SW nodes should be as small as possible.
C
C
IN2
IN
C
BST
L1
The boost capacitor (C ) should be as close to the BST
BST
and SW pins as possible.
C
OUT1
The input loop of the low voltage channel is formed by
the V pin, the input capacitor (C ) and the ground.
3641 F10
IN2
IN2
Place C close to the V and the GND pin to minimize
IN2
IN2
Figure 9. Recommended PCB Layout, FE28 Package
this loop. Place a local, unbroken ground plane below
this input loop.
Figure 10b shows a simple alternative. By tying EN2 to
IN2
minimum operating voltage of 2.3V.
KeeptheFB1andFB2nodessmallsothatthegroundtraces
will shield them from the switching nodes. The Exposed
Pad on the bottom of the package must be soldered to
the ground so that the pad acts as a heat sink. To keep
thermalresistancelow,extendthegroundplaneasmuchas
possible, and add thermal vias under and near the LT3641
to additional ground planes within the circuit board and
on the bottom side.
V
, channel 2 starts as soon as its input reaches its
Figure 10c shows a circuit that handles two other com-
mon requirements. If the system requires the low voltage
output to be in regulation before the higher voltage output
(for example core voltage must appear before the I/O sup-
ply), then add a PMOS switch and drive its gate with the
PGOOD2 pin, which will go low when both channels are
in regulation. This provides a third output OUT3, which is
present only when both OUT1 and OUT2 are in regulation.
Sequencing Options
In most LT3641 applications, the low voltage regulator
generating OUT2 will operate from the output of the
high voltage regulator generating OUT1. In this cascade
circuit, channel 1 must start before channel 2. However,
the LT3641 provides additional flexibility in programming
the sequencing of the outputs. Figure 10 shows several
possibilities.
Figure 10c also takes care of a potential problem in
cascaded power supply circuits. Because channel 2 is a
switchingregulator,itappearsasnegativeimpedanceload
to channel 1; as OUT1 decreases, the load required to sup-
ply the input of channel 2 increases. Since the channel 1
is current limited, you must be certain that it can supply
bothitsownloadandthepowerrequiredbychannel2.The
EN2 has an accurate threshold of 1.165V, and is used to
program an undervoltage lockout for channel 2, allowing
channel 1 to supply adequate power.
Figure 10a shows the easiest option. With EN2 tied to
FB1, channel 2 will start when OUT1 is within 10% of its
regulation point.
3641fa
21
LT3641
APPLICATIONS INFORMATION
OUT1
FB1
EN2
OUT1
OUT2
90%
V
IN2
OUT1
OUT1
(10a)
FB1
EN2
OUT1
OUT2
2.3V
V
IN2
OUT1
(10b)
OUT1
OUT3
FB1
OUT1
OUT2
OUT3
PROGRAMMED
LEVEL
PGOOD2
V
IN2
OUT1
90%
EN2
3641 F11
(10c)
Figure 10. The EN2 and PGOOD2 Pins Allow Serial Sequencing Options
3641fa
22
LT3641
TYPICAL APPLICATIONS
2MHz 3.3V/1.3A and 1.8V/1A Buck Regulators
V
0.22μF
IN
D2
5V TO 42V*
4.7μF
301k
100k
L1
3.3μH
V
OUT1
3.3V/1.3A
22μF
EN/UVLO
V
IN
SW
BST
SW1
80.6k
D1
DA
FB1
SYNC
49.9k
WDE
EN2
V
IN2
PGOOD2
LT3641
V
IN2
2.5V TO 5.5V
4.7μF
L2
1μH
RST1
RST2
WDO
V
OUT2
1.8V/1.1A
22μF
SW2
100k
WDI
FB2
SS1
CWDT CPOR
RT
GND SS2
49.9k
1nF
1.5nF
32.4k
1.5nF
1nF
3641 TA02
L1: VISHAY IHLP2020BZER3R3M01
L2: VISHAY IHLP1616ABER1R0M01
D1: DIODES PDS360
D2: CENTRAL SEMI CMDSH-4E
* RESTRICTIONS APPLY FOR INPUT VOLTAGES ABOVE 42V
2MHz 5V/0.8A and 1.2V/1A Buck Regulators
V
0.22μF
D2
IN
7V TO 42V*
4.7μF
100k
453k
L1
4.7μH
V
OUT1
5V/0.8A
EN/UVLO
V
IN
SW
BST
SW1
22μF
301k
100k
D1
DA
SYNC
WDE
WDI
FB1
EN2
LT3641
WDI
V
IN2
OUT1
100k
L2
0.47μH
PGOOD2
WDO
100k
100k
V
OUT2
SW2
1.2V/1A
22μF
100k
49.9k
49.9k
RST1
FB2
SS1
RST2
CWDT CPOR
RT
GND SS2
1nF
1.5nF
32.4k
1.5nF
1nF
3641 TA03
L1: VISHAY IHLP2020BZER4R7M01
L2: VISHAY IHLP1616ABERR47M01
D1: DIODES DFLS260
D2: CENTRAL SEMI CMDD6263
* RESTRICTIONS APPLY FOR INPUT VOLTAGES ABOVE 42V
3641fa
23
LT3641
TYPICAL APPLICATIONS
2MHz 3V/0.8A and 0.6V/1A Buck Regulators
0.22μF
D2
V
IN
L1
4V TO 42V*
3.3μH
V
OUT1
4.7μF
3V/0.8A
22μF
EN/UVLO
V
IN
SW
BST
SW1
68.1k
D1
DA
FB1
SYNC
49.9k
EN2
WDE
PGOOD2
LT3641
V
IN2
L2
0.47μH
RST1
RST2
WDO
V
OUT2
SW2
FB2
0.6V/1A
22μF
WDI
CWDT CPOR
RT
GND SS2
32.4k
SS1
1nF
1.5nF
1.5nF
1nF
3641 TA04
L1: VISHAY IHLP2020BZER3R3M01
L2: VISHAY IHLP1616ABERR47M01
D1: DIODES PDS360
D2: CENTRAL SEMI CMDSH2-3
* RESTRICTIONS APPLY FOR INPUT VOLTAGES ABOVE 42V
3641fa
24
LT3641
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation EB
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
4.75
(.187)
28 2726 25 24 23 22 21 20 19 18 1716 15
6.60 0.10
4.50 0.10
2.74
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
(.108)
SEE NOTE 4
6.40
2.74
(.252)
(.108)
BSC
0.45 0.05
1.05 0.10
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
5
7
1
2
3
4
6
8
9 10 12 13 14
11
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE28 (EB) TSSOP 0204
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
2. DIMENSIONS ARE IN
FOR EXPOSED PAD ATTACHMENT
MILLIMETERS
(INCHES)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3. DRAWING NOT TO SCALE
3641fa
25
LT3641
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 0.05
4.50 0.05
3.10 0.05
2.50 REF
2.65 0.05
3.65 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
3.50 REF
4.10 0.05
5.50 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45 CHAMFER
2.50 REF
R = 0.115
TYP
R = 0.05
TYP
0.75 0.05
4.00 0.10
(2 SIDES)
27
28
0.40 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 0.10
(2 SIDES)
3.50 REF
3.65 0.10
2.65 0.10
(UFD28) QFN 0506 REV B
0.25 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3641fa
26
LT3641
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
11/11 Added H-grade to Absolute Maximum Ratings, Order Information, and Note 2
2, 4
3641fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LT3641
TYPICAL APPLICATION
2MHz 3.3V/0.8A and 0.8V/1.2A Buck Regulators
0.22μF
V
IN
4V TO 42V*
3.3μH
V
OUT1
4.7μF
3.3V/0.8A
22μF
EN/UVLO
SYNC
V
IN
SW
BST
SW1
80.6k
49.9k
DA
FB1
EN2
PGOOD2
LT3641
V
IN2
WDE
RST1
RST2
WDO
0.47μH
V
OUT2
0.8V/1.2A
22μF
SW2
16.5k
49.9k
WDI
FB2
SS1
CWDT CPOR
RT
GND SS2
1nF
32.4k
1nF
3641 TA05
* RESTRICTIONS APPLY FOR INPUT VOLTAGES ABOVE 42V
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT3640
35V, 55V Transient Protection, 1.3A High Voltage Channel and V : 4V to 35V, Transient to 55V, V
= 0.6V, I = 290mA, 1μA,
IN
OUT(MIN) Q
1.1A Low Volume Channel
4mm × 5mm QFN-28, TSSOP-28E Packages
LT3689
36V, 60V Transient Protection, 800mA, 2.2MHz High
Efficiency MicroPower Step-Down DC/DC Converter with
POR Reset and Watchdog Timer
V : 3.6V to 36V, Transient to 60V, V
SD
= 0.8V, I = 75μA,
Q
IN
OUT(MIN)
I
< 1μA, 3mm × 3mm QFN-16 Package
LT3686/LT3686A 37V, 55V
, 1.2A, 2.5MHz High Efficiency Step-Down DC/
V : 3.6V to 37V, Transient to 55V, V
= 1.21V, I = 1.1mA,
Q
MAX
IN
OUT(MIN)
DC Converter
I
< 1μA, 3mm × 3mm DFN-10 Package
SD
LT3682
LT3971
LT3991
36V, 60V
, 1A, 2.2MHz High Efficiency Micropower
V : 3.6V to 36V, V
= 0.8V, I = 75μA, I < 1μA, 3mm × 3mm
Q SD
MAX
IN
OUT(MIN)
Step-Down DC/DC Converter
DFN-12 Package
38V, 1.2A (I ), 2MHz, High Efficiency Step-Down DC/DC
Converter with Only 2.8μA of Quiescent Current
V : 4.2V to 38V, V
= 1.2V, I = 2.8μA, I < 1μA, 3mm × 3mm
Q SD
OUT
IN
OUT(MIN)
DFN-10, MSOP-10E Packages
55V, 1.2A (I ), 2MHz, High Efficiency Step-Down DC/DC
Converter with Only 2.8μA of Quiescent Current
V : 4.2V to 55V, V
= 1.2V, I = 2.8μA, I < 1μA, 3mm × 3mm
Q SD
OUT
IN
OUT(MIN)
DFN-10, MSOP-10E Packages
3641fa
LT 1111 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
© LINEAR TECHNOLOGY CORPORATION 2011
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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