LT3688IUFPBF [Linear]
Dual 800mA Step-Down Switching Regulator with Power-On Reset; 双800毫安降压型开关稳压器具有上电复位
| 型号： | LT3688IUFPBF |
| 厂家： | 
Linear |
| 描述： | Dual 800mA Step-Down Switching Regulator with Power-On Reset |
| 文件： | 总28页 (文件大小：405K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3688
Dual 800mA Step-Down
Switching Regulator with
Power-On Reset and
Watchdog Timer
FEATURES
DESCRIPTION
The LT®3688 is an adjustable frequency (350kHz to
2.2MHz) dual monolithic step-down switching regulator
with two power-on reset timers and a watchdog timer.
The regulator operates off inputs up to 36V. Low ripple
Burst Mode® operation maintains high efficiency at low
output current while keeping output ripple below 25mV in
a typical application, with input quiescent current of just
115μA. Shutdown circuitry reduces input supply current
to less than 1μA while EN/UVLO is pulled low.
n
Wide Input Range:
Operation from 3.8V to 36V
n
Low Ripple (<25mV ) Burst Mode Operation:
P-P
IN
I = 115μA at 12V to 3.3V and 5V
Q
n
n
Programmable, Defeatable Window Watchdog Timer
Two Independently Programmable Power-On-Reset
Timers
n
n
n
n
Synchronizable, Adjustable 350kHz-2.2MHz
Switching Frequency
Two 800mA Output Switching Regulators with Internal
Power Switches
Programmable Input Undervoltage Lockout with
Hysteresis
Thermally Enhanced 24-Pin TSSOP and 4mm × 4mm
QFN Packages
The reset and watchdog timeout periods are both adjust-
able using external capacitors. Tight accuracy specifica-
tions and glitch immunity ensure reliable reset operation
without false triggering. The open collector RST pins will
pull down if the monitored output voltage drops 10%
belowtheprogrammedvalue.TheLT3688watchdogtimer
monitors for watchdog falling edges grouped too close
together or too far apart.
APPLICATIONS
n
Automotive Electronic Control Units
The LT3688 is available in 24-Pin TSSOP and 4mm ×
4mm QFN packages, each with an exposed pad for low
thermal resistance.
n
Industrial Power Supplies
n
High-Reliability ꢀProcessor Systems
L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective
owners.
TYPICAL APPLICATION
5V and 3.3V Regulator with Power-On Reset and Watchdog Timers
Efficiency
V
90
80
70
60
50
40
30
10000.0
1000.0
100.0
10.0
IN
6V TO 36V
V
V
= 12V
IN
OUT
= 3.3V
4.7ꢀF
EN/UVLO
BST1
V
BIAS
BST2
IN
L = 4.7ꢀH
f = 800kHz
18ꢀH
0.22ꢀF
0.22ꢀF 12ꢀH
V
V
OUT1
5V
OUT2
3.3V
SW1
SW2
800mA
800mA
LT3688
523k
316k
100k
DA1
FB1
DA2
FB2
22pF
22ꢀF
22pF
1nF
1nF
1.0
100k
22ꢀF
RUN/SS2
RUN/SS1
0.1
C
WDT
ꢀP
I/O
I/O
RESET
WDI
C
POR1
1nF
WDO
RST1
RST2
0.01
C
POR2
RT
0.0001
0.001
0.01
0.1
1
4.7nF
4.7nF
LOAD CURRENT (A)
SYNC
GND
3688 TA01b
110k
3688 TA01a
f
= 500kHz
SW
3688f
1
LT3688
ABSOLUTE MAXIMUM RATINGS
(Note 1)
V , EN/UVLO, CONFIG Voltage (Note 2)...................36V
Operating Junction Temperature Range (Note 3)
LT3688E, LT3688I ..............................–40°C to 125°C
LT3688H ............................................–40°C to 150°C
Maximum Junction Temperature
IN
BST Voltage ..............................................................55V
BST above SW Voltage .............................................30V
BIAS Voltage.............................................................30V
WDE, WDI, RST, WDO Voltage ...................................6V
FB, RT, SYNC, RUN/SS Voltage..................................6V
LT3688E, LT3688I ............................................. 125°C
LT3688H ........................................................... 150°C
Storage Temperature Range...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec)
C , C
WDT POR
Voltage ....................................................3V
FE Package ....................................................... 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
1
2
EN/UVLO
SYNC
RT
24
23
22
21
20
19
18
17
16
15
14
13
FB1
RUN/SS1
BST1
24 23 22 21 20 19
3
RT
SYNC
1
2
3
4
5
6
18 WDO
4
C
WDT
SW1
RST1
RST2
17
16
5
C
DA1
POR1
EN/UVLO
FB1
6
BIAS
25
GND
V
IN
25
GND
15 FB2
7
C
CONFIG
DA2
POR2
RUN/SS1
BST1
RUN/SS2
14
8
WDI
13 BST2
9
WDE
WDO
RST1
RST2
SW2
7
8
9 10 11 12
10
11
12
BST2
RUN/SS2
FB2
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
FE PACKAGE
24-LEAD PLASTIC TSSOP
θ
= 38°C/W
θ
= 37°C/W
JA
JA
EXPOSED PAD (PIN 25) IS GND, MUST BE ELECTRICALLY CONNECTED TO PCB
EXPOSED PAD (PIN 25) IS GND, MUST BE ELECTRICALLY CONNECTED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LT3688EFE#PBF
LT3688IFE#PBF
LT3688HFE#PBF
LT3688EUF#PBF
LT3688IUF#PBF
TAPE AND REEL
PART MARKING*
LT3688FE
LT3688FE
LT3688FE
3688
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–40°C to 125°C
–40°C to 125°C
LT3688EFE#TRPBF
LT3688IFE#TRPBF
LT3688HFE#TRPBF
LT3688EUF#TRPBF
LT3688IUF#TRPBF
24-Lead Plastic TSSOP
24-Lead Plastic TSSOP
24-Lead Plastic TSSOP
24-Lead (4mm × 4mm) Plastic QFN
24-Lead (4mm × 4mm) Plastic QFN
3688
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3688f
2
LT3688
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, unless otherwise noted. (Note 3)
SYMBOL
PARAMETER
Undervoltage Lockout
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
V
IN
3
3.5
3.8
V
Quiescent Current from V
V
V
V
= 0.3V
EN/UVLO
BIAS
BIAS
0.01
65
235
1
105
310
ꢀA
ꢀA
ꢀA
IN
= 5V, Not Switching
= 0V, Not Switching
Quiescent Current from BIAS
FB Voltage
V
V
V
= 0.3V
0.01
155
–5
1
ꢀA
ꢀA
ꢀA
EN/UVLO
l
= 5V, Not Switching
= 0V, Not Switching
200
–20
BIAS
BIAS
0.790
0.784
0.800
0.810
0.814
V
V
l
l
FB Pin Bias Current
V
FB
= 0.800V
–3
–50
nA
FB Voltage Line Regulation
Switching Frequency
5V < V < 36V
0.002
%/V
IN
l
l
R = 20k, V
= 12V
= 12V
1.85
460
2.1
500
2.35
540
MHz
kHz
T
BST
R = 110k, V
T
BST
l
l
Minimum Off-Time (Note 4)
Switch Current Limit (Note 5)
V
= 12V
115
1.7
180
2.2
ns
A
BST
DC = 15%
= 0.8A
1.2
0.9
Switch V
I
SW
280
–0.01
1.2
mV
ꢀA
A
CESAT
Switch Leakage Current (Note 8)
DA Current Limit
–1
1.6
2
l
Boost Schottky Reverse Leakage
Minimum BST Voltage above SW
BST Pin Current
V
BIAS
= 0V
0.01
2.15
15
ꢀA
V
2.5
25
I
SW
= 0.8A
mA
V
l
EN/UVLO Threshold Voltage
EN/UVLO Input Current
1.15
1.25
1.35
V
V
= 1.35V
= 1.15V
0.3
4
ꢀA
ꢀA
EN/UVLO
EN/UVLO
2.5
2.5
6
5.5
–4
Threshold Current Hysteresis
RUN/SS Pin Current
3.7
–2.8
0.8
ꢀA
ꢀA
V
V
= 0V
–1.4
0.15
0.4
RUN/SS
RUN/SS Switching Threshold
SYNC Threshold Voltage
Reset Threshold
1
0.8
1.3
92
V
l
l
l
l
V
UV
% of FB Voltage, V Falling
88
90
%
FB
t
t
t
t
Reset Timeout Period
C
POR
C
WDT
C
WDT
C
WDT
= 4700pF
= 1000pF
= 1000pF
= 1000pF
21.2
18
23.5
20
25.8
22
ms
ms
ms
ms
RST
Watchdog Window Upper Boundary
Watchdog Window Lower Boundary
Watchdog Timeout Period
RST Output Voltage Low
WDU
WDL
WDTO
0.8
1.25
2.5
1.6
l
l
I
I
= 2.5mA, V = 0.6V
= 100ꢀA, V = 0.6V
0.2
0.01
0.4
0.3
V
V
SINK
SINK
FB
FB
l
l
t
UV
UV Detect to RST Asserted
WDI Input Threshold
V
Set to 0.680V
4
10
0.95
–2
30
ꢀs
V
FB
0.4
1.3
WDI Input Pull-Up Current
WDI Input Pulse Width
WDE Threshold Voltage
WDE Input Pull-Down Current
WDO Output Voltage Low
ꢀA
ns
V
l
l
300
0.4
0.65
3.5
1
V
WDE
= 1.2V
ꢀA
l
l
I
I
= 2.5mA
= 100ꢀA
0.2
0.01
0.4
0.3
V
V
SINK
SINK
3688f
3
LT3688
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, unless otherwise noted. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
–1.5
–1.5
TYP
–2.5
–2.5
MAX
UNITS
ꢀA
ꢀA
V
RST Pull-Up Current (Note 6)
WDO Pull-Up Current (Note 6)
CONFIG Low Level Input Voltage
CONFIG High Level Input Voltage
CONFIG Pin Voltage When Open
l
l
0.2
1.4
V
0.64
V
l
l
Maximum CONFIG Input Current in Open
State
1
ꢀA
CONFIG Pin Bias Current
V
= 0V, V
20
ꢀA
CONFIG
IN
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: The LT3688 contains circuitry that extends the maximum duty
cycle if the BST voltage is 2V greater than the SW voltage. See the
Applications Information section for more details.
Note 5: Current limit is guaranteed by design and/or correlation to static
Note 2: Absolute Maximum Voltage at the V , CONFIG and EN/UVLO pins
test. Slope compensation reduces current limit at higher duty cycles.
IN
is 36V for continuous operation.
Note 6: The outputs of RST and WDO have a weak pull-up to V
of
BIAS
Note 3: The LT3688 is tested under pulsed load conditions such that
typically 2.5μA. However, external pull-up resistors may be used when
faster rise times are required or for V higher than V
T = T . The LT3688E is guaranteed to meet performance specifications
.
BIAS
J
A
OH
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3688I is guaranteed over the full –40°C to 125°C operating junction
temperature range. The LT3688H is guaranteed over the full –40°C to
150°C operating junction temperature range. High junction temperatures
degrade operating lifetimes. Operating lifetime is derated at junction
Note 7: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed the maximum operating junction temperature
when over-temperature protection is active. Continuous operation above
the specified maximum operating junction temperature may impair device
reliability.
Note 8: All currents into pins are positive; all voltages are referenced to
GND unless otherwise specified.
temperatures greater than 125°C. The junction temperature (T , in °C) is
J
calculated from the ambient temperature (T , in °C) and power dissipation
A
(PD, in Watts) according to the formula:
T = T + (PD θ ), where θ (in °C/W) is the package thermal
J
A
JA
JA
impedance.
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise noted.
Efficiency, VOUT = 5V
Efficiency, VOUT = 3.3V
Efficiency, VOUT = 1.8V
95
90
85
80
75
70
65
90
85
80
75
70
65
60
85
80
75
70
65
60
55
f
= 1MHz
= 12V
f
= 1MHz
= 12V
f
SW
V
IN
= 500kHz
= 12V
SW
IN
SW
IN
V
V
0
0.2
0.4
0.6
0.8
1
0
0.2
0.4
0.6
0.8
1
0
0.2
0.4
0.6
0.8
1
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
3688 G01
3688 G02
3688 G03
3688f
4
LT3688
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise noted.
No-Load Supply Current
(Temperature)
No-Load Supply Current (Input)
Maximum Load Current (5V)
160
140
120
100
80
3000
2500
2000
1500
1000
500
2
1.5
1
V
OUT2
= 5V
f
= 1MHz
OUT1
CATCH DIODE: B140HB
SW
V
= 3.3V
V
V
V
= 12V
IN
OUT1
OUT2
= 5V
= 3.3V
L = 15ꢀH
L = 10ꢀH
INCREASED SUPPLY
CURRENT DUE TO CATCH
DIODE LEAKAGE AT HIGH
TEMPERATURE
60
40
0.5
0
20
0
0
0
10
20
(V)
30
40
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
0
10
20
INPUT VOLTAGE (V)
30
40
V
IN
3688 G04
3688 G05
3688 G06
Switch Current Limit
vs Duty Cycle
Switch Current Limit
vs Temperature
Maximum Load Current (3.3V)
2
1.5
1
2.0
1.5
1.0
0.5
0
1.8
1.6
1.4
1.2
1
f
= 1MHz
SW
TYPICAL
L = 15ꢀH
L = 10ꢀH
MIN
0.8
0.6
0.4
0.2
0
0.5
0
DC = 15%
0
10
20
30
40
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
0
20
40
60
80
100
INPUT VOLTAGE (V)
DUTY CYCLE (%)
3688 G07
3688 G09
3688 G08
Switch Voltage Drop
BST Pin Current
Feedback Voltage
350
300
250
200
150
100
50
25
20
15
10
5
0.810
0.805
0.800
0.795
0.790
0
0
0
200
400
600
800
1000
0
200
400
600
800
1000
–50 –20
0
25 50 75 100 125 150
TEMPERATURE (°C)
SWITCH CURRENT (mA)
SWITCH CURRENT (mA)
3688 G10
3688 G11
3688 G12
3688f
5
LT3688
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise noted.
Switching Frequency
vs Temperature
Switching Frequency vs RT
Minimum Switch On-Time
2.5
2.0
1.5
1.0
0.5
0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
200
150
100
50
I
= 700mA
SW
R
= 49.9k
T
0
0
50
100
(kΩ)
150
200
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
–50 –20
0
25 50 75 100 125 150
TEMPERATURE (°C)
R
T
3688 G13
3688 G14
3688 G16
EN/UVLO Pin Current
EN/UVLO Pin Threshold
Boost Diode Forward Voltage
25
20
15
10
5
1.50
1.40
1.30
1.20
1.10
1.00
900
800
700
600
500
400
300
200
100
0
THRESHOLD FALLING
0
0
5
10 15 20 25 30 35 40
PIN VOLTAGE (V)
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
0
10
20
30
40
50
CURRENT (mA)
3688 G17
3688 G18
3688 G19
Switching Waveforms,
Transition from Burst Mode
to Full Frequency
Switching Waveforms,
Burst Mode Operation
Switching Waveforms, Full
Frequency Continuous Operation
I
I
I
L
L
L
0.2A/DIV
0.2A/DIV
0.2A/DIV
V
SW
V
V
SW
5V/DIV
SW
5V/DIV
5V/DIV
V
V
V
OUT
10mV/DIV
OUT
OUT
10mV/DIV
10mV/DIV
3688 G20
3688 G21
3688 G22
5ꢀs/DIV
5ꢀs/DIV
5ꢀs/DIV
V
LOAD
= 12V; FRONT PAGE APPLICATION
V
LOAD
= 12V; FRONT PAGE APPLICATION
V
LOAD
= 12V; FRONT PAGE APPLICATION
IN
IN
IN
I
= 7mA
I
= 40mA
I
= 160mA
3688f
6
LT3688
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise noted.
Power-On Reset Threshold
vs Temperature
Typical Transient Duration
vs Comparator Overdrive
Watchdog Window Mode Period
vs Temperature
700
600
500
400
300
200
100
0
0.730
0.725
0.720
0.715
0.710
25
20
15
10
5
C
= 1000pF
WDT
0
0.1
1
10
100
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
OVERDRIVE VOLTAGE (% of V
)
UV
3688 G24
3688 G23
3688 G26
Reset Timeout Period (tRST
vs Temperature
)
Reset Timeout Period (tRST
vs Capacitance
)
30
100000
10000
1000
100
25
20
15
10
5
C
= 4700pF
POR
10
1
0.1
0
0.01
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
0.001
0.1
10
(nF)
1000
100000
C
POR
3688 G27
3688 G28
Watchdog Window Upper
Boundary (tWDU) vs Capacitance
Watchdog Window Lower
Boundary (tWDL) vs Capacitance
100000
10000
1000
100
100000
10000
1000
100
10
10
1
1
0.1
0.1
0.01
0.001
0.1
10
(nF)
1000
100000
0.001
0.1
10
(nF)
1000
100000
C
C
WDT
WDT
3688 G30
3688 G29
3688f
7
LT3688
PIN FUNCTIONS (QFN/TSSOP)
RT (Pin 1/Pin 22): The RT pin is used to set the internal
oscillator frequency. Tie a resistor from RT to GND to set
the switching frequency.
CONFIG (Pin 10/Pin 7): The CONFIG pin programs the
start-up sequence of the two voltage regulators and the
behavior of the power-on reset and watchdog timers. To
selectoneofthreeconfigurationoptions,tietheCONFIGpin
SYNC (Pin 2/Pin 23): Drive the SYNC pin with a logic-
level signal with positive and negative pulse widths of at
least 150ns. Do not float this pin. Tie to GND if the SYNC
feature is not used.
to V , tie the CONFIG pin to GND or leave the CONFIG pin
IN
floating. With the CONFIG pin tied to V , each reset output
IN
dependsonitsrespectiveFBpin.Channel2onlystartswhen
FB1 rises above 0.72V, and the watchdog timer only starts
when both RST pins go high. With the CONFIG pin tied to
GND, both RST pins pull low until both FB pins rise above
EN/UVLO (Pin 3/Pin 24): The EN/UVLO pin is used to put
the LT3688 in shutdown mode. Pull the pin below 0.3V to
shut down the LT3688. The 1.25V threshold can function
as an accurate undervoltage lockout (UVLO), preventing
the regulator from operating until the input voltage has
reached the programmed level.
0.72V and the POR timer programmed by C
expires.
POR1
Again, channel 2 only starts when FB1 rises above 0.72V,
and the watchdog timer only starts when both RST pins go
high. Tie C
to GND if the CONFIG pin is tied low. With
POR2
theCONFIGpinfloating, bothchannelsstartcoincidentally,
each reset output depends on its respective FB pin, and the
watchdog timer starts when RST1 goes high.
FB1, FB2 (Pins 4, 15/Pins 1, 12): The LT3688 regulates
thefeedbackpinsto0.800V.Connectthefeedbackresistor
divider taps to this pin.
RST1, RST2 (Pins 17, 16/Pins 14, 13): The RST pins are
RUN/SS1, RUN/SS2 (Pins 5, 14/Pins 2, 11): Place a
capacitor from RUN/SS to GND to program the soft start
period. Use a 1000pF or larger capacitor at these pins. To
ensure the SS capacitors are discharged, internal circuitry
pulls the RUN/SS pins low and disables switching during
startup before initiating the soft-start sequence. Once
the RUN/SS pins fall below 0.2V, the pull down turns off,
the SS capacitors start charging again, and switching is
enabled. Do not drive these pins directly. Use an open
drain or collector to pull them low, if necessary.
active low, open-drain logic outputs with a weak pull-up to
BIAS.AfterV risesabove0.72V,theresetremainsasserted
FB
for the period set by the capacitor on the C
RSTpinstoBIASwitha100kresistorforastrongerpull-up.
pin. Tie the
POR
WDO (Pin 18/Pin 15): WDO will go low if the micropro-
cessor fails to drive the WDI pin of the LT3688 with the
appropriate signal. Tie the WDO pin to BIAS with a 100k
resistor for a stronger pull-up. Keep capacitive loading on
this pin below 1000pF.
BST1, BST2 (Pins 6, 13/Pins 3, 10): The BST pins are
used to provide drive voltage, higher than the input volt-
age, to the internal NPN power switches.
WDE (Pin 19/Pin 16): The watchdog timer enable pin
disables the watchdog timer if the WDE voltage exceeds
1V. Float this pin or tie to ground for normal operation.
SW1, SW2 (Pins 7, 12/Pins 4, 9): The SW pins are the
outputs of the internal power switches. Connect these
pins to the inductors, catch diodes and boost capacitors.
WDI (Pin 20/Pin 17): The watchdog timer input pin
receives the watchdog signal from the microprocessor.
If two or more negative edges occur on WDI before the
programmed fast timer period or no negative edge occurs
within the slow timer period, the part will pulse WDO low
with a pulse width of 1/8th of the slow timer period. Drive
the WDI pin with a pulse width of at least 300ns.
DA1, DA2 (Pins 8, 11/Pins 5, 8): Tie the DA pin to the
anode of the external catch Schottky diode. If the DA pin
current exceeds 1.2A, which could occur in an overload
or short-circuit condition, switching is disabled until the
DA pin current falls below 1.2A.
BIAS (Pin 22/Pin 19): The BIAS pin supplies current to the
internal circuitry when BIAS is above 3V, helping reduce
input quiescent current. The internal Schottky diodes are
connected from BIAS to BST, providing the charging path
for the boost capacitors.
V
(Pin 9/Pin 6): The V pin supplies current to the
IN
IN
LT3688’s internal circuitry and to the internal power
switches and must be locally bypassed.
3688f
8
LT3688
PIN FUNCTIONS (QFN/TSSOP)
C
, C
(Pins 23, 21/Pins 20, 18): Place a capacitor
Exposed Pad (Pin 25/Pin 25): Ground. Tie the exposed
pad directly to the ground plane. The exposed pad metal
of the package provides both electrical contact to ground
and good thermal contact to the printed circuit board. The
device must be soldered to the circuit board for proper
operation.
POR1 POR2
between this pin and ground to set the power-on-reset
timeout period.
C
(Pin 24/Pin 21): Place a capacitor between this pin
WDT
andgroundtosetthefastandslowwatchdogtimerperiods.
BLOCK DIAGRAM
V
IN
C1
R
T
OUT1
ON OFF
EN/UVLO
V
IN
SYNC RT
BIAS
–
+
–
+
INTERNAL
0.8V REF
SWITCH
LATCH
SWITCH
LATCH
SLOPE COMP
SLOPE COMP
BST1
SW1
DA1
BST2
SW2
DA2
R
R
C5
L2
C3
L1
SLAVE
OSCILLATOR
MASTER
SLAVE
OSCILLATOR
Q
Q
OUT1
OUT2
OSCILLATOR
S
S
DISABLE
C2
C4
Burst Mode
OPERATION
DETECT
Burst Mode
OPERATION
DETECT
ERROR
AMP
R
R
SEN2
SEN1
V
C
+
–
+
–
V
CLAMP
V CLAMP
C
C
+
+
R
C
C
C
R1
FB1
FB2
80mV
R2
–
–
+
RUN/SS1
RUN/SS2
+
–
–
+
+
2.5ꢀA
C
2.5ꢀA
22ꢀA
V
C
POR1
IN
POR2
3.4V
ADJUSTABLE
RESET PULSE
GENERATOR
ADJUSTABLE
RESET PULSE
GENERATOR
22ꢀA
CONFIGURATION
LOGIC
RST1
RST2
TRANSITION
DETECT
WATCHDOG
TIMER
THREE-STATE
DECODE
2ꢀA
22ꢀA
WDI
WDE
C
WDT
WDO
CONFIG
GND
3688 BD01
3688f
9
LT3688
OPERATION
The LT3688 is a constant-frequency, current mode step-
down regulator with two reset timers and a watchdog
timerthatperformmicroprocessorsupervisoryfunctions.
OperationcanbebestunderstoodbyreferringtotheBlock
Diagram. Keeping the EN/UVLO pin at ground completely
optimize efficiency, the LT3688 automatically switches to
Burst Mode operation in light load situations. Between
bursts, all circuitry associated with controlling the output
switch is shut down, reducing the input supply current to
115μA in a typical application.
shuts off the part drawing minimal current from the V
IN
A comparator monitors the current flowing through the
catchdiodeviatheDApin. Thiscomparatordelaysswitch-
ing if the diode current goes higher than 1.2A (typical)
during a fault condition such as a shorted output with high
input voltage. Switching will only resume once the diode
current has fallen below the 1.2A limit. This way the DA
comparator regulates the valley current of the inductor
to 1.2A during short circuit. This will ensure that the part
will survive a short-circuit event.
source. To turn on the internal bandgap and the rest of the
logic circuitry, raise the EN/UVLO pin above the accurate
threshold of 1.25V. Also, V needs to be higher than 3.5V
IN
for the part to start switching.
Switching Regulator Operation
An oscillator, with frequency set by R , enables an RS flip
T
flop, turning on the internal power switch. An amplifier
and comparator monitor the current flowing between the
V
and SW pins, turning the switch off when this cur-
Power-On Reset and Watchdog Timer Operation
IN
rent reaches a level determined by the voltage at V . An
C
The LT3688 has two power-on reset comparators that
error amplifier measures the output voltage through an
monitor the regulated output voltages. If V
is 10%
OUT
external resistor divider tied to the FB pin and servos the
below the regulation value, the RST pin is pulled low. Once
the output voltage crosses over 90% of the regulation
value, a reset timer is started and RST is released after
the programmed reset delay time. The reset delay is
V voltage. If the error amplifier’s output increases, more
C
current is delivered to the output; if it decreases, less
current is delivered. An active clamp on the V voltage
C
provides current limit. The V voltage is also controlled
C
programmable through the C
pin.
POR
by the internal soft-start circuit during start-up or after a
The watchdog typically monitors a microprocessor’s
activity. The watchdog can be enabled or disabled by ap-
plying a logic signal to the WDE pin. The watchdog timer
requires successive negative edges on the WDI pin to
come within a programmed time window to keep WDO
from going low. If the time between the two negative WDI
edges is too short or too long, then the WDO pin will be
pulled low. When the WDO pin goes low, it stays low for
a time period equivalent to 1/8th of the watchdog window
upper boundary. The WDO pin will go high again once the
timer expires or if the RST pin goes low. The watchdog
window upper and lower boundaries can be set through
fault condition takes place.
An internal regulator provides power to the control cir-
cuitry. The internal regulator normally draws current from
the V pin, but if the BIAS pin is connected to an external
IN
voltage higher than 3V, bias current will be drawn from the
external source (typically the regulated output voltage).
This improves efficiency. The BIAS pin also provides a
current path to the internal boost diode that charges up
theboostcapacitor. Theswitchdriveroperateseitherfrom
the V or from the BST pin. An external capacitor is used
IN
to generate a voltage at the BST pin that is higher than
the V supply. This allows the driver to fully saturate the
IN
the C
pin.
WDT
internalNPNpowerswitchforefficientoperation.Tofurther
3688f
10
LT3688
TIMING DIAGRAMS
Power-On Reset Timing
V
OUT
V
UV
t
t
RST
UV
RST
Watchdog Timing
t < t
WDL
t
WDTO
WDI
WDO
3686 TD01
t
t
WDU
WDTO
3688f
11
LT3688
TIMING DIAGRAMS
V
UV
V
OUT1
t
RST1
RST1
V
UV
V
OUT2
t
RST2
RST2
WDO
t
WDU
WDI
STARTUP TIMING (V
= HIGH)
CONFIG
V
UV
V
OUT1
V
UV
V
OUT2
t
RST1
RST1
RST2
WDO
t
WDU
WDI
STARTUP TIMING (V
= LOW)
CONFIG
V
UV
V
OUT1
t
RST1
RST1
V
UV
V
OUT2
t
RST2
RST2
WDO
t
WDU
WDI
STARTUP TIMING (V
= OPEN)
CONFIG
t
t
t
= PROGRAMMED RESET PERIOD (C
= PROGRAMMED RESET PERIOD (C
= WATCHDOG WINDOW UPPER BOUNDRY
= RESET THRESHOLD
)
)
RST1
RST2
WDU
POR1
POR2
V
UV
3688 TD
3688f
12
LT3688
APPLICATIONS INFORMATION
Setting the Output Voltage
where V is the typical input voltage, V
is the output
IN
OUT
voltage, V is the catch diode drop (~0.5V) and V is
F
SW
The output voltage is programmed with a resistor divider
betweentheoutputandtheFBpin.Choosethe1%resistors
according to:
the internal switch drop (~0.3V at maximum load). If the
LT3688 is programmed to operate at a frequency higher
than f
for a given input voltage, the LT3688 enters
SW(MAX)
V
0.8V
⎛
⎞
pulseskipmode,whereitskipsswitchingcyclestomaintain
regulation. Atfrequencieshigherthanf , theLT3688
OUT
R1= R2
– 1
⎜
⎝
⎟
⎠
SW(MAX)
no longer operates with constant frequency. The LT3688
For reference designators, refer to the Block Diagram.
enters pulse skip mode at frequencies higher than f
SW(MAX)
because of the limitation on the LT3688’s minimum on time
Setting the Switching Frequency
of140ns(180nsforT >125°C).Astheswitchingfrequency
J
The LT3688 uses a constant-frequency PWM architecture
thatcanbeprogrammedtoswitchfrom350kHzto2.2MHz
by using a resistor tied from the RT pin to ground. Table 1
is increased above f
, the part is required to switch
SW(MAX)
for shorter periods to maintain the same duty cycle. Delays
associated with turning off the power switch dictate the
minimum on-time of the part. When the required on-time
decreasesbelowtheminimumon-timeof140ns,theswitch
pulse width remains fixed at 140ns (instead of becoming
narrower) to accommodate the same duty cycle require-
ment. The inductor current ramps up to a value exceeding
the load current and the output ripple increases. The part
then remains off until the output voltage dips below the
programmed value before it begins switching again.
shows the R values for various switching frequencies
T
Table 1. Switching Frequency vs RT
RT
SWITCHING FREQUENCY (MHz)
(kΩ)
165
110
88.7
75
0.35
0.5
0.6
0.7
0.8
0.9
1
64.9
56.2
49.9
40.2
33.2
27.4
23.2
20
Maximum Operating Voltage Range
The maximum input voltage for LT3688 applications
depends on switching frequency, the absolute maximum
1.2
1.4
1.6
1.8
2.1
2.3
ratings of the V and BST pins, and by the minimum
IN
duty cycle (DC ). The LT3688 can operate from input
MIN
voltages up to 36V.
17.4
DC
= t
• f
MIN
ON(MIN) SW
Operating Frequency Tradeoffs
where t
is equal to 140ns and f is the switching
SW
ON(MIN)
Selection of the operating frequency is a tradeoff between
efficiency, component size and maximum input voltage.
The advantage of high frequency operation is that
smaller inductor and capacitor values may be used. The
disadvantages are lower efficiency, and narrower input
voltagerangeatconstant-frequency.Thehighestconstant-
frequency. Running at a lower switching frequency allows
a lower minimum duty cycle. The maximum input voltage
before pulse-skipping occurs depends on the output volt-
age and the minimum duty cycle:
VOUT + VF
DCMIN
Example: f = 2.1MHz, V
V
=
– VF + VSW
IN(PS)
switchingfrequency(f
)foragivenapplicationcan
SW(MAX)
be calculated as follows:
= 3.3V
OUT
VOUT + V
DC
= 140ns • 2.1MHz = 0.294
F
MIN
fSW(MAX)
=
tON(MIN) V + V – V
(
)
IN
F
SW
3.3V + 0.5V
V
IN(PS)
=
– 0.5V + 0.3V = 12.7V
0.294
3688f
13
LT3688
APPLICATIONS INFORMATION
The LT3688 will regulate the output voltage at input volt-
Unlike many fixed frequency regulators, the LT3688 can
extend its duty cycle by remaining on for multiple cycles.
The LT3688 will not switch off at the end of each clock
cycleifthereissufficientvoltageacrosstheboostcapacitor
(C3 in the Block Diagram). Eventually, the voltage on the
boost capacitor falls and requires refreshing. Circuitry
detects this condition and forces the switch to turn off,
allowing the inductor current to charge up the boost
capacitor. This places a limitation on the maximum duty
cycle as follows:
ages greater than V
. For example, an application
IN(PS)
with an output voltage of 3.3V and switching frequency
of 2.1MHz has a V of 12.7V, as shown in Figure 1.
IN(PS)
Figure 2 shows operation at 27V. Output ripple and peak
inductor current have significantly increased. A saturating
inductor may further reduce performance. In pulse skip
mode, the LT3688 skips switching pulses to maintain
output regulation. The LT3688 will also skip pulses at very
low load currents. V
vs load current is plotted in the
IN(PS)
Typical Performance section.
DC
= 90%
MAX
This leads to a minimum input voltage of:
V
OUT
50mV/DIV
(AC)
VOUT + VF
DCMAX
V
=
– VF + VSW
IN(MIN)
I
L
500mA/DIV
where V is the forward voltage drop of the catch diode
F
(~0.4V) and V is the voltage drop of the internal switch
SW
3688 F01
2ꢀs/DIV
(~0.3V at maximum load).
Figure 1. Operation Below Pulse-Skipping
Voltage. VOUT = 3.3V and fSW = 2.1MHz
Example: I =0.8A and V
= 3.3V
SW
OUT
3.3V + 0.4V
V
=
– 0.4 + 0.3V = 4V
IN(MIN)
90%
V
OUT
For best performance in dropout, use a 1ꢀF or larger
boost capacitor.
50mV/DIV
(AC)
I
L
500mA/DIV
Inductor Selection and Maximum Output Current
A good first choice for the inductor value is
1.8MHz
3688 F02
2ꢀs/DIV
L = V
+ V •
F
(
)
OUT
Figure 2. Operation Above VIN(ps). VIN = 27V,
VOUT = 3.3V and fSW = 2.1MHz. Output Ripple
and Peak Inductor Current Increase
fSW
where V is the voltage drop of the catch diode (~0.4V),
F
f
is in MHz, and L is in μH. The inductor’s RMS current
SW
rating must be greater than the maximum load current
and its saturation current should be at least 30% higher.
For robust operation in fault conditions (start-up or short-
circuit) and high input voltage (>30V), use an 8.2ꢀH or
greater inductor with a saturation rating of 2.2A, or higher.
For highest efficiency, the series resistance (DCR) should
be less than 0.1Ω. Table 2 lists several vendors and types
that are suitable.
Minimum Operating Voltage Range
The minimum input voltage is determined either by the
LT3688’s minimum operating voltage of ~3.6V or by its
maximum duty cycle. The duty cycle is the fraction of
time that the internal switch is on and is determined by
the input and output voltages:
VOUT + VF
DC =
V – V + VF
IN
SW
3688f
14
LT3688
APPLICATIONS INFORMATION
Table 2. Inductor Vendors
When the switch is off, the potential across the induc-
tor is the output voltage plus the catch diode drop. This
gives the peak-to-peak ripple current in the inductor
VENDOR
Murata
TDK
PART SERIES
TYPE
Open
URL
www.murata.com
LQH55D
SLF7045
SLF10145
Shielded
Shielded
www.component.tdk.com
1– DC V
)(
+ V
F
(
)
OUT
ΔIL =
L • f
Toko
DC62CB
D63CB
D75C
Shielded
Shielded
Shielded
Open
www.toko.com
wherefistheswitchingfrequencyoftheLT3688andListhe
valueoftheinductor.Thepeakinductorandswitchcurrentis
D75F
Sumida
CR54
CDRH74
CDRH6D38
CR75
Open
Shielded
Shielded
Open
www.sumida.com
ΔIL
2
ISW(PK) = IL(PK) = IOUT
+
To maintain output regulation, this peak current must be
The optimum inductor for a given application may differ
fromtheoneindicatedbythissimpledesignguide.Alarger
value inductor provides a higher maximum load current,
and reduces the output voltage ripple. If your load is lower
than the maximum load current, then you can relax the
valueoftheinductorandoperatewithhigherripplecurrent.
This allows you to use a physically smaller inductor, or
one with a lower DCR resulting in higher efficiency. Be
aware that if the inductance differs from the simple rule
above, then the maximum load current will depend on
input voltage. In addition, low inductance may result in
discontinuous mode operation, which further reduces
maximum load current. Discontinuous operation occurs
less than the LT3688’s switch current limit I . I is at
LIM LIM
least 1.25A for at low duty cycles and decreases linearly
to 0.9A at DC = 0.9. The maximum output current is a
function of the chosen inductor value:
ΔIL
2
IOUT(MAX) = ILIM
–
ΔIL
2
= 1.25A • 1– 0.3DC –
(
)
Choosing an inductor value so that the ripple current is
smallwillallowamaximumoutputcurrentneartheswitch
current limit.
when I
is less than ΔI / 2. For details of maximum
OUT
L
One approach to choosing the inductor is to start with the
simplerulegivenabove,lookattheavailableinductors,and
choose one to meet cost or space goals. Then use these
equations to check that the LT3688 will be able to deliver
therequiredoutputcurrent.Noteagainthattheseequations
assume that the inductor current is continuous.
output current and discontinuous mode operation, see
Linear Technology’s Application Note AN44. Finally, for
dutycyclesgreaterthan50%(V /V >0.5),aminimum
OUT IN
inductanceisrequiredtoavoidsub-harmonicoscillations:
1.2MHz
LMIN = V
+ V •
F
(
)
OUT
fSW
where V is the voltage drop of the catch diode (~0.4V),
Input Capacitor
F
Bypass the input of the LT3688 circuit with a ceramic
capacitor of an X7R or X5R type. Y5V types have poor
performance over temperature and applied voltage, and
should not be used. A 2.2μF to 4.7μF ceramic capacitor
is adequate to bypass the LT3688 and will easily handle
the ripple current. Note that larger input capacitance
is required when a lower switching frequency is used.
If the input power source has high impedance, or there
is significant inductance due to long wires or cables,
f
is in MHz, and L
is in μH.
SW
MIN
Thecurrentintheinductorisatrianglewavewithanaverage
value equal to the load current. The peak switch current
is equal to the output current plus half the peak-to-peak
inductor ripple current. The LT3688 limits its switch cur-
rentinordertoprotectitselfandthesystemfromoverload
faults. Therefore, the maximum output current that the
LT3688 will deliver depends on the switch current limit,
the inductor value, and the input and output voltages.
3688f
15
LT3688
APPLICATIONS INFORMATION
additional bulk capacitance may be necessary. This can be
provided with a lower performance electrolytic capacitor.
Step-down regulators draw current from the input supply
in pulses with very fast rise and fall times. The input
capacitor is required to reduce the resulting voltage ripple
at the LT3688 input and to force this very high frequency
switching current into a tight local loop, minimizing EMI.
A 2.2μF capacitor is capable of this task, but only if it is
placed close to the LT3688 and the catch diode (see the
PCB Layout section). A second precaution regarding the
ceramic input capacitor concerns the maximum input
voltage rating of the LT3688. A ceramic input capacitor
combined with trace or cable inductance forms a high
quality (under damped) tank circuit. If the LT3688 circuit
is plugged into a live supply, the input voltage can ring to
twice its nominal value, possibly exceeding the LT3688’s
voltage rating. See Linear Technology’s Application Note
88 for details.
High performance electrolytic capacitors can be used for
theoutputcapacitor. LowESRisimportant, sochooseone
that is intended for use in switching regulators. The ESR
should be specified by the supplier and should be 0.1Ω
or less. Such a capacitor will be larger than a ceramic
capacitor and will have a larger capacitance because the
capacitor must be large to achieve low ESR. Table 3 lists
several capacitor vendors.
Table 3. Capacitor Vendors
VENDOR
PART SERIES
COMMENTS
Panasonic
Ceramic
Polymer
Tantalum
EEEF Series
Kemet
Sanyo
Ceramic
Tantalum
T494, T495
POSCAP
Ceramic
Polymer
Tantalum
Murata
AVX
Ceramic
Ceramic
Tantalum
TPS Series
Output Capacitor and Output Ripple
Taiyo Yuden
Ceramic
The output capacitor has two essential functions. Along
withtheinductor,itfiltersthesquarewavegeneratedbythe
LT3688toproducetheDCoutput. Inthisroleitdetermines
the output ripple, and low impedance at the switching
frequency is important. The second function is to store
energy in order to satisfy transient loads and stabilize the
LT3688’s control loop. Ceramic capacitors have very low
equivalent series resistance (ESR) and provide the best
ripple performance. A good starting value is:
Catch Diode
The catch diode conducts current only during switch-off
time. Average forward current in normal operation can
be calculated from:
IOUT V – V
(
)
IN
OUT
ID(AVG)
where I
=
V
IN
is the output load current. The only reason to
50
VOUT • fSW
OUT
COUT
=
consider a diode with a larger current rating than neces-
sary for nominal operation is for the worst-case condition
of shorted output. The diode current will then increase to
the typical peak switch current limit. Peak reverse voltage
is equal to the regulator input voltage. Use a Schottky
diode with a reverse voltage rating greater than the input
voltage. Table 4 lists several Schottky diodes and their
manufacturers.
where f is in MHz and C
is the recommended output
OUT
SW
capacitance in μF. Use X5R or X7R types, which will
provide low output ripple and good transient response.
Transient performance can be improved with a high value
capacitor, but a phase lead capacitor across the feedback
resistor R1 may be required to get the full benefit (see the
Compensation section).
3688f
16
LT3688
APPLICATIONS INFORMATION
Table 4. Capacitor Vendors
With the recommended output capacitor, the loop cross-
VR
IAVE
(A)
VF at 1A
(mV)
overoccursabovetheR C zero.Thissimplemodelworks
C C
Part Number
On Semiconductor
MBR0520L
MBR0540
MBRM120E
MBRM140
Diodes Inc.
B0530W
(V)
well as long as the value of the inductor is not too high
and the loop crossover frequency is much lower than the
switchingfrequency.Withalargerceramiccapacitor(very
low ESR), crossover may be lower and a phase lead ca-
20
40
20
40
0.5
0.5
1
620
530
550
pacitor (C ) across the feedback divider may improve the
PL
1
phase margin and transient response. At minimum, use a
10pF phase lead capacitor to reduce noise injection to the
FB pin. If the output capacitor is different than the recom-
mended capacitor, stability should be checked across all
operatingconditions, includingloadcurrent, inputvoltage
and temperature. The LT1375 data sheet contains a more
thorough discussion of loop compensation and describes
how to test the stability using a transient load. Figure 4
shows the transient response when the load current is
stepped from 300mA to 600mA and back to 300mA.
30
20
30
40
40
0.5
1
B120
500
500
B130
1
B140HB
1
DFLS140
1.1
510
Ceramic Capacitors
Ceramic capacitors are small, robust and have very low
ESR. However, ceramic capacitors can cause problems
when used with the LT3688 due to their piezoelectric
nature. When in Burst Mode operation, the LT3688’s
switching frequency depends on the load current, and
at very light loads the LT3688 can excite the ceramic
capacitor at audio frequencies, generating audible noise.
Since the LT3688 operates at a lower current limit during
Burst Mode operation, the noise is typically very quiet. If
this is unacceptable, use a high performance tantalum or
electrolytic capacitor at the output.
LT3688
CURRENT MODE
POWER STAGE
–
0.7V
g
=
m
OUT
1.6A/V
+
C
R1
R2
PL
–
FB
g
=
V
m
C
300ꢀA/V
+
800mV
R
ESR
C
3M
ERROR
AMPLIFIER
80k
C1
+
C
C
C1
100pF
GND
TANTALUM OR CERAMIC
ELECTROLYTIC
3688 F03
Figure 3. Model for the Loop Response
Frequency Compensation
The LT3688 uses current mode control to regulate the
output, which simplifies loop compensation. In particular,
the LT3688 does not require the ESR of the output capaci-
tor for stability, allowing the use of ceramic capacitors to
achieve low output ripple and small circuit size. Figure 3
showsanequivalentcircuitfortheLT3688controlloop.The
errorampisatransconductanceamplifierwithfiniteoutput
impedance.Thepowersection,consistingofthemodulator,
power switch and inductor, is modeled as a transconduc-
tanceamplifiergeneratinganoutputcurrentproportionalto
V
OUT
100mV/DIV
I
LOAD
200mA/DIV
3688 F04
50ꢀs/DIV
Figure 4. Transient Load Response of the LT3688
Front Page Application as the Load Current is
Stepped from 300mA to 600mA
the voltage at the V node. Note that the output capacitor,
C
C1, integrates this current, and that the capacitor on the
V node (C ) integrates the error amplifier output current,
C
C
resulting in two poles in the loop. R provides a zero.
C
3688f
17
LT3688
APPLICATIONS INFORMATION
Low Ripple Burst Mode Operation
three ways to arrange the boost circuit. The BST pin must
be more than 2.3V above the SW pin for best efficiency.
For outputs of 3V and above, the standard circuit (Figure
6a) is best. For outputs between 2.8V and 3V, use a 1μF
boost capacitor. A 2.5V output presents a special case
because it is marginally adequate to support the boosted
drivestagewhileusingtheinternalboostdiode.Forreliable
BST pin operation with 2.5V outputs, use a good external
Schottky diode (such as the ON semi MBR0540), and a
1μF boost capacitor (see Figure 6b). For lower output
voltages, the boost diode can be tied to the input (Figure
6c), or to another supply greater than 2.8V. The circuit in
Figure 6a is more efficient because the BST pin current
and BIAS pin quiescent current comes from a lower volt-
To enhance efficiency at light loads, the LT3688 operates
in low ripple Burst Mode operation that keeps the output
capacitor charged to the proper voltage while minimizing
the input quiescent current. During Burst Mode opera-
tion, the LT3688 delivers single cycle bursts of current
to the output capacitor followed by sleep periods where
the output power is delivered to the load by the output
capacitor. Because the LT3688 delivers power to the
output with single, low current pulses, the output ripple
is kept below 25mV for a typical application. In addition,
V and BIAS quiescent currents are reduced to typically
IN
65μA and 155μA, respectively, during the sleep time. As
the load current decreases towards a no-load condition,
the percentage of time that the LT3688 operates in sleep
mode increases and the average input current is greatly
reduced, resultinginhighefficiencyevenatverylowloads
(see Figure 5). At higher output loads the LT3688 will be
V
OUT
BIAS
BST
V
V
IN
LT3688
IN
C3
SW
running at the frequency programmed by the R resistor,
T
GND
4.7ꢀF
and will be operating in standard PWM mode. The transi-
tion between PWM and low ripple Burst Mode operation
is seamless, and will not disturb the output voltage. The
front page application circuit will switch at full frequency
at output loads higher than about 60mA.
(6a) For V
> 2.8V
OUT
V
OUT
D2
BIAS
BST
I
L
V
V
IN
LT3688
IN
C3
0.2A/DIV
SW
V
SW
GND
4.7ꢀF
5V/DIV
V
OUT
10mV/DIV
(6b) For 2.5V < V
< 2.8V
OUT
3688 F05
5ꢀs/DIV
V
OUT
BIAS
BST
Figure 5. Burst Mode Operation
V
IN
V
LT3688
IN
C3
BST and BIAS Pin Considerations
SW
GND
4.7ꢀF
Capacitor C3 and the internal boost Schottky diodes (see
the Block Diagram) are used to generate boost voltages
that are higher than the input voltage. In most cases, a
0.22μF capacitor will work well. For the best performance
in dropout, use a 1ꢀF or larger capacitor. Figure 6 shows
3688 F06
(6c) For V
< 2.5V; V
= 30V
IN(MAX)
OUT
Figure 6. Three Circuits for Generating the Boost Voltage
3688f
18
LT3688
APPLICATIONS INFORMATION
age source. However, the full benefit of the BIAS pin is not
realized unless it is at least 3V. Ensure that the maximum
voltageratingsoftheBSTandBIASpinsarenotexceeded.
8
V
= 5V
OUT
7.5
TO START
7
6.5
The minimum operating voltage of an LT3688 application
is limited by the minimum input voltage (3.6V) and by the
maximum duty cycle, as outlined in a previous section. For
proper start-up, the minimum input voltage is also limited
by the boost circuit. If the input voltage is ramped slowly,
or the LT3688 is turned on with its EN/UVLO pin when the
outputisalreadyinregulation,thentheboostcapacitormay
notbefullycharged.Becausetheboostcapacitorischarged
with the energy stored in the inductor, the circuit will rely
on some minimum load current to get the boost circuit
running properly. This minimum load will depend on input
and output voltages, and on the arrangement of the boost
circuit. The minimum load generally goes to zero once the
circuit has started. Figure 7 shows a plot of minimum load
to start and to run as a function of input voltage. In many
cases, the discharged output capacitor will present a load
to the switcher, which will allow it to start. The plots show
6
TO RUN
5.5
5
4.5
4
1
10
100
1000
LOAD (mA)
3688 F07a
7.0
6.5
V
= 3.3V
OUT
6.0
5.5
TO START
5.0
4.5
4.0
3.5
TO RUN
10
the worst-case situation where V is ramping very slowly.
IN
For lower start-up voltage, the boost diode can be tied to
3.0
1
100
1000
V ;however, thisrestrictstheinputrangetoone-halfofthe
IN
LOAD (mA)
absolute maximum rating of the BST pin. At light loads, the
inductor current becomes discontinuous and the effective
dutycyclecanbeveryhigh.Thisreducestheminimuminput
3688 F07b
Figure 7. The Minimum Input Voltage Depends on
Output Voltage, Load Current and Boost Circuit
voltagetoapproximately300mVaboveV .Athigherload
OUT
currents, the inductor current is continuous and the duty
cycle is limited by the maximum duty cycle of the LT3688,
requiring a higher input voltage to maintain regulation.
regulator, pull the RUN/SS pin to ground with an open-
drain or collector. Note that if CONFIG is tied high or low
(not open), shutting down Channel 1 will also shut down
Channel 2 because of the sequencing function (See the
Configuration and Sequencing section for more details).
2.5ꢀA current sources pull up on each pin. If the RUN/SS
pin reaches ~0.2V, the channel will begin to switch
There is one particular issue to note if sequencing is
used. If the BIAS pin is tied to V
, it will be low during
OUT2
the startup of V
. This will prevent the boost circuit
OUT1
from working on V
until it has risen to 90% of its
OUT1
programmed value, increasing the required startup volt-
age. Using circuit in Figure 6b for V will reduce the
If a capacitor is tied from the RUN/SS pin to ground, then
theinternalpull-upcurrentwillgenerateavoltagerampon
OUT1
startup voltage to its normal value. An alternative is to tie
BIAS to V , if it is greater than 2.8V.
this pin. This voltage clamps the V pin, limiting the peak
C
OUT1
switch current and therefore input current during start up.
A good value for the soft-start capacitor is C /10,000,
OUT
Soft-Start and Individual Channel Shutdown
where C
is the value of the output capacitor.
OUT
The RUN/SS (Run/Soft-Start) pins are used to place the
individual switching regulators in shutdown mode. They
also provide a soft-start function. To shut down either
TheRUN/SSpinscanbeleftfloatingiftheSoft-Startfeature
is not used. They can also be tied together with a single
capacitorprovidingsoft-start.Theinternalcurrentsources
3688f
19
LT3688
APPLICATIONS INFORMATION
will charge these pins to ~2V. The RUN/SS pins provide
a soft-start function that limits peak input current to the
circuit during start-up. This helps to avoid drawing more
current than the input source can supply or glitching the
inputsupplywhentheLT3688isenabled.TheRUN/SSpins
do not provide an accurate delay to start or an accurately
controlledrampattheoutputvoltage,bothofwhichdepend
on the output capacitance and the load current.
comparator will force the part into shutdown below the
minimum V of 3.5V. This feature can be used to prevent
IN
excessive discharge of battery-operated systems. If an
adjustable UVLO threshold is required, the EN/UVLO pin
can be used. The threshold voltage of the EN/UVLO pin
comparatoris1.25V.Currenthysteresisisaddedabovethe
EN threshold. This can be used to set voltage hysteresis
of the UVLO using the following:
VH – VL
R3 =
Synchronization
3.7ꢀA
Synchronizing the LT3688 oscillator to an external fre-
quency can be done by connecting a square wave (with
positive and negative pulse width > 150ns) to the SYNC
pin. The square wave amplitude should have valleys that
are below 0.4V and peaks that are above 1.3V (up to 6V).
TheLT3688maybesynchronizedovera350kHzto2.5MHz
R3•1.25V
R4 =
VH – 1.25V – R3• 0.3ꢀA
Example:switchingshouldnotstartuntiltheinputisabove
4.40V, and is to stop if the input falls below 4V.
range. The R resistor should be chosen to set the LT3688
T
VH = 4.40V, V = 4V
L
switchingfrequency20%belowthelowestsynchronization
input. For example, if the synchronization signal will be
4.40V – 4V
R3 =
R4 =
= 107k
350kHz and higher, R should be chosen for 280kHz. To
T
3.7ꢀA
assure reliable and safe operation, the LT3688 will only
synchronize when the output voltage is above 90% of its
regulated voltage. It is therefore necessary to choose a
large enough inductor value to supply the required output
107k •1.25V
4.40V – 1.25V – 107k • 0.3ꢀA
= 43.2k
current at the frequency set by the R resistor (see the
T
LT3688
V
IN
V
C
Inductor Selection section). It is also important to note
–
1.25V
that the slope compensation is set by the R value. When
T
R3
the sync frequency is much higher than the one set by
EN/UVLO
+
R , the slope compensation will be significantly reduced,
T
RUN/SS
C1
R4
which may require a larger inductor value to prevent
subharmonic oscillation.
0.3ꢀA
3.7ꢀA
Shutdown and Undervoltage Lockout
Figure 8 shows how to add undervoltage lockout (UVLO)
to the LT3688. Typically, UVLO is used in situations where
the input supply is current limited, or has a relatively high
source resistance. A switching regulator draws constant
power from the source, so source current increases as
source voltage drops. This looks like a negative resistance
loadtothesourceandcancausethesourcetocurrentlimit
or latch low under low source voltage conditions.
3688 F08
Figure 8. Undervoltage Lockout
Keep the connection from the resistor to the EN/UVLO pin
short and make sure the interplane or surface capacitance
to switching nodes is minimized. If high resistor values
are used, the EN/UVLO pin should be bypassed with a
1nF capacitor to prevent coupling problems from the
UVLO prevents the regulator from operating at source
voltages where the problems might occur. An internal
switch node.
3688f
20
LT3688
APPLICATIONS INFORMATION
Output Voltage Monitoring
circuitry.Anytransientattheinputofthecomparatorneeds
to be of sufficient magnitude and duration (t ) before it
UV
The LT3688 provides power supply monitoring for
microprocessor-based systems. The features include
power-on reset (POR) and watchdog timing.
canchangethemonitorstate.Thecombinationofthereset
timeoutandanti-glitchcircuitrypreventsspuriouschanges
in output state without sacrificing threshold accuracy.
A precise internal voltage reference and glitch immune
precision POR comparator circuits monitor the LT3688
output voltages. Each channel’s output voltage must be
above 90% of the programmed value for RST not to be
asserted (refer to the Timing Diagram). The LT3688 will
assert RST during power-up, power-down and brownout
conditions. Once the output voltage rises above the RST
threshold, the adjustable reset timer is started and RST is
released after the reset timeout period. On power-down,
once the output voltage drops below RST threshold, RST
is held at a logic low. The reset timer is adjustable using
external capacitors. This capability helps hold the micro-
processor in a stable shutdown condition. The RST pin
has weak pull-up to the BIAS pin.
Watchdog Timer
The LT3688 includes an adjustable watchdog timer that
monitors a μP’s activity. If a code execution error occurs
in a μP, the watchdog will detect this error and will set the
WDO low. This signal can be used to interrupt a routine
or to reset a μP.
The watchdog circuitry is triggered by negative edges on
the WDI pin. The window mode restricts the WDI pin’s
negative going pulses to appear inside a programmed
time window (see the Timing Diagram) to prevent WDO
from going low. If more than two pulses are registered
in the window’s fast period, the WDO is forced to go low.
The WDO also goes low if no negative edge is supplied
to the WDI pin in the window’s slow timer period. During
a code execution error, the microprocessor will output
WDI pulses that would be either too fast or too slow. This
condition will assert WDO and force the microprocessor
to reset the program. In window mode, the WDI signal
frequency is bounded by an upper and lower limit for
normal operation. The WDI input frequency period should
be higher than the window mode’s fast period and lower
than the window mode’s slow period to keep WDO high
undernormalconditions.Thewindowmode’sfastandslow
times have a fixed ratio of 16 between them. These times
can be increased or decreased by adjusting an external
The above discussion is concerned only with the DC
value of the monitored supply. Real supplies also have
relatively high-frequency variation, from sources such as
loadtransients,noise,andpickup.Thesevariationsshould
not be considered by the monitor in determining whether
a supply voltage is valid or not. The variations may cause
spurious outputs at RST, particularly if the supply voltage
is near its trip threshold.
Twotechniquesareusedtocombatspuriousresetwithout
sacrificing threshold accuracy. First, the timeout period
helpspreventhigh-frequencyvariationwhosefrequencyis
above 1/ t
from appearing at the RST output. When the
RST
voltageatFBgoesbelowthethreshold,theRSTpinasserts
low.Whenthesupplyrecoverspastthethreshold,thereset
timerstarts(assumingitisnotdisabled),andRSTdoesnot
go high until it finishes. If the supply becomes invalid any
time during the timeout period, the timer resets and starts
fresh when the supply next becomes valid. While the reset
timeoutisusefulforpreventingtogglingoftheresetoutput
in most cases, it is not effective at preventing nuisance
resetsduetoshortglitches(duetoloadtransientsorother
effects) on a valid supply. To reduce sensitivity to these
short glitches, the comparator has additional anti-glitch
capacitor on the C
pin.
WDT
When WDO is asserted, a timer is enabled for a time
equivalent to 1/8th of the watchdog window upper
boundary. Any WDI pulses that appear while the reset
timer is running are ignored. When the timer expires, the
WDO is allowed to go high again. Therefore, if no input
is applied to the WDI pin, then the watchdog circuitry
produces a train of pulses on the WDO pin. The high
time of this pulse train is equal to the watchdog window
upper boundary, and low time is equal to the 1/8th of the
watchdog window upper boundary.
3688f
21
LT3688
APPLICATIONS INFORMATION
If WDO is low and RST goes low, then WDO will go
high. The WDE pin allows the user to turn on and off the
watchdog function. Leaving this pin open is okay and
will automatically enable the watchdog. It has an internal
weak pull-down to ground. The WDI pin has an internal
weak pull-up that keeps the WDI pin high. If watchdog is
disabled, leaving this pin open is acceptable.
V
V
(10V/DIV)
(10V/DIV)
RST1 (5V/DIV)
OUT1
OUT2
RST2 (5V/DIV)
WDO (5V/DIV)
WDI (10V/DIV)
3688 F09a
3688 F09b
3688 F09c
Configuration and Sequencing
10ms/DIV
Figure 9a. CONFIG = HIGH
Use the CONFIG pin to adjust the sequencing and the
behavior of the power-on reset and watchdog timers. The
table below shows all of the configuration options.
V
V
(10V/DIV)
(10V/DIV)
OUT1
OUT2
Table 5. Configuration Options
CONFIG
RST1 (5V/DIV)
RST2 (5V/DIV)
CONDITION
HIGH LOW OPEN
Channel 1 starts before Channel 2
Channel 1 and Channel 2 start simultaneously
Watchdog operates only if Reset 1 Expires
×
×
WDO (5V/DIV)
×
×
WDI (10V/DIV)
Watchdog operates only if Reset 1 and Reset
2 Expire
×
×
×
×
10ms/DIV
Figure 9b. CONFIG = LOW
RST1 and RST2 high only if Timer 1 Expires
RST1 and RST2 use independent timers
×
V
V
(10V/DIV)
(10V/DIV)
With the CONFIG pin tied high, V
will rise first, as
OUT1
OUT2
OUT1
reaches V , V
shown in Figure 9a. After V
will
OUT1
UV OUT2
RST1 (5V/DIV)
RST2 (5V/DIV)
start increasing. In addition, the reset timer for Channel 1
starts.OnceV reachesV ,theresettimerforChannel2
OUT2
UV
WDO (5V/DIV)
starts.OncetheresettimersforbothChannel1andChannel
2 have expired, the Watchdog will start operation.
WDI (10V/DIV)
With the CONFIG pin tied low, V
will rise first. After
OUT1
10ms/DIV
V
reaches V , V
will start increasing. The reset
OUT1
OUT1
UV OUT2
Figure 9c. CONFIG = OPEN
timerwillonlystartifbothV
andV
areaboveV ,
OUT2 UV
as shown in Figure 9b. Once the reset timer programmed
by C expires, both RST1 and RST2 can pull high,
Figure 9. Startup Waveforms with the
Three Configuration Settings
POR1
and the Watchdog will start operation. In this mode, tie
C
to GND.
POR2
Selecting the Reset Timing Capacitors
With the CONFIG pin open, V
and V
can rise
reaches
OUT1
OUT2
OUT1
The reset timeout period is adjustable in order to
accommodate a variety of microprocessor applications.
simultaneously,asshowninfigure9c.AfterV
V
the reset timer for Channel 1 starts. Once V
UV
OUT2
The reset timeout period, t , is adjusted by connecting
reaches V , the reset timer for Channel 2 starts. Once
RST
UV
a capacitor, C , between the C
value of this capacitor is determined by:
pin and ground. The
the reset timer for Channel 1 has expired, the Watchdog
POR
POR
will start operation.
3688f
22
LT3688
APPLICATIONS INFORMATION
Shorted and Reversed Input Protection
pF
ms
⎛
⎞
CPOR = tRST • 200
⎜
⎝
⎟
⎠
Ifaninductorischosentopreventexcessivesaturation,the
LT3688 will tolerate a shorted output. When operating in
short-circuitcondition,theLT3688willreduceitsfrequency
untilthevalleycurrentisatatypicalvalueof1.2A(seeFigure
12).Thereisanothersituationtoconsiderinsystemswhere
the output will be held high when the input to the LT3688 is
absent. This may occur in battery charging applications or
in battery backup systems where a battery or some other
Thisequationisaccurateforresettimeoutperiodsof1ms,
or greater. To program faster timeout periods, see the
Reset Timeout Period vs Capacitance graph in the Typical
Characteristicssection.LeavingtheC
pinunconnected
POR
will generate a minimum reset timeout of approximately
65μs. Maximum reset timeout is limited by the largest
available low leakage capacitor. The accuracy of the
timeout period will be affected by capacitor leakage (the
nominal charging current is 2.5μA), capacitor tolerance
and temperature coefficient. A low leakage, low tempco,
capacitor is recommended.
supply is diode ORed with the LT3688’s output. If the V
IN
pin is allowed to float and the EN/UVLO pin is held high
(either by a logic signal or because it is tied to V ), then
IN
theLT3688’sinternalcircuitrywillpullitsquiescentcurrent
through its SW pin. This is fine if the system can tolerate a
few mA in this state. If the EN/UVLO pin is grounded, the
SW pin current will drop to essentially zero.
Selecting the Watchdog Timing Capacitor
The watchdog timeout period is adjustable and can be
optimized for software execution. The watchdog window
However, if the V pin is grounded while the output is
IN
held high, then parasitic diodes inside the LT3688 can
upperboundary,t
WDT
isadjustedbyconnectingacapacitor,
WDU
, betweentheC
pull large currents from the output through the SW pin
C
pinandground. Givenaspecified
WDT
and the V pin. Figure 13 shows a circuit that will run
IN
watchdog timeout period, the capacitor is determined by:
only when the input voltage is present and that protects
pF
ms
⎛
⎞
against a shorted or reversed input.
CWDT = tWDU • 50
⎜
⎝
⎟
⎠
The window lower boundary (t
) and the watchdog
WDL
V
SW
10V/DIV
timeout (t
) have a fixed relationship to t
for a
WDTO
WDU
given capacitor. The window lower boundary is related to
t
by the following:
1
WDU
I
L
500mA/DIV
tWDL
=
• tWDU
16
3688 F12
5ꢀs/DIV
The watchdog timeout is related to t
by the following:
WDU
1
tWDTO = •tWDU
Figure 12. The LT3688 Reduces Its Frequency to Below
70kHz to Protect Against Shorted Output with 36V Input
8
Leaving the C
pin unconnected will generate a minimum
WDT
watchdog window upper boundary of approximately 200μs.
Maximum window upper boundary is limited by the largest
available low leakage capacitor. The timing accuracy of the
reset and watchdog signals depends on the initial accuracy
and stability of the programing capacitors. Use capacitors
withspecifiedaccuracy,leakageandvoltageandtemperature
coefficients. For surface mount ceramic capacitors C0G and
NP0 types are superior to alternatives such as X5R and X7R.
PCB Layout
ForproperoperationandminimumEMI,caremustbetaken
during printed circuit board layout. Figure 14 shows the
recommended component placement with trace, ground
plane and via locations. Note that large, switched currents
flow in the LT3688’s V , DA and SW pins, the catch diode
(D1) and the input capacitor (C1). The loop formed by
IN
3688f
23
LT3688
APPLICATIONS INFORMATION
keep thermal resistance low, extend the ground plane as
much as possible, and add thermal vias under and near
the LT3688 to additional ground planes within the circuit
board and on the bottom side.
D4
BIAS
V
V
BOOST
IN
IN
LTC3688
V
SW
OUT
DA
FB
+
High Temperature Considerations
EN/UVLO
GND
The PCB must provide heat sinking to keep the LT3688
cool. The exposed pad on the bottom of the package must
be soldered to a ground plane. This ground should be tied
to large copper layers below with thermal vias; these lay-
ers will spread the heat dissipated by the LT3688. Placing
additional vias can reduce thermal resistance further. With
these steps, the thermal resistance from die (or junction)
3688 F13
Figure 13. Diode D4 Prevents a Shorted Input from Discharging
a Backup Battery Tied to the Output; It Also Protects the Circuit
from a Reversed Input. The LT3688 Runs Only When the Input
Is Present
to ambient can be reduced to θ = 40°C/W or less. With
JA
100 LFPM airflow, this resistance can fall by another 25%.
Further increases in airflow will lead to lower thermal re-
sistance. Because of the large output current capability of
the LT3688, it is possible to dissipate enough heat to raise
the junction temperature beyond the absolute maximum
of 125°C (150°C for H Grade). When operating at high
ambient temperatures, the maximum load current should
be derated as the ambient temperature approaches 125°C
(150°C for H Grade). Power dissipation within the LT3688
can be estimated by calculating the total power loss from
anefficiencymeasurementandsubtractingthecatchdiode
loss. The die temperature is calculated by multiplying the
LT3688 power dissipation by the thermal resistance from
junction-to-ambient. Thermal resistance depends on the
layout of the circuit board, but values from 30°C/W to
60°C/W are typical. Die temperature rise was measured
on a 4-layer, 5cm • 7.5cm circuit board in still air at a load
current of 0.8A (f = 800kHz). For a 12V input to 3.3V
3688 F14
SW
output the die temperature elevation above ambient was
Figure 14. Top Layer PCB Layout in the LT3688
Demonstration Board
14°C; for 12V to 5V
the rise was 15°C and for 12V
IN
OUT
IN
to 5V
and 3.3V
the rise was 30°C.
OUT
OUT
these components should be as small as possible. These
components,alongwiththeinductorandoutputcapacitor,
should be placed on the same side of the circuit board.
Other Linear Technology Publications
Application Notes 19, 35 and 44 contain more detailed
descriptions and design information for buck regulators
and other switching regulators. The LT1376 data sheet
has a more extensive discussion of output ripple, loop
compensation and stability testing. Design Note 318
shows how to generate a bipolar output supply using a
buck regulator.
Place a local, unbroken ground plane below these com-
ponents. The SW and BST nodes should be as small as
possible.Finally,keeptheFBnodesmallsothattheground
traces will shield them from the SW and BST nodes.
The exposed pad on the bottom of the package must be
soldered to ground so that the pad acts as a heat sink. To
3688f
24
LT3688
TYPICAL APPLICATIONS
V
IN
6V TO 36V
C1
4.7ꢀF
V
IN
EN/UVLO
BST1
BIAS
BST2
ON OFF
L2
12ꢀH
L1
18ꢀH
C2
0.22ꢀF
C3
0.22ꢀF
V
V
OUT1
5V
OUT2
3.3V
SW1
SW2
800mA
800mA
C6
R1
R3
C7
10pF
LT3688
D1
D2
10pF 523k
316k
DA1
FB1
DA2
FB2
C8
1nF
C9
1nF
C4
22ꢀF
C5
22ꢀF
R4
100k
R2
100k
CONFIG
RUN/SS2
RUN/SS1
C
WDT
WDE
C
C
POR1
ꢀP
C10
4.7nF
I/O
I/O
WDI
POR2
RT
WDO
RST1
RST2
RESET
C12
1nF
C11
4.7nF
SYNC
GND
R5
110k
C1-C5: X5R OR X7R
D1, D2: DIODES INC. B140
3688 TA02
f
= 500kHz
SW
5V and 3.3V Regulator with Power-On Reset and Watchdog Timers
V
IN
8V TO 36V
C1
4.7ꢀF
R6
475k
V
CONFIG
IN
EN/UVLO
BIAS
BST2
R7
100k
BST1
L2
12ꢀH
L1
10ꢀH
C2
0.22ꢀF
C3
0.22ꢀF
V
V
OUT
OUT2
1.8V
3.3V
SW1
SW2
800mA
800mA
C6
10pF
C7
10pF
LT3688
R1
D1
D2
R3
187k
316k
DA1
FB1
DA2
FB2
C8
1nF
C9
1nF
C4
47ꢀF
C5
22ꢀF
R4
100k
R2
150k
RUN/SS2
RUN/SS1
C
WDT
WDE
C
C
POR1
ꢀP
C10
4.7nF
I/O
I/O
WDI
POR2
RT
WDO
RST1
RST2
RESET
C12
1nF
C11
4.7nF
SYNC
GND
R5
110k
C1-C5: X5R OR X7R
D1, D2: DIODES INC. B140
3688 TA02
f
= 500kHz
SW
3.3V and 1.8V Regulator with Power-On Reset and Watchdog Timers
and Input Under Voltage Lockout
3688f
25
LT3688
TYPICAL APPLICATIONS
V
IN
6V TO 36V
C1
4.7ꢀF
V
IN
EN/UVLO
BST1
BIAS
BST2
ON OFF
L1
8.2ꢀH
L2
8.2ꢀH
C2
0.1ꢀF
C3
0.1ꢀF
V
V
OUT1
5V
OUT2
3.3V
SW1
SW2
800mA
800mA
C6
10ꢀF
LT3688
R3
C7
10pF
R1
D1
D2
316k
523k
DA1
FB1
DA2
FB2
C8
1nF
C9
1nF
C4
10ꢀF
C5
22ꢀF
R4
100k
R2
100k
CONFIG
RUN/SS1
WDE
RUN/SS2
C
WDT
C
C
POR1
ꢀP
C10
4.7nF
I/O
I/O
WDI
POR2
RT
WDO
RST1
RST2
RESET
C12
1nF
C11
4.7nF
SYNC
GND
R5
20k
C1-C5: X5R OR X7R
D1, D2: DIODES INC. B140
3688 TA04
f
= 2MHz: 8V < V < 16V, T < 85°C
IN J
SW
2MHz Switching Frequency, 5V and 3.3V Regulator with
Power-On Reset and Watchdog Timers
V
IN
4V TO 36V
C1
4.7ꢀF
V
IN
EN/UVLO
BST1
BIAS
BST2
ON OFF
L2
15ꢀH
L1
8.2ꢀH
C2
0.22ꢀF
C3
0.22ꢀF
V
V
OUT1
1.2V
OUT2
3.3V
SW1
SW2
800mA
800mA
LT3688
R3
R1
D1
D2
C6
10pF
C7
10pF
316k
90.9k
DA1
FB1
DA2
FB2
C8
1nF
C9
1nF
C4
100ꢀF
C5
22ꢀF
R4
100k
R2
182k
CONFIG
RUN/SS1
WDE
RUN/SS2
C
WDT
WATCHDOG DEFEAT
C
C
POR1
ꢀP
C10
4.7nF
WDI
POR2
RT
I/O
WDO
RST1
RST2
C12
1nF
C11
4.7nF
RESET
SYNC
GND
R5
143k
C1-C5: X5R OR X7R
D1, D2: DIODES INC. B140
3688 TA05
f
= 400kHz: V < 25V
IN
SW
3.3V and 1.2V Regulator with Power-On Reset Timer and
Defeatable Watchdog, Timing Error Resets Microprocessor
3688f
26
LT3688
PACKAGE DESCRIPTION
FE Package
24-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1771 Rev Ø)
Variation AA
7.70 – 7.90*
3.25
(.128)
(.303 – .311)
3.25
(.128)
24 23 22 21 20 19 18 17 16 15 14 13
6.60 p0.10
4.50 p0.10
2.74
(.108)
6.40
(.252)
BSC
2.74
(.108)
SEE NOTE 4
0.45 p0.05
1.05 p0.10
0.65 BSC
5
7
8
1
2
3
4
6
9 10 11 12
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0o – 8o
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE24 (AA) TSSOP 0208 REV Ø
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
R = 0.115
TYP
0.75 0.05
4.00 0.10
(4 SIDES)
23 24
0.70 0.05
PIN 1
TOP MARK
(NOTE 6)
0.40 0.10
1
2
4.50 0.05
3.10 0.05
2.45 0.05
(4 SIDES)
2.45 0.10
(4-SIDES)
PACKAGE
OUTLINE
(UF24) QFN 0105
0.25 0.05
0.50 BSC
0.200 REF
0.25 0.05
0.50 BSC
0.00 – 0.05
NOTE:
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3688f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LT3688
TYPICAL APPLICATION
V
IN
6V TO 36V
C1
4.7ꢀF
V
IN
EN/UVLO
BST1
BIAS
BST2
ON OFF
L2
12ꢀH
L1
18ꢀH
C2
0.22ꢀF
C3
0.22ꢀF
V
V
OUT1
5V
OUT2
3.3V
SW1
SW2
800mA
800mA
C6
R1
R3
C7
10pF
LT3688
D1
D2
10pF 523k
340k
DA1
FB1
DA2
FB2
C8
1nF
C9
1nF
C4
22ꢀF
C5
22ꢀF
R4
100k
R2
100k
CONFIG
RUN/SS1
WDE
RUN/SS2
C
WDT
C
C
POR1
ꢀP
C10
4.7nF
I/O
I/O
WDI
POR2
RT
WDO
RST1
RST2
RESET
C12
1nF
C11
4.7nF
SYNC
GND
R5
49.9k
C1-C5: X5R OR X7R
D1, D2: DFLS140
3688 TA06
f
= 1MHz: 7V < V < 21V
IN
SW
1MHz 5V and 3.3V Regulator with Power-On Reset and Watchdog Timers
RELATED PARTS
PART NUMBER
DESCRIPTION
35V, 55V MAX, Dual (1.3A, 1.1A), 2.5MHz High Efficiency Step-
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COMMENTS
Min = 4V, V Max = 35V, Transient to 55V, V
LT3640
V
IN
= 0.6V,
OUT(MIN)
IN
I = <290ꢀA, I = <1ꢀA, 4mm × 5mm QFN-28 TSSOP-28E Package
Q
SD
LT3689/LT3689–5 36V, 60V Transient Protection, 800mA, 2.2MHz High Efficiency
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V
Min = 3.6V, V Max = 36V, Transient to 60V, V = 0.8V,
OUT(MIN)
IN
IN
I = 75ꢀA, I = <1ꢀA, 3mm × 3mm QFN-16 Package
Q
SD
LT3686
LT3682
LT3971
LT3991
LT3970
LT3990
37V, 55Vmax, 1.2A, 2.5MHz High Efficiency Step-Down DC/DC
Converter
V
Min = 3.6V, V Max = 37V, Transient to 55V, V = 1.21V,
OUT(MIN)
IN
IN
I = 1.1mA, I = <1ꢀA, 3mm × 3mm DFN-10 Package
Q
SD
36V, 60Vmax, 1A, 2.2MHz High Efficiency Micropower Step-
Down DC/DC Converter
V
Min = 3.6V, V Max = 36V, V
= 0.8V,
IN
IN
OUT(MIN)
I = 75ꢀA, I = <1ꢀA, 3mm × 3mm DFN-12 Package
Q
SD
38V, 1.2A (I ), 2MHz, High Efficiency Step-Down DC/DC
V
Min = 4.2V, V Max = 38V, V
= 1.2V,
OUT
IN
IN
OUT(MIN)
Converter with only 2.8uA of Quiescent Current
I = 2.8ꢀA, I = <1ꢀA, 3mm × 3mm DFN-10, MSOP-10E Package
Q
SD
55V, 1.2A (I ), 2MHz, High Efficiency Step-Down DC/DC
V
Min = 4.2V, V Max = 55V, V
= 1.2V,
OUT
IN
IN
OUT(MIN)
Converter with only 2.8uA of Quiescent Current
I = 2.8ꢀA, I = <1ꢀA, 3mm × 3mm DFN-10, MSOP-10E Package
Q
SD
40V, 350mA (I ), 2MHz, High Efficiency Step-Down DC/DC
V
Min = 4.2V, V Max = 40V, V
= 1.2V,
OUT
IN
IN
OUT(MIN)
Converter with only 2.5uA of Quiescent Current
I = 2.5ꢀA, I = <1ꢀA, 2mm × 3mm DFN-10, MSOP-10E Package
Q
SD
60V, 350mA (I ), 2MHz, High Efficiency Step-Down DC/DC
V
Min = 4.2V, V Max = 60V, V
= 1.2V,
OUT
IN
IN
OUT(MIN)
Converter with only 2.5uA of Quiescent Current
I = 2.5ꢀA, I = <1ꢀA, 3mm × 3mm DFN-10, MSOP-16E Package
Q
SD
3688f
LT 0111 • PRINTED IN USA
28 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
© LINEAR TECHNOLOGY CORPORATION 2011
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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