LT3689EMSE-PBF [Linear]
700mA Step-Down Regulator with Power-On Reset and Watchdog Timer; 700毫安降压型稳压器具有上电复位和看门狗定时器
| 型号： | LT3689EMSE-PBF |
| 厂家： | 
Linear |
| 描述： | 700mA Step-Down Regulator with Power-On Reset and Watchdog Timer |
| 文件： | 总32页 (文件大小：388K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3689/LT3689-5
700mA Step-Down
Regulator with Power-On Reset
and Watchdog Timer
FEATURES
DESCRIPTION
TheLT®3689isanadjustablefrequency(350kHzto2.2MHz)
monolithicstep-downswitchingregulatorwithapower-on
reset and watchdog timer. The regulator operates from
inputs up to 36V and withstands transients up to 60V. Low
ripple Burst Mode® operation maintains high efficiency at
lowoutputcurrentwhilekeepingoutputripplebelow15mV
in a typical application, with input quiescent current of just
85μA. Shutdown circuitry reduces input supply current to
less than 1μA while EN/UVLO is pulled low. Using a resis-
tor divider on the EN/UVLO pin provides a programmable
undervoltage lockout. Current limit, frequency foldback
and thermal shutdown provide fault protection.
n
Wide Input Range:
Operation from 3.6V to 36V
Overvoltage Lockout Protects Circuits through
60V Transients
n
85μA I at 12V to 3.3V
Q
IN
OUT
Low Ripple Burst Mode® Operation Allows Output
n
Ripple <15mV
P-P
n
Programmable, Defeatable Watchdog Timer with
Window or Timeout Control
n
n
Programmable Power-On Reset Timer (POR)
Synchronizable, Adjustable 350kHz to 2.2MHz
Switching Frequency
700mA Output Switching Regulator with Internal
Power Switch
n
The reset and watchdog timeout periods are indepen-
dentlyadjustableusingexternalcapacitors.Tightaccuracy
specifications and glitch immunity ensure reliable reset
operation of a system without false triggering. The open
collector RST will pull down if output voltage drops 10%
below the programmed value. The watchdog timer is
pin-selectable for window or timeout modes. In timeout
mode, WDO pulls low if too long of a period passes before
a watchdog transition is detected. In window mode, the
LT3689 monitors for WDI falling edges grouped too close
together or too far apart.
n
n
n
Fixed 5V or Adjustable Output Voltage
800mV Feedback Voltage
Programmable Input Undervoltage Lockout with
Hysteresis
16-Pin 3mm × 3mm QFN and 16-Pin MSOP Packages
n
APPLICATIONS
n
Automotive Electronic Control Units
Industrial Power Supplies
n
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks of
Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Efficiency
3.3V Regulator with Power-On Reset Timer and Watchdog Timer
90
80
70
60
50
40
30
20
10
0
1000
100
10
V
V
= 12V
IN
OUT
V
IN
= 3.3V
4.5V TO 36V
f = 700kHz
L = 12μH
2.2μF
V
EN/UVLO
LT3689
TRANSIENT TO 60V
OUT
BST
IN
T
= 25°C
A
0.1μF
12μH
10pF
μP
3.3V
I/O
WDI
WDO
RST
SW
700mA
I/O
RESET
DA
FB
316k
C
C
WDT
POR
C
WDT
RT
10nF
= 182ms
= 5.9ms
22μF
C
GND
SYNC
POR
t
20.5k 100k
WDU
WDL
68nF
t
f
= 700kHz
t
= 157ms
SW
RST
1
3689 TA01
0.0001
0.001
0.01
0.1
1
LOAD CURRENT (A)
3689 TA01b
3689fa
1
LT3689/LT3689-5
ABSOLUTE MAXIMUM RATINGS (Note 1)
V , EN/UVLO Voltage (Note 2).................................60V
Operating Junction Temperature Range (Note 3)
LT3689E............................................. –40°C to 125°C
LT3689I.............................................. –40°C to 125°C
LT3689H ............................................ –40°C to 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
IN
BST Voltage ..............................................................60V
BST Above SW Voltage.............................................30V
OUT, WDE Voltage.....................................................30V
FB, RT, SYNC, W/T, WDI, RST, WDO Voltage...............6V
C
, C
WDT POR
Voltage.....................................................3V
MSOP ............................................................... 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
16 15 14 13
1
2
3
4
5
6
7
8
WDO
16 RST
15 WDI
14 W/T
13 WDE
12 FB
BST
1
2
3
4
12
C
WDT
C
WDT
V
IN
11 WDO
C
POR
RT
17
17
SW
DA
RST
10
9
SYNC
OUT
BST
11 EN/UVLO
10 DA
WDI
5
6
7
8
V
9
SW
IN
MSE PACKAGE
16-LEAD PLASTIC MSOP
θ
= 43°C/W, θ = 4.3°C/W
JC
JA
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
UD PACKAGE
16-LEAD (3mm s 3mm) PLASTIC QFN
= 68°C/W, θ = 4.2°C/W
θ
JA
JC
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LT3689EMSE#PBF
LT3689IMSE#PBF
LT3689HMSE#PBF
LT3689EMSE-5#PBF
LT3689IMSE-5#PBF
LT3689HMSE-5#PBF
LT3689EUD#PBF
TAPE AND REEL
PART MARKING*
3689
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3689EMSE#TRPBF
LT3689IMSE#TRPBF
LT3689HMSE#TRPBF
LT3689EMSE-5#TRPBF
LT3689IMSE-5#TRPBF
LT3689HMSE-5#TRPBF
LT3689EUD#TRPBF
LT3689IUD#TRPBF
16-Lead Plastic MSOP with Exposed Pad –40°C to 125°C
16-Lead Plastic MSOP with Exposed Pad –40°C to 125°C
16-Lead Plastic MSOP with Exposed Pad –40°C to 150°C
16-Lead Plastic MSOP with Exposed Pad –40°C to 125°C
16-Lead Plastic MSOP with Exposed Pad –40°C to 125°C
16-Lead Plastic MSOP with Exposed Pad –40°C to 150°C
3689
3689
36895
36895
36895
LDND
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
16-Lead (3mm × 3mm) Plastic QFN
16-Lead (3mm × 3mm) Plastic QFN
16-Lead (3mm × 3mm) Plastic QFN
16-Lead (3mm × 3mm) Plastic QFN
LT3689IUD#PBF
LDND
LT3689EUD-5#PBF
LT3689IUD-5#PBF
LT3689EUD-5#TRPBF
LT3689IUD-5#TRPBF
LFFM
LFFM
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3689fa
2
LT3689/LT3689-5
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VOUT = 5V, unless otherwise noted. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
3.4
38
MAX
3.7
UNITS
l
l
V
V
Fixed Undervoltage Lockout
Overvoltage Lockout
V
V
IN
IN
36
40
Quiescent Current from V
V
V
V
= 0.3V
EN/UVLO
OUT
OUT
0.01
50
0.5
95
μA
μA
μA
IN
l
l
l
= 3V, Not Switching
= 0V, Not Switching
125
175
Quiescent Current from OUT
V
V
V
= 0.3V
0.01
75
–5
0.5
150
–20
μA
μA
μA
EN/UVLO
= 3V, Not Switching (Note 7)
= 0V, Not Switching
OUT
OUT
LT3689-5 Quiescent Current from V
V
V
V
= 0.3V
0.01
50
125
0.5
95
175
μA
μA
μA
IN
EN/UVLO
= 5.5V (Note 8)
= 0V
OUT
OUT
LT3689-5 Quiescent Current from OUT
LT3689 FB Voltage
V
V
= 0.3V
8
16
μA
μA
EN/UVLO
OUT
l
l
= 5.5V
95
150
0.790
0.780
0.800
5.000
0.812
0.812
V
V
LT3689-5 Output Voltage
4.950
4.900
5.050
5.100
V
V
l
l
LT3689 FB Pin Bias Current
V
FB
= 0.800V
–30
–100
nA
%/V
%/V
LT3689 FB Voltage Line Regulation
LT3689-5 Output Voltage Line Regulation
Switching Frequency
5V < V < 36V
0.005
0.005
IN
5.5V < V < 36V
IN
l
l
f
t
R = 4.02k
R = 31.62k
1.84
420
2
500
2.16
540
MHz
kHz
SW
T
T
Switch Off-Time
V
= 12V
120
250
1.55
450
0.01
1.2
160
ns
kHz
A
SW(OFF)
BST
Foldback Frequency
R = 4.22k, V
= 0V
= 0V
T
OUT
l
Switch Current Limit (Note 4)
1.15
0.85
1.95
Switch V
I
= 0.8A
SW
mV
μA
A
CESAT
Switch Leakage Current
DA Current Limit
1
1.5
5
Boost Schottky Reverse Leakage
Minimum BST Above SW Voltage
BST Pin Current
V
BST
= 12V, V
0.1
μA
V
OUT
1.8
2.5
25
I
SW
= 0.8A
15
mA
V
EN/UVLO Threshold Voltage
EN/UVLO Pin Current
1.150
1.260
1.350
V
V
= 1.35V
= 1.15V
0. 01
4.1
1
5.5
μA
μA
EN/UVLO
EN/UVLO
2.5
2.8
0.4
88
EN/UVLO Pin Current Hysteresis
SYNC Threshold Voltage
I(V
= 1.35V) – I(V
= 1.15V)
3.8
0.8
90
4.8
1
μA
V
EN/UVLO
EN/UVLO
l
l
l
l
V
Reset Threshold as % of V
Reset Timeout Period
92
21
21
785
%
RST
FB
t
t
t
C
POR
C
WDT
C
WDT
= 8200pF
17
19
ms
ms
μs
RST
Watchdog Upper Boundary
Watchdog Lower Boundary
RST, WDO Output Voltage Low
= 1000pF
= 1000pF
17
19
WDU
WDL
610
675
l
l
V
I
I
= 2.5mA, V
= 100μA, V
= 0V
= 0V
0.15
0.05
0.4
0.3
V
V
OL
SINK
SINK
OUT
OUT
l
V
RST, WDO Output Voltage High (Note 6)
V
–1
V
OH
OUT
3689fa
3
LT3689/LT3689-5
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VOUT = 5V, unless otherwise noted. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
Step V from 0.9V to 0.5V
MIN
10
TYP
30
MAX
65
UNITS
μs
V
l
l
t
UV Detect to RST Asserted
WDI Input Threshold
UV
FB
0.4
0.95
–2
1.15
WDI Input Pull-Up Current
WDI Input Pulse Width
W/T Threshold Voltage
W/T Input Pull-Down Current
WDE Threshold Voltage
WDO Pull-Up Current (Note 6)
RST Pull-Up Current (Note 6)
μA
ns
V
l
l
300
0.4
0.8
2.6
1
1
μA
V
l
0.4
0.8
–0.6
–0.6
–0.85
–0.85
μA
μA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: Current limit is guaranteed by design and/or correlation to static
test. Slope compensation reduces current limit at higher duty cycles.
Note 5: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 150°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 2: Absolute maximum voltage at V and EN/UVLO pins is 60V for
IN
nonrepetitive 1 second transients, and 36V for continuous operation.
Note 3: The LT3689E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3689I is guaranteed over the full –40°C to 125°C operating junction
temperature range. The LT3689H is guaranteed over the full –40°C to
150°C operating junction temperature range. High junction temperatures
degrade operating lifetimes. Operating lifetime is derated at junction
temperatures greater than 125°C.
Note 6: The output of RST and WDO has a weak pull-up to V
of
OUT
typically 1μA. However, external pull-up resistors may be used when faster
rise times are required or for V higher than V
.
OUT
OH
Note 7: Polarity specification for all currents into pins is positive. All
voltages are referenced to GND unless otherwise specified.
Note 8: For the LT3689-5, V
is set to 5.5V to ensure the switching.
OUT
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency, VOUT = 5V
Efficiency, VOUT = 3.3V
Efficiency, VOUT = 1.8V
95
90
85
80
75
70
65
90
85
80
75
70
65
80
T
= 25°C
T
= 25°C
T = 25°C
A
f = 1MHz
A
A
V = 5V
IN
f = 1MHz
f = 700kHz
V
= 12V
= 24V
IN
IN
75
70
65
60
55
50
V
= 12V
= 24V
IN
V
= 12V
IN
V
V
IN
V
= 32V
IN
V
= 32V
IN
0.3 0.4 0.5 0.6 0.7
0.1 0.2
LOAD CURRENT (A)
0
0.3 0.4 0.5 0.6 0.7
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7
0
0.1 0.2
LOAD CURRENT (A)
LOAD CURRENT (A)
3689 G01
3689 G02
3689 G03
3689fa
4
LT3689/LT3689-5
TYPICAL PERFORMANCE CHARACTERISTICS
No-Load Supply Current vs VIN
No-Load Supply Current
Maximum Load Current, 5VOUT
1.4
140
120
800
700
600
500
400
300
200
100
0
T
= 25°C
CATCH DIODE: DIODES INC. B140HB
A
TYPICAL
V
V
= 12V
IN
OUT
1.2
1.0
0.8
0.6
0.4
0.2
0
= 3.3V
100
INCREASED SUPPLY
CURRENT DUE TO
CATCH DIODE LEAKAGE
AT HIGH TEMPERATURE
80
60
40
20
MINIMUM
T
= 25°C
A
L = 12μH
f = 1MHz
0
10 15 20 25 30
INPUT VOLTAGE (V)
40
0
5
35
–50 –25
25 50 75 100 125 150
0
6
12
18
24
30
36
TEMPERATURE (°C)
V
IN
(V)
3689 G05
3689 G06
3689 G04
Maximum VIN for Full Frequency
Maximum VIN for Full Frequency
Maximum Output Current, 3.3VOUT
35
30
25
20
15
10
5
1.2
1.0
0.8
0.6
0.4
0.2
0
40
35
30
25
20
15
10
5
TYPICAL
T
= 25°C
= 85°C
A
A
T
= 25°C
= 85°C
A
T
T
A
MINIMUM
V
= 3.3V
V
= 5V
O
O
T
= 25°C
L = 4.7μH
f = 2MHz
L = 6.8μH
f = 2MHz
A
L = 12μH
f = 700kHz
SYNC = 3.3V
SYNC = 5V
0
0
0.3 0.4 0.5 0.6 0.7
LOAD CURRENT (A)
4
8
16 20 24 28 32 36
0
0.1 0.2
12
0.3 0.4 0.5 0.6 0.7
LOAD CURRENT (A)
0
0.1 0.2
V
(V)
IN
3689 G09
3689 G08
3689 G07
Switch Current Limit
vs Duty Cycle
Switch Current Limit
vs Temperature
Switch Voltage Drop
2.0
1.6
1.2
0.8
0.4
0
2.0
1.5
1.0
600
500
400
300
200
100
0
T
= 25°C
A
SYNC = LOW
SYNC = LOW
SYNC = HIGH
TYPICAL
T
= 25°C
A
MINIMUM
T
= –50°C
A
0.5
0
T
= 125°C
A
0
40
60
80
100
20
400
600
800
1000
–50 –25
25 50 75 100 125 150
0
200
0
DUTY CYCLE (%)
TEMPERATURE (°C)
SWITCH CURRENT (mA)
3689 G10
3689 G11
3689 G12
3689fa
5
LT3689/LT3689-5
TYPICAL PERFORMANCE CHARACTERISTICS
Output Voltage
BST Pin Current
Feedback Voltage
25
20
15
10
5
0.810
0.805
0.800
0.795
0.790
5.05
5.04
5.03
5.02
5.01
5.00
4.99
4.98
4.97
4.96
4.95
T
= 125°C
A
T
= –50°C
A
T
= 25°C
A
0
400
600
800
1000
0
200
–50 –25
25 50 75 100 125 150
–50 –25
25 50 75 100 125 150
0
0
TEMPERATURE (°C)
TEMPERATURE (°C)
SWITCH CURRENT (mA)
3689 G15
3689 G14
3689 G13
Frequency Foldback
Switching Frequency
Switching Frequency vs RT
50
40
30
20
10
0
1200
1000
800
600
400
200
0
900
850
800
750
700
650
600
550
500
T
= 25°C
= 12.7k
T
= 25°C
R
= 20.5k
A
T
A
T
R
0
0.8
1.2
1.6
2
2.4
0.4
0
100 200 300 400 500 600 700 800 900
50
TEMPERATURE (°C)
100 125 150
–50 –25
0
25
75
FREQUENCY (MHz)
FB VOLTAGE (mV)
3689 G18
3689 G17
3689 G16
Minimum Switch On-Time
Overvoltage Lockout
VIN Fixed Undervoltage Lockout
40
39
38
37
36
3.6
3.5
3.4
3.3
3.2
3.1
140
120
100
80
I
= 700mA
LOAD
V
RISING
IN
V
FALLING
IN
60
40
20
0
–50 –25
25 50 75 100 125 150
50
TEMPERATURE (°C)
100 125 150
0
–50 –25
25 50 75 100 125 150
–50 –25
0
25
75
0
TEMPERATURE (°C)
TEMPERATURE (°C)
3689 G20
3689 G21
3689 G19
3689fa
6
LT3689/LT3689-5
TYPICAL PERFORMANCE CHARACTERISTICS
EN/UVLO Pin Current
EN/UVLO Pin Threshold
Boost Diode Forward Voltage
7
6
5
4
3
2
1
0
900
1.300
1.290
1.280
1.270
1.260
1.250
1.240
1.230
1.220
1.210
1.200
V
= 12V
IN
800
700
600
500
400
300
200
100
0
T
= –50°C
A
T
= –50°C
A
T
= 25°C
A
T
= 25°C
A
T
= 150°C
A
EN/UVLO THRESHOLD RISING
EN/UVLO THRESHOLD FALLING
T
= 150°C
A
0
10
30
40
50
0
5
15
20
(V)
25
30
35
20
10
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
3689 G23
0
BOOST DIODE CURRENT (mA)
V
EN/UVLO
3689 G24
3689 G22
Switching Waveform:
Transition from Burst Mode
to Full Frequency
Switching Waveform:
Burst Mode Operation
EN/UVLO Hysteresis Current
5.0
4.5
4.0
3.5
3.0
V
V
OUT
OUT
10mV/DIV
10mV/DIV
I
L
I
L
0.2A/DIV
0.2A/DIV
V
SW
V
SW
5V/DIV
5V/DIV
3689 G27
3689 G26
1μs/DIV
5μs/DIV
V
I
= 12V, FRONT PAGE APPLICATION
= 60mA
V
I
= 12V, FRONT PAGE APPLICATION
= 6mA
IN
LOAD
IN
LOAD
–50 –25
25 50 75 100 125 150
0
TEMPERATURE (°C)
3689 G25
Power-On-Reset Threshold
vs Temperature
Switching Waveform:
Full Frequency Continuous Operation
0.730
0.725
0.720
0.715
0.710
V
OUT
10mV/DIV
I
L
0.5A/DIV
V
SW
10V/DIV
3689 G28
1μs/DIV
V
LOAD
= 12V, FRONT PAGE APPLICATION
IN
I
= 600mA
–50 –25
25 50 75 100 125 150
0
TEMPERATURE (°C)
3689 G29
3689fa
7
LT3689/LT3689-5
TYPICAL PERFORMANCE CHARACTERISTICS
Transient Duration
vs POR Comparator Overdrive
Watchdog Upper Boundary Period
Watchdog Lower Boundary Period
800
700
600
500
400
300
200
100
0
7.0
6.5
6.0
5.5
5.0
21
20
19
18
17
C
= 10nF
C
= 1nF
WDT
MURATA:
WDT
MURATA:
GRM1885C1H102FA01
GRM1882C1H102FA01
RESET OCCURS
ABOVE THE CURVE
0.10
POR COMPARATOR OVERDRIVE VOLTAGE AS PERCENTAGE
OF RESET THRESHOLD, V (%)
1.00
10.00
100.00
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
–50 –25
25 50 75 100 125 150
0
TEMPERATURE (°C)
3689 G32
3689 G31
RST
3689 G30
Watchdog Upper Boundary Period
vs Capacitance
Reset Timeout Period
100000
10000
1000
100
21
20
19
18
17
C
= 8.2nF
POR
MURATA:
GRM2195C1H822FA01
10
1
0.1
0.001 0.01
0.1
1
10 100 1000
(nF)
WDT
–50 –25
25 50 75 100 125 150
0
C
PIN CAPICITANCE, C
TEMPERATURE (°C)
WDT
3689 G33
3689 G34
Watchdog Lower Boundary Period
vs Capacitance
Reset Timeout Period
vs Capacitance
10000
1000
100
10
10000
1000
100
10
1
1
0.1
0.1
0.01
0.01
0.001 0.01 0.1
1
10 100 1000 10000
(nF)
0.001 0.01 0.1
1
10 100 1000 10000
(nF)
C
PIN CAPICITANCE, C
C
PIN CAPICITANCE, C
WDT
WDT
POR
POR
3689 G36
3689 G35
3689fa
8
LT3689/LT3689-5
PIN FUNCTIONS
BST: The BST pin is used to provide drive voltage higher
than the input voltage to the internal NPN power switch.
RST: Active low, open collector logic output with a weak
pull-up to V . After V
rises above 90% of its pro-
OUT
OUT
grammed value, the reset remains asserted for the period
set by the capacitor on the C pin.
V : The V pin supplies current to the LT3689’s internal
IN
IN
POR
circuitry and to the internal power switch and must be
locally bypassed.
WDO: Active low, open collector logic output with weak
pull-up to V . WDO pulls low if the WDE is enabled
OUT
SW: The SW pin is the output of the internal power switch.
Connect this pin to the inductor, catch diode and boost
capacitor.
and the microprocessor fails to drive the WDI pin of the
LT3689 with an appropriate signal.
C
: Watchdog Timer Programming Pin. Place a capa-
WDT
WDT
citor (C
DA: Tie the DA pin to the anode of the external catch
Schottky diode. If the DA pin current exceeds 1.2A,
which could occur in an overload or short-circuit condi-
tion, switching is disabled until the DA pin current falls
below 1.2A.
) between this pin and ground to adjust the
watchdogupperandlowerboundaryperiod. Todetermine
thewatchdogupperboundaryperiod,andthelowerbound-
ary period, use the following equations:
t
= 18.2 • C
(watchdog upper boundary period)
(watchdog lower boundary period)
WDU
WDT
EN/UVLO: The EN/UVLO pin is used to put the LT3689 in
shutdown mode. Pull the pin below 0.3V to shut down the
LT3689. The 1.26V threshold can function as an accurate
undervoltage lockout (UVLO), preventing the regulator
from operating until the input voltage has reached the
programmed level.
t
= 0.588 • C
WDT
WDL
t
and t
are in ms and C
is in nF. As an example,
WDU
WDL
WDT
a 47nF capacitor will generate an 855ms watchdog upper
boundary period and a 27.6ms watchdog lower boundary
period.
FB: The LT3689 regulates the feedback pin to 0.800V. Con-
nect the feedback resistor divider tap to this pin. For the
fixed LT3689-5 output, this pin can be used to connect a
phase lead capacitor between the OUT pin and FB pin to
optimize transient response.
C
: Reset Delay Timer Programming Pin. Attach an
POR
external capacitor (C ) to GND to set a reset delay time
POR
of 2.3ms/nF.
RT: SetstheInternalOscillatorFrequency.Tiea31.6kresis-
tor from RT to GND for a 500kHz switching frequency.
WDE: Watchdog Timer Enable Pin. This pin disables the
watchdog timer if the WDE voltage exceeds 1V. WDO is
high in this condition.
SYNC: Drive the SYNC pin with a logic level signal with
positive and negative pulse widths of at least 80ns. The
R resistor should be chosen to set the LT3689 switching
T
W/T:SettingW/TlowputstheLT3689watchdogtimerinto
window mode. If two or more negative edges occur on
frequency at least 20% below the lowest synchronization
input frequency.
WDI before the watchdog lower boundary (t
) period
WDL
OUT: The OUT pin supplies current to the internal circuitry
when OUT is above 3V, reducing input quiescent current.
TheinternalSchottkydiodeisconnectedfromOUTtoBST,
providing the charging path for the boost capacitor. For
the LT3689-5, this pin connects to the internal feedback
divider that programs the fixed 5V output.
expires, or no negative edge occurs within the watchdog
upper boundary (t ) period, the part will set WDO low.
WDU
If W/T is set high, the part will only set WDO low if no
transition occurs within the watchdog upper boundary
period.
WDI: Watchdog Timer Input Pin. This pin receives the
watchdogsignalfromamicroprocessor. Iftheappropriate
signal is not received, the part will pulse WDO low for a
period equal to the reset timeout period. The watchdog
timer is disabled until the WDO pin goes high again.
GND: Ground. Tie the exposed pad directly to the ground
plane.Theexposedpadmetalofthepackageprovidesboth
electrical contact to ground and good thermal contact to
the printed circuit board. The device must be soldered to
the circuit board for proper operation.
3689fa
9
LT3689/LT3689-5
BLOCK DIAGRAM
V
IN
V
IN
C1
–
+
INTERNAL
0.8V
REF
OUT
BST
EN/UVLO
SLOPE COMP
OSCILLATOR
3
SWITCH
LATCH
R
RT
C2
L1
Q
S
R
T
SW
DA
SYNC
V
OUT
DISABLE
SOFT-START
C3
D1
Burst Mode
OPERATION
DETECT
V
OUT
OUT
LT3689-5
ONLY
ERROR AMP
V
C
+
–
R1
R2
525k
R
SEN
FB
V CLAMP
C
GND
R
C
100k
C
C
WDE
WDI
W/T
2μA
C
WDT
TRANSITION
DETECT
WATCHDOG
TIMER
22μA
1μA
OUT
+
80mV
FB
WDO
–
+
OUT
ADJUSTABLE
RESET PULSE
GENERATOR
1μA
V
IN
–
+
RST
2μA
3.4V
22μA
C
POR
3689 BD
3689fa
10
LT3689/LT3689-5
TIMING DIAGRAMS
V
OUT
V
UV
t
t
RST
UV
RST
POWER-ON RESET TIMING
WDI
WDO
t
WDU
t
t
RST
WATCHDOG TIMING (W/T = HIGH), TIMEOUT MODE
t < t
WDL
RST
WDI
WDO
3689 TD
t
t
WDU
RST
WATCHDOG TIMING (W/T = LOW), WINDOW MODE
t
t
t
t
= TIME REQUIRED TO ASSERT RST LOW ONCE V
GOES BELOW V
UV
OUT UV
= PROGRAMMED RESET PERIOD
RST
WDU
WDL
= WATCHDOG UPPER BOUNDARY PERIOD
= WATCHDOG WINDOW MODE LOWER BOUNDARY PERIOD
= OUTPUT VOLTAGE RESET THRESHOLD
V
UV
3689fa
11
LT3689/LT3689-5
OPERATION
The LT3689 is a constant-frequency, current mode step-
down regulator with a watchdog and a reset timer that
allows microprocessor supervisory functions. Operation
can be best understood by referring to the Block Diagram.
Keeping the EN/UVLO pin at ground completely shuts off
A comparator monitors the current flowing through the
catchdiodeviatheDApin. Thiscomparatordelaysswitch-
ing if the diode current goes higher than 1.2A (typical)
during a fault condition such as a shorted output with
high input voltage. The switching will only resume once
the diode current has fallen below the 1.2A limit. This
way the DA comparator regulates the valley current of the
inductor to 1.2A during a short-circuit.
the part drawing minimal current from the V source. To
IN
turn on the internal bandgap and the rest of the logic cir-
cuitry,raisetheEN/UVLOpinabovetheaccuratethreshold
of 1.26V. Also, V needs to be higher than 3.7V for the
IN
The LT3689 has an overvoltage protection feature which
part to start switching.
disables switching when the V goes above 38V (typical)
IN
during transients. When switching is disabled, the LT3689
can safely sustain transient input voltages up to 60V.
Switching Regulator Operation
An oscillator, with frequency set by R , enables an RS flip-
T
Power-On Reset and Watchdog Timer Operation
flop, turning on the internal power switch. An amplifier
and comparator monitor the current flowing between the
The LT3689 has a power-on reset (POR) comparator that
monitors the regulated output voltage. If the output volt-
age is below 10% of the regulation value, the RST pin is
pulled low. Once the output voltage crosses over 90% of
the regulation value, a reset timer is started and RST is
released after the programmed reset delay time. The reset
V and SW pins, turning the switch off when this current
IN
reaches a level determined by the voltage at V . An error
C
amplifiermeasurestheoutputvoltagethroughtheresistor
divider tied to the FB pin and servos the V voltage. If the
C
erroramplifier’soutputincreases,morecurrentisdelivered
to the output; if it decreases, less current is delivered. An
delay is programmable through the C
pin.
POR
active clamp on the V voltage provides current limit.
C
Thewatchdogtypicallymonitorsamicroprocessor’sactiv-
ity. The watchdog can be enabled or disabled by applying
a logic signal to the WDE pin. The watchdog can be oper-
ated in either timeout or window mode by applying a logic
signaltotheW/Tpin.Intimeoutmode,themicroprocessor
is required to change the logic state of the WDI pin on a
periodic basis in order to clear the watchdog timer and to
prevent the WDO from going low. In window mode, the
watchdogtimerrequiressuccessivenegativeedgesonthe
WDI pin to come within a programmed time window to
keep WDO from going low. Therefore, in window mode, if
the time between the two negative WDI edges is too short
or too long, then the WDO pin will be pulled low. When the
WDO pin goes low, either in timeout or in window mode,
the reset timer turns on and keeps the WDO pin low. The
WDO pin will go high again once the reset timer expires or
the RST pin goes low when the output voltage falls 10%
below the regulation value. Both the timeout and window
Aninternalregulatorprovidespowertothecontrolcircuitry.
The bias regulator normally draws current from the V
IN
pin, but if the OUT pin is connected to an external volt-
age higher than 3V, bias current will be drawn from the
external source (typically the regulated output voltage).
This improves efficiency. The OUT pin also provides a
current path to the internal boost diode that charges up
theboostcapacitor. Theswitchdriveroperateseitherfrom
the V or from the BST pin. An external capacitor is used
IN
to generate a voltage at the BST pin that is higher than
the V supply. This allows the driver to fully saturate the
IN
internal bipolar NPN power switch for efficient operation.
To further optimize efficiency, the LT3689 automatically
switches to Burst Mode operation in light load situations.
Between bursts, all circuitry associated with controlling
the output switch is shut down, reducing the input sup-
ply current to 85μA in a typical application. The oscillator
reduces the LT3689’s operating frequency when the volt-
age at the FB pin is low. This frequency foldback helps to
control the output current during start-up and overload
conditions.
periods can be set through the C
pin.
WDT
3689fa
12
LT3689/LT3689-5
APPLICATIONS INFORMATION
The output voltage is programmed with a resistor divider
between the output and the FB pin. Choose 1% resistors
according to:
Operating Frequency Tradeoffs
Selection of the operating frequency is a tradeoff between
efficiency, component size and maximum input voltage.
The advantage of high frequency operation is that smaller
inductor and capacitor values may be used. The disad-
vantages are lower efficiency, and narrower input voltage
rangeatconstant-frequency.Thehighestconstant-switch-
VOUT
0.8V
R1=R2
1
For reference designators, refer to the Block Diagram.
ing frequency (f
calculated as follows:
) for a given application can be
SW(MAX)
Setting the Switching Frequency
The LT3689 uses a constant-frequency PWM architecture
thatcanbeprogrammedtoswitchfrom350kHzto2.2MHz
by using a resistor tied from the RT pin to ground. Table 1
V
OUT + VD
fSW(MAX)
=
tON(MIN) V – V + V
IN
SW
D
shows the R values for various switching frequencies.
T
where V is the typical input voltage, V
is the output
IN
OUT
voltage, V is the catch diode drop (~0.5V) and V is
the internal switch drop (~0.5V at maximum load). If the
D
SW
Table 1. Switching Frequency vs RT
SWITCHING FREQUENCY (MHz)
R (kΩ)
T
LT3689 is programmed to operate at a frequency higher
0.35
0.5
0.6
0.7
0.8
0.9
1
48.7
31.6
24.9
20.5
16.9
14.7
12.7
9.53
7.5
than f
for a given V input voltage, the LT3689
IN
SW(MAX)
enters pulse-skipping mode, where it skips switching
cycles to maintain regulation. At frequencies higher than
f , the LT3689 no longer operates with constant-
SW(MAX)
frequency. The LT3689 enters pulse-skipping mode at
frequencies higher than f because of the limita-
SW(MAX)
tion on the LT3689’s minimum on-time of 130ns. As the
switching frequency is increased above f , the part
1.2
1.4
1.6
1.8
2
SW(MAX)
isrequiredtoswitchforshorterperiodsoftimetomaintain
the same duty cycle. Delays associated with turning off
the power switch dictate the minimum on-time of the part.
Whentherequiredon-timedecreasesbelowtheminimum
on-time of 130ns, the switch pulse width remains fixed at
130ns (instead of becoming narrower to accommodate
the duty cycle requirement). The inductor current ramps
up to a value exceeding the load current and the output
ripple increases. The part then remains off until the output
voltage dips below the programmed value before it begins
switching again.
6.04
4.87
4.02
3.16
2.2
3689fa
13
LT3689/LT3689-5
APPLICATIONS INFORMATION
Maximum Operating Voltage
with an output voltage of 1.8V and switching frequency
of 1.5MHz has a V of 11.3V, as shown in Figure 1.
IN(PS)
The maximum input voltage for LT3689 applications
depends on switching frequency, the absolute maximum
Figure 2 shows operation at 24V. Output ripple and peak
inductor current have significantly increased. A saturating
inductor may further reduce performance. For input volt-
ages over 30V, there are restrictions on the inductor size
and saturation rating. See the Inductor Selection section
formoredetails.Inpulse-skippingmode,theLT3689skips
switchingpulsestomaintainoutputregulation.Above38V
(typical) switching will stop. Transients of up to 60V are
acceptable, regardless of switching frequency.
ratings of the V and BST pins, and by the minimum
IN
duty cycle (DC ). The LT3689 can operate from input
MIN
voltages up to 36V, and safely withstand input transient
voltages up to 60V. Note that while V > 38V (typical),
IN
the LT3689 will stop switching, allowing the output to fall
out of regulation.
DC
= t
• f
ON(MIN) SW
MIN
where t
is equal to 130ns (for T > 125°C t
J ON(MIN)
ON(MIN)
Minimum Operating Voltage Range
is equal to 150ns) and f is the switching frequency.
SW
Running at a lower switching frequency allows a lower
minimum duty cycle. The maximum input voltage before
pulse-skipping occurs depends on the output voltage and
the minimum duty cycle:
The minimum input voltage is determined either by the
LT3689’s minimum operating voltage of ~3.4V or by its
maximum duty cycle. The duty cycle is the fraction of
time that the internal switch is on and is determined by
the input and output voltages:
V
OUT + VD
DCMIN
V
=
– VD + VSW
= 3.3V,
IN(PS)
V
OUT + V
D
DC =
V – VSW + V
IN
D
Example: f = 790kHz, V
SW
OUT
DC
= 130ns • 790kHz = 0.103
MIN
Unlike many fixed frequency regulators, the LT3689 can
extend its duty cycle by remaining on for multiple cycles.
TheLT3689willnotswitchoffattheendofeachclockcycle
if there is sufficient voltage across the boost capacitor (C3
in the Block Diagram). Eventually, the voltage on the boost
capacitor falls and requires refreshing. Circuitry detects
3.3V + 0.4V
V
=
– 0.4V + 0.4V = 36V
IN(PS)
0.103
The LT3689 will regulate the output current at input volt-
ages greater than V . For example, an application
IN(PS)
V
OUT
V
OUT
50mV/DIV
(AC)
50mV/DIV
(AC)
I
I
L
L
0.5A/DIV
0.5A/DIV
3689 F01
3689 F02
5μs/DIV
5μs/DIV
Figure 1. Operation Below VIN(PS). VIN = 10V,
VOUT = 1.8V and fSW = 1.5MHz
Figure 2. Operation Above VIN(PS). VIN = 24V,
VOUT = 1.8V and fSW = 1.5MHz. Output Ripple
and Peak Inductor Current Increase
3689fa
14
LT3689/LT3689-5
APPLICATIONS INFORMATION
this condition and forces the switch to turn off, allowing
the inductor current to charge up the boost capacitor.
This places a limitation on the maximum duty cycle. The
maximum duty cycle that the LT3689 can sustain is 90%.
higher. To keep the efficiency high, the series resistance
(DCR) should be less than 0.15Ω and the core mate-
rial should be intended for high frequency applications.
Table 2 lists several vendors and suitable types.
From this DC
number, the minimum operating voltage
MAX
The current in the inductor is a triangle wave with an
average value equal to the load current. The peak switch
currentisequaltotheoutputcurrentplushalfthepeak-to-
peak inductor ripple current. The LT3689 limits its switch
current in order to protect itself and the system from
overload faults. Therefore, the maximum output current
that the LT3689 will deliver depends on the switch current
limit, the inductor value, and the input and output volt-
ages. Also, if the inductor current’s bottom peak exceeds
can be calculated using the following equation:
V
OUT + V
0.90
V
=
D − V + VSW
IN(MIN)
D
Example: V
= 3.3V
OUT
3.3V + 0.4V
V
=
– 0.4V + 0.4V = 4.1V
IN(MIN)
0.90
the DA current limit (I
) at high output currents
LIM(DA)
Inductor Selection and Maximum Output Current
then the DA current comparator will regulate the bottom
peak to I . This will result in higher inductor ripple
A good first choice for the inductor value is:
LIM(DA)
current and will further limit the max output current. The
DA current limit consists of a DC and an AC component.
The nominal DC component is fixed at 1.2A. The AC
component depends on the output voltage, inductor size
and a fixed time delay between the DA comparator turn-
ing off and switch turning on. Therefore, the DA current
2.2MHz
L = (VOUT + VF) •
fSW
where V is the voltage drop of the catch diode (~0.4V),
F
f
is the switching frequency in MHz, and L is in μH. The
SW
inductor’s RMS current rating must be greater than the
maximum load current and its saturation current should
be at least 30% higher. For robust operation in fault con-
ditions (start-up or short-circuit) and high input voltage
limit I
will increase as the output voltage collapses
LIM(DA)
under overload conditions.
V
OUT + VD
(
)
ILIM(DA) = 1.2A −
• 0.25µs
(>30V), use an 8.2μH or greater inductor (for T > 125°C,
use 10μH or larger) with a saturation rating of 2.5A, or
J
L
Table 2. Inductor Vendors
INDUCTANCE RANGE
(μH)
SIZE
(mm)
VENDOR
URL
PART SERIES
Sumida
www.sumida.com
CDRH4D28
CDRH5D28
1.2 to 4.7
2.5 to 10
4.5 × 4.5
5.5 × 5.5
Toko
www.toko.com
A916CY
D585LC
2 to 12
1.1 to 39
6.3 × 6.2
8.1 × 8
Würth Elektronik
www.we-online.com
WE-TPC(M)
WE-PD2(M)
1 to 10
2.2 to 22
4.8 × 4.8
5.2 × 5.8
3689fa
15
LT3689/LT3689-5
APPLICATIONS INFORMATION
Choose an inductor using the previous inductor selection
equation to guarantee 700mA of output current. If using
a smaller inductor, check the DA current limit equation to
verify that the DA circuitry will not lower the switching
frequency.
load is lower than 0.7A, decrease the value of the inductor
and operate with a higher ripple current. This allows the
use of a physically smaller inductor, or one with a lower
DCR resulting in higher efficiency. There are graphs in
the Typical Performance Characteristics section of this
data sheet that show the maximum load current as a
function of input voltage for several popular output volt-
ages. Low inductance may result in discontinuous mode
operation, which is okay but further reduces maximum
load current. For details of maximum output current and
discontinuous mode operation, see Linear Technology
Application Note 44. Finally, for duty cycles greater than
When the switch is off, the potential across the inductor
is the output voltage plus the catch diode drop. This gives
the peak-to-peak ripple current in the inductor:
(1−DC)(VOUT + VD)
ΔIL =
L • fSW
where f is the switching frequency of the LT3689 and L
50% (V /V > 0.5), a minimum inductance is required
SW
OUT IN
to avoid subharmonic oscillations:
is the value of the inductor. The peak inductor and switch
current is:
1.4 VOUT + VD
(
)
LMIN
=
ΔIL
2
I
SW(PK) =IL(PK) =IOUT +
fSW
where L
is in MHz.
is in μH, V
and V are in volts, and f
OUT D SW
MIN
To maintain output regulation, this peak current must be
less than the LT3689’s switch current limit I . I is at
LIM LIM
Input Capacitor
least 1.5A for at low duty cycles and decreases linearly
to 0.87A at DC = 85%. The maximum output current is a
function of the chosen inductor value.
Bypass the input of the LT3689 circuit with a ceramic
capacitor of an X7R or X5R type. Y5V types have poor
performance over temperature and applied voltage, and
should not be used. The minimum value of input capaci-
tance depends on the switching frequency. Use an input
capacitor of 1μF or more for switching frequencies be-
tween 1MHz to 2.2MHz, and 2.2μF or more for frequen-
cies lower than 1MHz. If the input power source has high
impedance, or there is significant inductance due to long
wires or cables, additional bulk capacitance may be nec-
essary. This can be provided with a lower performance
electrolytic capacitor. Step-down regulators draw current
from the input supply in pulses with very fast rise and
fall times. The input capacitor is required to reduce the
resulting voltage ripple at the LT3689 input and to force
thisveryhighfrequencyswitchingcurrentintoatightlocal
loop, minimizing EMI. A ceramic capacitor is capable of
this task, but only if it is placed close to the LT3689 and
the catch diode (see the PCB Layout section). A second
precautionregardingtheceramicinputcapacitorconcerns
themaximuminputvoltageratingoftheLT3689.Aceramic
input capacitor combined with trace or cable inductance
forms a high quality (under damped) tank circuit. If the
ΔIL
2
I
OUT(MAX) = ILIM −
ΔIL
2
= 1.15A • (1−0.28 • DC)−
Choosing an inductor value so that the ripple current is
smallwillallowamaximumoutputcurrentneartheswitch
current limit.
One approach to choosing the inductor is to start with the
preceding simple rule, determine the available inductors,
and choose one to meet cost or space goals. Next, use
these equations to check that the LT3689 will be able to
deliver the required output current. Note again that these
equations assume that the inductor current is continu-
ous. Discontinuous operation occurs when I
is less
OUT
than ΔI /2.
L
Of course, such a simple design guide will not always
result in the optimum inductor for the application. A larger
value inductor provides a slightly higher maximum load
current and will reduce the output voltage ripple. If the
3689fa
16
LT3689/LT3689-5
APPLICATIONS INFORMATION
LT3689 circuit is plugged into a live supply, the input volt-
agecanringtotwiceitsnominalvalue, possiblyexceeding
the LT3689’s voltage rating. For a complete discussion,
see Linear Technology’s Application Note 88.
capacitor must be large to achieve low ESR. Table 3 lists
several capacitor vendors.
Table 3. Capacitor Vendors
VENDOR
Panasonic
Kemet
PHONE
URL
Output Capacitor and Output Ripple
(714) 373-7366
(864) 963-6300
(408) 749-9714
(408) 436-1300
www.panasonic.com
www.kemet.com
The output capacitor has two essential functions. Along
withtheinductor,itfiltersthesquarewavegeneratedbythe
LT3689toproducetheDCoutput. Inthisroleitdetermines
the output ripple, and low impedance at the switching
frequency is important. The second function is to store
energy in order to satisfy transient loads and stabilize the
LT3689’s control loop. Ceramic capacitors have very low
equivalent series resistance (ESR) and provide the best
ripple performance. A good starting value is:
Sanyo
www.sanyovideo.com
www.murata.com
www.avxcorp.com
www.taiyo-yuden.com
Murata
AVX
Taiyo Yuden
(864) 963-6300
Catch Diode
The catch diode conducts current only during switch-off
time. Average forward current in normal operation can
be calculated from:
50
COUT
=
VOUT SW
f
IOUT (VIN − VOUT
)
ID(AVG)
=
VIN
where f is in MHz, and C
is the recommended out-
OUT
SW
put capacitance in μF. Use X5R or X7R types, which will
provide low output ripple and good transient response.
Transient performance can be improved with a high value
capacitor, but a phase lead capacitor across the feedback
resistor R1 may be required to get the full benefit (see the
Frequency Compensation section).
where I
is the output load current. The only reason to
OUT
consider a diode with a larger current rating than neces-
sary for nominal operation is for the worst-case condition
of shorted output. The diode current will then increase to
the typical peak switch current limit. Peak reverse voltage
is equal to the regulator input voltage. Use a Schottky
diode with a reverse voltage rating greater than the input
voltage. The overvoltage protection feature in the LT3689
High performance electrolytic capacitors can be used for
theoutputcapacitor. LowESRisimportant, sochooseone
that is intended for use in switching regulators. The ESR
should be specified by the supplier and should be 0.1Ω
or less. Such a capacitor will be larger than a ceramic
capacitor and will have a larger capacitance because the
will keep the switch off when V > 38V (typical), which
IN
allows the use of a 40V rated Schottky even when V
IN
ranges up to 60V. Table 4 lists several Schottky diodes
and their manufacturers.
3689fa
17
LT3689/LT3689-5
APPLICATIONS INFORMATION
Table 4. Diode Vendors
Frequency Compensation
V
I
V AT I
F AVE
(mV)
R
AVE
The LT3689 uses current mode control to regulate the
output, which simplifies loop compensation. In particular,
the LT3689 does not require the ESR of the output capaci-
tor for stability, allowing the use of ceramic capacitors to
achieve low output ripple and small circuit size. Figure 3
shows an equivalent circuit for the LT3689 control loop.
The error amp is a transconductance amplifier with finite
output impedance. The power section, consisting of the
modulator, power switch and inductor, is modeled as a
transconductance amplifier generating an output current
PART NUMBER
(V)
(A)
On Semiconductor
MBRM120E
20
40
1
1
530
550
MBRM140
Diodes Inc.
B120
B130
B140
B0540W
B140HB
20
30
40
40
40
1
1
1
0.5
1
500
500
500
510
530
Ceramic Capacitors
proportional to the voltage at the V node. Note that the
C
Ceramic capacitors are small, robust and have very low
ESR. However, ceramic capacitors can cause problems
when used with the LT3689 due to their piezoelectric
nature. When in Burst Mode operation, the LT3689’s
switching frequency depends on the load current, and at
very light loads the LT3689 can excite the ceramic capaci-
tor at audio frequencies, generating audible noise. Since
the LT3689 operates at a lower current limit during Burst
Mode operation, the noise is typically very quiet. If this
noise is unacceptable, use a high performance tantalum
or electrolytic capacitor at the output.
output capacitor, C1, integrates this current, and that the
capacitor on the V node (C ) integrates the error ampli-
C
C
fier output current, resulting in two poles in the loop. R
C
provides a zero. With the recommended output capacitor,
theloopcrossoveroccursabovetheR C zero.Thissimple
C C
model works well as long as the value of the inductor is
not too high and the loop crossover frequency is much
lower than the switching frequency. With a larger ceramic
capacitor (very low ESR), crossover may be lower and a
phaseleadcapacitor(C )acrossthefeedbackdividermay
PL
improve the phase margin and transient response. Large
electrolytic capacitors may have an ESR large enough to
create an additional zero, and the phase lead may not be
necessary.
LT3689
CURRENT MODE
POWER STAGE
–
0.7V
g
=
m
OUT
1.2A/V
+
C
R1
R2
PL
–
FB
g
=
V
m
C
300μA/V
ESR
+
800mV
R
37k
C
C1
ERROR
AMPLIFIER
+
C1
C
C
3M
100pF
GND
3689 F03
Figure 3. Model for the Loop Response
3689fa
18
LT3689/LT3689-5
APPLICATIONS INFORMATION
Most applications running at V greater than 20V will
where the output power is delivered to the load by the
outputcapacitor.BecausetheLT3689deliverspowertothe
output with single, low current pulses, the output ripple is
kept below 15mV for a typical application. The LT3689-5
has a slightly higher output ripple of 25mV. This higher
ripple can be reduced by using a larger output capacitor.
IN
require a small phase lead capacitor, ranging from 2pF to
about30pF,betweentheFBpinandV
forgoodtransient
OUT
response. The circuits in the Typical Applications section
use the appropriate phase lead capacitors and are stable
at all input voltages.
In addition, V and OUT quiescent currents are reduced
IN
If the output capacitor is different than the recommended
capacitor, stability should be checked across all operating
conditions, including load current, input voltage and tem-
perature.TheLT1375datasheetcontainsamorethorough
discussion of loop compensation and describes how to
test the stability using a transient load. Figure 4 shows
the transient response when the load current is stepped
from 360mA to 720mA and back to 360mA.
to typically 50μA and 75μA, respectively, during the sleep
time. As the load current decreases towards a no-load
condition, thepercentageoftimethattheLT3689operates
in sleep mode increases and the average input current is
greatly reduced, resulting in high efficiency even at very
low loads (see Figure 5).
At higher output loads (above approximately 60mA at
V =12Vforthefrontpageapplication)theLT3689willbe
IN
Low Ripple Burst Mode Operation and Pulse-Skipping
Mode
running at the frequency programmed by the R resistor,
T
and will be operating in standard PWM mode. The transi-
tion between PWM and low ripple Burst Mode operation
is seamless, and will not disturb the output voltage. If low
quiescent current is not required, the LT3689 can oper-
ate in pulse-skipping mode. The benefit of this mode is
that the LT3689 will enter full frequency standard PWM
operation at a lower output load current than when in
Burst Mode operation. The front page application circuit
will switch at full frequency at output loads higher than
TheLT3689iscapableofoperatingineitherlowrippleBurst
Modeoperationorpulse-skippingmode,whichisselected
using the SYNC pin. See the Synchronization section for
details. To enhance efficiency at light loads, the LT3689
can be operated in low ripple Burst Mode operation that
keeps the output capacitor charged to the proper voltage
whileminimizingtheinputquiescentcurrent.DuringBurst
Modeoperation, theLT3689deliverssinglecycleburstsof
current to the output capacitor followed by sleep periods
about 15mA at 12V .
IN
V
OUT
V
10mV/DIV
OUT
50mV/DIV
I
L
0.2A/DIV
I
L
250mA/DIV
V
SW
5V/DIV
3689 F04
3689 F05
10μs/DIV
5μs/DIV
V
LOAD
= 12V, FRONT PAGE APPLICATION
IN
I
= 8mA
Figure 4. Transient Load Response of the LT3689 Front
Page Application as the Load Current is Stepped from
360mA to 720mA. VOUT = 3.3V, VIN = 12V
Figure 5. Burst Mode Operation
3689fa
19
LT3689/LT3689-5
APPLICATIONS INFORMATION
BST and OUT Pin Considerations
age source. Ensure that the maximum voltage ratings of
the BST and OUT pins are not exceeded.
Capacitor C3 and the internal boost Schottky diode (see
the Block Diagram) are used to generate a boost voltage
thatishigherthantheinputvoltage. Inmostcases, a0.1μF
capacitor will work well. Figure 6 shows three ways to ar-
range the boost circuit. The BST pin must be more than
2.3V above the SW pin for best efficiency. For outputs of
3V and above, the standard circuit (Figure 6a) is best. For
outputs between 2.8V and 3V, use a 0.47μF boost capaci-
tor. A 2.5V output presents a special case because it is
marginally adequate to support the boosted drive stage
while using the internal boost diode. For reliable BST pin
operation with 2.5V outputs, use a good external Schottky
diode (such as ON Semiconductor’s MBR0540), and a
0.47μF boost capacitor (see Figure 6b). For lower output
voltages,theboostdiodecanbetiedtotheinput(Figure6c),
or to another supply greater than 2.8V. The circuit in
Figure 6a is more efficient because the BST pin current
and OUT pin quiescent current comes from a lower volt-
The minimum operating voltage of an LT3689 application
is limited by the minimum input voltage (3.7V) and by the
maximumdutycycle,asoutlinedintheMinimumOperating
Voltage Range section. For proper start-up, the minimum
inputvoltageisalsolimitedbytheboostcircuit.Iftheinput
voltage is ramped slowly, or the LT3689 is turned on with
its EN/UVLO pin when the output is already in regulation,
thentheboostcapacitormaynotbefullycharged.Because
the boost capacitor is charged with the energy stored in
the inductor, the circuit will rely on some minimum load
current to get the boost circuit running properly. This
minimum load will depend on input and output voltages,
andonthearrangementoftheboostcircuit. Theminimum
load generally goes to zero once the circuit has started.
For lower start-up voltage, the boost diode can be tied to
V ; however, this restricts the input range to one-half of
IN
the absolute maximum rating of the BST pin.
V
V
OUT
OUT
D2
OUT
OUT
BST
BST
SW
V
V
IN
V
V
IN
LT3689
LT3689
IN
IN
C3
C3
SW
GND
GND
2.2μF
2.2μF
(6a) For V
> 2.8V
OUT
(6b) For 2.5V < V
< 2.8V
OUT
V
OUT
OUT
BST
SW
V
V
IN
LT3689
IN
C3
GND
2.2μF
3689 F06
(6c) For V
< 2.5V; V
= 30V
IN(MAX)
OUT
Figure 6. Three Circuits for Generating the Boost Voltage
3689fa
20
LT3689/LT3689-5
APPLICATIONS INFORMATION
Another way to lower the start-up voltage is by using a
resistor divider on the EN/UVLO pin (see the Shutdown
and Undervoltage Lockout section). A resistor divider on
EN/UVLO pin programs the turn-on threshold to slightly
dutycyclecanbeveryhigh.Thisreducestheminimuminput
voltagetoapproximately300mVaboveV . Athigherload
OUT
currents, the inductor current is continuous and the duty
cycle is limited by the maximum duty cycle of the LT3689,
requiring a higher input voltage to maintain regulation.
higherthantheminimumV voltagerequiredtorunatfull
IN
load. Below the EN/UVLO high voltage, the part will stay
Soft-Start
shut off and the output cap will remain discharged during
the worse case slow V ramp. When the EN/UVLO pin
IN
The LT3689 has an internal soft-start that gradually ramps
up the switch current limit from about 100mA to the
switch’s maximum current limit in typical value of 150μs,
as shown in Figure 8. This feature limits the inrush current
duringstart-upandpreventstheswitchcurrentfromspik-
ing when the EN/UVLO pin crosses the UVLO threshold.
crosses the EN/UVLO high threshold, the part will turn on
and the empty output capacitor will provide enough load
to bring the output voltage in regulation. This technique
significantly lowers the start-up voltage of the circuit. The
plot in Figure 7 depicts the minimum load required to start
and run (as a function of input voltage). It also depicts the
benefit of programming the EN/UVLO threshold to lower
the start-up voltage at low load currents. At light loads, the
inductor current becomes discontinuous and the effective
A soft-start sequence is also initiated right after a V
IN
overvoltage/undervoltage lockout, or thermal shutdown
fault in order to prevent the switch current from suddenly
jumping to its maximum current limit.
8.0
6.0
TO START:
EN/UVLO TIED TO V
TO START:
IN
EN/UVLO TIED TO V
IN
7.5
7.0
6.5
6.0
5.5
5.0
5.5
5.0
4.5
4.0
3.5
3.0
TO START: EN/UVLO HIGH
THRESHOLD = 4.85V
TO START: EN/UVLO HIGH
THRESHOLD = 6.15V
TO RUN
TO RUN
1
10
100
1000
1
10
100
1000
LOAD (mA)
3589 F07a
LOAD (mA)
= 800KHz
3589 F07b
V
= 5V
f
= 800KHz
= 25°C
V
= 3.3V f
OUT
SW
A
OUT SW
L = 8.2μH
T
L = 8.2μH
T = 25°C
A
Figure 7. LT3689 Minimum VIN to Start and Run vs Load
V
OUT
2V/DIV
I
L
0.5A/DIV
I
VIN
0.2A/DIV
3689 F08
20μs/DIV
V
V
= 12V f = 2MHz
IN
= 5V
C
= 1μF CERAMIC + 100μF ELECTROLYTIC
OUT
IN
Figure 8. Internal Soft-Start
3689fa
21
LT3689/LT3689-5
APPLICATIONS INFORMATION
Synchronization
should be calculated using the RT programmed frequency
to avoid subharmonic oscillation.
ToselectlowrippleBurstModeoperation,tietheSYNCpin
below0.3V(thiscanbegroundoralogicoutput).Synchro-
nizing the LT3689 oscillator to an external frequency can
be done by connecting a square wave (with positive and
negative pulse width >80ns) to the SYNC pin. The square
wave amplitude should have valleys that are below 0.3V
and peaks that are above 1V (up to 6V).
Shutdown and Undervoltage Lockout
Figure 9 shows how to add undervoltage lockout (UVLO)
to the LT3689. Typically, UVLO is used in situations where
the input supply is current limited, or has a relatively high
source resistance. A switching regulator draws constant
power from the source, so source current increases as
source voltage drops. This looks like a negative resistance
loadtothesourceandcancausethesourcetocurrentlimit
or latch low under low source voltage conditions. UVLO
prevents the regulator from operating at source voltages
where the problems might occur. An internal comparator
The LT3689 will not enter Burst Mode operation at low
output loads while synchronized to an external clock, but
instead will skip pulses to maintain regulation.
TheLT3689maybesynchronizedovera350kHzto2.5MHz
range. The R resistor should be chosen to set the LT3689
T
switchingfrequency20%belowthelowestsynchronization
will force the part into shutdown below the minimum V
IN
input. For example, if the synchronization signal will be
of 3.4V. This feature can be used to prevent excessive
discharge of battery-operated systems. If an adjustable
UVLOthresholdisrequired, theEN/UVLOpincanbeused.
The threshold voltage of the EN/UVLO pin comparator is
1.26V. CurrenthysteresisisaddedabovetheENthreshold.
This can be used to set voltage hysteresis of the UVLO
using the following:
350kHz and higher, the R should be chosen for 280kHz.
T
To assure reliable and safe operation, the LT3689 will only
synchronize when the output voltage is above 90% of its
regulated voltage. It is therefore necessary to choose a
large enough inductor value to supply the required output
current at the frequency set by the R resistor (see the
T
Inductor Selection section). It is also important to note
VH VL
R3 =
4k
that the slope compensation is set by the R value. When
T
4µA
the sync frequency is much higher than the one set by
R , the slope compensation will be significantly reduced,
1.26V
VH 1.26V
R3
T
R4 =
which may require a larger inductor value to prevent
4µA
subharmonic oscillation. The minimum inductor value
LT3689
V
IN
V
C
–
+
1.25V
EN/UVLO
R3
R4
C1
SS
4μA
3689 F09
Figure 9. Undervoltage Lockout
3689fa
22
LT3689/LT3689-5
APPLICATIONS INFORMATION
Example:switchingshouldnotstartuntiltheinputisabove
4.40V, and is to stop if the input falls below 4V.
POR Comparator Overdrive in the Typical Performance
Characteristics section). This prevents spurious resets
caused by output voltage transients such as load steps
or short brownout conditions without sacrificing the DC
reset threshold accuracy.
VH = 4.40V,VL = 4V
4.40V−4V
R3 =
− 4k = 95.3k
4µA
Watchdog
1.26V
4.40V−1.26V
The LT3689 includes an adjustable watchdog timer that
monitors a μP’s activity. If a code execution error occurs
in a μP, the watchdog will detect this error and will set the
WDO low. This signal can be used to interrupt a routine
or to reset a microprocessor.
R4 =
= 43.2k
(Nearest 1% Resistor)
– 4µA
95.3k
Keep the connection from the resistor to the EN/UVLO
pin short and make sure the interplane or surface capaci-
tance to switching nodes is minimized. If high resistor
valuesareused,theEN/UVLOpinshouldbebypassedwith
a 1nF capacitor to prevent coupling problems from the
switch node.
The watchdog is operated either in timeout or window
mode. In timeout mode, the microprocessor needs to
toggle the WDI pin before the watchdog timer expires, to
keep the WDO pin high. If no WDI pulse (either positive or
negative)appearsduringtheprogrammedtimeoutperiod,
then the circuitry will pull WDO low. During normal opera-
tion, the WDI input signal’s high to low, and low to high
transitionperiodsshouldbesetlowerthanthewatchdog’s
programmed time to keep WDO inactive.
Output Voltage Monitoring
The LT3689 provides power supply monitoring for micro-
processor-based systems. The features include power-on
reset (POR) and watchdog timing.
In window mode, the watchdog circuitry is triggered by
negativeedgesontheWDIpin.Thewindowmoderestricts
the WDI pin’s negative going pulses to appear inside a
programmed time window (see the Timing Diagram) to
prevent WDO from going low. If more than two pulses are
registeredinthewatchdoglowerboundaryperiod,the WDO
is forced to go low. The WDI edges are ignored while the
A precise internal voltage reference and glitch immune
precision POR comparator circuit monitor the LT3689
output voltage. The switcher’s output voltage must be
above 90% of programmed value for RST not to be as-
serted (refer to the Timing Diagram). The LT3689 will
assert RST during power-up, power-down and brownout
conditions. Once the output voltage rises above the RST
threshold, the adjustable reset timer is started and RST is
released after the reset timeout period. On power-down,
once the output voltage drops below RST threshold, RST
is held at a logic low. The reset timer is adjustable using
external capacitors. The RST pin has a weak pull-up to
the OUT pin.
C
capacitor charges from 0V to 200mV right after a
WDT
low to high transition on the WDO or RST pin. The WDO
also goes low if no negative edge is supplied to the WDI
pininthewatchdogupperboundaryperiod. Duringacode
executionerror,themicroprocessorwilloutputWDIpulses
that would be either too fast or too slow. This condition
will assert WDO and force the microprocessor to reset the
program. In window mode, the WDI signal frequency is
boundedbyanupperandlowerlimitfornormaloperation.
The WDI input frequency period should be higher than the
The POR comparator is designed to be robust against FB
pinnoise,whichcouldpotentiallyfalsetriggertheRSTpin.
The POR comparator lowpass filters the first stage of the
comparator.Thisfilterintegratestheoutputofthecompara-
torbeforeassertingtheRST.Thebenefitofaddingthisfilter
is that any transients at the buck regulator’s output must
be of sufficient magnitude and duration before it triggers
a logic change in the output (see the Typical Transient vs
t
period, and lower than the t
period, to keep WDO
WDL
WDU
high under normal conditions. The window mode’s t
WDL
and t
times have a fixed ratio of 31 between them.
WDU
These times can be increased or decreased by adjusting
an external capacitor on the C pin.
WDT
3689fa
23
LT3689/LT3689-5
APPLICATIONS INFORMATION
Inbothwatchdogmodes,whenWDOisasserted,thereset
timer is enabled. Any WDI pulses that appear while the
reset timer is running are ignored. When the reset timer
expires, the WDO is allowed to go high again. Therefore,
if no input is applied to the WDI pin, then the watchdog
circuitry produces a train of pulses on the WDO pin. The
high time of this pulse train is equal to the timeout period,
and low time is equal to the reset period. Also, WDO and
RST cannot be logic low simultaneously. If WDO is low
and RST goes low, then WDO will go high.
high. If watchdog is disabled, leaving this pin open is
acceptable.
Selecting the Reset Timing Capacitors
The reset timeout period is adjustable in order to accom-
modate a variety of microprocessor applications. The
reset timeout period, (t ), is adjusted by connecting a
RST
capacitor, C
, between the C
value of this capacitor is determined by:
pin and ground. The
POR
POR
pF
ms
C
POR = tRST • 432
The WDE pin allows the user to turn on and off the
watchdog function. Do not leave this pin open. Tie it high
or low to turn watchdog off or on, respectively. The W/T
pin enables/disables the window/timeout mode. Leaving
this pin open is fine and will put the watchdog in window
mode. It has a weak pull-down to ground. The WDI pin
has an internal 2μA weak pull-up that keeps the WDI pin
This equation is accurate for reset timeout periods of
5ms, or greater. To program faster timeout periods, see
the Reset Timeout Period vs Capacitance graph in the
Typical Performance Characteristics section. Leaving the
C
pin unconnected will generate a minimum reset
POR
C
= 10nF, t
= 5.8ms
WDL
WDT
WDI
5V/DIV
V
OUT
2V/DIV
WDO
2V/DIV
RST
2V/DIV
C
WDT
1V/DIV
t
= 165ms
POR
RST
C
POR
C
= 71nF
1V/DIV
C
POR
1V/DIV
3689 F10
3689 F11
50ms/DIV
5ms/DIV
Figure 10. Reset Timer Waveforms
Figure 11. Window Watchdog Waveforms (W/T = Low)
t
= 165ms, C
= 71nF
POR
RST
WDI
5V/DIV
WDO
2V/DIV
t
= 180ms, C
= 10nF
WDT
WDU
C
WDT
1V/DIV
C
POR
1V/DIV
3689 F12
100ms/DIV
Figure 12. Timeout Watchdog Waveforms (W/T = High)
3689fa
24
LT3689/LT3689-5
APPLICATIONS INFORMATION
timeout of approximately 25μs. Maximum reset timeout
is limited by the largest available low leakage capacitor.
The accuracy of the timeout period will be affected by
capacitor leakage (the nominal charging current is 2μA)
and capacitor tolerance. A low leakage ceramic capacitor
is recommended.
Shorted and Reversed Input Protection
If an inductor is chosen to prevent excessive saturation,
the LT3689 will tolerate a shorted output. When operat-
ing in short-circuit condition, the LT3689 will reduce
its frequency until the valley current is at a typical value
of 1.2A (see Figure 13). There is another situation to
consider in systems where the output will be held high
when the input to the LT3689 is absent. This may occur in
batterychargingapplicationsorinbatterybackupsystems
where a battery or some other supply is diode ORed with
Selecting the Watchdog Timing Capacitor
The watchdog timeout period is adjustable and can be
optimized for software execution. The watchdog upper
boundary timeout period, t
is adjusted by connect-
WDU
, between the C
ing a capacitor, C
pin and ground.
WDT
WDT
Given a specified watchdog timeout period, the capacitor
is determined by:
V
SW
20V/DIV
pF
ms
C
WDT = tWDU • 55
I
L
0.5A/DIV
This equation is accurate for upper boundary periods of
20ms, or greater. The watchdog lower boundary period
3689 F13
(t
)hasafixedrelationshiptot
foragivencapacitor.
10μs/DIV
WDL
WDU
The t
period is related to t
by the following:
WDL
WDU
Figure 13. The LT3689 Reduces its Frequency to Below
100kHz to Protect Against Shorted Output with 36V Input
1
31
tWDL
=
• tWDU
Inaddition, thefollowingequationcanbeusedtocalculate
the watchdog lower boundary period for a given C
capacitor value.
WDT
OUT
V
V
BST
SW
IN
IN
1.7nF
ms
LT3689
V
CWDT = tWDL
•
OUT
DA
FB
+
EN/UVLO
GND
These lower boundary period equations are accurate for a
t
of 3ms, or greater. To program faster t and t
WDL
WDU
WDL
periods, see the Watchdog Upper and Lower Boundary
PeriodsvsCapacitancegraphsintheTypicalPerformance
Characteristics section.
3689 F14
Figure 14. Diode D4 Prevents a Shorted Input from
Discharging a Backup Battery Tied to the Output; It Also
Protects the Circuit from a Reversed Input. The LT3689
Runs Only When the Input is Present
LeavingtheC
pinunconnectedwillgenerateaminimum
WDT
watchdog timeout of approximately 200μs. Maximum
timeout is limited by the largest available low leakage
capacitor. The accuracy of the timeout period will be af-
fected by capacitor leakage (the nominal charging current
is 2μA) and capacitor tolerance. A low leakage ceramic
capacitor is recommended.
3689fa
25
LT3689/LT3689-5
APPLICATIONS INFORMATION
the LT3689’s output. If the V pin is allowed to float and
PCB Layout
IN
the EN/UVLO pin is held high (either by a logic signal or
For proper operation and minimum EMI, care must be
taken during printed circuit board layout. Figure 15 shows
the recommended component placement with trace,
ground plane and via locations. Note that large, switched
becauseitistiedtoV ),thentheLT3689’sinternalcircuitry
IN
will pull its quiescent current through its SW pin. This is
fine if the system can tolerate a few mA in this state. If the
EN/UVLO pin is grounded, the SW pin current will drop to
currents flow in the LT3689’s V and SW pins, the catch
IN
essentially zero. However, if the V pin is grounded while
IN
diode (D1) and the input capacitor (C1). The loop formed
by these components should be as small as possible.
These components, along with the inductor and output
capacitor, should be placed on the same side of the circuit
board. Place a local, unbroken ground plane below these
components. The SW and BST nodes should be as small
the output is held high, then parasitic diodes inside the
LT3689 can pull large currents from the output through
the SW pin and the V pin. Figure 14 shows a circuit that
IN
will run only when the input voltage is present and that
protects against a shorted or reversed input.
Figure 15. Example Layout for QFN Package.
A Good PCB Layout Ensures Proper Low EMI Operation
3689fa
26
LT3689/LT3689-5
APPLICATIONS INFORMATION
as possible. Finally, keep the FB node small so that the
ground traces will shield them from the SW and BOOST
nodes. The Exposed Pad on the bottom of the package
must be soldered to ground so that the pad acts as a heat
sink. To keep thermal resistance low, extend the ground
plane as much as possible, and add thermal vias under
and near the LT3689 to additional ground planes within
the circuit board and on the bottom side.
be derated as the ambient temperature approaches 125°C
(150°CforH-grade).Aboardmeasuring5cm×7.5cmwith
a top layer layout similar to Figure 15 was evaluated in
stillairat3.3V , 700kHzswitchingfrequency. At700mA
OUT
load, the temperature reached approximately 12°C above
ambient for input voltages equal to 12V and 24V. Power
dissipationwithintheLT3689canbeestimatedbycalculat-
ing the total power loss from an efficiency measurement
and subtracting the catch diode loss. The die temperature
is calculated by multiplying the LT3689 power dissipation
by the thermal resistance from junction-to-ambient.
High Temperature Considerations
The PCB must provide heat sinking to keep the LT3689
cool. The Exposed Pad on the bottom of the package
must be soldered to a ground plane. This ground should
be tied to large copper layers below with thermal vias;
these layers will spread the heat dissipated by the LT3689.
Placing additional vias can reduce thermal resistance
further. Because of the large output current capability of
the LT3689, it is possible to dissipate enough heat to raise
the junction temperature beyond the absolute maximum
of 125°C (150°C for H-grade). When operating at high
ambient temperatures, the maximum load current should
Other Linear Technology Publications
Application Notes 19, 35 and 44 contain more detailed
descriptions and design information for buck regulators
and other switching regulators. The LT1376 data sheet
has a more extensive discussion of output ripple, loop
compensation and stability testing. Design Note 318
shows how to generate a bipolar output supply using a
buck regulator.
TYPICAL APPLICATIONS
5V Step-Down Converter
V
IN
6.3V TO 36V
TRANSIENT
TO 60V
C1
1μF
V
IN
EN/UVLO
OUT
BST
WINDOW TIMEOUT
W/T
C2
0.1μF
L1
12μH
WATCHDOG_DEFEAT
WDE
μP
I/O
I/O
WDI
WDO
RST
SW
LT3689
C4
5.6pF
D1
RESET
R1
536k
DA
FB
5V
700mA
C
C
WDT
RT
SYNC
C3
10μF
C6
R2
POR
10nF
WDU
102k
GND
f
t
= 182ms
C5
R
T
68nF
= 1MHz
SW
12.7k
t
= 157ms
RST
3689 TA02
L1: CDR125NP-12MC
D1: MBRM140
C1, C2, C3: X7R or X5R
3689fa
27
LT3689/LT3689-5
TYPICAL APPLICATIONS
3.3V Step-Down Converter
V
IN
4.5V TO 36V
TRANSIENT
TO 60V
C1
2.2μF
V
IN
EN/UVLO
OUT
BST
WINDOW TIMEOUT
WATCHDOG_DEFEAT
W/T
C2
0.1μF
L1
12μH
WDE
μP
I/O
I/O
WDI
WDO
RST
SW
LT3689
C4
10pF
D1
RESET
R1
316k
DA
FB
3.3V
700mA
C
C
WDT
POR
RT
SYNC
C3
22μF
C6
10nF
WDU
R2
100k
GND
f
t
= 182ms
C5
R
T
68nF
= 700kHz
SW
20.5k
t
= 157ms
RST
3689 TA03
L1: CDR125NP-12MC
D1: MBRM140
C1, C2, C3: X7R or X5R
5V, 2MHz Step-Down Converter
V
IN
6.3V TO 18V
TRANSIENT
TO 60V
C1
1μF
V
EN/UVLO
OUT
IN
BST
WINDOW TIMEOUT
W/T
L1
10μH
C2
0.1μF
WATCHDOG_DEFEAT
WDE
μP
I/O
I/O
WDI
WDO
RST
SW
LT3689-5
D1
RESET
C4
2.7pF
DA
FB
RT
5V
700mA
C
C
WDT
POR
C3
4.7μF
C6
SYNC
10nF
WDU
GND
t
= 182ms
C5
R
T
68nF
f
= 2MHz
SW
4.02k
t
= 157ms
RST
3689 TA04
C1, C2, C3: X7R OR X5R
D1: MBRM140
3689fa
28
LT3689/LT3689-5
PACKAGE DESCRIPTION
MSE Package
16-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1667 Rev A)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 p 0.102
(.112 p .004)
2.845 p 0.102
(.112 p .004)
0.889 p 0.127
(.035 p .005)
1
8
0.35
REF
5.23
(.206)
MIN
1.651 p 0.102
(.065 p .004)
1.651 p 0.102
(.065 p .004)
3.20 – 3.45
(.126 – .136)
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
DETAIL “B”
16
9
0.305 p 0.038
0.50
(.0197)
BSC
NO MEASUREMENT PURPOSE
4.039 p 0.102
(.159 p .004)
(NOTE 3)
(.0120 p .0015)
TYP
0.280 p 0.076
(.011 p .003)
RECOMMENDED SOLDER PAD LAYOUT
16151413121110
9
REF
DETAIL “A”
0.254
(.010)
3.00 p 0.102
(.118 p .004)
(NOTE 4)
0o – 6o TYP
4.90 p 0.152
(.193 p .006)
GAUGE PLANE
0.53 p 0.152
(.021 p .006)
1 2 3 4 5 6 7 8
DETAIL “A”
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 p 0.0508
(.004 p .002)
MSOP (MSE16) 0608 REV A
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3689fa
29
LT3689/LT3689-5
PACKAGE DESCRIPTION
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691)
0.70 p0.05
3.50 p 0.05
2.10 p 0.05
1.45 p 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 p0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 s 45o CHAMFER
R = 0.115
TYP
0.75 p 0.05
3.00 p 0.10
(4 SIDES)
15 16
PIN 1
TOP MARK
(NOTE 6)
0.40 p 0.10
1
2
1.45 p 0.10
(4-SIDES)
(UD16) QFN 0904
0.200 REF
0.25 p 0.05
0.00 – 0.05
0.50 BSC
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3689fa
30
LT3689/LT3689-5
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
04/10 Added LT3689-5 Fixed Output Voltage Option
1–32
3689fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LT3689/LT3689-5
TYPICAL APPLICATION
1.8V Step-Down Converter with System Reset Generated by
Watchdog Timing or Output Voltage Failure
V
IN
C1
1μF
3.6V TO 16V
V
EN/UVLO
OUT
TRANSIENT TO 27V
IN
BST
WINDOW TIMEOUT
W/T
L1
C2
WATCHDOG_DEFEAT
WDE
μP
4.7μH
0.1μF
I/O
WDI
WDO
RST
SW
1.8V
700mA
LT3689
C4
15pF
D1
RESET
R1
127k
DA
FB
RT
C
C
WDT
POR
C5
C3
C6
10nF
WDU
R
T
R2
SYNC
68nF
RST
47μF
14.7k
102k
GND
L1: WE-PD2: 7447745047
D1: MBRM140
C1, C2, C3: X7R OR X5R
t
= 182ms
t
= 157ms
3689 TA05
f
= 900kHz
SW
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LT1766
60V, 1.2A (I ), 200kHz, High Efficiency Step-Down DC/DC V : 5.5V to 60V, V
= 1.20V, I = 2.5mA, I = 25μA, TSSOP-16
Q SD
OUT
IN
OUT(MIN)
Converter
and TSSOP-16E Packages
LT1936
36V, 1.4A (I ), 500kHz High Efficiency Step-Down DC/DC V : 3.6V to 36V, V
= 1.2V, I = 1.9mA, I <1μA, MS8E Package
OUT
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
OUT(MIN)
Q
SD
Converter
LT1976/LT1977 60V, 1.2A (I ), 200kHz/500kHz, High Efficiency Step-Down V : 3.3V to 60V, V
= 1.20V, I = 100μA, I <1μA, TSSOP-16E
Q SD
OUT
IN
DC/DC Converter with Burst Mode Operation
Package
LT3434/LT3435 60V, 2.4A (I ), 200kHz/500kHz, High Efficiency Step-Down V : 3.3V to 60V, V
= 1.20V, I = 100mA, I <1μA, TSSOP-16E
Q SD
OUT
IN
DC/DC Converter with Burst Mode Operation
Package
LT3437
LT3480
60V, 400mA (I ), Micropower Step-Down DC/DC
V : 3.3V to 60V, V
= 1.25V, I = 100μA, I <1μA, 3mm × 3mm
Q SD
OUT
IN
Converter with Burst Mode Operation
DFN-10 and TSSOP-16E Packages
36V with Transient Protection to 60V, 2A (I ), 2.4MHz,
V : 3.6V to 38V, V
= 0.78V, I = 70μA, I <1μA, 3mm × 3mm
Q SD
OUT
IN
OUT(MIN)
High Efficiency Step-Down DC/DC Converter with Burst
Mode Operation
DFN-10 and MSOP-10E Packages
LT3481
34V with Transient Protection to 36V, 2A (I ), 2.8MHz,
V : 3.6V to 34V, V = 1.26V, I = 50mA, I <1μA, 3mm × 3mm
OUT
IN
OUT(MIN)
Q
SD
High Efficiency Step-Down DC/DC Converter with Burst
Mode Operation
DFN-10 and MSOP-10E Packages
LT3493
LT3500
LT3505
LT3507
LT3508
LT3682
LT3684
LT3685
36V, 1.4A (I ), 750kHz High Efficiency Step-Down DC/DC
V : 3.6V to 36V, V
= 0.8V, I = 1.9mA, I <1μA, 2mm × 3mm
Q SD
OUT
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
Converter
DFN-6 Package
36V, 40V
, 2A, 2.5MHz High Efficiency Step-Down DC/DC
V : 3.6V to 36V, V
= 0.8V, I = 2.5mA, I <10μA, 3mm × 3mm
Q SD
MAX
IN
Converter and LDO Controller
DFN-10 Package
36V with Transient Protection to 40V, 1.4A (I ), 3MHz,
V : 3.6V to 34V, V
= 0.78V, I = 2mA, I = 2μA, 3mm × 3mm
Q SD
OUT
IN
High Efficiency Step-Down DC/DC Converter
DFN-8 and MSOP-8E Packages
36V 2.5MHz, Triple (2.4A + 1.5A + 1.5A (I )) with LDO
V : 3.6V to 36V, V
= 0.8V, I = 2.5mA, I = 10μA, TSSOP-16
OUT
IN
OUT(MIN) Q SD
Controller High Efficiency Step-Down DC/DC Converter
and TSSOP-16E Packages
36V with Transient Protection to 40V, Dual 1.4A (I ),
V : 3.7V to 37V, V
= 0.8V, I = 4.6mA, I = 1μA, 4mm × 4mm
OUT
IN
OUT(MIN)
Q
SD
3MHz, High Efficiency Step-Down DC/DC Converter
QFN-24 and TSSOP-16E Packages
36V, 60V
, 1A, 2.2MHz High Efficiency Micropower Step-
V : 3.6V to 36V, V
= 0.8V, I = 75mA, I <1μA, 3mm × 3mm
Q SD
MAX
IN
OUT(MIN)
Down DC/DC Converter
DFN-12 Package
34V with Transient Protection to 36V, 2A (I ), 2.8MHz,
V : 3.6V to 34V, V
= 1.26V, I = 850μA, I <1μA, 3mm × 3mm
Q SD
OUT
IN
OUT(MIN)
High Efficiency Step-Down DC/DC Converter
DFN-10 and MSOP-10E Packages
36V with Transient Protection to 60V, 2A (I ), 2.4MHz,
V : 3.6V to 38V, V
= 0.78V, I = 70μA, I <1μA, 3mm × 3mm
Q SD
OUT
IN
OUT(MIN)
High Efficiency Step-Down DC/DC Converter
DFN-10 and MSOP-10E Packages
3689fa
LT 0410 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
32
●
●
© LINEAR TECHNOLOGY CORPORATION 2010
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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