LT3692AHUH#TRPBF [Linear]
LT3692A - Monolithic Dual Tracking 3.5A Step-Down Switching Regulator; Package: QFN; Pins: 32; Temperature Range: -40°C to 125°C;
| 型号： | LT3692AHUH#TRPBF |
| 厂家： | 
Linear |
| 描述： | LT3692A - Monolithic Dual Tracking 3.5A Step-Down Switching Regulator; Package: QFN; Pins: 32; Temperature Range: -40°C to 125°C 开关 |
| 文件： | 总36页 (文件大小：643K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3692
Monolithic Dual Tracking
3.5A Step-Down
Switching Regulator
DescripTion
The LT®3692 is a dual current mode PWM step-down
DC/DCconverterwithtwointernal3.8Aswitches.Indepen-
dentinputvoltage,shutdown,feedback,soft-start,current
limit and comparator pins for each channel simplify com-
plexpowersupplytrackingandsequencingrequirements.
FeaTures
n
Wide Input Range:
– Operation from 3V to 36V
– OVLO Protects Circuit Through 60V Transients
Independent Supply, Shutdown, Soft-Start,
n
Programmable Current Limit and Programmable
Power Good for Each 3.5A Regulator
To optimize efficiency and component size, both convert-
ers have a programmable maximum current limit and are
synchronized to either a common external clock input,
or a resistor settable fixed 250kHz to 2.25MHz internal
oscillator. A frequency divider is provided for channel 1
to further optimize component size. At all frequencies, a
180° phase relationship between channels is maintained,
reducingvoltagerippleandcomponentsize.Aclockoutput
is available for synchronizing multiple regulators.
n
Die Temperature Monitor
n
Adjustable/Synchronizable Fixed Frequency
Operation from 250kHz to 2.25MHz with
Synchronized Clock Output
n
Independent Synchronized Switching Frequencies
Optimize Component Size
n
Antiphase Switching
n
Outputs Can Be Paralleled
n
Flexible Output Voltage Tracking
n
n
n
Minimum input to output voltage ratios are improved by
allowingtheswitchtostayonthroughmultipleclockcycles
onlyswitchingoffwhentheboostcapacitorneedsrecharg-
ing. Independent channel operation can be programmed
using the SHDN pin. Disabling both converters reduces
the total quiescent to <10µA.
Enhanced Short-Circuit Protection
Low Dropout: 95% Maximum Duty Cycle
5mm × 5mm QFN Package
applicaTions
n
Automotive Supplies
Distributed Supply Regulation
L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective
owners.
n
Independent Synchronized Switching Frequencies
Extend Full Frequency Input Range
Typical applicaTion
Dual 1.8V/3.5A and 5V/3.5A Step-Down Converter
CLKOUT
V
IN
6V TO 32V
4.7µF
×2
SW1
V
V
IN2
IN1
SHDN1
BST1
SHDN2
BST2
V
SW1
IND1
SW2
IND2
OUT2
SW2
6.8µH
6.8µH
42.2k
0.47µF
1µF
V
OUT1
3692 TA01b
LT3692
V
OUT2
V
IN
= 12V
1µs/DIV
1.8V 3.5A
500kHz/
250kHz
5V 3.5A
500kHz
V
OUT1
V
OUT2
FB2
100µF
8.06k
47µF
10k
FB1
100k
8.06k
×2
CMPI1
CMPO1
SS1
CMPI2
CMPO2
SS2
143k
CLKOUT
SW1
PG2
SS2
7.15k
60.4k
ILIM2
ILIM1
DIV
ILIM2
CLOCKOUT
500kHz
CLKOUT
60.4k
V
C2
V
C1
60.4k
47pF
680pF
330pF
36.5k
RT/SYNC
T
J
0.1µF
GND
33pF
SW2
13.0k
17.8k
0.1µF
3692 TA01c
3692 TA01a
V
IN
= 24V
1µs/DIV
3692fa
1
For more information www.linear.com/3692
LT3692
absoluTe MaxiMuM raTings
pin conFiguraTion
(Note 1)
TOP VIEW
V
V
, SHDN1/2, CMPO1/2............................ 40V/–0.3V
Transient (Note 2)................................ 60V/–0.3V
IN1/2
IN1/2
32 31 30 29 28 27 26 25
SW1/2....................................................................V
IN1/2
BST1
CMPO1
CMPI1
FB1
1
2
3
4
5
6
7
8
24 ILIM1
BST1/2 ........................................................... 60V/–0.3V
23
22
21
20
19
18
V
C1
BST1/2 Pin Above SW1/2..........................................25V
RT/SYNC
CLKOUT
IND1/2, V
.........................................40V/–0.3V, 7A
OUT1/2
33
GND
FB1/2, CMPI1/2, SS1/2................................................5V
RT/SYNC .....................................................................5V
DIV, ILIM1/2.............................................................2.5V
FB2
T
J
CMPI2
CMPO2
BST2
DIV
V
C2
17 ILIM2
V
, T .............................................................. 100µA
C1/2
J
9
10 11 12 13 14 15 16
UH PACKAGE
Operating Junction Temperature Range (Note 3)
LT3692EUH........................................ –40°C to 125°C
LT3692IUH......................................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
32-LEAD (5mm × 5mm) PLASTIC QFN
θ
JA
= 35°C/W
EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB
*DO NOT CONNECT
orDer inForMaTion
LEAD FREE FINISH
LT3692EUH#PBF
LT3692IUH#PBF
TAPE AND REEL
PART MARKING*
3692
3692
PACKAGE DESCRIPTION
32-Lead (5mm × 5mm) Plastic QFN
32-Lead (5mm × 5mm) Plastic QFN
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
LT3692EUH#TRPBF
LT3692IUH#TRPBF
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
The l denotes the specifications which apply over the full operating
elecTrical characTerisTics
temperature range, otherwise specifications are at TA = 25°C. VVIN1/2 = 15V unless otherwise specified. (Note 3)
PARAMETER
CONDITIONS
MIN
TYP
1.32
1.5
2.8
38
MAX
1.4
5
UNITS
V
l
SHDN Voltage Threshold Ch 1/2 (Note 4)
SHDN Input Current Ch 1/2
1.24
V
V
= 1.3V
= 0V, V
µA
V
SHDN
V
V
V
V
V
V
Undervoltage Lockout (Note 5)
= 0V, V = 0V
IND1/2
2.5
36
3.1
41
IN1
FB1/2
VOUT1/2
Overvoltage Lockout Ch 1/2 (Note 6)
V
IN
l
l
Shutdown Current
Shutdown Current
Quiescent Current
Quiescent Current
V
SHDN
V
SHDN
V
FB1/2
V
FB1/2
V
VC1/2
= 0V
6
10
µA
µA
mA
µA
mV
IN1
IN2
IN1
IN2
= 0V
0
2
= 0.9V
= 0.9V
= 1V
3
4
5
400
790
630
806
1000
822
l
Feedback Voltage Ch 1/2
3692fa
2
For more information www.linear.com/3692
LT3692
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VVIN1/2 = 15V unless otherwise specified. (Note 3)
PARAMETER
CONDITIONS
MIN
780
–12
0
TYP
806
0
MAX
830
12
UNITS
mV
l
l
l
Feedback Voltage Regulation
Feedback Voltage Offset Ch 1 to Ch 2
Feedback Bias Current Ch 1/2
V
VIN1/2
V
VC1/2
V
FB1/2
= 3 to 40V, V
= 0.6 to 1.6V
VC1/2
= 1V
mV
= 0.8V, V
= 1V
85
200
nA
VC1/2
T Output Voltage (Note 7)
J
T = 25°C, I = 25µA, Temperature = 25°C
250
1.23
–380
mV
V
mV
J
TJ
I
I
= 25µA, Temperature = 125°C
TJ
TJ
= 25µA, Temperature = –40°C
l
T Error
–60
350
19
0
400
25
60
450
31
mV
µMho
µA
µA
V
J
Error Amp g Ch 1/2
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 1V, I
VC1/2
=
5µA
m
VC1/2
Error Amp Source Current Ch 1/2
Error Amp Sink Current Ch 1/2
Error Amp High Clamp Ch 1/2
= 0.6V, V
= 1V
FB1/2
VC1/2
=1V, V
= 1V
VC1/2
22
28
34
FB1/2
= 0.6V
= 0.6V
= 0.9V, V
= 0.9V
= 0.4V, V
= 0V
1.7
0.75
9.5
1.9
0.9
120
–12
150
70
1.9
0.9
12
2.1
FB1/2
Error Amp Switching Threshold Ch 1/2
Soft-Start Source Current Ch 1/2
1.05
14.5
2.4
V
FB1/2
l
= 0.05V
= 2V
µA
V
FB1/2
SS1/2
SS1/2
Soft-Start V Ch 1/2
2.15
1.4
160
0
OH
FB1/2
Soft-Start Sink Current Ch 1/2
2
mA
mV
mV
µA
mV
mV
nA
nA
mV
%
FB1/2
Soft-Start V Ch 1/2
200
12
OL
FB1/2
l
Soft-Start to Feedback Offset Ch 1/2
Soft-Start Sink Current Ch 1/2 POR
Soft-Start POR Threshold Ch 1/2
Soft-Start SW Disable Ch 1/2
CMPI Bias Current Ch 1/2
= 1V, V
= 0V, V
= 0.4V
VC1/2
SS1/2
SS1/2
= 0.12V (Note 8)
400
90
600
120
150
100
200
740
94
FB1/2
= 0V (Note 8)
= 0V (Note 8)
FB1/2
95
115
0
FB1/2
= 0.8V
= 0.8V, V
Rising
–100
CMPI1/2
CMP1/2
CMPI1/2
CMPI1/2
CMPI1/2
CMPI1/2
CMPO Leakage Ch 1/2
= 25V,
70
CMPO1/2
l
CMPI Threshold Ch 1/2
700
86
720
90
CMPI Threshold Ch 1/2 of V
CMPI Hysteresis Ch 1/2
Rising (Note 9)
FB1/2
35
60
85
mV
µA
µA
kHz
MHz
MHz
Deg
µA
V
CMPO Sink Current Ch 1/2
RT/SYNC Reference Current
= 0.6V, V
= 0.2V,
200
11.3
50
300
12
400
12.7
150
1075
2.75
CMPO1/2
l
= 0.9V, V
= 0.5V
RT/SYNC
FB1/2
Minimum Switching Frequency
Switching Frequency
R
R
R
=0Ω
110
1
RT/SYNC
RT/SYNC
RT/SYNC
= 28k
=100k
925
2.25
Maximum Switching Frequency
Switching Phase Angle Ch 1 ≥ Ch 2
DIV Reference Current
2.5
185
12
l
V
= 0.9V, V = 0.5V
10.5
0.51
0.9
13.5
0.61
1.1
FB1/2
DIV
CH1 DIV 2 Threshold
R
R
R
= 0V
= 0V
= 0V
0.58
1.05
1.55
0.25
2
RT/SYNC
RT/SYNC
RT/SYNC
CH1 DIV 4 Threshold
V
CH1 DIV 8 Threshold
1.45
V
CLKOUT V
CLKOUT V
I
I
= –100µA
= 100µA
V
OL
OH
CLKOUT
CLKOUT
V
CLKOUT to SW1ON Delay ( t
CLKOUT to SW2ON Delay ( t
)
)
CLKOUT Rising
CLKOUT Falling
60
ns
DCLKOSW1
30
ns
DCLKOSW2
3692fa
3
For more information www.linear.com/3692
LT3692
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VVIN1/2 = 15V unless otherwise specified. (Note 3)
PARAMETER
CONDITIONS
MIN
TYP
300
150
MAX
UNITS
ns
RT/SYNC to CLKOUT Delay ( t
RT/SYNC to CLKOUT Delay ( t
SYNC Frequency Range
)
V
V
= 0V to 2V Rising Edge
= 2V to 0V Falling Edge
DRTSYNCH
RT/SYNC
RT/SYNC
)
ns
DRTSYNCL
250
2000
kHz
Deg
ns
SYNC Phase Angle Ch 1 to Ch 2
Minimum Switch On-Time Ch 1/2
Minimum Switch Off-Time Ch 1/2
SYNC Frequency = 250kHz
180
180
200
1.8
ns
Minimum Boost for 100% DC Ch 1/2 (Note 10)
IND + V Current Ch 1/2
1.4
10
2.2
V
V
V
= 0V
= 5V
1.5
0.5
5
5
µA
µA
OUT
VOUT1/2
VOUT1/2
l
ILIM1/2 Reference Current
IND to V Maximum Current Ch 1/2
V
FB1/2
= 0.9V, V
= 0.4V
12
14
µA
ILIM
V
V
V
V
V
V
= 0V, V
= 0V, V
= 0.5V, V
= 0.5V, V
= 1.5V, V
= 1.5V, V
= 1V (Note 11)
= 5V (Note 11)
1
1.8
2
2.6
2.8
4.8
4.8
2.6
2.75
3.6
A
A
A
A
A
A
OUT
ILIM1/2
ILIM1/2
ILIM1/2
ILIM1/2
ILIM1/2
ILIM1/2
VOUT
VOUT
1.25
1.6
1.8
3.8
3.8
= 1V (Note 11)
= 5V (Note 11)
= 1V (Note 11)
= 5V (Note 11)
VOUT
VOUT
VOUT
VOUT
3.8
l
l
5.8
5.8
l
Switch Leakage Current Ch 1/2
Switch Saturation Voltage Ch 1/2
V
= 0V
1
5.0
µA
SW1/2
I
I
= 500mA, V
= 3A, V
= 18V
100
300
mV
mV
SW1/2
SW1/2
BST1/2
BST1/2
= 18V
Boost Current Ch 1/2
I
I
= 500mA, V
= 18V
9
40
13
55
17
70
mA
mA
SW1/2
SW1/2
BST1/2
= 3A, V
= 18V
BST1/2
Minimum Boost Voltage Ch1/2 (Note 12)
I
= 3A, V
= 18V
1.75
2.0
2.5
V
SW1/2
BST1/2
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 7: The T output voltage represents the temperature at the center
of the die while dissipating quiescent power. Due to switch power
J
dissipation and temperature gradients across the die, the T output
J
voltage measurement does not guarantee that absolute maximum junction
temperature will not be exceeded.
Note 2: Absolute Maximum Voltage at V
and SHDN1/2 pins is 60V for
IN1/2
nonrepetitive 1 second transients and 40V for continuous operation.
Note 8: An internal power on reset (POR) latch is set on the positive
transition of the SHDN1/2 pin through its threshold, thermal shutdown or
overvoltage lockout. The output of the latch activates current sources on
each SS pin which typically sink 400µA and discharge the SS capacitor.
The latch is reset when both SS pins are driven below the soft-start POR
threshold or the SHDN pin is taken below its threshold.
Note 3: The LT3692EUH is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3692IUH is guaranteed over the full –40°C to 125°C operating junction
temperature range.
Note 9: The threshold is expressed as a percentage of the feedback
reference voltage for the channel.
Note 4: The SHDN pins can be connected to V or driven by a logic-level
IN
source with a series current limiting resistor.
Note 10: To enhance dropout operation, the output switch will be turned
off for the minimum off-time only when the voltage across the boost
capacitor drops below the minimum boost for 100% duty cycle threshold.
Note 5: V undervoltage lockout is defined as the voltage which the V
IN
IN
pin must exceed for operation. The threshold guarantees that internal bias
lines are regulated and switching frequency is constant. Actual minimum
input voltage to maintain a regulated output will depend upon output
voltage and load current. See Applications Information.
Note 11: The IND to V
current flowing from the IND pin to the V
maximum current is defined as the value of
OUT
pin which resets the switch
OUT
latch when the V pin is at its high clamp.
C
Note 6: V overvoltage lockout is defined as the voltage when exceeded
halts converter operation. See Applications Information.
Note 12: This is the minimum voltage across the boost capacitor needed
to guarantee full saturation of the internal power switch.
IN
3692fa
4
For more information www.linear.com/3692
LT3692
Typical perForMance characTerisTics
VIN Overvoltage Threshold
vs Temperature
Shutdown Threshold and Minimum
Input Voltage vs Temperature
Shutdown Pin Input Current
vs Temperature
50
45
40
35
30
25
20
15
10
5
3.5
3.0
40.0
39.5
39.0
MINIMUM
INPUT VOLTAGE
V
SHDN
= 15V
IN
V
= 15V
2.5
38.5
38.0
37.5
37.0
36.5
36.0
35.5
35.0
2.0
1.5
1.0
0.5
SHUTDOWN
THRESHOLD VOLTAGE
V
SHDN
= 15V
IN
V
= 1.3V
0
0
–25
0
150
–50
25 50 75 100 125
TEMPERATURE (°C)
125
100
150
–50
50
50 75
TEMPERATURE (°C)
–25
0
25
75
–50 –25
0
25
100 125 150
TEMPERATURE (°C)
3692 G01
3692 G02
3692 G03
FB Voltage and CH1-CH2 FB
Offset vs Temperature
V
IN1 Quiescent Current
Shutdown Quiescent Current
vs Temperature
vs SHDN1 Voltage
820
815
810
805
800
8
6000
5000
4000
3000
2000
1000
0
10
9
8
7
6
5
4
3
2
1
0
V
= V
= 0V
SHDN1
SHDN2
6
4
I
Q1
2
OFFSET
150°C
125°C
25°C
–50°C
0
–2
–4
–6
–8
CH2
CH1
I
Q2
1
1.2
0
0.2 0.4 0.6 0.8
VOLTAGE (V)
1.4
75 100
125 150
–50 –25
0
25 50
–50
50
100 125
150
–25
0
25
75
TEMPERATURE (°C)
TEMPERATURE (°C)
3692 G04
3692 G05
3692 G06
Error Amplifier Transconductance
vs Temperature
Soft-Start-to-Feedback Offset
vs Temperature
TJ Output Voltage vs Temperature
425
420
415
410
405
400
395
390
385
380
375
370
1.50
1.25
1.00
0.75
0.50
0.25
0
4
3
V
= 0.4V
SS
2
1
0
R
= 30k
–1
–2
–3
–4
TJ
TO GND
–0.25
–0.50
R
TJ
= 30k TO –1V
50 75
50 75
TEMPERATURE (°C)
–50 –25
0
25
100 125 150
50 70
150
–50 –25
0
25
100 125 150
–50
10 30
90 110 130
–30 –10
TEMPERATURE (°C)
TEMPERATURE (°C)
3692 G07
3692 G09
3692 G08
3692fa
5
For more information www.linear.com/3692
LT3692
Typical perForMance characTerisTics
Comparator Sink Current
vs Temperature
Switching Frequency
vs Temperature
Comparator Thresholds
vs Temperature
750
740
730
720
710
700
690
680
670
660
650
400
350
300
250
200
150
100
50
1800
1600
1400
1200
1000
800
600
400
200
0
SINK CURRENT AT V
= 0.4V
CMPO
R
= 44.2k
RT/SYNC
RISING
THRESHOLD
R
R
= 28.0k
RT/SYNC
= 13.0k
= 0k
RT/SYNC
R
FALLING
THRESHOLD
RT/SYNC
0
50 75
TEMPERATURE (°C)
50 75
25
TEMPERATURE (°C)
–50 –25
0
25
100 125 150
–50 –25
0
100 125
150
–50
50
100 125
150
–25
0
25
75
TEMPERATURE (°C)
3692 G11
3692 G12
3692 G10
CLKOUT-to-SW1 Delay
vs Temperature
RT/SYNC-to-CLKOUT and SW1
Delay vs Temperature
Switching Phase vs Temperature
195
193
191
450
400
350
300
250
200
150
100
50
160
150
140
130
120
110
100
90
SW1
189
187
185
183
181
179
177
175
CLKOUT
80
70
60
0
50 75
TEMPERATURE (°C)
–50 –25
0
25
100 125 150
50 75
TEMPERATURE (°C)
–50 –25
0
25
100 125 150
–50
50
100 125
150
–25
0
25
75
TEMPERATURE (°C)
3692 G13
3692 G14
3695 G15
Synchronization Duty Cycles
vs Temperature
DIV Voltage Threshold
vs Temperature
Switch Saturation Voltage
vs Temperature
100
90
80
70
60
50
40
30
20
10
0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
300
250
200
150
100
50
RT/SYNC FREQUENCY = 1MHz
÷8
I
= 3A
SW
MAXIMUM RT/SYNC DUTY CYCLE
÷4
÷2
I
= 1A
SW
MINIMUM RT/SYNC DUTY CYCLE
I
= 500mA
SW
0
50 75
25
TEMPERATURE (°C)
–50 –25
0
100 125 150
75 100
–50
50
100 125
150
–50 –25
0
25 50
125 150
–25
0
25
75
TEMPERATURE (°C)
TEMPERATURE (°C)
3695 G17
3692 G16
3692 G18
3692fa
6
For more information www.linear.com/3692
LT3692
Typical perForMance characTerisTics
Switch Peak Current
vs Temperature
Minimum Boost Voltage
vs Temperature
Boost Current vs Temperature
100
90
80
70
60
50
40
30
20
10
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
I
= 3A
SW
V
= 1.5V
ILIM
3A
V
= 0.5V
ILIM
V
= 0V
ILIM
1A
0.5A
50 75
TEMPERATURE (°C)
–50 –25
0
25
100 125 150
–50
50
100 125
–50
50
100 125
150
–25
0
25
75
150
–25
0
25
75
TEMPERATURE (°C)
TEMPERATURE (°C)
3692 G21
3692 G19
3692 G20
Switching Frequency
vs RT/SYNC Resistance
Efficiency, TJ vs Load Current
Efficiency, TJ vs Load Current
90
88
86
84
82
80
78
76
74
72
70
80
70
60
50
40
30
20
10
0
86
84
82
80
78
76
74
72
70
70
60
50
40
30
20
10
0
2500
2000
EFFICIENCY
EFFICIENCY
1500
T
J
T
J
1000
500
0
V
V
= 12V
V
V
= 12V
= 5V
IN
OUT
IN
OUT
= 3.3V
FREQ = 1MHz
FREQ = 1MHz
3.5
4
2
2.5
0
0.5
1
1.5
3
3.5
4
0
10 20 30 40 50 60 70 80 90
RESISTANCE (kΩ)
0
2
3
0.5
1
1.5
2.5
LOAD CURRENT (A)
LOAD CURRENT (A)
3692 G24
3692 G22
3692 G23
Efficiency, TJ vs Load Current
Efficiency, TJ vs Load Current
80
78
76
74
72
70
68
66
64
62
60
60
50
40
30
20
10
0
82
80
78
76
74
72
70
68
70
60
50
40
30
20
10
0
EFFICIENCY
EFFICIENCY
T
J
T
J
V
V
= 12V
V
V
= 12V
IN
OUT
IN
OUT
= 2.5V
= 1.8V
FREQ = 1MHz
FREQ = 1MHz
2
2.5
0
0.5
1
1.5
3
3.5
4
0
3.5
0.5
1
1.5
2
2.5
3
4
LOAD CURRENT (A)
LOAD CURRENT (A)
3692 G25
3692 G26
3692fa
7
For more information www.linear.com/3692
LT3692
pin FuncTions
BST1/2: The BST pin provides a higher than V base
ILIM1/2: The voltage present at the ILIM pin determines
the peak inductor current for the channel. The ILIM pin is
driven by an internal current source with a typical value
of 12µA. A resistor from the ILIM pin to ground sets the
ILIM voltage. The maximum current limit range is 4.8A to
2A when the ILIM voltages are 1.5V and 0V respectively.
IN
drive to the power NPN to ensure a low switch drop. If the
voltage between the BST pin and the V pin is less than
IN
the voltage required to fully turn on the power NPN, the
power switch is turned off to recharge the BST capacitor.
CMPI1/2: The CMPI pin is an input to a comparator with a
threshold of 720mV and 60mv of hysteresis. Connecting
the CMPI pin to the FB pin will generate a power good
signalwhentheoutputiswithin90%ofitsregulatedvalue.
IND1/2:TheINDpinistheinputtotheinternalsenseresistor
that measures current flowing in the inductor. When the
current in the resistor exceeds the current dictated by the
V pin, the SW latch is held in reset, disabling the output
C
CMPO1/2: The CMPO pin is an open-collector output that
sinks current when the CMPI pin falls below its threshold.
For a typical input voltage above 2.8V, its output state re-
switch. Bias current flows out of the IND pin.
RT/SYNC: The voltage present at the RT/SYNC pin deter-
mines the constant switching frequency. The RT/SYNC
pin is driven by an internal current source with a typical
value of 12µA which allows a single resistor from the RT/
SYNCpintogroundtosettheRT/SYNCvoltageandresult-
ing switching frequency. Minimum switching frequency
mains true, although during shutdown, V undervoltage
IN1
lockout or thermal shutdown, its current sink capability is
reduced. The COMPO pins can be left open circuit or tied
together to form a single power good signal.
DIV:ThevoltagepresentattheDIVpindeterminestheratio
of channel 1 frequency to the master clock frequency set
by the RT/SYNC pin. The DIV pin is driven by an internal
current source with a typical value of 12µA which allows
a single resistor from the DIV pin to ground to set the
DIV voltage and resulting channel 1 frequency divider.
Ratios of 1, 2, 4 and 8 are available. See the Applications
Information section for more information.
is typically 110kHz when V
is 0V and maximum
RT/SYNC
switching frequency is typically 2.5MHz when V
is above 950mV.
RT/SYNC
Driving the RT/SYNC pin with an external clock signal will
synchronize the switch to the applied frequency. Synchro-
nization occurs on the rising edge of the clock signal after
theclocksignalisdetected.Eachrisingclockedgeinitiates
an oscillator ramp reset. A gain control loop servos the
oscillator charging current to maintain constant oscillator
amplitude. Hence, the slope compensation and channel
phase relationship remain unchanged. If the clock signal
is removed, the oscillator reverts to resistor mode after
thesynchronizationdetectioncircuitrytimesout.Theclock
source impedance should be set such that the current out
oftheRT/SYNCpininresistormodegeneratesafrequency
roughly equivalent to the synchronization frequency. See
theApplicationsInformationsectionformoreinformation.
DNC: Do Not Connect.
GND: The exposed pad pin is the only ground connec-
tion for the device. The exposed pad should be soldered
to a large copper area to reduce thermal resistance. The
GND pin is common to both channels and also serves as
small-signal ground. For ideal operation all small-signal
ground paths should connect to the GND pin at a single
point avoiding any high current ground returns.
FB1/2:TheFBpinisthenegativeinputtotheerroramplifier.
The output switches to regulate this pin to 806mV with
respect to the exposed ground pad. Bias current flows
out of the FB pin.
3692fa
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For more information www.linear.com/3692
LT3692
pin FuncTions
SHDN1/2: The shutdown pin is used to control each
channel’s operation. In addition to controlling channel 1,
the SHDN1 pin also activates control circuitry for both
channels and must be present for channel 2 to operate.
When SHDN1 is below its threshold, switching on both
channels is halted. Further reducing the SHDN1 voltage
to 0.6V reduces the quiescent current to a typical value of
6µA. If the shutdown features are not used, the SHDN pin
T : The T pin outputs a voltage proportional to junction
J J
temperature. The pin is 250mV for 25°C and has a slope
of 10mV/°C. See the Applications Information section for
more information.
V
:TheV pinistheoutputoftheerroramplifierandthe
C
C1/2
input to the peak switch current comparator. It is normally
used for frequency compensation, but can also be used
as a current clamp or control loop override. If the error
can be tied to V . If SHDN pin is driven by a logic signal,
IN
amplifier drives V above the maximum switch current
C
aseriesresistorisrequired. SeeApplicationsInformation.
level, a voltage clamp activates. This indicates that the
output is overloaded and current is pulled from the SS
pin reducing the regulation point.
SS1/2: Current flowing out the SS pin into an external
capacitor defines the rise time of the output voltage. When
the SS pin is lower than the 0.8V reference, the feedback
is regulated to the SS voltage. When the SS pin exceeds
the reference voltage, the output will regulate the FB pin
voltage to 0.8V and the SS pin will continue to rise until
V
: The V pin powers the internal control circuitry for
IN1
IN1
bothchannelsandismonitoredbyovervoltage/undervolt-
age lockout comparators. The V pin is also connected
IN1
to the collector of channel 1’s on-chip power NPN switch.
its clamp voltage. During an output overload, the V pin is
C
The V pin has high dI/dt edges and must be decoupled
IN1
driven above the maximum switch current level activating
to ground close to the pin of the device.
its voltage clamp. When the V clamp is activated, the SS
C
V
: The V pin powers the output stage for channel 2
IN2
pinisdischargeduntiltheoutputreachesaregulationpoint
that the maximum output current can maintain. When the
overload condition is removed, the output soft starts from
that voltage. In the case of a SHDN or thermal shutdown
event, a power on reset latch ensures the capacitors on
bothchannelsarefullydischargedbeforeeitherisreleased.
Connecting both SS pins together ensures the outputs
track together.
IN2
and is monitored by overvoltage/undervoltage lockout
comparators. V voltage must be greater than 2.8V for
IN1
V
operation. TheV pinisalsothecollectorofchannel
IN2
IN2
2’s on-chip power NPN switch. The V pin has high dI/
IN2
dt edges and must be decoupled to ground close to the
pin of the device.
V
: The V
pin is the output to the internal sense
OUT1/2
OUT
resistor that measures current flowing in the inductor.
CLKOUT: The CLKOUT pin generates a square wave of 0V
to 2.5V which is synchronized to the internal oscillator. If
the switching frequency is set by an external resistor the
resultant clock duty cycle will be 50%. If the RT/SYNC pin
isdrivenbyanexternalclocksource,theresultantCLKOUT
duty cycle will mirror the external source.
When the current in the resistor exceeds the current dic-
tated by the V pin, the SW latch is held in reset disabling
C
the output switch. Bias current flows out of the V
pin.
OUT
SW1/2: The SW pin is the emitter of the internal power
NPN. At switch off, the inductor will drive this pin below
ground with a high dV/dt. An external Schottky catch
diode to ground, close to the SW pin and respective V
IN
decoupling capacitor’s ground, must be used to prevent
this pin from excessive negative voltages.
3692fa
9
For more information www.linear.com/3692
LT3692
block DiagraM
V
IN1
V
IN1
1.3V
+
–
+
–
SHDN1
38V
CHANNEL 1
BST1
SW1
IND1
DROPOUT
THERMAL
SHUTDOWN
ENHANCEMENT
PRE
S
R
DRIVER
CIRCUITRY
–
+
Q
2.5V
PRE
12µA
S
R
Q
–
+
+
–
SS1
V
OUT1
90mV
V
C1
R1
R2
FB1
2.5V
CMPI1
12µA
CMPO1
+
–
ILIM1
0.806V
+
0.72V
+
–
R
LIM
SLOPE
2.5V
2.5V
COMPENSATION
12µA
12µA
RT/SYNC
DIV
T
J
CLK1
R3
INTERNAL
2.5V
CLKOUT
GND
V
+
–
IN1
MASTER CLOCK
OSCILLATOR
AND AGC
REGULATOR
AND
2.8V
CLK2 TO CHANNEL 2
REFERENCES
R
DIV
3692 F01
Figure 1. LT3692 Block Diagram
applicaTions inForMaTion
The LT3692 is a dual channel, constant frequency, current
mode buck converter with internal 3.5A switches. Each
channelcanbeindependentlycontrolledwiththeexception
Once the internal reference reaches its regulation point,
the internal oscillator will start generating a master clock
signal for the two regulators at a frequency determined
by the voltage present at the RT/SYNC pin. The channel 1
clock is then divided by 1, 2, 4 or 8 depending on the
voltage present at the DIV pin. Channel 2’s clock runs at
the master clock frequency with a 180° phase shift from
channel 1.
that V must be above the 2.8V undervoltage lockout
IN1
threshold to power the common internal regulator, oscil-
lator and thermometer circuitry.
If the SHDN1 pin is taken below its 1.3V threshold switch-
ingonbothchannelswillbedisabled. Furtherreducingthe
SHDN1 below a typical value of 0.6V will place the LT3692
in a low quiescent current mode. In this mode the LT3692
Alternatively, if a synchronization signal is detected by
the LT3692 the RT/SYNC pin, the master clock will be
generated at the incoming frequency on the rising edge
of the synchronization pulse with channel 1 in phase with
the synchronization signal. Frequency division and phase
remainsthesameastheinternallygeneratedmasterclock.
typically draws 6µA from V and <1µA from V . When
IN1
IN2
theSHDNpinisdrivenabove1.3V,theinternalbiascircuits
turnongeneratinganinternalregulatedvoltage,0.806V ,
FB
12µA RT/SYNC, DIV and ILIM current references, and a
POR signal which sets the soft-start latch.
3692fa
10
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LT3692
applicaTions inForMaTion
In addition, the internal slope compensation will be au-
tomatically adjusted to prevent subharmonic oscillation
during synchronization. In either mode of oscillator op-
eration, a square wave with the master clock frequency,
synchronized to channel 1 is present at the CLKOUT pin.
is turned off. Once the switch is turned off the inductor
will drive the voltage at the SW pin low until the external
Schottky diode starts to conduct, decreasing the current
in the inductor. The cycle is repeated with the start of each
clock cycle. However, if the internal sense resistor voltage
exceedsthepredeterminedlevelatthestartofaclockcycle,
the flip-flop will not be set resulting in a further decrease
in inductor current. Since the output current is controlled
The two regulators are constant frequency, current mode
step-down converters. Current mode regulators are con-
trolled by an internal clock and two feedback loops that
control the duty cycle of the power switch. In addition to
thenormalerroramplifier,thereisacurrentsenseamplifier
that monitors switch current on a cycle-by-cycle basis.
This technique means that the error amplifier commands
current to be delivered to the output rather than voltage.
A voltage fed system will have low phase shift up to the
resonant frequency of the inductor and output capacitor,
then an abrupt 180° shift will occur. The current fed sys-
tem will have 90° phase shift at a much lower frequency,
but will not have the additional 90° shift until well beyond
the LC resonant frequency. This makes it much easier to
frequency compensate the feedback loop and also gives
much quicker transient response.
by the V voltage, output regulation is achieved by the
C
error amplifier continually adjusting the V pin voltage.
C
The error amplifier is a transconductance amplifier that
compares the FB voltage to the lowest voltage present at
eithertheSSpinoraninternal806mVreference. Compen-
sationoftheloopiseasilyachievedwithasimplecapacitor
or series resistor/capacitor from the V pin to ground.
C
The regulators’ maximum output current occurs when the
V pin is driven to its maximum clamp value by the error
C
amplifier. The value of the maximum switch current can be
programmed from 4.8A to 2A by placing a resistor from
the ILIM pin to ground.
Since the SS pin is driven by a constant current source, a
singlecapacitoronthesoft-startpinwillgeneratecontrolled
linear ramp on the output voltage.
The Block Diagram in Figure 1 shows only one of the
switching regulators whose operation will be discussed
below. The additional regulator will operate in a similar
manner with the exception that its clock will be 180° out
of phase with the other regulator.
If the current demanded by the output exceeds the maxi-
mum current dictated by the V pin clamp, the SS pin
C
will be discharged, lowering the regulation point until the
outputvoltagecanbesupportedbythemaximumcurrent.
Once the overload condition is removed, the regulator will
soft-start from the overload regulation point.
When, during power-up, an internal POR signal sets the
soft-start latch, both SS pins will be discharged to ground
to ensure proper start-up operation. When the SS pin volt-
age drops below 90mV, the V pin is driven low disabling
C
Shutdowncontrol, V overvoltage,orthermalshutdown
switching and the soft-start latch is reset. Once the latch
is reset the soft-start capacitor starts to charge with a
typical value of 12µA.
IN
will set the soft-start latch, resulting in a complete soft-
start sequence.
The switch driver operates from either the V or BST volt-
As the voltage rises above 115mV on the SS pin, the V
IN
C
age. An external diode and capacitor are used to generate
pin will be driven high by the error amplifier. When the
a drive voltage higher than V to saturate the output NPN
voltageontheV pinexceeds0.8V,theclockset-pulsesets
IN
C
and maintain high efficiency. If the BST capacitor voltage
is sufficient, the switch is allowed to operate to 100% duty
cycle. If the boost capacitor discharges towards a level
insufficient to drive the output NPN, a BST pin compara-
tor forces a minimum cycle off time, allowing the boost
capacitor to recharge.
the driver flip-flop, which turns on the internal power NPN
switch. This causes current from V , through the NPN
IN
switch, inductor and internal sense resistor to increase.
When the voltage drop across the internal sense resistor
exceeds a predetermined level set by the voltage on the
V pin, the flip-flop is reset and the internal NPN switch
C
3692fa
11
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LT3692
applicaTions inForMaTion
A comparator with a threshold of 720mV and 60mV of
hysteresis is provided for detecting error conditions. The
CMPO output is an open-collector NPN that is off when
the CMPI pin is above the threshold allowing a resistor
to pull the CMPO pin to a desired voltage.
the RT/SYNC pin which determines the master oscillator
frequency as illustrated in Figure 2. A 0V to 2.5V square
wave with the same frequency as the master oscillator
and in phase with channel 1 is output via the CLKOUT pin.
The CLKOUT signal can be used to synchronize multiple
switching regulators.
The voltage present at the T pin is proportional to the
J
junction temperature of the LT3692. The T pin will be
Toalleviatedutycyclerestrictionsduetominimumswitch-
on times, channel 1’s switching frequency can be divided
fromthemasterclockby1,2,4or8determinedbyresistor
J
250mV for a die temperature of 25°C and will have a
slope of 10mV/°C.
R
in Figure 1. Channel 2’s switching frequency is not
DIV
Choosing the Output Voltage
affected by the DIV pin. The DIV pin is driven by a 12µA
currentsource. SettingresistorR setsthevoltagepres-
DIV
The output voltage is programmed with a resistor divider
between the output and the FB pin. Choose the 1% resis-
tors according to:
ent at the DIV pin which determines the divisor as shown
in Table 1. The DIV pin doesn’t have any input hysteresis
near the ratio thresholds.
VOUT
0.806
R1= R2 •
– 1
Table 1. Channel 1 Divisor vs VDIV
DIV VOLTAGE
< 0.5V
FREQUENCY RATIO
R
DIV
V
DIV
1
2
4
8
0
R2 should be 10k or less to avoid bias current errors. Ref-
erence designators refer to the Block Diagram in Figure 1.
0.5V < V < 1.0V
62k
100k
150k
DIV
1.0V < V < 1.5V
DIV
1.5V < V
DIV
2500
2000
The switching frequency is typically set as high as pos-
sible to reduce overall solution size. The LT3692 employs
techniques to enhance dropout at high frequencies but
efficiency and maximum input voltage decrease due to
switching losses and minimum switch on times.
1500
1000
500
0
The maximum recommended frequency can be approxi-
mated by the equation:
VOUT + VD
1
Frequency (Hz) =
•
0
10 20 30 40 50 60 70 80 90
RESISTANCE (kΩ)
V – V + VD tON(MIN)
IN
SW
3692 F02
whereV istheforwardvoltagedropofthecatchdiode(D1
D
Figure 2. Switching Frequency vs RT/SYNC Resistance
Figure 2), V is the voltage drop of the internal switch,
SW
and t
in the minimum on-time of the switch.
ON(MIN)
Choosing the Switching Frequency
The following example along with the data in Table 2
illustrates the trade-offs of switch frequency selection for
a single input voltage system.
The LT3692 switching frequency is set by resistor R3 in
Figure 1. The RT/SYNC pin is driven by a 12µA current
source. Setting resistor R3 sets the voltage present at
3692fa
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For more information www.linear.com/3692
LT3692
applicaTions inForMaTion
Table 2. Efficiency and Size Comparisons for Different RRT/SYNC Values, 3.3V Output
EFFICIENCY
VIN1/2
†
FREQUENCY
250kHz
RT/SYNC
5.90kΩ
13.0kΩ
28.0kΩ
44.2kΩ
71.5kΩ
V
= 12V
V
L*
C*
C + L (Area)
IN(MAX)
2
77.8%
38V
12µH
120µF
60µF
30µF
22µF
15µF
59.8mm
2
500kHz
81.2%
80.5%
79.3%
76.7%
31V
16V
10V
6.5V
6.8µH
3.3µH
1.5µH
0.82µH
54.6mm
2
1000kHz
1500kHz
2250kHz
51.9mm
2
46.9mm
2
19.1mm
†
V
is defined as the highest input voltage that maintains constant output voltage ripple.
IN(MAX)
*Inductor and capacitor values chosen for stability and constant ripple current.
has the same effect as lowering the clock frequency for a
fixed off time, resulting in a higher duty cycle and lower
minimum input voltage. The resultant duty cycle depends
on the charging times of the boost capacitor and can be
approximated by the following equation:
Example.
V
= 25V, V
= 3.3V, I
= 2.5A, t
= 250ns,
~ 600kHz
IN
OUT
SW
OUT
ON(MIN)
V = 0.6V, V = 0.4V:
D
3.3+ 0.6
25 – 0.4+ 0.6 250e-9
1
Max Frequency =
•
1
DCMAX
=
1
B
RT/SYNC ~ 15.8kΩ (Figure 2 )
1+
Input Voltage Range
where B is 3A divided by the typical boost current from
the Electrical Characteristics table.
Once the switching frequency has been determined, the
inputvoltagerangeoftheregulatorcanbedetermined.The
minimuminputvoltageisdeterminedbyeithertheLT3692’s
minimum operating voltage of ~2.8V, or by its maximum
duty cycle. The duty cycle is the fraction of time that the
internal switch is on during a clock cycle. Unlike most
fixed frequency regulators, the LT3692 will not switch off
at the end of each clock cycle if there is sufficient voltage
across the boost capacitor (C3 in Figure 1) to fully satu-
rate the output switch. Forcing switch off for a minimum
time will only occur at the end of a clock cycle when the
boost capacitor needs to be recharged. This operation
This leads to a minimum input voltage of:
VOUT + VD
DCMAX
V
=
– VD + VSW
IN(MIN)
where V is the voltage drop of the internal switch.
SW
Figure 4 shows a typical graph of minimum input voltage
vsloadcurrentforFigure19,the3.3Vand1.8Vapplication.
6
V
= 3.3V
OUT
5
4
3
2
1
0
t
P
START-UP
RUNNING
SW1
SW2
t /2
P
t
P
t /2
P
t
P
CLKOUT
0
1000 1500 2000 2500 3000 3500
CURRENT (mA)
500
3692 F03
t
DCLKOSW1
t
3692 F04
DCLKOSW2
Figure 3. Timing Diagram RT/SYNC = 28.0k, tP = 1µs, VDIV = 0V
Figure 4. Minimum Input Voltage vs Load Current
3692fa
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LT3692
applicaTions inForMaTion
In cases where multiple input voltages are present, or the
V /V ratio for channel 1 is significantly different than
The maximum input voltage is determined by the absolute
maximum ratings of the V and BST pins and by the
IN OUT
IN
channel2, channel1’sfrequencycanbedividedbyafactor
of 2, 4 or 8 from the programmed value by setting the DIV
pin resistor to the appropriate value. Dividing channel 1’s
frequency will increase the maximum input voltage by the
same ratio. Channel 1’s external components will have to
be chosen according to the resulting frequency.
frequency and minimum duty cycle. The minimum duty
cycle is defined as:
DC
= t
• Frequency
ON(MIN)
MIN
Maximum input voltage as:
VOUT + VD
DCMIN
V
=
– VD + VSW
IN(MAX)
Example:
V
= 3.3V, I
= 1A, Frequency = 1MHz, Temperature
OUT
OUT
Note that the LT3692 will regulate if the input voltage is
taken above the calculated maximum voltage as long as
= 25°C, V = 0.1V, B = 50 (from boost characteristics
SW
specification), V = 0.4V, t
= 225ns. V = 0.75V.
D
ON(MIN)
DIV
maximum ratings of the V and BST pins are not violated.
IN
However operation in this region of input voltage will
exhibit pulse skipping behavior.
DCMIN1 = tON(MIN1) • Frequency/2 = 0.1125
3.3+ 0.4
Example:
V
=
– 0.4+ 0.1= 32.6V
IN1(MAX)
0.1125
V
= 3.3V, I
= 1A, Frequency = 1MHz, Temperature
OUT
OUT
= 25°C, V = 0.1V, B = 50 (from boost characteristics
SW
Inductor Selection and Maximum Output Current
specification), V = 0.4V, t
= 225ns:
D
ON(MIN)
A good first choice for the LT3692 inductor value is:
1
DCMAX
=
= 98%
VOUT
f
1
L =
1+
50
where f is frequency in MHz and L is in µH.
3.3+ 0.4
0.98
V
=
– 0.4+ 0.1= 3.48V
IN(MIN)
With this value the maximum load current will be ~3.5A,
independent of input voltage. The inductor’s RMS cur-
rent rating must be greater than your maximum load
current and its saturation current should be higher than
the maximum peak switch current, and will reduce the
output voltage ripple.
DCMIN = tON(MIN) •Frequency = 0.225
3.3+ 0.4
V
=
– 0.4+ 0.1= 16.1V
IN(MAX)
0.225
If the maximum load for a single channel is lower than
2.5A, then you can decrease the value of the inductor and
operate with higher ripple current, or you can adjust the
maximum switch current for the channel via the ILIM pin.
Thisallowsyoutouseaphysicallysmallerinductor, orone
with a lower DCR resulting in higher efficiency.
2 • t
P
SW1
SW2
1/(2 • t )
t
P
P
t /2
P
t
P
The peak inductor and switch current is:
CLKOUT
∆IL
2
ISW(PK) = IL(PK) = IOUT
+
3692 F05
t
DCLKOSW1
t
DCLKOSW2
To maintain output regulation, this peak current must be
less than the LT3692’s switch current limit, ILIM. ILIM
3692fa
Figure 5. Timing Diagram RT/SYNC = 28.0k,
tP = 1µs, VDIV = 0.75V
14
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LT3692
applicaTions inForMaTion
can be set between 2A and 4.8A for each channel via
a resistor from the ILIM pin to ground. The ILIM pin is
driven by a 12µA current source. Setting resistor R
sets the voltage present at the ILIM pin which determines
the maximum switch current as illustrated in Figure 6. A
capacitor from the ILIM pin to ground, or a resistor divider
from the output, can be used to limit the peak current dur-
ing start-up. If a capacitor is used it must be discharged
before power-up to ensure proper operation (see 3.3V and
1.8V 2-Stage Dual Step-Down Multi-Frequency Converter
in Typical Applications).
WhentheLT3692’sinputsuppliesareoperatedatdifferent
input voltages, an input capacitor sized for that channel
should be placed as close as possible to the respective
LIM
V pins.
IN
A caution regarding the use of ceramic capacitors at the
input. A ceramic input capacitor can combine with stray
inductance to form a resonant tank circuit. If power is
applied quickly (for example by plugging the circuit into
a live power source) this tank can ring, doubling the in-
put voltage and damaging the LT3692. The solution is to
either clamp the input voltage or dampen the tank circuit
by adding a lossy capacitor in parallel with the ceramic
capacitor. For details, see Application Note 88.
Referring to Figure 6, as the peak current limit is reduced,
slope compensation further reduces the peak current with
increasing duty cycle.
Output Capacitor Selection
When the ILIM pin is used to reduce the peak switch cur-
rent, the equation for inductor choice becomes:
Typicallystep-downregulatorsareeasilycompensatedwith
an output crossover frequency that is 1/10 of the switch-
ing frequency. This means that the time that the output
capacitor must supply the output load during a transient
step is ~2 or 3 switching periods. With an allowable 1%
drop in output voltage during the step, a good starting
value for the output capacitor can be expressed by:
50 • VOUT
L =
f •RILIM
where f is frequency in MHz, L in µH and R in kΩ.
4.5
4.0
Max Load Step
Frequency • 0.01• VOUT
CVOUT
=
3.5
3.0
2.5
2.0
1.5
Example:
V
= 3.3V, Frequency = 1MHz, Max Load Step = 2A.
2
OUT
CVOUT
=
= 60µF
1E6• 0.01• 3.3V
1.0
0
30
50 60 70 80 90 100
10 20
40
The calculated value is only a suggested starting value.
Increasethevalueiftransientresponseneedsimprovement
or reduce the capacitance if size is a priority. The output
capacitor filters the inductor current to generate an output
with low voltage ripple. It also stores energy in order to
satisfytransientloadsandtostabilizetheLT3692’scontrol
loop. The switching frequency of the LT3692 determines
the value of output capacitance required. Also, the current
mode control loop doesn’t require the presence of output
capacitor series resistance (ESR). For these reasons, you
are free to use ceramic capacitors to achieve very low
output ripple and small circuit size.
ILIM PIN RESISTOR (kΩ)
3692 F06
Figure 6. Peak Switch Current vs ILIM Resistor
Input Capacitor Selection
Bypass the inputs of the LT3692 circuit with a 4.7µF or
higher ceramic capacitor of X7R or X5R type. A lower
value or a less expensive Y5V type can be used if there
is additional bypassing provided by bulk electrolytic or
tantalum capacitors.
3692fa
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LT3692
applicaTions inForMaTion
Youcanalsouseelectrolyticcapacitors. TheESRsofmost
aluminum electrolytics are too large to deliver low output
ripple. Tantalum and newer, lower ESR organic electrolytic
capacitors intended for power supply use, are suitable
and the manufacturers will specify the ESR. The choice of
capacitor value will be based on the ESR required for low
ripple. Because the volume of the capacitor determines
its ESR, both the size and the value will be larger than a
ceramic capacitor that would give you similar ripple per-
formance. One benefit is that the larger capacitance may
give better transient response for large changes in load
current. Table 3 lists several capacitor vendors.
BST Pin Considerations
The capacitor and diode tied to the BST pin generate a
voltage that is higher than the input voltage. In most cases
a0.47µFcapacitorandasmallSchottkydiode(suchasthe
CMDSH-4E)willworkwell.Toensureoptimalperformance
at duty cycles greater than 80%, use a 0.5A Schottky
diode (such as a PMEG4005). Almost any type of film or
ceramic capacitor is suitable, but the ESR should be <1Ω
to ensure it can be fully recharged during the off time of
the switch. The capacitor value can be approximated by:
IOUT(MAX) • VOUT
CBST
=
5 • V
V
OUT
– 2 • f
(
)
IN
Table 3
VENDOR
Taiyo Yuden
AVX
TYPE
SERIES
where I
is the maximum load current.
OUT(MAX)
Ceramic X5R, X7R
Figure 7 shows four ways to arrange the boost circuit. The
BST pin must be more than 3V above the SW pin for full
efficiency. Generally, for outputs of 3.3V and higher the
standard circuit (Figure 7a) is the best. For lower output
voltages the boost diode can be tied to the input (Fig-
ure 7b). The circuit in Figure 7a is more efficient because
the BST pin current comes from a lower voltage source.
Figure 7c shows the boost voltage source from available
DC sources that are greater than 3V. The highest efficiency
is attained by choosing the lowest boost voltage above 3V.
For example, if you are generating 3.3V and 1.8V and the
3.3V is on whenever the 1.8V is on, the 1.8V boost diode
can be connected to the 3.3V output. In any case, you
must also be sure that the maximum voltage at the BST
pin is less than the maximum specified in the Absolute
Maximum Ratings section.
Ceramic X5R, X7R
Tantalum
Kemet
Tantalum
TA Organic
AL Organic
T491, T494, T495
T520
A700
Sanyo
Panasonic
TDK
TA/AL Orgainic
AL Organic
POSCAP
SP CAP
Ceramic X5R, X7R
Catch Diode
The diode D1 conducts current only during switch off
time. Use a Schottky diode to limit forward voltage drop to
increase efficiency. The Schottky diode must have a peak
reverse voltage that is equal to regulator input voltage and
sized for average forward current in normal operation.
Average forward current can be calculated from:
IOUT
V
IN
The boost circuit can also run directly from a DC voltage
that is higher than the input voltage by more than 3V, as
in Figure 7d. The diode is used to prevent damage to the
ID(AVG)
=
• V – V
(
IN
OUT
)
Withashortedcondition, diodecurrentwillincreasetothe
typical value determined by the peak switch current limit
of the LT3692 set by the ILIM pin. This is safe for short
periods of time, but it would be prudent to check with the
diode manufacturer if continuous operation under these
conditions can be tolerated.
LT3692 in case V is held low while V is present. The
X
IN
circuit saves several components (both BST pins can be
tied to D2). However, efficiency may be lower and dissipa-
tion in the LT3692 may be higher. Also, if V is absent, the
X
LT3692 will still attempt to regulate the output, but will do
so with very low efficiency and high dissipation because
3692fa
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D2
C3
C3
D2
V
BST
BST
V
V
SW
V
V
IN
SW
IN
IN
IN
LT3692
LT3692
IND
OUT
IND
OUT
V
< 3V
OUT
V
V
OUT
GND
GND
V
V
– V = V
V
V
– V = V
BST SW IN
BST(MAX)
BST
SW
OUT
= V + V
= 2 • V
IN
BST(MAX)
IN
OUT
D2
(7a)
(7b)
D2
V
= LOWEST V
IN
X
V
> V + 3V
IN
X
OR V
> 3V
OUT
C3
BST
BST
V
V
SW
V
V
IN
SW
IN
IN
IN
LT3692
LT3692
IND
OUT
IND
OUT
V
< 3V
V
< 3V
OUT
V
V
OUT
GND
GND
V
V
V
– V = V
V
V
V
– V = V
BST SW X
BST
SW
X
3692 F07
= V + V
= V
X
BST(MAX)
IN
X
BST(MAX)
= 3V
= V + 3V
IN
X(MIN)
X(MIN)
(7c)
(7d)
Figure 7. BST Pin Considerations
Outputs Greater Than 6V
the switch will not be able to saturate, dropping 1.5V to
2V in conduction.
For outputs greater than 6V, add a resistor of 1k to 2.5k
across the inductor to damp the discontinuous ringing of
the SW node, preventing unintended SW current. The 12V
output circuit in the Typical Applications section shows
the location of this resistor.
The minimum input voltage of an LT3692 application is
limited by the minimum operating voltage (<3V) and by
the maximum duty cycle as outlined above. For proper
start-up, the minimum input voltage is also limited by
the boost circuit. If the input voltage is ramped slowly, or
the LT3692 is turned on with its SS pin when the output
is already in regulation, then the boost capacitor may not
be fully charged. Because the boost capacitor is charged
with the energy stored in the inductor, the circuit will rely
on some minimum load current to get the boost circuit
running properly. This minimum load will depend on input
and output voltages, and on the arrangement of the boost
circuit. The Typical Performance Characteristics section
shows plots of the minimum load current to start and to
runasafunctionofinputvoltagefor3.3Voutputs.Inmany
cases the discharged output capacitor will present a load
to the switcher which will allow it to start. The plots show
Frequency Compensation
The LT3692 uses current mode control to regulate the
output.Thissimplifiesloopcompensation.Inparticular,the
LT3692 does not require the ESR of the output capacitor
for stability so you are free to use ceramic capacitors to
achieve low output ripple and small circuit size. Frequency
compensation is provided by the components tied to the
V pin. Generally a capacitor and a resistor in series to
C
ground determine loop gain. In addition, there is a lower
value capacitor in parallel. This capacitor is not part of
the loop compensation but is used to filter noise at the
switching frequency.
theworst-casesituationwhereV isrampingveryslowly.
IN
Use a Schottky diode for the lowest start-up voltage.
3692fa
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LT3692
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Loop compensation determines the stability and transient
performance.Designingthecompensationnetworkisabit
complicatedandthebestvaluesdependontheapplication
and in particular the type of output capacitor. A practical
approach is to start with one of the circuits in this data
sheet that is similar to your application and tune the com-
pensation network to optimize the performance. Stability
should then be checked across all operating conditions,
including load current, input voltage and temperature.
Synchronization
The RT/SYNC pin can also be used to synchronize the
regulatorstoanexternalclocksource.DrivingtheRT/SYNC
resistor with a clock source triggers the synchronization
detection circuitry. Once synchronization is detected, the
rising edge of SW1 will be synchronized to the rising edge
of the RT/SYNC signal and the rising edge of SW2 syn-
chronized to the falling edge of the RT/SYNC signal (see
Figures 10 and 11). During synchronization, a 0V to 2.4V
square wave with the same frequency and duty cycle as
the synchronization signal is output via the CLKOUT pin
with a typical propagation delay of 250ns. In addition, an
internal AGC loop will adjust slope compensation to avoid
subharmonic oscillation. If the synchronization signal is
halted, thesynchronizationdetectioncircuitrywilltimeout
in typically 10µs at which time the LT3692 reverts to the
free-runningfrequencybasedontheRT/SYNCpinvoltage.
The LT1375 data sheet contains a more thorough discus-
sion of loop compensation and describes how to test the
stability using a transient load.
Figure8showsanequivalentcircuitfortheLT3692control
loop. The error amp is a transconductance amplifier with
finite output impedance. The power section, consisting of
the modulator, power switch and inductor, is modeled as
a transconductance amplifier generating an output cur-
rent proportional to the voltage at the V pin. Note that
The synchronizing clock signal input to the LT3692 must
have a frequency between 200kHz and 2MHz, a duty cycle
between 20% and 80%, a low state below 0.5V and a high
state above 1.6V. Synchronization signals outside of these
parameters will cause erratic switching behavior. If the
RT/SYNC pin is held above 1.6V at any time, switching
will be disabled.
C
the output capacitor integrates this current, and that the
capacitor on the V pin (C ) integrates the error amplifier
C
C
output current, resulting in two poles in the loop. In most
cases a zero is required and comes from either the output
capacitor ESR or from a resistor in series with C .
C
This simple model works well as long as the value of the
inductor is not too high and the loop crossover frequency
is much lower than the switching frequency. A phase lead
If the synchronization signal is not present during regu-
lator start-up (for example, the synchronization circuitry
is powered from the regulator output) the RT/SYNC pin
must remain below 1V until the synchronization circuitry
is active for proper start-up operation.
capacitor (C ) across the feedback divider may improve
PL
the transient response.
LT3692
CURRENT MODE
POWER STAGE
m
OUTPUT
g
= 4.8mho
C
R1
R2
ESR
PL
g
= 400µmho
m
FB
–
+
+
V
C
C1
C1
3.6M
R
C
CERAMIC
ERROR
AMP
TANTALUM
OR
POLYMER
0.806V
C
F
C
C
3692 F08
Figure 8. Model for Loop Response
3692fa
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t
P
Ifthesynchronizationsignalpowersupinanundetermined
state (V , V , Hi-Z), connect the synchronization clock
OL OH
SW1
SW2
to the LT3692 as shown in Figure 9. The circuit as shown
will isolate the synchronization signal when the output
voltage is below 90% of the regulated output. The LT3692
will start up with a switching frequency determined by the
resistor from the RT/SYNC pin to ground.
t
P
t
t
P
PON
CLKOUT
Ifthesynchronizationsignalpowersupinalowimpedance
state (V ), connect a resistor between the RT/SYNC pin
OL
t
t
DCLKOSW1
DCLKOSW2
PON
t
t
P
and the synchronizing clock. The equivalent resistance
seen from the RT/SYNC pin to ground will set the start-
up frequency.
RT/SYNC
DRTSYNCH
3692 F11
t
t
DRTSYNCH
If the synchronization signal powers up in a high imped-
ance state (Hi-Z), connect a resistor from the RT/SYNC
pin to ground. The equivalent resistance seen from the
RT/SYNC pin to ground will set the start-up frequency.
Figure 11. Timing Diagram RT/SYNC = 1MHz, Duty Cycle > 50%
Reducing Input Ripple Voltage
Synchronizing the switches to the rising and falling edges
ofthesynchronizationsignalprovidestheuniqueabilityto
V
V
CC
OUT1
reduceinputripplecurrentsinsystemswhereV andV
IN1
IN2
LT3692
RT/SYNC
SYNCHRONIZATION
CIRCUITRY
are connected to the same supply. Decreasing the input
current ripple reduces the required input capacitance. For
example, the input ripple voltage shown in Figure 12 for
a typical antiphase dual 14.4V to 8.5V and 14.4V to 3.3V
regulator is decreased from a peak of 472mV to 160mV
as shown in Figure 13 by driving the LT3692 with a 71%
duty cycle synchronization signal.
PG1
CLK
3692 F09
Figure 9. Synchronous Signal Powered from Regulator’s Output
t
P
SW1
SW2
SW1
SW2
t /2
P
t
P
INPUT
RIPPLE V
t /2
P
t
P
RT/SYNC
3692 F12
CLKOUT
Figure 12. Dual 14.4V/8.5V, 14.4V/3.3V with 180° Phase
t
DCLKOSW1
t
DCLKOSW2
t /2
SW1
SW2
t
P
P
RT/SYNC
3692 F10
t
DRTSYNC
INPUT
RIPPLE V
Figure 10. Timing Diagram RT/SYNC = 1MHz, Duty Cycle = 50%
RT/SYNC
3692 F13
Figure 13. Dual 14.4V/8.5V, 14.4V/3.3V with 256° Phase
3692fa
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LT3692
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Shutdown and Undervoltage/Overvoltage Lockout
There is no hysteresis on the SHDN pins. If the SHDN pins
are not connected to V , then an internal clamp regulates
IN
Typically, undervoltage lockout (UVLO) is used in situa-
tions where the input supply is current limited, or has a
relatively high source resistance. A switching regulator
draws constant power from the source, so source cur-
rent increases as source voltage drops. This looks like a
negative resistance load to the source and can cause the
sourcetocurrentlimitorlatchlowunderlowsourcevoltage
conditions. UVLO prevents the regulator from operating
at source voltages where these problems might occur.
the SHDN pin voltage to 2.5V.
If the SHDN pin is driven by a logic signal greater than
2.5V, a series resistor is required to limit the current into
the SHDN pin to no more than 10µA.
Referring to Figure 15, a 249k resistor will suffice for
a typical logic-level signal. If the logic signal is 5V or
greater, chooseacurrentlimitingresistorequaltoR
=
SHDN
(V
– 2.5V)/10µA. Place a small Schottky diode (such
LOGIC
Overvoltagelockout(OVLO)istypicallyusedtoshutdown
the switching regulator during potentially harmful input
voltage transients.
as a BAT54) in parallel to the current-limiting resistor as
shown in Figure 15.
KeeptheconnectionsfromanyseriesresistorstotheSHDN
pins short and make sure that the interplane or surface
capacitance to switching nodes is minimized.
Referring to Figure 14, if the SHDN pin is connected to
V , then the overvoltage lockout threshold is set to the
IN
typical maximum value of 38V.
R
SHDN
SHDN
LT3692
V
LOGIC
Additionally, an internal comparator will force both chan-
+
–
nels into shutdown below the minimum V
of 2.8V.
IN1
SCHOTTKY
OPTIONAL
LOGIC
This feature can be used to prevent excessive discharge
of battery-operated systems. In addition to the V un-
3692 F15
IF V
< 5V
IN1
dervoltage lockout, both channels will be disabled when
SHDN1 is less than 1.3V.
Figure 15. External Control of the SHDN Pin
Programmable UVLO may be implemented using an input
voltage divider and one of the internal comparators (see
the Typical Applications section).
Soft-Start
The output of the LT3692 regulates to the lowest voltage
presentateithertheSSpinoraninternal0.806Vreference.
A capacitor from the SS pin to ground is charged by an
internal 12µA current source resulting in a linear output
ramp from 0V to the regulated output whose duration is
given by:
When the SHDN pin is taken above 1.3V, its respective
channelisallowedtooperate.WhentheSHDNpinisdriven
below 1.3V, its channel is disabled. Taking SHDN1 below
0.6VwillplacetheLT3692inalowquiescentcurrentmode.
A graph of quiescent current vs SHDN1 voltage can be
found in the Typical Performance Characteristics section.
CSS • 0.806V
tRAMP
=
12µA
V
INX
At power-up, a reset signal sets the soft-start latch and
discharges both SS pins to approximately 0V to ensure
proper start-up. When both SS pins are fully discharged
the latch is reset and the internal 12µA current source
starts to charge the SS pin.
1.3V
+
–
+
–
SHDN1
38V
THERMAL
SHUTDOWN
When the SS pin voltage is below 115mV, the V pin is
C
CHANNEL
DISABLE
LT3692
pulled low which disables switching. This allows the SS
3692 F15
pin to be used as an individual shutdown for each channel.
Figure 14. Connect SHDN to VIN to Select Default OVLO and UVLO
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As the SS pin voltage rises above 90mV, the V pin is re-
The comparators can be used to monitor input and output
voltages as well as die temperature. See the Typical Ap-
plications circuit collection for examples.
C
leased and the output is regulated to the SS voltage. When
the SS pin voltage exceeds the internal 0.806V reference,
theoutputisregulatedtothereference. TheSSpinvoltage
will continue to rise until it is clamped at 2V.
Output Tracking/Sequencing
Complexoutputtrackingandsequencingbetweenchannels
can be implemented using the LT3692’s SS and CMPO
pins. Figure 16 shows several configurations for output
tracking/sequencing for a 3.3V and 1.8V application.
In the event of a V undervoltage lockout, the soft-start
IN1
latch is set for both channels, triggering a full start-up
sequence. If a channel’s SHDN pin is driven below 1.3V,
its overvoltage lockout is enabled, or the internal die
temperature for its power switch exceeds its maximum
rating during normal operation, the soft-start latch is set
for that channel.
Independent soft-start for each channel is shown in Fig-
ure 16a. The output ramp time for each channel is set by
thesoft-startcapacitorasdescribedinthesoft-startsection.
Inaddition,iftheloadexceedsthemaximumoutputswitch
Ratiometric tracking is achieved in Figure 16b by con-
necting both SS pins together. In this configuration, the
SS pin source current is doubled (24µA) which must be
taken into account when calculating the output rise time.
current, the output will start to drop causing the V pin
C
clamp to be activated. As long as the V pin is clamped,
C
the SS pin will be discharged. As a result, the output will
be regulated to the highest voltage that the maximum
output current can support. For example, if a 6V output is
loaded by 1Ω the SS pin will drop to 0.48V, regulating the
output at 4.8V ( 4.8A • 1Ω ). Once the overload condition
is removed, the output will soft start from the temporary
voltage level to the normal regulation point.
By connecting a feedback network from V
to the SS2
OUT1
voltage, absolute
pin with the same ratio that sets V
OUT2
tracking shown in Figure 16c is implemented. The mini-
mum value of the top feedback resistor (R1) should be set
such that the SS pin can be driven all the way to ground
with 1.4mA of sink current when V
is at its regulated
OUT1
Since the SS pin is clamped at 2V and has to discharge
to 0.806V before taking control of regulation, momentary
overload conditions will be tolerated without a soft-start
recovery.ThetypicaltimebeforetheSSpintakescontrolis:
voltage. In addition, a small V
voltage offset will be
OUT2
present due to the SS2 12µA source current. This offset
can be corrected for by slightly reducing the value of R2.
Figure 16d illustrates output sequencing. When V
is
OUT1
CSS •1.2V
1.4mA
within 10% of its regulated voltage, CMPO1 releases the
SS2 soft-start pin allowing V to soft-start. In this case
tSS(CONTROL)
=
OUT2
CMPO1 will be pulled up to 2V by the SS pin. If a greater
voltage is needed for CMPO1 logic, a pull-up resistor to
Open-Collector Comparators
V
can be used. This will decrease the soft-start ramp
OUT1
The CMPO pin is the open-collector output of an internal
comparator. The comparator compares the CMPI pin volt-
age to 90% of the reference voltage (0.72V) with 60mV
of hysteresis.
time and increase tolerance to momentary shorts.
If precise output ramp up and down is required, drive the
SS pins as shown in Figure 16e. The minimum value of
resistor (R3) should be set such that the SS pin can be
driven all the way to ground with 1.4mA of sink current
during power-up and fault conditions.
The CMPO pin has a typical sink capability of 300µA when
theCMPIpinisbelowthethresholdandcanwithstand38V
when the threshold is exceeded. The CMPO pin is active
(sink capability is reduced in shutdown and undervoltage
lockoutmode)aslongastheV pinvoltageexceeds2.8V.
IN1
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Independent Start-Up
Ratiometric Start-Up
Absolute Start-Up
V
V
OUT1
0.5V/DIV
V
OUT1
OUT1
0.5V/DIV
0.5V/DIV
PG1
PG2
PG1
PG2
PG1
V
V
V
OUT2
OUT2
OUT2
0.5V/DIV
0.5V/DIV
0.5V/DIV
PG2
5ms/DIV
10ms/DIV
10ms/DIV
LT3692
LT3692
LT3692
V
OUT1
V
OUT1
V
OUT1
R1 R3
R2
R1 R3
R1 R3
FB1
CMPI1
FB1
CMPI1
FB1
CMPI1
R2
R2
2.5V
2.5V
2.5V
CMPO1
CMPO1
CMPO1
12µA
SS1
12µA
SS1
12µA
SS1
PG1
PG1
PG1
0.72V
+
–
0.72V
+
–
0.72V
+
–
0.1µF
0.1µF
R4 R6
0.1µF
V
V
V
OUT2
OUT2
OUT2
R4 R6
R5
R4 R6
R5
FB2
FB2
FB2
CMPI2
CMPI2
CMPI2
R5
2.5V
2.5V
2.5V
CMPO2
CMPO2
CMPO2
PG2
PG2
PG2
12µA
SS2
12µA
SS2
12µA
SS2
0.72V
+
–
0.72V
+
–
0.72V
+
–
R8
0.22µF
R7
(16a)
(16b)
(16c)
Output Sequencing
Controlled Power Up and Down
V
OUT1
V
OUT1
0.5V/DIV
0.5V/DIV
PG1/PG2
V
OUT2
V
OUT2
0.5V/DIV
0.5V/DIV
PG1
PG2
SS1/2
10ms/DIV
10ms/DIV
LT3692
LT3692
V
OUT1
V
OUT1
R1
R2
R1 R3
FB1
CMPI1
FB1
CMPI1
R2
2.5V
2.5V
CMPO1
CMPO1
12µA
SS1
12µA
SS1
PG1
PG1
0.72V
+
–
0.72V
+
–
R5
+
0.1µF
–
V
OUT2
V
OUT2
R4 R6
R5
R4 R6
R5
FB2
CMPI2
FB2
CMPI2
2.5V
2.5V
CMPO2
CMPO2
PG2
PG2
12µA
SS2
12µA
SS2
0.72V
+
–
0.72V
+
–
3692 F16
0.22µF
(16d)
(16e)
Figure 16. SS Pin Configurations
3692fa
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LT3692
applicaTions inForMaTion
Application Optimization
Single Step Down:
1.8 + 0.6
36V – 0.4+ 0.6 225ns
1
In multiple channel applications requiring large V to
OUT
IN
Frequency (Hz) =
•
≅ 250kHz
V
ratios, the maximum frequency and resulting in-
ductor size is determined by the channel with the largest
ratio. The LT3692’s multi-frequency operation allows the
user to minimize component size for each channel while
maintaining constant frequency operation. The circuit in
Figure 17 illustrates this approach. A 2-stage step-down
approach coupled with multi-frequency operation will
further reduce external component size by allowing an
36V – 3.3 • 3.3
36V • 250kHz
(
)
L1=
L2 =
≥ 12µH
36V – 1.8 •1.8
36V • 250kHz
(
)
≥ 6.8µH
2-Stage Step-Down:
increase in frequency for the channel with the lower V
IN
3.3+ 0.6
1
to V
ratio. The drawback to this approach is that the
OUT
Frequency (Hz) =
•
≅ 400kHz
36V – 0.4+ 0.6 225ns
output power capability for the first stage is determined
by the output power drawn from the second stage. The
dual step-down application in Figure 18 steps down the
36V – 3.3 • 3.3
(
)
L1=
L2 =
≥ 7.5µH
≥ 2µH
36V • 400kHz
input voltage (V ) to the highest output voltage then
IN1
usesthatvoltagetopowerthesecondoutput(V ).V
IN2
OUT1
3.3 – 1.8 •1.8
3.3 • 400kHz
(
)
must be able to provide enough current for its output plus
V
maximum load. Note that the V
voltage must
OUT2
OUT1
be above V ’s minimum input voltage as specified in the
IN2
2-Stage Step-Down Multi-Frequency:
= 100k, FREQ1 = 400kHz, FREQ2 = 1600kHz.
Electrical Characteristics (2.8V) when the second channel
starts to switch. Delaying channel 2 can be accomplished
by either independent soft-start capacitors or sequencing
with the CMP01 output.
R
DIV
36V – 3.3 • 3.3
36V • 400kHz
(
)
L1=
≥ 7.5µH
For example, assume a maximum input of 36V:
3.3 – 1.8 •1.8
3.3 • 2MHz
(
)
L2 =
≥ 500nH
V = 36V, V
= 3.3V at 1.5A and V
= 1.8V at 1.5A.
IN
OUT1
OUT2
VOUT + VD
1
Frequency (Hz) =
•
In addition, R
= 40.2k reduces the peak current limit
ILIM2
V – V + VD tON(MIN)
IN
SW
on channel to 2.5A, which reduces inductor size and catch
diode requirements.
V – V
• V
OUT
(
)
IN
OUT
L =
V • f
IN
3692fa
23
For more information www.linear.com/3692
LT3692
applicaTions inForMaTion
V
IN
5V TO 36V
4.7µF
4.7µF
V
IN1
V
IN2
SHDN1
BST1
SHDN2
BST2
SW1
IND1
SW2
IND2
8.2µH
8.2µH
24.9k
0.47µF
0.47µF
LT3692
V
V
OUT2
OUT1
3.3V 3A
400kHz
V
OUT1
V
1.8V 3A
200kHz
OUT2
100µF
×3
100µF
100pF 10k
100pF
8.06k
FB1
FB2
8.06k
100k
CMPI1
CMPI2
CMPO1
SS1
CMPO2
SS2
PG
ILIM1
ILIM2
V
V
C2
C1
CLOCKOUT
400kHz
RT/SYNC CLKOUT
DIV
0.1µF
680pF
470pF
T
J
GND
0.1µF
33pF
33pF
120k
10k
10.2k 62k
0.1µF
49.9k
16.5k
120k
3692 F17
Figure 17. 3.3V and 1.8V Dual Step-Down Multi-Frequency Converter
V
IN
5V TO 36V
4.7µF
1µF
V
V
IN2
IN1
SHDN1
BST1
SHDN2
BST2
SW1
IND1
SW2
IND2
8.2µH
24.9k
1µH
0.47µF
0.22µF
LT3692
V
V
OUT2
OUT1
1.8V 1A
V
OUT1
V
3.3V 2.5A
400kHz
OUT2
1600kHz
47µF
100µF
100pF
8.06k
10k
100pF
8.06k
FB1
FB2
100k
PG
CMPI1
CMPI2
CMPO1
SS1
CMPO2
SS2
ILIM1
ILIM2
0.1µF
V
V
C2
C1
CLOCKOUT
1600kHz
RT/SYNC CLKOUT
DIV
470pF
330pF
T
J
GND
0.1µF
33pF
33pF
49.9k
120k
16.5k
47.5k 100k
36.5k
40.2k
0.1µF
3692 F18
Figure 18. 3.3V and 1.8V 2-Stage Dual Step-Down Multi-Frequency Converter
3692fa
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LT3692
applicaTions inForMaTion
Shorted and Reverse Input Protection
PCB Layout
If the inductor is chosen so that it won’t saturate exces-
sively,anLT3692step-downregulatorwilltolerateashorted
output. There is another situation to consider in systems
where the output will be held high when the input to the
LT3692 is absent. This may occur in battery charging
applicationsorinbatteryback-upsystemswhereabattery
or some other supply is diode OR-ed with the LT3692’s
For proper operation and minimum EMI, care must be
taken during printed circuit board (PCB) layout. Figure 20
shows the high di/dt paths in the buck regulator circuit.
Notethatlargeswitchedcurrentsflowinthepowerswitch,
the catch diode and the input capacitor. The loop formed
by these components should be as small as possible.
These components, along with the inductor and output
capacitor, should be placed on the same side of the circuit
board and their connections should be made on that layer.
Place a local, unbroken ground plane below these com-
ponents, and tie this ground plane to system ground at
one location, ideally at the ground terminal of the output
capacitor C2. Additionally, the SW and BST traces should
be kept as short as possible.
output. If the V
pin is allowed to float and the SHDN
IN1/2
pin is held high (either by a logic signal or because it is
tied to V ), then the LT3692’s internal circuitry will pull its
IN
quiescent current through its SW pin. This is fine if your
system can tolerate a few mA in this state. If you ground
the SHDN pin, the SW pin current will drop to essentially
zero. However, if the V pin is grounded while the output
IN
is held high, then parasitic diodes inside the LT3692 can
pull large currents from the output through the SW pin
Thermal Considerations
and the V
pin. Figure 19 shows a circuit that will run
IN1/2
The PCB must also provide heat sinking to keep the
LT3692 cool. The exposed metal on the bottom of the
package must be soldered to a ground plane. This ground
should be tied to other copper layers below with thermal
vias; these layers will spread the heat dissipated by the
LT3692.Placeadditionalviasnearthecatchdiodes.Adding
more copper to the top and bottom layers and tying this
copper to the internal planes with vias can further reduce
thermal resistance. With these steps, the thermal resis-
tance from die (or junction) to ambient can be reduced to
only when the input voltage is present and that protects
against a shorted or reversed input.
PARASITIC DIODE
D4
V
SW
IN
V
V
IN1/2
OUT1/2
LT3692
3692 F19
θ
JA
= 35°C/W.
Figure 19. Diode D4 Prevents a Shorted Input from Discharging a
Backup Battery Tied to the Output
LT3692
GND
LT3692
GND
LT3692
GND
V
V
V
IN
SW
SW
SW
IN
IN
3692 F20
(20a)
(20b)
(20c)
Figure 20. Subtracting the Current when the Switch is On (20a) from the Current when the Switch is Off (20b) Reveals the Path of the
High Frequency Switching Current (20c). Keep this Loop Small. The Voltage on the SW and BST Traces will Also Be Switched; Keep
These Traces as Short as Possible. Finally, Make Sure the Circuit is Shielded with a Local Ground Plane
3692fa
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LT3692
applicaTions inForMaTion
The power dissipation in the other power components
such as catch diodes, boost diodes and inductors, cause
additional copper heating and can further increase what
the IC sees as ambient temperature. See the LT1767 data
sheet’s Thermal Considerations section.
Generating a Negative Regulated Voltage
The simple charge pump circuit in Figure 22 uses the
CLKOUT pin output to generate a negative voltage, elimi-
nating the need for an external regulated supply. Surface
mount capacitors and dual-package Schottky diodes
minimize the board area needed to implement the nega-
tive voltage supply.
Die Temperature and Thermal Shutdown
The LT3692 T pin outputs a voltage proportional to the
J
internal junction temperature. The T pin typically outputs
J
250mV for 25°C and has a slope of 10mV/°C. Without the
LT3692
R1
aidofexternalcircuitry,theT pinoutputisvalidfrom20°C
J
T
J
to150°C(200mVto1.5V)withamaximumloadof100µA.
V
NEG
GND
+
Full Temperature Range Measurement
3692 F23
To extend the operating temperature range of the T out-
J
put below 20°C, connect a resistor from the T pin to a
J
Figure 21. Circuit to Extend the TJ Pin Operating Range
negative supply as shown in Figure 21. The negative rail
voltage and T pin resistor may be calculated using the
J
following equations:
30k
2 • TEMP(MIN)°C
T
J
VNEG
≤
100
LT3692
CLKOUT
GND
330pF
D4
| VNEG
33µA
|
R1 ≤
0.1µF
D3
3692 F23
D3, D4: ZETEX BAT54S
where:
TEMP(MIN)°C is the minimum temperature where a
Figure 22. Circuit to Generate the Negative Voltage Rail to
Extend the TJ Pin Operating Range
valid T pin output is required.
J
V
NEG
= Regulated negative voltage supply.
For example:
TEMP(MIN)°C = –40°C
V
NEG
V
NEG
≤ –0.8V
= –1, R1 ≤ |V |/33µA = 30.2kΩ
NEG
3692fa
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For more information www.linear.com/3692
LT3692
applicaTions inForMaTion
As a safeguard, the LT3692 has an additional thermal
shutdownthresholdsetatatypicalvalueof163°Cforeach
channel. Each time the threshold is exceeded, a power on
sequence for that channel will be initiated. The sequence
will then repeat until the thermal overload is removed.
clock signal phase delay. Figures 23 and 24 show the im-
pact of capacitive loading on the CLKOUT signal rise and
fall times. Note that a typical 10:1 150MHz oscilloscope
probe contributes significant capacitance to the CLKOUT
node, necessitating a low capacitance probe for accurate
measurements.ApplicationsrequiringCLKOUTtogenerate
the negative supply voltage and provide the synchroniza-
tion clock to other regulators may benefit from buffering
CLKOUT prior to the charge pump circuitry.
It should be noted that the T pin voltage represents
J
a steady-state temperature and should not be used to
guarantee that maximum junction temperatures are
not exceeded. Instantaneous power along with thermal
gradients and time constants may cause portions of the
die to exceed maximum ratings and thermal shutdown
thresholds. Be sure to calculate die temperature rise for
steady state (>1Min) as well as impulse conditions.
Other Linear Technology Publications
Application notes AN19, AN35 and AN44 contain more
detailed descriptions and design information for buck
regulators and other switching regulators. The LT1376
data sheet has a more extensive discussion of output
ripple, loop compensation and stability testing. Design
Note DN100 shows how to generate a dual (+ and –)
output supply using a buck regulator.
CLKOUT Capacitive Loading
A minor drawback to generating a negative rail from the
CLKOUT pin is that the charge pump adds capacitance to
the CLKOUT pin, resulting in an output synchronization
SCOPE PROBE: 15pF
CHARGE PUMP
CHARGE PUMP
SCOPE PROBE: 15pF
SYNCHRONIZED LT3692
RT/SYNC PIN
FET PROBE: 2pF
SYNCHRONIZED
LT3692 RT/SYNC PIN
500mV/DIV
500mV/DIV
FET PROBE: 2pF
3692 F23
3692 F24
40ns/DIV
FREQUENCY: 1.000MHz
20ns/DIV
FREQUENCY: 1.000MHz
Figure 23. CLKOUT Rise Time
Figure 24. CLKOUT Fall Time
3692fa
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For more information www.linear.com/3692
LT3692
Typical applicaTions
3692fa
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LT3692
Typical applicaTions
3.3V and 1.8V 2-Stage Dual Step-Down Multi-Frequency Converter
V
IN
5V TO 36V
4.7µF
1µF
V
V
IN2
IN1
SHDN1
BST1
SHDN2
BST2
SW1
IND1
SW2
IND2
8.2µH
24.9k
1µH
0.47µF
0.22µF
LT3692
V
V
OUT2
OUT1
1.8V 1A
V
OUT1
V
3.3V 2.5A
400kHz
OUT2
1600kHz
47µF
100µF
100pF
8.06k
10k
100pF
8.06k
FB1
FB2
100k
PG
CMPI1
CMPI2
CMPO1
SS1
CMPO2
SS2
ILIM1
ILIM2
0.1µF
V
V
C2
C1
CLOCKOUT
1600kHz
RT/SYNC CLKOUT
DIV
470pF
330pF
T
J
GND
0.1µF
33pF
33pF
49.9k
120k
16.5k
47.5k 100k
36.5k
40.2k
0.1µF
3692 TA02
12V to 3.3V and 2.5V Converter with Start-Up Current Limiting
V
IN
12V
4.7µF
4.7µF
V
V
IN2
IN1
SHDN1
BST1
SHDN2
BST2
SW1
IND1
SW2
IND2
2.2µH
2.2µH
24.9k
0.22µF
0.22µF
100pF
LT3692
V
V
OUT2
OUT1
3.3V 3A
1MHz
V
OUT1
V
2.5V 3A
1MHz
OUT2
100pF 16.9k
47µF
47µF
FB1
FB2
8.06k
8.06k
CMPI1
CMPI2
CMPO2
SS2
CMPO1
SS1
ILIM1
ILIM2
V
V
C2
C1
CLOCKOUT
1MHz
RT/SYNC CLKOUT
DIV
33pF
0.1µF
120k
0.1µF
330pF
T
J
GND
33pF
330pF
120k
0.1µF
0.1µF
21.0k
28.0k
0.1µF
49.9k
24.9k
3692 TA04
3692fa
29
For more information www.linear.com/3692
LT3692
Typical applicaTions
3.3V/6A Single Output with UVLO and 100°C Temperature Warning
V
IN
6V TO 30V
4.7µF
4.7µF
80.6k
V
V
IN2
IN1
6.5V UVLO RISING
6V UVLO FALLING
SHDN1
BST1
SHDN2
BST2
SW1
IND1
SW2
IND2
10k
6.8µH
6.8µH
FB1
0.22µF
8.06k
0.22µF
100k
V
OUT
LT3692
3.3V 6A
V
V
OUT1
V
OUT
OUT2
FB2
800kHz
EFFECTIVE RIPPLE
100pF 24.9k
47µF
47µF
FB1
CMPI1
CMPI2
CMPO2
SS2
100°C TEMP FLAG
CMPO1
SS1
SS1
ILIM1
ILIM2
ILIM1
V
C1
V
C2
V
C1
RT/SYNC CLKOUT
DIV
CLOCKOUT 400kHz
0.1µF
680pF
T
J
GND
28k
33pF
R3
73.2k
60.4k
10k
10.2k
0.1µF
3692 TA05
Power Supply Dual Input Single 3.3V/4A Output Step-Down Converter
V
IN2
V
IN1
5V TO 36V
1A MAX
5V TO 36V
4.7µF
2.2µF
V
V
IN2
IN1
SHDN1
BST1
SHDN2
BST2
SW1
IND1
SW2
IND2
5.6µH
24.9k
6.8µH
0.22µF
0.22µF
47µF
LT3692
V
OUT1
3.3V
4A
V
V
OUT1
V
OUT1
OUT2
100pF
47µF
FB1
FB2
CMPI2
CMPO2
SS2
8.06k
100k
CMPI1
FB1
PG
CMPO1
SS1
ILIM1
ILIM2
V
C1
V
C2
V
C1
RT/SYNC CLKOUT
DIV
CLOCKOUT 400kHz
0.1µF
330pF
0.1µF
T
J
GND
33pF
49.9k
0.1µF
120k
24.9k
10.2k
3692 TA07
3692fa
30
For more information www.linear.com/3692
LT3692
Typical applicaTions
5V and 1.8V Dual 2-Stage Converter
1µF
V
IN
6V TO 36V
4.7µF
V
V
IN2
IN1
SHDN1
BST1
SHDN2
BST2
SW1
IND1
SW2
IND2
8.2µH
42.2k
1µH
0.22µF
0.22µF
LT3692
V
V
OUT2
OUT1
1.8V 2A
2MHz
V
OUT1
V
5V 2A
OUT2
500kHz
47µF
×2
220pF
8.06k
47µF
10k
100pF
8.06k
FB1
FB2
FB1
CMPI1
CMPI2
R9
100k
PG
CMPO1
SS1
CMPO2
SS2
ILIM1
ILIM2
V
C1
V
C2
RT/SYNC CLKOUT
DIV
330pF
47pF
33pF
330pF
0.1µF
T
J
GND
0.1µF
120k
36.5k
61.9k 100k
49.9k 39.2k
120k
0.1µF
3692 TA10
3692fa
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For more information www.linear.com/3692
LT3692
Typical applicaTions
3692fa
32
For more information www.linear.com/3692
LT3692
Typical applicaTions
5V, 3.3V, 2.5V, 1.8V Synchronized Quad Output
V
5V
2A
OUT1
2.2µF
SV
PV
IN
IN2
PV
DDR
IN
3.3µH
270k
V
3.3V
2A
OUT2
V
PGOOD
SW
FB
IN1
7V TO 36V
100µF
100µF
100µF
4.7µF
×2
LT3612
RUN
MODE
RT
ITH
TRACK/SS
PGND
60.4k
SGND
V
V
IN2
IN1
SHDN1
BST1
SHDN2
BST2
SW1
IND1
SW2
IND2
6.8µH
6.8µH
FB1
2.2µF
0.22µF
0.22µF
47µF
SV
PV
IN
IN2
PV
LT3692
DDR
IN
V
OUT1
V
3.3µH
V
2.5V
2A
OUT2
OUT3
PGOOD
SW
FB
100pF 42.2k
47µF
FB1
FB2
LT3612
191k
RUN
MODE
RT
CMPI1
CMPI2
100k
8.06k
ITH
100°C
TEMP FLAG
CMPO2
SS2
TRACK/SS
PGND
CMPO1
SS1
60.4k
SS1
SGND
ILIM1
ILIM2
ILIM1
V
C1
CLOCKOUT
600kHz
V
V
C2
C1
RT/SYNC CLKOUT
DIV
0.1µF
330pF
T
J
2.2µF
GND
28k
33pF
SV
IN
PV
IN2
PV
73.2k
DDR
IN
3.3µH
V
1.8V
2A
0.1µF
OUT4
60.4k
24.9k
16k
R14
49.9k
PGOOD
SW
FB
LT3612
121k
RUN
MODE
RT
ITH
TRACK/SS
PGND
60.4k
SGND
3692 TA08
0.1µF
3692fa
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For more information www.linear.com/3692
LT3692
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
0.70 ±0.05
5.50 ±0.05
4.10 ±0.05
3.45 ± 0.05
3.50 REF
(4 SIDES)
3.45 ± 0.05
PACKAGE OUTLINE
0.25 ± 0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
R = 0.05
TYP
0.00 – 0.05
R = 0.115
TYP
0.75 ± 0.05
5.00 ± 0.10
(4 SIDES)
31 32
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.45 ± 0.10
3.50 REF
(4-SIDES)
3.45 ± 0.10
(UH32) QFN 0406 REV D
0.200 REF
0.25 ± 0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3692fa
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For more information www.linear.com/3692
LT3692
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
3/13
Clarified Shutdown Quiescent Current vs Temperature Graph
Clarified SHDN1/2 Pin Function description
5
9
Clarified SHDN pin operation in Applications Information operation in general description
Clarified SHDN pin operation description in Applications Information
10
20
3692fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
35
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT3692
Typical applicaTion
1.2MHz, 12V to 3.3V at 3A, 5V at 3A
V
IN
12V
4.7µF
4.7µF
V
V
IN2
IN1
SHDN1
BST1
SHDN2
BST2
SW1
IND1
SW2
IND2
2.2µH
2.2µH
42.2k
0.22µF
0.22µF
LT3692
V
V
OUT2
OUT1
3.3V 3A
1.2MHz
5V 3A
V
OUT1
V
OUT2
FB2
1.2MHz
100pF 24.9k
100pF
8.06k
22µF
47µF
FB1
100k
100k
CMPI1
CMPI2
8.06k
PG1
CMPO1
SS1
CMPO2
SS2
PG
ILIM1
ILIM2
V
V
C2
C1
CLOCKOUT
1.2MHz
RT/SYNC CLKOUT
DIV
0.1µF
120k
330pF
33pF
330pF
30.1k
T
J
GND
0.1µF
33pF
49.9k
24.9k
42.2k
0.1µF
120k
3692 TA09
relaTeD parTs
PART
DESCRIPTION
COMMENTS
V : 4V to 36V, V
LT3507
36V, Triple 2.4A, 1.4A and 1.4A (I ), 2.5MHz, High Efficiency Step-Down
DC/DC Converter with LDO Controller
= 0.8V, I = 7mA, I = 1µA,
OUT(MIN) Q SD
OUT
IN
(5mm × 7mm) QFN-38
LT3508
LT3680
LT3693
LT3480
LT3980
LT3971
LT3991
36V with Transient Protection to 40V, Dual 1.4A (I ), 3MHz, High Efficiency V : 3.7V to 37V, V
= 0.8V, I = 4.6mA, I = 1µA,
OUT
IN
OUT(MIN) Q SD
Step-Down DC/DC Converter
(4mm × 4mm) QFN-24, TSSOP-16E
36V, 3A, 2.4MHz High Efficiency Micropower Step-Down DC/DC Converter
36V, 3A, 2.4MHz High Efficiency Step-Down DC/DC Converter
V : 3.6V to 36V, V = 0.8V, I = 75µA, I < 1µA,
IN
OUT(MIN)
Q
SD
(3mm × 3mm) DFN-10, MSOP-10E
V : 3.6V to 36V, V
= 0.8V, I = 1.3mA, I < 1µA,
IN
OUT(MIN)
Q
SD
(3mm × 3mm) DFN-10, MSOP-10E
36V with Transient Protection to 60V, 2A (I ), 2.4MHz, High Efficiency
V : 3.6V to 38V, Transients to 60V, V
Q SD
= 0.78V,
OUT
IN
OUT(MIN)
Step-Down DC/DC Converter with Burst Mode® Operation
I = 70µA, I < 1µA, (3mm × 3mm) DFN-10, MSOP-10E
58V with Transient Protection to 80V, 2A (I ), 2.4MHz, High Efficiency
V : 3.6V to 58V, Transients to 80V, V
= 0.79V,
OUT
IN
OUT(MIN)
Step-Down DC/DC Converter with Burst Mode Operation
I = 75µA, I < 1µA, (3mm × 4mm) DFN-16, MSOP-16E
Q SD
38V, 1.2A (I ), 2MHz, High Efficiency Step-Down DC/DC Converter with
V : 4.2V to 38V, V
= 1.2V, I = 2.8µA, I < 1µA,
OUT(MIN) Q SD
OUT
IN
Only 2.8µA of Quiescent Current
(3mm × 3mm) DFN-10, MSOP-10E
55V, 1.2A (I ), 2MHz, High Efficiency Step-Down DC/DC Converter with
V : 4.2V to 55V, V = 1.2V, I = 2.8µA, I < 1µA,
OUT
IN
OUT(MIN)
Q
SD
Only 2.8µA of Quiescent Current
(3mm × 3mm) DFN-10, MSOP-10E
3692fa
LT 0313 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
36
●
●
LINEAR TECHNOLOGY CORPORATION 2011
(408)432-1900 FAX: (408) 434-0507 www.linear.com/3692
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