LT3741EUF-PBF [Linear]
High Power, Constant Current, Constant Voltage, Step-Down Controller; 高功率，恒定电流，恒定电压，降压型控制器
| 型号： | LT3741EUF-PBF |
| 厂家： | 
Linear |
| 描述： | High Power, Constant Current, Constant Voltage, Step-Down Controller |
| 文件： | 总24页 (文件大小：321K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3741
High Power, Constant
Current, Constant Voltage,
Step-Down Controller
FeaTures
DescripTion
The LT®3741 is a fixed frequency synchronous step-down
DC/DCcontrollerdesignedtoaccuratelyregulatetheoutput
current at up to 20A. The average current-mode controller
willmaintaininductorcurrentregulationoverawideoutput
n
Control Pin Provides Accurate Control of Regulated
Output Current
n
1.5% Voltage Regulation Accuracy
n
±±% Current Regulation Accuracy
6V to 36V Input Voltage Range
Wide Output Voltage Range Up to (V – 2V)
Average Current Mode Control
n
voltage range of 0V to (V – 2V). The regulated current is
IN
n
set by an analog voltage on the CTRL pins and an external
sense resistor. Due to its unique topology, the LT3741 is
capable of sourcing and sinking current. The regulated
voltage and overvoltage protection are set with a voltage
dividerfromtheoutputtotheFBpin.Soft-Startisprovided
to allow a gradual increase in the regulated current during
startup. The switching frequency is programmable from
200kHz to 1MHz through an external resistor on the RT
pin or through the use of the SYNC pin and an external
clock signal.
IN
n
n
<1µA Shutdown Current
Up to 94% Efficiency
n
n
Additional Pin for Thermal Control of Load Current
n
Thermally Enhanced 4mm × 4mm QFN and 20-Pin
FE Package
applicaTions
n
General Purpose Industrial
Additional Features include an accurate external reference
voltage for use with the CTRL pins, an accurate UVLO/EN
pin that allows for programmable UVLO hysteresis, and
thermal shutdown.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 7199560, 7321203 and others pending.
n
Super-Cap Charging
n
Applications Needing Extreme Short-Circuit
Protection and/or Accurate Output Current Limit
n
Constant Current or Constant Voltage Source
Typical applicaTion
10V/20A Constant Current, Constant Voltage Step-Down Converter
VOUT vs IOUT
V
IN
V
EN/UVLO
82.5k
EN/UVLO
RT
SYNC
IN
14V TO 36V
12
10
8
1µF
100µF
HG
LT3741
220nF
V
REF
CBOOT
SW
2.2µH
V
10V
20A
2.5mΩ
10nF
OUT
CTRL1
VC
6
V
CC_INT
22µF
39.2k
5.6nF
4
R
LG
HOT
150µF
s2
45.3k
GND
V
V
I
= 18V
2
IN
OUT
+
–
CTRL2
SS
SENSE
SENSE
= 10V
= 20A
88.7k
12.1k
LIMIT
0
R
NTC
FB
0
2
4
6
8
10 12 14 16 18 20 22
(A)
10nF
I
OUT
3741 TA01b
3741 TA01a
3741f
ꢀ
LT3741
absoluTe maximum raTings (Note 1)
V Voltage................................................................40V
CBOOT – SW Voltage..................................................6V
RT Voltage...................................................................3V
FB Voltage...................................................................3V
SS Voltage ..................................................................6V
IN
EN/UVLO Voltage ........................................................6V
V
Voltage................................................................3V
REF
CTRL1 and CTRL2 Voltage..........................................3V
+
SENSE Voltage ........................................................40V
V
Voltage...........................................................6V
CC_INT
–
SENSE Voltage ........................................................40V
SYNC Voltage..............................................................6V
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
VC Voltage ..................................................................3V
SW Voltage ...............................................................40V
CBOOT ......................................................................46V
TSSOP .............................................................. 300°C
pin conFiguraTion
TOP VIEW
TOP VIEW
V
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
LG
CC_INT
GND
CBOOT
SW
20 19 18 17 16
V
IN
EN/UVLO
HG
1
2
3
4
5
15
14
13
12
11
EN/UVLO
HG
V
GND
SYNC
RT
REF
V
GND
SYNC
RT
REF
21
GND
21
GND
CTRL2
GND
CTRL2
GND
CTRL1
GND
CTRL1
SS
VC
–
SENSE
SENSE
6
7
8
9 10
+
FB 10
FE PACKAGE
20-LEAD PLASTIC TSSOP
UF PACKAGE
20-LEAD (4mm s 4mm) PLASTIC QFN
= 125°C, θ = 37°C/W
T
= 125°C, θ = 38°C/W
JA
JMAX
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
T
JMAX
JA
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
orDer inFormaTion
LEAD FREE FINISH
LT3741EUF#PBF
LT3741IUF#PBF
LT3741EFE#PBF
LT3741IFE#PBF
TAPE AND REEL
PART MARKING*
3741
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3741EUF#TRPBF
LT3741IUF#TRPBF
LT3741EFE#TRPBF
LT3741IFE#TRPBF
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
20-Lead (4mm × 4mm) Plastic QFN
20-Lead (4mm × 4mm) Plastic QFN
20-Lead Plastic TSSOP
3741
LT3741FE
LT3741FE
20-Lead Plastic TSSOP
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3741f
ꢁ
LT3741
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VEN/UVLO = 5V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
Input Voltage Range
6
36
V
V
Pin Quiescent Current (Note 2)
Non-Switching Operation
Shutdown Mode
IN
Not Switching
EN/UVLO
1.8
0.1
2.5
1
mA
µA
V
= 0V
EN/UVLO Pin Falling Threshold
EN/UVLO Hysteresis
EN/UVLO Pin Current
SYNC Pin Threshold
CTRL1 Pin Control Range
CTRL1 Pin Current
1.49
0
1.55
130
5.5
1.61
V
mV
µA
V
V
= 6V, EN/UVLO = 1.45V
IN
1.0
1.5
V
CTRL1 = 1.5V
100
2
nA
Reference
l
l
Reference Voltage (V Pin)
1.94
48
2.06
54
V
REF
Inductor Current Sensing
+
–
Full Range SENSE to SENSE
V
= 1.5V
51
50
10
mV
nA
µA
CTRL1
+
SENSE Pin Current
–
SENSE Pin Current
With V
~ 4V, V
= 0V
CTRL1
OUT
Internal V Regulator (V
Pin)
CC
CC_INT
l
Regulation Voltage
4.7
5
5.2
V
NMOS FET Driver
Non-Overlap time HG to LG
Non-Overlap time LG to HG
Minimum On-Time LG
Minimum On-Time HG
Minimum Off-Time LG
100
60
50
80
65
ns
ns
ns
ns
ns
(Note 3)
(Note 3)
(Note 3)
High Side Driver Switch On-Resistance
Gate Pull Up
V
– V = 5V
SW
CBOOT
2.3
1.3
Ω
Ω
Gate Pull Down
Low Side Driver Switch On-Resistance
Gate Pull Up
V
= 5V
CC_INT
2.3
1.0
Ω
Ω
Gate Pull Down
Switching Frequency
l
f
R = 40kΩ
T
900
190
1000
218
1070
233
kHz
kHz
SW
T
R = 200kΩ
Soft-Start
Charging Current
Voltage Regulation Amplifier
Input Bias Current
11
µA
FB = 1.3V
850
800
1.21
nA
µA/V
V
g
m
–
l
Feedback Regulation Voltage
CTRL1 = 1.5V, I
= 23µA
1.192
1.228
SENSE
3741f
ꢂ
LT3741
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VEN/UVLO = 5V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Current Control Loop g Amp
m
l
Offset Voltage
–3
0
3
mV
Input Common Mode Range
V
V
0
2
V
V
CM(LOW)
CM(HIGH)
V
Measured from V to V
IN CM
CM(HIGH)
Output Impedance
3.5
475
1.7
MΩ
µA/V
mV/V
g
375
625
m
Differential Gain
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3741I is guaranteed to meet performance specifications over the –40°C
to 125°C operating junction temperature range.
Note 2: The LT3741E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
Note 3: The minimum on and off times are guaranteed by design and are
not tested.
3741f
ꢃ
LT3741
Typical perFormance characTerisTics
EN/UVLO Threshold (Falling)
EN/UVLO Pin Current
IQ in Shutdown
0.5
0.4
0.3
0.2
0.1
0
1.70
1.64
1.58
1.52
1.46
1.40
10
8
6
–50°C
130°C
130°C
25°C
4
2
25°C
130°C
–50°C
0
0
8
16
24
(V)
32
40
6
12
18
24
(V)
30
36
6
12
24
(V)
30
36
18
V
V
V
IN
IN
IN
3741 G03
3741 G01
3741 G02
Quiescent Current (Non-Switching)
VREF Pin Voltage
VREF Current Limit
1.6
1.4
1.2
1.0
0.8
2.0
1.6
1.2
0.8
0.4
0
2.06
2.05
2.04
2.03
2.02
2.01
2.00
1.99
1.98
T
= 25°C
A
V
= 36V
IN
T
= 130°C
A
V
= 6V
IN
T
= –50°C
A
T
T
T
= 25°C
= 130°C
= –50°C
A
A
A
6
12
18
24
30
36
6
12
18
24
(V)
30
36
–50
–15
20
55
90
125
V
(V)
V
TEMPERATURE (°C)
IN
IN
3741 G04
3741 G06
3741 G05
VCC_INT Current Limit
RT Pin Current Limit
Soft-Start Pin Current
14
13
12
11
10
9
90
80
70
60
50
40
6
5
4
3
2
1
0
V
IN
= 36V
V
IN
= 6V
8
7
V
A
= 12V
IN
T
= 25°C
6
–50
–15
20
55
90
125
–50
–15
20
55
90
125
0
10
30
(mA)
40
50
20
60
TEMPERATURE (°C)
TEMPERATURE (°C)
I
LOAD
3741 G07
3741 G08
3741 G09
3741f
ꢄ
LT3741
Typical perFormance characTerisTics
CBOOT-SW UVLO Voltage
VCC_INT UVLO
Internal UVLO
5.0
4.5
4.0
3.5
3.0
3.00
2.75
4.00
3.75
2.50
2.25
3.50
3.25
2.00
1.75
1.50
3.00
2.75
2.50
–50
–15
20
55
90
125
–50
–15
20
55
90
125
–50
–15
20
55
90
125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3741 G11
3741 G10
3741 G12
Regulated Current vs VFB
Overvoltage Threshold
VCC_INT Load Reg at 12V
150
100
50
1.75
1.65
1.55
1.45
1.35
1.25
6.0
5.6
5.2
4.8
4.4
4.0
0
25°C
–50
–100
–150
–200
–50°C
130°C
1.30 1.35
1.10
1.15
1.20
V
1.25
(V)
–50 –25
0
25
50
75 100 125
0
10
20
30
(mA)
40
50
60
TEMPERATURE (°C)
I
FB
LOAD
3741 G14
3741 G15
3741 G13
Overvoltage Timeout
Regulated Sense Voltage
Common Mode Lockout
19
17
15
13
11
9
60
50
2.5
2.0
1.5
1.0
0.5
0
MEASURED V – V
IN
OUT
V
= 6V
IN
40
30
V
= 36V
IN
20
10
0
–50
–15
20
55
90
125
0
0.5
1.0
1.5
2.0
–50
–15
20
55
90
125
V
(V)
TEMPERATURE (°C)
TEMPERATURE (°C)
CTRL
3741 G16
3741 G17
3741 G18
3741f
ꢅ
LT3741
Typical perFormance characTerisTics
HG Driver RDS(ON)
LG Driver RDS(ON)
Minimum Off-Time
5
4
3
2
1
0
300
240
180
120
60
5
4
3
2
1
0
HG
PULL-UP
PULL-UP
PULL-DOWN
LG
PULL-DOWN
0
–50
–15
20
55
90
125
–50
–15
20
55
90
125
–50
–15
20
55
90
125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3741 G21
3741 G25
3741 G20
Non-Overlap Time
Minimum On-Time
Oscillator Frequency
150
120
90
60
30
0
150
120
90
60
30
0
1.5
1.2
0.9
0.6
0.3
0
1.2MHz
HG TO LG
900kHz
HG
LG
LG TO HG
220kHz
–50
–15
20
55
90
125
–50
–15
20
55
90
125
–50
–15
20
55
90
125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3741 G23
3741 G24
3741 G36
Current Regulation Accuracy
CTRL1 = 1.5V, VIN = 12V
Current Regulation Accuracy
CTRL1 = 0.75V, VIN = 12V
Overcurrent Threshold
6
4
120
100
3
2
2
0
80
60
1
0
25°C
25°C
–2
–4
–6
40
20
0
–1
–2
–3
0
2.5
5.0
7.5
10
0
0.75
1.5
2.25
3.0
0
2.5
5.0
7.5
10
OUTPUT VOLTAGE (V)
CTRL_H (V)
OUTPUT VOLTAGE (V)
3741 G27
3741 G28
3741 G26
3741f
ꢆ
LT3741
Typical perFormance characTerisTics
VOUT vs IOUT
VOUT vs IOUT
6
5
4
3
2
1
0
25
20
15
10
5
V
V
I
= 20V
= 5V
LIMIT
V
V
I
= 25V
IN
OUT
IN
OUT
= 20V
= 24A
= 9.5A
LIMIT
0
0
2
4
6
8
10 12 14 16 18 20 22 24 26
(A)
0
1
2
3
4
5
6
7
8
9
10
I
I
(A)
OUT
OUT
3741 G19
3741 G22
Efficiency and Power Loss
vs Load Current
VOUT vs IOUT
12
10
8
100
95
90
85
80
75
70
30
25
20
15
10
5
EFFICIENCY
6
4
POWER LOSS
V
V
I
= 24V
2
IN
OUT
= 10V
= 18A
V
= 20V
= 5V
IN
OUT
V
LIMIT
0
0
0
2
4
6
8
10 12 14 16 18 20
(A)
0
5
10
15
20
25
LOAD CURRENT (A)
I
OUT
3741 G33
3741 G29
Efficiency and Power Loss
vs Load Current
Efficiency and Power Loss
vs Load Current
100
95
90
85
80
75
70
4.8
4.0
3.2
2.4
1.6
0.8
0
100
95
90
85
80
75
70
65
60
55
50
45
40
12
10
8
EFFICIENCY
EFFICIENCY
6
POWER LOSS
4
POWER LOSS
2
V
V
= 25V
OUT
V
V
= 24V
OUT
IN
IN
= 20V
= 10V
0
0
2
4
6
8
10
0
5
10
15
20
LOAD CURRENT (A)
LOAD CURRENT (A)
3741 G30
3741 G37
3741f
ꢇ
LT3741
Typical perFormance characTerisTics
Voltage Regulation with 10A
Regulated Inductor Current
5A Load Step Recovery
V
OUT
20mV/DIV
V
OUT
AC-COUPLED
2V/DIV
I
L
I
L
2A/DIV
5A/DIV
3741 G31
3741 G34
20ms/DIV
100µs/DIV
C
OUT
= 470µF
Shutdown and Recovery
1.5nF Soft-Start Capacitor
Common Mode Lockout
EN/UVLO
5V/DIV
V
OUT
I
2V/DIV
L
5A/DIV
I
L
V
OUT
200mA/DIV
2V/DIV
3741 G32
3741 G35
100µs/DIV
1ms/DIV
C
V
= 1mF
= 5V
OUT
OUT
V
= 7V
IN
10A LOAD
18A CURRENT LIMIT
3741f
ꢈ
LT3741
pin FuncTions (QFN/TSSOP)
EN/UVLO (Pin 1/Pin 4): Enable Pin. The EN/UVLO pin
acts as an enable pin and turns on the internal current
bias core and subregulators at 1.55V. The pin does
not have any pull-up or pull-down, requiring a voltage
bias for normal part operation. Full shutdown occurs at
approximately 0.5V.
VC (Pin 10/Pin 13): VC provides the necessary com-
pensation for the average current loop stability. Typical
compensation values are 20k to 50k for the resistor and
2nF to 5nF for the capacitor.
RT(Pin12/Pin14):Aresistortogroundsetstheswitching
frequency between 200kHz and 1MHz. When using the
SYNC function, set the frequency to be 20% lower than
the SYNC pulse frequency. This pin is current limited to
60µA. Do not leave this pin open.
V
(Pin 2/Pin 5): Buffered 2V reference capable of
REF
0.5mA drive.
CTRL2(Pin3/Pin±):Thermalcontrolinputusedtoreduce
the regulated current level.
SYNC (Pin 13/Pin 15): Frequency Synchronization Pin.
Thispinallowstheswitchingfrequencytobesynchronized
GND (Pins 4,11,14, Exposed Pad Pin 21/Pins 2,7,1±,
Exposed Pad Pin 21): Ground. The exposed pad must be
soldered to the PCB
to an external clock. The R resistor should be chosen to
T
operate the internal clock at 20% slower than the SYNC
pulse frequency. This pin should be grounded when not
in use. When laying out board, avoid noise coupling to
or from SYNC trace.
CTRL1 (Pin 5/Pin 8): The CTRL1 pin sets the high level
regulated output current and overcurrent. The maximum
inputvoltageisinternallyclampedto1.5V.Theovercurrent
setpointisequaltothehighlevelregulatedcurrentlevelset
by the CTRL1 pin with an additional 23mV offset between
HG (Pin 15/Pin 17): HG is the top-FET gate drive signal
that controls the state of the high-side external power FET.
The driver impedance is approximately 1.8Ω.
+
–
the SENSE and SENSE pins.
SW (Pin 1±/Pin 18): The SW pin is used internally as the
lower-rail for the floating high-side driver. Externally, this
node connects the two power-FETs and the inductor.
SS (Pin ±/Pin 9): The Soft-Start Pin. Place an external
capacitor to ground to limit the regulated current during
start-up conditions. The soft-start pin has a 11µA charg-
ing current. This pin controls regulated output current
determined by CTRL1.
CBOOT (Pin 17/Pin 19): The CBOOT pin provides a float-
ing 5V regulated supply for the high-side FET driver. An
external Schottky diode is required from the V
pin
CC_INT
FB (Pin 7/Pin 10): Feedback Pin for Voltage Regulation
andOvervoltageProtection.Thefeedbackvoltageis1.21V.
Overvoltage is also sensed through the FB pin. When the
feedback voltage exceeds 1.5V, the overvoltage lockout
prevents switching for 13μs to allow the inductor current
to discharge.
to the CBOOT pin to charge the CBOOT capacitor when
the switch-pin is near ground.
LG (Pin 18/Pin 20): LG is the bottom-FET gate drive signal
that controls the state of the low-side external power-FET.
The driver impedance is approximately 1.8Ω.
+
+
SENSE (Pin 8/Pin 11): SENSE is the inverting input of
V
(Pin 19/Pin 1): A regulated 5V output for charging
CC_INT
the average current mode loop error amplifier. This pin is
connected to the external current sense resistor, R . The
voltage drop between SENSE and SENSE referenced to
the voltage drop across an internal resistor produces the
input voltages to the current regulation loop.
the CBOOT capacitor. V
also provides the power for
CC_INT
the digital and switching subcircuits. Below 6V V , tie this
S
IN
+
–
pintotherail.V
iscurrentlimitedto50mA.Shutdown
CC_INT
operation disables the output voltage drive.
V
(Pin 20/Pin 3): Input Supply Pin. Must be locally
IN
–
–
SENSE (Pin 9/Pin 12): SENSE is the non-inverting input
oftheaveragecurrentmodelooperroramplifier. Therefer-
ence current, based on CTRL1 or CTRL2 flows out of the
bypassed with a 4.7μF low-ESR capacitor to ground.
pin to the output side of the sense resistor, R .
S
3741f
ꢀ0
LT3741
block Diagram (QFN Package)
V
IN
V
IN
20
19
V
IN
402k
133k
1µF
47µF
EN/UVLO
1
2
INTERNAL
REGULATOR
AND
V
CC_INT
10µF
V
REF
UVLO
2V REFERENCE
OSCILLATOR
100nF
HIGH SIDE
DRIVER
CBOOT
HG
17
15
16
SYNC
RT
SYNC
82.5k
13
12
–
+
0.1µF
2.4µH
SW
SYNCRONOUS
CONTROLLER
R
Q
S
LG
18
PWM
COMPARATOR
LOW SIDE
DRIVER
+
–
+
SENSE
8
9
R
S
5mΩ
1.5V
–
3k
SENSE
g
AMP
= 450µA/V
= 4M
V
OUT
m
m
O
CURRENT
MIRROR
g
150µF
s2
+
+
R
I
11µA
CTRL1
= 40µA
OUT
5
–
40.2k
–
+
FB
7
CTRL BUFFER
10k
SS
6
3
90k
1.21V
100nF
VOLTAGE
REGULATOR
AMP
CTRL2
VC
g
= 850µA/V
10
m
40.2k
5.6µF
3741 F01
Figure 1. Block Diagram
3741f
ꢀꢀ
LT3741
operaTion
TheLT3741utilizesfixed-frequency,averagecurrentmode
control to accurately regulate the inductor current, inde-
pendently from the output voltage. This is an ideal solu-
tion for applications requiring a regulated current source.
The control loop will regulate the current in the inductor
at an accuracy of 6%. Once the output has reached the
regulation voltage determined by the resistor divider from
the output to the FB pin and ground, the inductor current
will be reduced by the voltage regulation loop. In voltage
regulation, the output voltage has an accuracy of 1.5%.
For additional operation information, refer to the Block
Diagram in Figure 1.
is limited on a cycle-by-cycle basis; shutting switching
down once the overcurrent level is reached. Overcurrent
is not soft-started.
The regulated output voltage is set with a resistor divider
from the output back to the FB pin. The reference at the
FB pin is 1.21V. If the output voltage level is high enough
to engage the voltage loop, the regulated inductor current
will be reduced to support the load at the output. If the
voltage at the FB pin reaches 1.5V (~25% higher than the
regulation level), an internal overvoltage flag is set, shut-
ting down switching for 13μs.
The EN/UVLO pin functions as a precision shutdown
pin. When the voltage at the EN/UVLO pin is lower than
1.55V, the internal reset flag is asserted and switching is
terminated. Full shutdown occurs at approximately 0.5V
with a quiescent current of less than 1μA in full shutdown.
The EN/UVLO pin has 130mV of built-in hysteresis. In
addition, a 5.5µA current source is connected to this pin
that allows any amount of hysteresis to be added with a
The current control loop has two reference inputs, deter-
minedbythevoltageattheanalogcontrolpins,CTRL1and
CTRL2. The lower of the two analog voltages on CTRL1
and CTRL2 determines the regulated output current. The
analog voltage at the CTRL1 pin is buffered and produces
areferencevoltageacrossaninternalresistor. Theinternal
buffer has a 1.5V clamp on the output, limiting the analog
control range of the CTRL1 and CTRL2 pins from 0V to
1.5V – corresponding to a 0mV to 51mV range on the
series resistor or resistor divider from V .
IN
During startup, the SS pin is held low until the internal
reset goes low. Once reset goes low, the capacitor at the
soft-start pin is charged with an 11μA current source.
The internal buffers for the CTRL1 and CTRL2 signals are
limited by the voltage at the soft-start pin, slowly ramping
the regulated inductor current to the current determined
by the voltage at the CTRL1 or CTRL2 pins.
sense resistor, R . The average current-mode control
S
loop uses the internal reference voltage to regulate the
inductor current, as a voltage drop across the external
sense resistor, R .
S
A 2V reference voltage is provided on the V
pin to al-
REF
low the use of a resistor voltage divider to the CTRL1 and
CTRL2 pins. The V pin can supply up to 500μA and is
REF
The thermal shutdown is set at 163°C with 8°C hysteresis.
During thermal shutdown, all switching is terminated and
the part is in reset (forcing the SS pin low).
current limited to 1mA.
The error amplifier for the average current-mode control
loophasacommonmodelockoutthatregulatestheinduc-
tor current so that the error amplifier is never operated out
of the common mode range. The common mode range is
The switching frequency is determined by a resistor at
the RT pin. The RT pin is also limited to 60µA, while not
recommended,thislimitstheswitchingfrequencyto2MHz
when the RT pin is shorted to ground. The LT3741 may
also be synchronized to an external clock through the use
of the SYNC pin.
from 0V to 2V below the V supply rail.
IN
The overcurrent set point is equal to the regulated current
level set by the CTRL1 pin with an additional 23mV offset
+
–
between the SENSE and SENSE pins. The overcurrent
3741f
ꢀꢁ
LT3741
applicaTions inFormaTion
Programming Inductor Current
Inductor Selection
The analog voltage at the CTRL1 pin is buffered and
Size the inductor to have no less than 30% peak-to-peak
ripple. The overcurrent set point is equal to the high
level regulated current level set by the CTRL1 pin with
produces a reference voltage, V
, across an internal
CTRL
resistor. The regulated average inductor current is deter-
mined by:
+
an additional 23mV offset between the SENSE and
–
SENSE pins. The saturation current for the inductor
VCTRL1
30 •RS
should be at least 20% higher than the maximum regu-
lated current. The following equation sizes the inductor
for best performance:
IO =
where R is the external sense resistor and I is the aver-
S
O
2
age inductor current, which is equal to the output current.
V • VO – VO
IN
L =
Figure 2 shows the maximum output current vs R . The
S
0.3• f •I • V
IN
S
O
maximum power dissipation in the resistor will be:
2
whereV istheoutputvoltage,I isthemaximumregulated
O
O
0.05V
RS
(
)
PRS =
current in the inductor and f is the switching frequency.
S
Using this equation, the inductor will have approximately
15% ripple at maximum regulated current.
Table1containsseveralresistorsvalues,thecorresponding
maximumcurrentandpowerdissipationinthesenseresis-
tor. Susumu, Panasonic and Vishay offer accurate sense
Table 2. Recommended Inductor Manufacturers
VENDOR
Coilcraft
WEBSITE
resistors. Figure 3 shows the power dissipation in R .
S
www.coilcraft.com
www.sumida.com
www.vishay.com
www.we-online.com
www.nec-tokin.com
Sumida
Table 1. Sense Resistor Values
MAXIMUM OUTPUT
Vishay
CURRENT (A)
RESISTOR, R (mΩ) POWER DISSIPATION (W)
S
Würth Electronics
NEC-Tokin
1
5
50
10
5
0.05
0.25
0.5
10
25
1.4
1.2
2
1.25
1.0
30
25
0.8
0.6
0.4
0.2
20
15
10
5
0
0
6
2
4
8
10 12 14 16 18 20
R
S
(mΩ)
3741 F03
0
Figure 3. Power Dissipation in RS
0
2
4
6
8
10 12 14 16 18 20
R
S
(mΩ)
3741 F02
Figure 2. RS Value Selection for Regulated Output Current
3741f
ꢀꢂ
LT3741
applicaTions inFormaTion
Switching MOSFET Selection
higher R
and lower C . The power loss in the high
DS(ON) GD
side MOSFET can be approximated by:
When selecting switching MOSFETs, the following pa-
rameters are critical in determining the best devices for
P
LOSS
= (ohmic loss) + (transition loss)
a given application: total gate charge (Q ), on-resistance
G
V +R I
(
)
•IO RDS(ON) •ρ
F
D O
2
(R
), gate to drain charge (Q ), gate-to-source
DS(ON)
GD
P
≈
+
T
LOSS
V
charge (Q ), gate resistance (R ), breakdown voltages
IN
GS
G
(maximumV andV )anddraincurrent(maximumI ).
GS
DS
D
V •I
OUT
IN
The following guidelines provide information to make the
• QGD +QGS • 2•R +R +R
• f
S
(
) (
)
(
)
G
PU
PD
5V
selection process easier.
BothoftheswitchingMOSFETsneedtohavetheirmaximum
rated drain currents greater than the maximum inductor
current. The following equation calculates the peak induc-
tor current:
whereρ isatemperature-dependanttermoftheMOSFET’s
T
on-resistance.Using70°Casthemaximumambientoperat-
ing temperature, ρ is roughly equal to 1.3. R and R
T
PD
PU
are the LT3741 high side gate driver output impedance,
1.3Ω and 2.3Ω respectively.
2
V • VO – VO
IN
IMAX =I +
A good approach to MOSFET sizing is to select a high
side MOSFET, then select the low side MOSFET. The trade-
O
2• fS •L • V
IN
off between R
, Q , Q and Q for the high side
DS(ON)
G GD GS
where V is the input voltage, L is the inductance value,
IN
MOSFET is shown in the following example. V is equal
O
V is the output voltage, I is the regulated output current
O
O
to 4V. Comparing two N-channel MOSFETs, with a rated
and f is the switching frequency. During MOSFET selec-
S
V
of 40V and in the same package, but with 8× different
DS(ON)
DS
R
tion,noticethatthemaximumdraincurrentistemperature
dependant. Most data sheets include a table or graph of
the maximum rated drain current vs temperature.
and 4.5× different Q and Q :
G GD
M1: R
GS
= 2.3mΩ, Q = 45.5nF,
G
DS(ON)
Q
= 13.8nF, Q = 14.4nF, R = 1Ω
GD G
The maximum V should be selected to be higher than
DS
M2: R
GS
= 18mΩ, Q = 10nF,
G
GD G
the maximum input supply voltage (including transient)
for both MOSFETs. The signals driving the gates of the
switching MOSFETs have a maximum voltage of 5V with
respect to the source. During start-up and recovery con-
ditions, the gate drive signals may be as low as 3V. To
ensure that the LT3741 recovers properly, the maximum
threshold should be less than 2V. For a robust design,
DS(ON)
Q
= 4.5nF, Q = 3.1nF, R = 3.5Ω
PowerlossforbothMOSFETsisshowninFigure4.Observe
thatwhiletheR ofM1iseighttimeslower,thepower
DS(ON)
loss at low input voltages is equal, but four times higher
at high input voltages than the power loss for M2.
AnotherpowerlossrelatedtoswitchingMOSFETselection
isthepowerlosttodrivingthegates.Thetotalgatecharge,
select the maximum V greater than 7V.
GS
Power losses in the switching MOSFETs are related to
Q ,mustbechargedanddischargedeachswitchingcycle.
G
the on-resistance, R
; the transitional loss related
DS(ON)
The power is lost to the internal LDO within the LT3741.
to the gate resistance, R ; gate-to-drain capacitance, Q
G
GD
The power lost to the charging of the gates is:
and gate-to-source capacitance, Q . Power loss to the
on-resistance is an Ohmic loss, I R
GS
2
P
≈ (V – 5V) • (Q
+ Q ) • f
GLG GHG S
LOSS_LDO
IN
, and usually
DS(ON)
dominates for input voltages less than ~15V. Power losses
to the gate capacitance dominate for voltages greater than
~12V. When operating at higher input voltages, efficiency
can be optimized by selecting a high side MOSFET with
where Q
is the low side gate charge and Q
is the
GLG
GHG
high side gate charge.
Whenever possible, utilize a switching MOSFET that
minimizes the total gate charge to limit the internal power
dissipation of the LT3741.
3741f
ꢀꢃ
LT3741
applicaTions inFormaTion
7
6
5
2.5
2.0
1.5
1.0
0.5
0
TOTAL
4
3
TOTAL
TRANSITIONAL
TRANSITIONAL
OHMIC
2
1
OHMIC
0
20
INPUT VOLTAGE (V)
30
0
10
10
20
40
40
0
30
INPUT VOLTAGE (V)
3741 F04a
3741 F04b
Figure 4a. Power Loss Example for M1
Figure 4b. Power Loss Example for M2
Figure 4
Thecapacitorsalsoneedtobesurgeratedtothemaximum
outputcurrent.ToachievethelowestpossibleESR,several
low ESR capacitors should be used in parallel. Many ap-
plications benefit from the use of high density POSCAP
capacitors, which are easily destroyed when exposed to
overvoltage conditions. To prevent this, select POSCAP
capacitors that have a voltage rating that is at least 50%
higher than the regulated voltage
Table 3. Recommended Switching FETs
V
V
I
OUT OUT
IN
(V) (V) (A)
TOP FET
BOTTOM FET MANUFACTURER
8
4
4
5-10 RJK0365DPA RJK0330DPB Renesas
www.renesas.com
24
5
RJK0368DPA RJK0332DPB
24 2-4 20 RJK0365DPA RJK0346DPA
12 2-4 10 FDMS8680 FDMS8672AS Fairchild
www.fairchildsemi.com
36
24
4
4
20
40
Si7884BDP
SiR470DP Vishay
www.vishay.com
C
BOOT
Capacitor Selection
PSMN4R0- RJK0346DPA NXP/Philips
30YL www.nxp.com
The C
capacitor must be sized less than 220nF and
BOOT
more than 50nF to ensure proper operation of the LT3741.
Use 220nF for high current switching MOSFETs with high
gate charge.
Input Capacitor Selection
The input capacitor should be sized at 4µF for every 1A
of output current and placed very close to the high side
MOSFET. A small 1µF ceramic capacitor should be placed
V
Capacitor Selection
CC_INT
The bypass capacitor for the V
pin should be larger
CC_INT
near the V and ground pins of the LT3741 for optimal
IN
than 5µF for stability and has no ESR requirement. It
is recommended that the ESR be lower than 50mΩ to
reduce noise within the LT3741. For driving MOSFETs
with gate charges larger than 10nC, use 0.5µF/nC of total
gate charge.
noise immunity. The input capacitor should have a ripple
currentratingequaltohalfofthemaximumoutputcurrent.
ItisrecommendedthatseverallowESRceramiccapacitors
be used as the input capacitance. Use only type X5R or
X7R capacitors as they maintain their capacitance over a
wide range of operating voltages and temperatures.
Soft-Start
Output Capacitor Selection
Unlike conventional voltage regulators, the LT3741 utilizes
thesoft-startfunctiontocontroltheregulatedinductorcur-
rent.Thechargingcurrentis11µAandreducestheregulated
current when the SS pin voltage is lower than CTRL1.
TheoutputcapacitorsneedtohaveverylowESR(equivalent
series resistance) to reduce output ripple. A minimum of
20µF/A of load current should be used in most designs.
3741f
ꢀꢄ
LT3741
applicaTions inFormaTion
Output Current Regulation
V
REF
To adjust the regulated load current, an analog voltage is
applied to the CTRL1 pin. Figure 5 shows the regulated
voltage across the sense resistor for control voltages up
to 2V. Figure 6 shows the CTRL1 voltage created by a volt-
LT3741
R2
R1
CTRL1
3741 F06
age divider from V to ground. When sizing the resistor
REF
Figure ±. Analog Control of Inductor Current
divider, please be aware that the V pin is current limited
REF
to 500µA. Above 1.5V, the control voltage has no effect on
the regulated inductor current.
V
OUT
60
50
LT3741
R2
FB
R1
40
30
3741 F07
Figure 7. Output Voltage Regulation and Overvoltage Protection
Feedback Connections
20
10
0
not leave this pin open under any condition. The RT pin
is also current limited to 60µA. See Table 4 and Figure 8
for resistor values and the corresponding switching
frequencies.
0
0.5
1.0
1.5
2.0
V
(V)
CTRL
3741 F05
Table 4. Switching Frequency
SWITCHING FREQUENCY (MHz)
Figure 5. Sense Voltage vs CTRL Voltage
R (kΩ)
T
1
0.750
0.5
40.2
53.6
82.5
143
221
453
Voltage Regulation and Overvoltage Protection
The LT3741 uses the FB pin to regulate the output voltage
and to provide a high speed overvoltage lockout to avoid
high voltage conditions. The regulated output voltage
is programmed using a resistor divider from the output
and ground (Figure 7). When the output voltage exceeds
125% of the regulated voltage level (1.5V at the FB pin),
the internal overvoltage flag is set, terminating switching.
The regulated output voltage must be greater than 1.5V
and is set by the equation:
0.3
0.2
0.1
1.2
1.0
0.8
0.6
R2
R1
VOUT =1.21V 1+
0.4
0.2
0
Programming Switching Frequency
The LT3741 has an operational switching frequency range
between200kHzand1MHz.Thisfrequencyisprogrammed
with an external resistor from the RT pin to ground. Do
0
50 100 150 200 250 300 350 400 450 500
(kΩ)
R
T
3743 F08
Figure 8. Frequency vs RT Resistance
3741f
ꢀꢅ
LT3741
applicaTions inFormaTion
Thermal Shutdown
V
IN
V
IN
The internal thermal shutdown within the LT3741 engages
at 163°C and terminates switching and resets soft-start.
When the part has cooled to 155°C, the internal reset is
cleared and soft-start is allowed to charge.
LT3741
EN/UVLO
R2
R1
3741 F09
Switching Frequency Synchronization
Figure 9. UVLO Configuration
The nominal switching frequency of the LT3741 is deter-
mined by the resistor from the RT pin to ground and may
be set from 200kHz to 1MHz. The internal oscillator may
alsobesynchronizedtoanexternalclockthroughtheSYNC
pin. The external clock applied to the SYNC pin must have
a logic low below 0.3V and a logic high higher than 1.25V.
Theinputfrequencymustbe20%higherthanthefrequency
determined by the resistor at the RT pin. The duty cycle of
theinputsignalneedstobegreaterthan10%andlessthan
90%. Input signals outside of these specified parameters
will cause erratic switching behavior and subharmonic
oscillations. When synchronizing to an external clock,
pleasebeawarethattherewillbeafixeddelayfromtheinput
clock edge to the edge of switch. The SYNC pin must be
grounded if the synchronization to an external clock is not
required.WhenSYNCisgrounded,theswitchingfrequency
is determined by the resistor at the RT pin.
The EN/UVLO pin has an absolute maximum voltage of
6V. To accommodate the largest range of applications,
there is an internal Zener diode that clamps this pin. For
applications where the supply range is greater than 4:1,
size R2 greater than 375k.
Load Current Derating Using the CTRL2 Pin
The LT3741 is designed specifically for driving high power
loads. In high current applications, derating the maximum
current based on operating temperature prevents damage
to the load. In addition, many applications have thermal
limitations that will require the regulated current to be re-
ducedbasedonloadand/orboardtemperature.Toachieve
this, theLT3741usestheCTRL2pintoreducetheeffective
regulated current in the load. While CTRL1 programs the
regulated current in the load, CTRL2 can be configured to
reduce this regulated current based on the analog voltage
at the CTRL2 pin. The load/board temperature derating is
programmed using a resistor divider with a temperature
dependant resistance (Figure 10). When the board/load
temperature rises, the CTRL2 voltage will decrease. To
reduce the regulated current, the CTRL2 voltage must be
lower than voltage at the CTRL1 pin.
Shutdown and UVLO
TheLT3741hasaninternalUVLOthatterminatesswitching,
resetsallsynchronouslogic, anddischargesthesoft-start
capacitor for input voltages below 4.2V. The LT3741 also
has a precision shutdown at 1.55V on the EN/UVLO pin.
Partial shutdown occurs at 1.55V and full shutdown is
guaranteed below 0.5V with <1µA I in the full shutdown
Q
R
R
V
V
state. Below 1.55V, an internal current source provides
5.5µA of pull-down current to allow for programmable
UVLO hysteresis. The following equations determine the
voltage divider resistors for programming the UVLO volt-
age and hysteresis as configured in Figure 9.
V
REF
R
R
R
R
R
R
X
LT3741
NTC
NTC
X
NTC
NTC
R2
CTRL2
3741 F10
R1
(OPTION A TO D)
A
B
C
D
VHYST
R2=
Figure 10. Load Current Derating vs Temperature
Using NTC Resistor
5.5µA
1.55V •R2
–1.55V
R1=
V
UVLO
3741f
ꢀꢆ
LT3741
applicaTions inFormaTion
Average Current Mode Control Compensation
the error amplifier will be the compensation resistor, R .
C
Use the following equation as a good starting point for
compensation component sizing:
Theuseofaveragecurrentmodecontrolallowsforprecise
regulation of the inductor and load currents. Figure 11
shows the average current mode control loop used in the
LT3741, where the regulation current is programmed by
a current source and a 3k resistor.
fS •L •1000V
VO •RS
0.002
fS
RC =
[Ω], CC =
[F]
where f is the switching frequency, L is the inductance
S
V
• 11µA/V
CTRL
3k
value, V is the output voltage and R is the sense resistor.
O
S
For most applications, a 4.7nF compensation capacitor
is adequate and provides excellent phase margin with
optimized bandwidth. Please refer to Table 6 for recom-
mended compensation values.
L
R
S
MODULATOR
LOAD
+
g
m
ERROR AMP
Board Layout Considerations
3741 F11
R
–
C
Average current mode control is relatively immune to the
switching noise associated with other types of control
schemes. Placing the sense resistor as close as possible
C
C
+
–
Figure 11. LT3741 Average Current Mode Control Scheme
to the SENSE and SENSE pins avoids noise issues. Due
to sense resistor ESL (equivalent series inductance), a
To design the compensation network, the maximum com-
pensation resistor needs tobe calculated. Incurrent mode
controllers, the ratio of the sensed inductor current ramp
to the slope compensation ramp determines the stability
of the current regulation loop above 50% duty cycle. In
the same way, average current mode controllers require
the slope of the error voltage to not exceed the PWM ramp
slope during the switch off-time.
+
–
10Ω resistor in series with the SENSE and SENSE pins
with a 33nF capacitor placed between the SENSE pins is
recommended. Utilizing a good ground plane underneath
the switching components will minimize interplane noise
coupling. To dissipate the heat from the switching com-
ponents, use a large area for the switching mode while
keeping in mind that this negatively affects the radiated
noise.
Since the closed-loop gain at the switching frequency
produces the error signal slope, the output impedance of
Table ±. Recommended Compensation Values
V
(V)
V (V)
I (A)
f
SW
(MHz)
0.5
L (µH)
1.5
R (mΩ)
R (kΩ)
C (nF)
IN
O
L
S
C
C
12
4
4
5
4
4
5
5
47.5
47.5
38.3
52.3
52.3
4.7
4.7
8.2
4.7
4.7
12
12
24
24
10
20
2
0.5
1.5
5
0.25
0.5
1.8
2.5
2.5
2.5
1.0
20
0.5
1.0
3741f
ꢀꢇ
LT3741
Typical applicaTions
20A Super Capacitor Charger with 5V Regulated Output
V
IN
V
IN
EN/UVLO
EN/UVLO
10V TO 36V
1µF
100µF
RT
SYNC
M1
HG
100nF
82.5k
L1
1.0µH
V
R1
2.5mΩ
OUT
CBOOT
SW
20A MAXIMUM
V
REF
150µF
s2
2.2µF
LT3741
V
CC_INT
10Ω
10Ω
22µF
R
HOT
LG
M2
CTRL1
50k
45.3k
GND
+
CTRL2
SS
SENSE
33nF
R
NTC
–
38.3k
12.1k
SENSE
470k
10nF
FB
VC
L1: IHLP4040DZER1R0M01
M1: RJK0365DPA
47.5k
4.7nF
3741 TA02
M2: RJK0346DPA
R1: VISHAY WSL25122L500FEA
Efficiency and Power Loss
vs Load Current
VOUT vs IOUT
100
95
90
85
80
75
70
30
25
20
15
10
5
6
5
4
3
2
EFFICIENCY
POWER LOSS
V
V
I
= 20V
= 5V
LIMIT
1
0
IN
OUT
V
V
= 20V
OUT
IN
= 20A
= 5V
0
0
5
10
15
20
25
0
2
4
6
8
10 12 14 16 18 20 22 24 26
(A)
LOAD CURRENT (A)
I
OUT
3741 TA02b
3741 TA02c
3741f
ꢀꢈ
LT3741
Typical applicaTions
20A LED Driver
V
IN
V
IN
EN/UVLO
EN/UVLO
12V TO 36V
1µF
100µF
RT
SYNC
M1
HG
150nF
82.5k
L1
1.1µH
V
OUT
CBOOT
6V, 20A MAXIMUM
2.5mΩ
V
SW
REF
680µF
2.2µF
LT3741
D1
V
CC_INT
22µF
CONTROL
R
LG
GND
+
M2
HOT
CTRL1
CTRL2
INPUT
45.3k
10Ω
10Ω
SENSE
33nF
R
NTC
–
470k
SENSE
47.5k
SS
FB
10nF
VCH
12.1k
82.5k
4.7nF
3741 TA03
LED Current Waveforms 10A to
20A Current Step
1.5V
CTRL1
1V/DIV
0.75V
20A
I
LED
5A/DIV
10A
3741 TA03b
1ms/DIV
3741f
ꢁ0
LT3741
Typical applicaTions
10A Single-Cell Lithium-Ion Battery Charger
V
24V
IN
V
EN/UVLO
CTRL1
IN
1µF
33µF
µCONTROLLER
HG
220nF
1%
5mΩ
V
RT
SYNC
OUT
CBOOT
SW
2.2µH
4.2V, 10A MAXIMUM
82.5k
LT3741
+
3.6V
V
V
CC_INT
REF
22µF
2.2µF
LG
R
10Ω
10Ω
HOT
GND
+
45.3k
CTRL2
SS
SENSE
20nF
R
470k
NTC
–
30.1k
SENSE
FB
VC
1nF
12.1k
82.5k
8.2nF
3741 TA04
3741f
ꢁꢀ
LT3741
package DescripTion
UF Package
20-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1710 Rev A)
0.70 ±0.05
4.50 ± 0.05
3.10 ± 0.05
2.45 ± 0.05
2.00 REF
2.45 ± 0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
PIN 1 NOTCH
R = 0.20 TYP
OR 0.35 × 45°
CHAMFER
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
BOTTOM VIEW—EXPOSED PAD
R = 0.05
TYP
R = 0.115
0.75 ± 0.05
TYP
4.00 ± 0.10
19 20
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
2.45 ± 0.10
2.00 REF
4.00 ± 0.10
2.45 ± 0.10
(UF20) QFN 01-07 REV A
0.200 REF
0.25 ± 0.05
0.50 BSC
0.00 – 0.05
NOTE:
1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220
VARIATION (WGGD-1)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3741f
ꢁꢁ
LT3741
package DescripTion
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation CB
6.40 – 6.60*
(.252 – .260)
3.86
(.152)
3.86
(.152)
20 1918 17 16 15 14 1312 11
6.60 ±0.10
2.74
(.108)
4.50 ±0.10
6.40
(.252)
BSC
2.74
(.108)
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
5
7
8
1
2
3
4
6
9 10
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
FE20 (CB) TSSOP 0204
0.195 – 0.30
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
3741f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ꢁꢂ
LT3741
Typical applicaTion
20V Regulated Output with 5A Current Limit
V
IN
V
IN
EN/UVLO
EN/UVLO
36V
1µF
22µF
RT
SYNC
M1
HG
100nF
82.5k
L1
8.2µH
V
R1
10mΩ
OUT
CBOOT
SW
5A MAXIMUM
V
REF
100µF
2.2µF
LT3741
V
CC_INT
10Ω
10Ω
22µF
R
LG
M2
HOT
CTRL1
45.3k
GND
+
CTRL2
SS
SENSE
10nF
R
NTC
–
187k
12.1k
SENSE
470k
10nF
FB
VC
30.1k
3.9nF
3741 TA05
relaTeD parTs
PART NUMBER
DESCRIPTION
Synchronous Step-Down LED Driver
COMMENTS
92% Efficiency, I
LT3743
to 20A, V : 5.5V to 36V, I = 2mA, I < 1µA, 4mm x 5mm
IN Q SD
OUT
QFN-28, TSSOP-28E
3741f
LT 0310 • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
ꢁꢃ
●
●
LINEAR TECHNOLOGY CORPORATION 2010
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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