LT3751IUFD-PBF [Linear]
Capacitor Charger Controller with Regulation; 电容充电器控制器调节
| 型号： | LT3751IUFD-PBF |
| 厂家： | 
Linear |
| 描述： | Capacitor Charger Controller with Regulation |
| 文件： | 总28页 (文件大小：272K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3751
Capacitor Charger
Controller with Regulation
FEATURES
DESCRIPTION
The LT®3751 is a high input voltage capable flyback con-
troller designed to rapidly charge a large capacitor to a
user-adjustabletargetvoltagesetbythetransformerturns
ratioandthreeexternalresistors. Anoptionalfeedbackpin
can be used to provide a low noise high-voltage regulated
output.
n
Charges Any Size Capacitor
n
Low Noise Output in Voltage Regulation Mode
n
Stable Operation Under a No-Load Condition
n
Integrated 2A MOSFET Gate Driver with Rail-to-Rail
Operation for V ≤ 8V
CC
n
Selectable 5.6V or 10.5V Internal Gate Drive
Voltage Clamp
The LT3751 has an integrated rail-to-rail MOSFET gate
driver that allows for efficient operation down to 4.75V.
A low 106mV differential current sense threshold voltage
accurately limits the peak switch current. Added protec-
tion is achieved with user-selectable overvoltage and
n
User-Selectable Over/Undervoltage Detect
n
Easily Adjustable Output Voltage
n
Primary or Secondary Side Output Voltage Sense
n
Wide Input V Voltage Range (5V to 24V)
CC
n
Available in a 20-Pin QFN 4mm × 5mm
undervoltage lockouts for both V and V
. A typical
CC
TRANS
application can charge a 1000μF capacitor to 500V in less
than one second.
APPLICATIONS
The CHARGE pin is used to initiate a new charge cycle and
providesON/OFFcontrol.TheDONEpinindicateswhenthe
capacitor has reached its programmed value and the part
has stopped charging. The FAULT pin indicates when the
LT3751 has shut down due to either V or V
exceeding the user-programmed supply tolerances.
n
High Voltage Regulated Supply
n
High Voltage Capacitor Charger
n
Professional Photoflash Systems
n
Emergency Strobe
voltage
n
CC
TRANS
Security/Inventory Control Systems
n
Detonators
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents including
6518733 and 6636021.
TYPICAL APPLICATION
Regulation Mode Load Regulation
and Efficiency vs Load Current
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
T1
1:10
D1
V
500V
TRANS
24V
500
498
496
494
492
490
90
84
78
72
66
60
0 TO 150mA
330μF
10μF
×2
•
40.2k
TRANS
+
s2
100μF
•
RV
CHARGE
CLAMP
18.2k
0.47μF
OFF ON
RDCM
40.2k
RV
OUT
V
CC
24V
V
CC
LT3751
10μF
HVGATE
LVGATE
CSP
TO
DONE
FAULT
V
CC
MICRO
374k
475k
374k
475k
UVLO1
OVLO1
UVLO2
6mΩ
V
TRANS
CSN
FB
715k
OUTPUT VOLTAGE
EFFICIENCY
V
CC
OVLO2
GND
1.74k
10nF
RBG
0
50
100
150
732Ω
LOAD CURRENT (mA)
3751 TA01b
3751 TA01a
3751f
1
LT3751
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
V , CHARGE, CLAMP ..............................................24V
CC
DONE, FAULT ............................................................24V
LVGATE (Note 8) .......................................................24V
20 19 18 17
V
– LVGATE..............................................................8V
CC
OVLO1
UVLO2
OVLO2
FAULT
1
2
3
4
5
6
16 RV
15 NC
OUT
HVGATE ................................................................Note 9
RBG, CSP, CSN............................................................2V
FB ...............................................................................5V
Current into DONE Pin ........................................... 1mA
Current into FAULT Pin........................................... 1mA
14 RBG
21
13 HVGATE
12 LVGATE
DONE
CHARGE
11 V
CC
7
8
9 10
Current into RV
Current into RV
Pin ....................................... 1mA
TRANS
Pin......................................... 10mA
OUT
Current into RDCM Pin ........................................ 10mA
Current into UVLO1 Pin.......................................... 1mA
Current into UVLO2 Pin.......................................... 1mA
Current into OVLO1 Pin.......................................... 1mA
Current into OVLO2 Pin.......................................... 1mA
Maximum Junction Temperature........................... 125°C
Operating Temperature Range (Note 2)..–40°C to 125°C
Storage Temperature Range...................–65°C to 125°C
UFD PACKAGE
20-PIN (4mm × 5mm) PLASTIC QFN
= 125°C, θ = 43°C/W
T
JMAX
JA
EXPOSED PAD (PIN 21) IS GND, MUST BE TIED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LT3751EUFD#PBF
LT3751IUFD#PBF
LEAD BASED FINISH
LT3751EUFD
TAPE AND REEL
LT3751EUFD#TRPBF
LT3751IUFD#TRPBF
TAPE AND REEL
LT3751EUFD#TR
LT3751IUFD#TR
PART MARKING*
3751
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
20-Lead (4mm × 5mm) Plastic QFN
20-Lead (4mm × 5mm) Plastic QFN
PACKAGE DESCRIPTION
3751
PART MARKING*
3751
20-Lead (4mm × 5mm) Plastic QFN
20-Lead (4mm × 5mm) Plastic QFN
LT3751IUFD
3751
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3751f
2
LT3751
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC = CHARGE = 5V, CLAMP = 0V, unless otherwise noted. Individual 25kΩ
resistors tied from 5V VTRANS supply to RVTRANS, RVOUT, RDCM, unless otherwise noted. (Note 2)
PARAMETER
Voltage
CONDITIONS
MIN
4.75
4.75
TYP
MAX
24
UNITS
l
l
V
V
V
CC
RV
TRANS
Voltage
(Note 3)
65
V
CC
Quiescent Current
Not Switching, CHARGE = 5V
Not Switching, CHARGE = 0.3V
5.5
0
8
1
mA
μA
RV
, R
Quiescent Current
(Note 4)
TRANS DCM
Not Switching, CHARGE = 5V
Not Switching, CHARGE = 0.3V
l
l
35
42
40
0
45
1
μA
μA
RV
Quiescent Current
(Note 4)
Not Switching, CHARGE = 5V
Not Switching, CHARGE = 0.3V
OUT
47
0
52
1
μA
μA
UVLO1, UVLO2, OVLO1, OVLO2 Clamp Voltage
RV , RV , R Clamp Voltage
Measured at 1mA into Pin, CHARGE = 0V
Measured at 1mA into Pin, CHARGE = 0V
55
60
V
V
TRANS
OUT DCM
CHARGE Pin Current
CHARGE = 24V
CHARGE = 5V
CHARGE = 0V
425
60
μA
μA
μA
1
l
l
CHARGE Minimum Enable Voltage
CHARGE Maximum Disable Voltage
Minimum CHARGE Pin Low Time
One-Shot Clock Period
1.5
V
V
I
≤ 1μA
0.3
VCC
20
38
ꢀs
ꢀs
V
l
l
32
44
1.005
40
V
OUT
V
OUT
Comparator Trip Voltage
Comparator Overdrive
Measured RBG at Pin
2μs Pulse Width,
RV
R
0.955
0.98
20
mV
, RV
TRANS
= 25kꢁ
OUT
= 0.83kꢁ
BG
DCM Comparator Trip Voltage
Measured as V
– V , R = 25kΩ (Note 5)
TRANS DCM
350
600
900
mV
DRAIN
Current Limit Comparator Trip Voltage
FB Pin = 0V
FB Pin = 1.3V
l
l
100
7
106
11
112
15
mV
mV
FB Pin Bias Current
Current Sourced from FB Pin, Measured at FB Pin Voltage
(Note 6)
64
1.22
1.16
55
1.34
60
5
300
1.25
1.2
nA
V
l
FB Pin Voltage
1.19
1.12
FB Pin Charge Mode Threshold
FB Pin Charge Mode Hysteresis
FB Pin Overvoltage Mode Threshold
FB Pin Overvoltage Hysteresis
DONE Output Signal High
DONE Output Signal Low
DONE Leakage Current
FAULT Output Signal High
FAULT Output Signal Low
FAULT Leakage Current
UVLO1 Pin Current
V
mV
V
1.29
1.38
mV
V
100kΩ to 5V
100kΩ to 5V
40
5
200
200
mV
nA
V
DONE = 5V
100kΩ to 5V
5
100kΩ to 5V
40
5
200
200
mV
nA
ꢀA
ꢀA
ꢀA
ꢀA
FAULT = 5V
l
l
l
l
UVLO1 Pin Voltage = 1.24V
UVLO2 Pin Voltage = 1.24V
OVLO1 Pin Voltage = 1.24V
OVLO2 Pin Voltage = 1.24V
48.5
48.5
48.5
48.5
50
50
50
50
51.5
51.5
51.5
51.5
UVLO2 Pin Current
OVLO1 Pin Current
OVLO2 Pin Current
3751f
3
LT3751
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC = CHARGE = 5V, CLAMP = 0V, unless otherwise noted. Individual 25kΩ
resistors tied from 5V VTRANS supply to RVTRANS, RVOUT, RDCM, unless otherwise noted. (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
1.225
1.225
1.225
1.225
0.7
MAX
1.255
1.255
1.255
1.255
UNITS
l
l
l
l
UVLO1 Threshold
UVLO2 Threshold
OVLO1 Threshold
OVLO2 Threshold
Gate Minimum High Time
Gate Peak Pull-Up Current
Measured from Pin to GND
Measured from Pin to GND
Measured from Pin to GND
Measured from Pin to GND
1.195
1.195
1.195
1.195
V
V
V
V
ꢀs
V
CC
V
CC
= 5V, LVGATE Active
= 12V, LVGATE Inactive
2.0
1.5
A
A
Gate Peak Pull-Down Current
Gate Rise Time
V
V
= 5V, LVGATE Active
1.2
1.5
A
A
CC
CC
= 12V, LVGATE Inactive
10% → 90%, C
= 3.3nF (Note 8)
GATE
40
55
ns
ns
V
V
= 5V, LVGATE Active
CC
CC
= 12V, LVGATE Inactive
Gate Fall Time
90% → 10%, C
= 3.3nF (Note 8)
GATE
30
30
ns
ns
V
V
= 5V, LVGATE Active
CC
= 12V, LVGATE Inactive
CC
Gate High Voltage
(Note 8):
V
V
V
V
= 5V, LVGATE Active
4.98
10
5
5
V
V
V
V
CC
CC
CC
CC
= 12V, LVGATE Inactive
= 12V, LVGATE Inactive, CLAMP Pin = 5V
= 24V, LVGATE Inactive
10.5
5.6
11.5
6.5
11.5
10
10.5
Gate Turn-Off Propagation Delay
C
= 3.3nF
180
ns
GATE
25mV Overdrive Applied to CSP Pin
Gate Voltage Overshoot
CLAMP Pin Threshold
500
1.6
mV
V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3751E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design
characterization and correlation with statistical process controls. The
LT3751I is guaranteed over the full –40°C to 125°C operating junction
temperature range.
Note 5: Refer to Block Diagram for V
and V
definitions.
DRAIN
TRANS
Note 6: Low noise regulation of the output voltage requires a resistive
voltage divider from output voltage to FB pin. FB pin should not be
grounded in this configuration. Refer to the Typical Application diagram for
proper FB pin configuration.
Note 7: The feedback pin has built-in hysteresis that defines the boundary
between charge-only mode and low noise regulation mode.
Note 8: LVGATE should be used in parallel with HVGATE when V is less
than or equal to 8V (LVGATE active). When not in use, LVGATE should be
CC
tied to V (LVGATE inactive).
CC
Note 3: A 60V internal clamp is connected to RV
, RDCM, RV
,
TRANS
OUT
Note 9: Do not apply a positive or negative voltage or current source to
HVGATE, otherwise permanent damage may occur.
UVLO1, UVLO2, OVLO1 and OVLO2. Resistors should be used such that
the pin currents do not exceed the Absolute Maximum Ratings.
Note 4: Currents will increase as pin voltages are taken higher than the
internal clamp voltage.
3751f
4
LT3751
TYPICAL PERFORMANCE CHARACTERISTICS
VTRANS Supply Current
CHARGE Pin Current
vs Pin Voltage
VCC Pin Current vs Pin Voltage
vs Supply Voltage
7
6
5
4
3
2
1
0
150
145
140
135
130
125
120
115
110
450
400
350
300
250
200
150
100
50
RV
V
, RV , R
= 25k
TRANS
CC
OUT DCM
, CHARGE = 5V
I
= I
+ I
+ I
VTRANS RVTRANS RVOUT RDCM
–40°C
25°C
–40°C
25°C
125°C
–40°C
25°C
125°C
125°C
0
0
4
8
12
16
20
24
0
10
20
30
40
50
60
0
4
8
12
16
20
24
PIN VOLTAGE (V)
PIN VOLTAGE (V)
PIN VOLTAGE (V)
3751 G01
3751 G02
3751 G03
CHARGE Pin Minimum Enable
Voltage vs Temperature
CHARGE Pin Maximum Disable
Voltage vs Temperature
DONE, FAULT Pin Voltage Low
vs Temperature
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
400
350
300
250
200
150
100
50
V
CC
V
CC
V
CC
= 5V
= 12V
= 24V
1mA SINK
100μA SINK
10μA SINK
V
CC
V
CC
V
CC
= 5V
= 12V
= 24V
0
–40 –20
0
20 40 60 80 100 120
–40 –20
0
20 40 60 80 100 120
–40 –20
0
20 40 60 80 100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3751 G04
3751 G05
3751 G06
VOUT Comparator Trip Voltage
vs Temperature
UVLO1 Trip Voltage
vs Temperature
UVLO1 Trip Current
vs Temperature
30.8
30.4
30.0
29.6
29.2
28.8
28.4
1.236
1.234
1.232
1.230
1.228
1.226
1.224
50.5
50.4
50.3
50.2
50.1
50.0
49.9
49.8
49.7
RV
, RV
TRANS
= 25.5k (R
= 1%)
TOL
OUT
V
CC
V
CC
V
CC
= 5V
= 12V
= 24V
V
CC
V
CC
V
CC
= 5V
= 12V
= 24V
V
V
V
= 5V
= 12V
= 24V
TRANS
TRANS
TRANS
V
= 48V
= 72V
TRANS
TRANS
V
–40 –20
0
20 40 60 80 100 120
TEMPERATURE (°C)
–40 –20
0
20 40 60 80 100 120
–40 –20
0
20 40 60 80 100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
3751 G07
3751 G08
3751 G09
3751f
5
LT3751
TYPICAL PERFORMANCE CHARACTERISTICS
Current Comparator Minimum
Trip Voltage (Regulation Mode)
vs Temperature
Current Comparator Trip Voltage
(Charge Mode) vs Temperature
FB Pin Regulation Mode
Threshold vs Temperature
1.168
1.164
1.160
1.156
1.152
109.0
108.5
108.0
107.5
107.0
13.0
12.8
12.6
12.4
12.2
12.0
11.8
11.6
11.4
11.2
11.0
V
= V
– V
V
= V
– V
CSP CSN
TH
CSP
CSN
TH
FB = 1.3V
V
V
V
= 5V
= 12V
= 24V
V
CC
V
CC
V
CC
= 5V
= 12V
= 24V
V
CC
V
CC
V
CC
= 5V
= 12V
= 24V
CC
CC
CC
–40 –20
0
20 40 60 80 100 120
–40 –20
0
20 40 60 80 100 120
TEMPERATURE (°C)
–40 –20
0
20 40 60 80 100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
3751 G12
3751 G10
3751 G11
FB Pin Regulation Mode
Hysteresis vs Temperature
FB Pin Overvoltage Mode
Threshold Voltage vs Temperature
FB Pin Overvoltage Mode
Hysteresis vs Temperature
60
58
56
54
52
50
1.356
1.354
1.352
1.350
1.348
1.346
1.344
61.0
60.6
60.2
59.8
59.4
59.0
V
V
V
= 5V
= 12V
= 24V
V
CC
V
CC
V
CC
= 5V
= 12V
= 24V
CC
CC
CC
V
V
V
= 5V
= 12V
= 24V
CC
CC
CC
–40 –20
0
20 40 60 80 100 120
–40 –20
0
20 40 60 80 100 120
–40 –20
0
20 40 60 80 100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3751 G13
3751 G14
3751 G15
HVGATE Pin Clamp Voltage
vs Temperature
CLAMP Pin Threshold
vs Temperature
1.9
11.0
10.9
10.8
10.7
10.6
10.5
10.4
V
CC
V
CC
= 12V
= 24V
V
= 24V
CC
CLAMP = 0V
1.8
1.7
1.6
1.5
1.4
–40
0
40
80
120
–40 –20
0
20 40 60 80 100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
3751 G16
3751 G17
3751f
6
LT3751
TYPICAL PERFORMANCE CHARACTERISTICS
DCM Trip Voltage (VDRAIN
–
VTRANS) vs Temperature (RVTRANS
= RDCM = 25kΩ)
HVGATE Pin Clamp Voltage
vs Temperature
0.64
0.62
0.60
0.58
0.56
0.54
5.70
5.65
5.60
5.55
5.50
V
V
V
V
= 5V
V
= 12V
TRANS
TRANS
TRANS
TRANS
CC
= 12V
= 24V
= 48V
CLAMP = 12V
–40
0
40
80
120
–40 –20
0
20 40 60 80 100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
3751 G19
3751 G18
PIN FUNCTIONS
OVLO1 (Pin 1): V
Overvoltage Lockout Pin. Senses
FAULT (Pin 4): Open Collector Indication Pin. When either
or V exceeds the user-selected voltage range, a
TRANS
when V
rises above:
V
TRANS
TRANS
CC
transistor turns on. The part will stop switching. This pin
needs a proper pull-up resistor or current source.
VOVLO1 =1.225+50μA •ROVLO1
DONE (Pin 5): Open Collector Indication Pin. When the
target output voltage (charge mode) is reached, a transis-
tor turns on. This pin needs a proper pull-up resistor or
current source.
and trips the FAULT latch low, disabling switching. After
V
drops below V
, toggling the CHARGE pin
TRANS
OVLO1
reactivates switching.
UVLO2 (Pin 2): V Undervoltage Lockout Pin. Senses
CHARGE (Pin 6): Charge Pin. Initiates a new charge cycle
(charge mode) or enables the part (regulation mode)
when driven higher than 1.5V. Bring this pin below 0.3V
to discontinue charging and put the part into shutdown.
Turn-on ramp rates should be between 10ns to 10ms.
CC
when V drops below:
CC
VUVLO2 =1.225+50μA •RUVLO2
CHARGE pin should not be directly ramped with V or
and trips the FAULT latch low, disabling switching. After
CC
LT3751 may not properly initiate.
V
rises above V
, toggling the CHARGE pin reac-
UVLO2
CC
tivates switching.
CLAMP (Pin 7): Internal Clamp Voltage Selection Pin.
Tie this pin to V to activate the internal 5.6V gate driver
OVLO2 (Pin 3): V Overvoltage Lockout Pin. Senses
CC
CC
clamp. Tie this pin to ground to activate the internal 10.5V
when V rises above:
CC
gate driver clamp.
VOVLO2 =1.225+50μA •ROVLO2
FB(Pin8):FeedbackRegulationPin.Usethispintoachieve
low noise voltage regulation. FB is internally regulated
to 1.22V when a resistive divider is tied from this pin to
the output. FB pin should not float. Tie FB pin to either a
and trips the FAULT latch low, disabling switching. After
V
drops below V
, toggling the CHARGE pin reac-
CC
OVLO2
tivates switching.
resistor divider or ground.
3751f
7
LT3751
PIN FUNCTIONS
CSN (Pin 9): Negative Current Sense Pin. Senses external
NMOS source current. Connect to local R
RDCM (Pin 17): Discontinuous Mode Sense Pin. Senses
when the external NMOS drain is equal to 20μA • R
ground
+
DCM
SENSE
connection for proper Kelvin sensing. The current limit
is set by 106mV/R
V
and initiates the next charge cycle. Place a resis-
TRANS
.
tor equal to 0.45 times the resistor on the RV
between this pin and V
pin
SENSE
TRANS
.
DRAIN
CSP (Pin 10): Positive Current Sense Pin. Senses NMOS
source current. Connect the NMOS source terminal and
the current sense resistor to this pin. The current limit is
RV
(Pin19):TransformerSupplySensePin.Connect
TRANS
a resistor between the RV
pin and the V
supply.
TRANS
TRANS
fixed at 106mV/R
in charge mode. The current limit
RefertoFigure11forpropersizingoftheRV
The minimum operation voltage for V
resistor.
SENSE
TRANS
can be reduced to a minimum 11mV/R
mode.
in regulation
is 4.75V.
SENSE
TRANS
UVLO1(Pin20):V
UndervoltageLockoutPin.Senses
TRANS
drops below:
V
(Pin 11): Input Supply Pin. Must be locally bypassed
when V
CC
TRANS
with high-grade (X5R or better) ceramic capacitor. The
minimum operating voltage for V is 4.75V.
VUVLO1 =1.225+50μA •RUVLO1
CC
LVGATE (Pin 12): Low Voltage Gate Pin. Connect the
and trips the FAULT latch low, disabling switching. After
NMOS gate terminal to this pin when operating V below
CC
V
rises above V
, toggling the CHARGE pin
8V. The internal gate driver will drive the voltage to the
TRANS
UVLO1
reactivates switching.
V
rail. When operating V higher than 8V, tie this pin
CC
CC
directly to V .
CC
GND (Pin 21): Ground. Tie directly to local ground plane.
HVGATE (Pin 13): High Voltage Gate Pin. Connect NMOS
gate terminal to this pin for all V operating voltages.
CC
Internal gate driver will drive the voltage to within V
CC
– 2V during each switch cycle.
RBG (Pin 14): Bias Generation Pin. Generates a bias
current set by 0.98V/R . Select R to achieve desired
BG
BG
TRANS
resistance for R
, RV , and RV
.
DCM
OUT
RV
(Pin 16): Output Voltage Sense Pin. Develops a
OUT
currentproportionaltooutputcapacitorvoltage.Connecta
resistor between this pin and drain of NMOS such that:
⎛
⎞
RVOUT
RBG
VOUT = 0.98 •N•
− VDIODE
⎜
⎟
⎝
⎠
when RV
is set equal to RV , otherwise:
TRANS
OUT
⎡
⎤
⎥
⎛
⎞
RVOUT
RBG
RVOUT
RV
TRANS
VOUT =N• 0.98 •
+ VTRANS
−1
⎢
⎜
⎟
⎝
⎠
⎢
⎣
⎥
⎦
− VDIODE
where V
= forward voltage drop of diode D1 (refer
DIODE
to Block Diagram).
3751f
8
LT3751
BLOCK DIAGRAM
T1
1:10
•
D1
V
V
OUT
450V
TRANS
12V
+
47μF
×2
RV
TRANS
40.2k
10μF
+
C
OUT
•
RV
TRANS
V
OUT
COMPARATOR
–
+
CHARGE
0.98V
60V
REFERENCE
OFF ON
OTLO
START-UP
RV
OUT
RV
OUT
ONE SHOT
40.2k
V
CC
V
CC
12V
MASTER
LATCH
DIFF. AMP
COMPARATOR
WITH
INTERNAL
60V CLAMPS
60V
100k
DONE
DCM
COMPARATOR
10μF
R
DCM
S
R
Q
RDCM
60V
–
+
18.2k
Q
ENABLE
GATE
DRIVER
DCM
ONE SHOT
100k
1.22V
REFERENCE
FAULT
V
DRAIN
S
Q
R
Q
FAULT
LATCH
V
CC
26kHz ONE SHOT
CLOCK
HVGATE
GATE DRIVE
CIRCUITRY
M1
S
R
Q
INTERNAL
UVLO
Q
3.8V
+
–
SWITCH
LATCH
CLAMP
LVGATE
V
CC
V
CC
R
UVLO1
191k
UVLO1
OVLO1
UVLO2
OVLO2
V
V
RESET
TRANS
+
–
CC
AUXILIARY
CLK
55V
COUNT
+
COUNTER
162mV
R
OVLO1
240k
– +–
+
–
26kHz
ONE SHOT
CLOCK
55V
MAIN
CSP
CSN
+
R
SENSE
12mꢁ
106mV
UVLO/OVLO
R
UVLO2
191k
COMPARATORS
– +–
V
+
–
CC
TIMING AND PEAK
CURRENT CONTROL
55V
55V
11mV TO 106mV
MODULATION
TO CHARGE
1-SHOT
26kHz
ONE SHOT
CLOCK
ERROR
AMP
1.22V
REFERENCE
+
–
R
OVLO2
240k
A1
+
–
R
FBH
3.65M
FB
DIE
TEMP
TO V
OUT
COMPARATOR
160ºC
MODE
CONTROL
1.22V
REFERENCE
R
FBL
10k
10nF
GND
RBG
3751 BD
R
BG
1.33k
3751f
9
LT3751
OPERATION
TheLT3751canbeusedaseitherafast,efficienthighvoltage
capacitor charger controller or as a high voltage, low noise
voltage regulator. The FB pin voltage determines one of the
three primary modes: charge mode, low noise regulation,
or overvoltage Burst Mode® Operation (see Figure 1).
I
LPRI
V
– V
PRI
TRANS
DS(ON)
I
L
PK
FB PIN
VOLTAGE
I
LSEC
OVERVOLTAGE
1.34V
V
+ V
L
OUT
DIODE
SEC
I
PK
N
REGULATION
1.16V
CHARGE
MODE
V
PRI
V
– V
TRANS
DS(ON)
0.0V
3751 F01
Figure 1. FB Pin Modes
CHARGE MODE
–(V
+ V
N
)
DIODE
OUT
When the FB pin voltage is below 1.16V, the LT3751 acts
as a rapid capacitor charger. The charging operation has
four basic states for charge mode steady-state operation
(see Figure 2).
V
SEC
V
OUT
+ V
DIODE
1. Start-Up
The first switching cycle is initiated approximately 2μs
after the CHARGE pin is raised high. During this phase,
the start-up one-shot enables the master latch turning
on the external NMOS and beginning the first switching
cycle. After start-up, the master latch will remain in the
switching-enable state until the target output voltage is
reached or a fault condition occurs.
–N (V
– V
)
DS(ON)
TRANS
V
+ V
N
OUT
DIODE
V
+
TRANS
V
DRAIN
V
TRANS
TheLT3751utilizescircuitrytoprotectagainsttransformer
primarycurrententeringarunawayconditionandremains
in start-up mode until the DCM comparator has enough
headroom. Refer to the Start-Up Protection section for
more detail.
V
V
DS(ON)
DS(ON)
1.
3751 F02
2.
3.
PRIMARY-SIDE
CHARGING
SECONDARY
ENERGY TRANSFER
AND OUTPUT
DISCONTINUOUS
MODE
DETECTION
DETECTION
2. Primary Side Charging
Figure 2. Idealized Charging Waveforms
When the NMOS switch latch is set, and depending on the
use of LVGATE, the gate driver rapidly charges the gate
pin to V – 2V in high voltage applications or directly to
CC
V
in low voltage applications (refer to the Application
CC
Burst Mode is a registered trademark of Linear Technology Corporation.
3751f
10
LT3751
OPERATION
Information section for proper use of LVGATE). With the
gate driver output high, the external NMOS turns on,
comparator sets the NMOS switch latch and a new charge
cycle begins. Steps 2-4 continue until the target output
voltage is reached.
forcing V
– V
across the primary winding.
TRANS
DS(ON)
Consequently, current in the primary coil rises linearly at
a rate (V – V )/L . The input voltage is mir-
Start-Up Protection
TRANS
DS(ON) PRI
rored on the secondary winding –N • (V
– V
)
TRANS
DS(ON)
TheLT3751atstart-up,whentheoutputvoltageisverylow
(or shorted), usually does not have enough V
voltage to trip the DCM comparator. The part in start-up
modeusestheinternal26kHzclockandanauxiliarycurrent
comparator. Figure 3 shows a simplified block diagram of
the start-up circuitry.
which reverse-biases the diode and prevents current flow
in the secondary winding. Thus, energy is stored in the
core of the transformer.
node
DRAIN
3. Secondary Energy Transfer
Whencurrentlimitisreached,thecurrentlimitcomparator
resets the NMOS switch latch and the device enters the
third phase of operation, secondary energy transfer. The
energy stored in the transformer core forward-biases the
diode and current flows into the output capacitor. During
this time, the output voltage (neglecting the diode drop)
is reflected back to the primary coil. If the target output
FROM AUXILIARY
INCREMENT
CURRENT
COMPARATOR
COUNTER 1
–
FROM DCM
RESET
COMPARATOR
FROM CLK
SWITCH
LATCH
+
INCREMENT
COUNTER 2
RESET
FROM GATE
DRIVER ON
voltage is reached, the V
comparator resets the master
OUT
3751 F03
latch and the DONE pin goes low. Otherwise, the device
enters the next phase of operation.
Figure 3. Start-Up Protection Circuitry
Toggling the CHARGE pin always generates a start-up
one-shottoturnontheexternalswitch,initiatingthecharg-
ing process. After the start-up one-shot, the LT3751 waits
for either the DCM comparator to generate a one-shot or
the output of the start-up protection circuitry going high,
4. Discontinuous Mode Detection
During secondary energy transfer to the output capacitor,
(V
+ V
)/N will appear across the primary wind-
OUT
DIODE
ing. A transformer with no energy cannot support a DC
voltage, so the voltage across the primary will decay to
zero. In other words, the drain of the NMOS will ring
which ever comes first. If the switch drain node, V
,
DRAIN
is below the DCM comparator threshold (see Entering
Normal Boundary Mode), the DCM comparator will never
fire and the start-up circuitry is dominant.
down from V
+ (V
+ V
TRANS
)/N to V
. When
TRANS
OUT
DIODE
+ 20μA • R
TRANS
the drain voltage falls to V
, the DCM
DCM
V
V
TH1
V
TH2
V
DRAIN
V
OUT
DCM
1-SHOT
t
START-UP
(DCM THRESHOLD = V
BOUNDARY-MODE
(DCM THRESHOLD = V
BELOW V
TH2
(WAIT FOR TIME-OUT)
)
)
TH2
TH1
3751 F04
Figure 4. DCM Comparator Thresholds
3751f
11
LT3751
OPERATION
Atverylowoutputvoltages,theboundary-modeswitching
cycle period increases significantly such that the energy
stored in the transformer core is not depleted before the
next clock cycle. In this situation, the clock may initiate
another switching cycle before the secondary winding
current reaches zero and cause the LT3751 to enter con-
tinuous-modeconduction.Normally,thisisnotaproblem;
however, if the secondary energy transfer time is much
longer than the CLK period, significant primary current
overshoot can occur. This is due to the non-zero starting
point of the primary current when the switch turns on and
the finite speed of the current comparator.
V
, and indicates that the energy in the secondary
DRAIN
winding has depleted. For this to happen, V
must
DRAIN
exceed V
+ ΔV
prior to its negative edge; oth-
TRANS
DRAIN
erwise, the DCM comparator will not generate a one-shot
to initiate the next switching cycle. The part would remain
stuck in this state indefinitely; however, the LT3751 uses
the start-up protection circuitry to jumpstart switching if
the DCM comparator does not generate a one-shot after
a maximum time-out of 500μs.
Figure 4 shows a typical V
a test circuit voltage clamp applied to the output. V
node waveform with
DRAIN
TH1
is the start-up threshold and is set internally by forcing
to 40ꢀA. Once the first DCM one-shot is initiated,
The LT3751 startup circuitry adds an auxiliary current
comparator with a trip level 50% higher than the nominal
trip level. Every time the auxiliary current comparator
trips, therequiredclockcountbetweenswitchingcyclesis
incremented by one. This allows more time for secondary
energy transfer.
I
OFFSET
the mode latch is set to boundary-mode. The mode latch
then sets the clock count to maximum (500μs) and lowers
the DCM comparator threshold to V (I
= 20ꢀA).
TH2 OFFSET
This provides needed hysteresis between start-up mode
and boundary-mode operation.
Counter 1 in Figure 3 is set to its maximum count when
the first DCM comparator one-shot is generated. If no
DCM one-shot is initiated in normal boundary-mode
operation during a maximum count of approximately
500μs, the LT3751 re-enters start-up mode and the count
is returned to zero.
LOW NOISE REGULATION
Low noise voltage regulation can be achieved by adding
a resistive divider from the output node to the LT3751 FB
pin. At start-up (FB pin below 1.16V), the LT3751 enters
the charge mode to rapidly charge the output capacitor.
Once the FB pin is within the threshold range of 1.16V
to 1.34V, the part enters into low noise regulation. The
switching methodology in regulation mimics that used
in the capacitor charging mode, but with the addition of
peak current and duty cycle control techniques. Figure 5
shows the steady state operation for both regulation
techniques. Figure 6 shows how both techniques are
combined to provide stable, low noise operation over a
wide load and supply range.
Note that Counter 1 is initialized to zero at start-up. Thus,
theoutputofthestartupcircuitrywillgohighafteroneclock
cycle. Counter 2 is reset when the gate driver goes high.
This repeats until either the auxiliary current comparator
incrementstherequiredclockcountoruntilV
ishigh
DRAIN
enough to sustain normal operation described in steps 2
through 4 in the previous section.
Entering Normal Boundary Mode
The LT3751 has two DCM comparator thresholds that are
dependent on what mode the part is in, either start-up
modeornormalboundary-mode,andthestateofthemode
latch. For boundary-mode switching, the LT3751 requires
During heavy load conditions, the LT3751 sets the peak
primarycurrenttoitsmaximumvalue,106mV/R
and
SENSE
sets the maximum duty cycle to approximately 95%. This
allows for maximum power delivery. At very light loads,
the opposite occurs, and the LT3751 reduces the peak
primary current to approximately one tenth its maximum
value while modulating the duty cycle below 10%. The
LT3751 controls moderate loads with a combination of
peak current mode control and duty cycle control.
the DCM sense voltage (V
) to exceed V
by the
DRAIN
TRANS
ΔDCM comparator threshold, ΔV
:
DRAIN
ΔV
= (40μA + I
) • R – 40μA • RV
OFFSET DCM TRANS
DRAIN
where I
is mode dependent. The DCM one-shot
OFFSET
signal is negative edge triggered by the switch node,
3751f
12
LT3751
OPERATION
CHARGE MODE
LIGHT LOAD OPERATION
26kHz
ONE-SHOT
CLK
26kHz
ONE-SHOT
CLK
...
...
...
...
SWITCH
ENABLE
MAXIMUM
PEAK CURRENT
NO BLANKING
SWITCH
ENABLE
DUTY CYCLE
CONTROL
DUTY CYCLE
CONTROL
FORCED
BLANKING
I
I
PRI
PRI
...
...
t
t
t
≈ 38μs
PER
NO LOAD OPERATION
HEAVY LOAD OPERATION
26kHz
ONE-SHOT
CLK
26kHz
ONE-SHOT
CLK
...
...
...
...
110%
OUT, NOM
V
SWITCH
ENABLE
PEAK CURRENT
CONTROL
V
OUT
FORCED
BLANKING
105%
OUT, NOM
V
...
1/10TH I
I
PK
PRI
...
I
PRI
t
t
t
≈ 38μs
PER
3751 F05
Figure 5. Modes of Operation (Steady State)
I
(
) DUTY CYCLE(
)
LIM
I
MAX
95%
NO LOAD
OPERATION
1/10
MAX
10%
0
I
LOAD
CURRENT
CHARGE
MODE
3751 F06
LIGHT LOAD
MODERATE
LOAD
HEAVY LOAD
Figure 6. Regulation Technique
3751f
13
LT3751
OPERATION
Periodic Refresh
Light Load Operation
When the LT3751 enters regulation, the internal circuitry
deactivates switching when the internal one-shot clock
is high. The clock operates at a 1/20th duty cycle with a
minimum blank time of 1.5μs. This reset pulse is timed to
drastically reduce switching frequency content within the
audiospectrumandisactiveduringallloadingconditions.
Each reset pulse guarantees at least one energy cycle. A
minimum load is required to prevent the LT3751 from
entering overvoltage Burst Mode Operation.
The LT3751 uses duty cycle control to drastically reduce
audible noise in both the transformer (mechanical) and
the ceramic capacitors (piezoelectric effects). Internal
control circuitry forces a one-shot condition at a periodic
rate greater than 20kHz and out of the audio spectrum.
The regulation loop then determines the number of pulses
that are required to maintain the correct output voltage.
Figure 5 shows the use of duty-cycle control.
No Load Operation
Heavy Load Operation
The LT3751 can remain in low noise regulation at very low
loading conditions. Below a certain load current threshold
(LightLoadOperation), theoutputvoltagewouldcontinue
to increase and a runaway condition could occur. This is
due to the periodic one-shot forced by the periodic refresh
circuitry. By design, the LT3751 has built-in overvoltage
protection associated with the FB pin.
The LT3751 enters peak current mode control at higher
output load conditions. The control loop maximizes the
number of switch cycles between each reset pulse. Since
the control scheme operates in boundary mode, the reso-
nant boundary-mode period changes with varying peak
primary current:
⎡
⎢
⎣
⎤
⎥
⎦
1
N
When the FB pin voltage exceeds 1.34V ( 20mV), the
LT3751 enters overvoltage Burst Mode Operation.
Overvoltage Burst Mode Operation does not reset with
the one-shot clock. Instead, the pulse train is completely
load-dependent. These bursts are asynchronous and can
contain long periods of inactivity. This allows regulation at
a no-load condition but with the increase of audible noise
andvoltageripple.Notethatwhenoperatinginovervoltage
Burst Mode Operation, the output voltage will increase
10% above the nominal output voltage.
Period=IPK •LPRI
•
+
VTRANS VOUT
and the power output is proportional to the peak primary
current:
1/ 2•IPK
POUT
=
⎡
⎢
⎣
⎤
⎥
⎦
1
N
+
VTRANS VOUT
Noise becomes an issue at very low load currents. The
LT3751 remedies this problem by setting the lower peak
current limit to one tenth the maximum level and begins
to employ duty-cycle control.
3751f
14
LT3751
APPLICATIONS INFORMATION
100
90
80
70
60
50
40
30
20
10
0
The LT3751 charger controller can be optimized for either
capacitor charging only or low noise regulation applica-
tions. Several equations are provided to aid in the design
process.
P = 20 WATTS
P = 50 WATTS
P = 100 WATTS
Safety Warning
Largecapacitorschargedtohighvoltagecandeliveralethal
amount of energy if handled improperly. It is particularly
important to observe appropriate safety measures when
designing the LT3751 into applications. First, create a dis-
charge circuit that allows the designer to safely discharge
theoutputcapacitor.Second,adequatelyspacehighvoltage
nodes from adjacent traces to satisfy printed circuit board
voltage breakdown requirements.
1
10
PEAK PRIMARY CURRENT (A)
100
3751 F07
Figure 7. Maximum Power Output
Selecting Transformer Turns Ratio
Selecting Operating Mode
The transformer ratio, N, should be selected based on
the input and output voltages. Smaller N values equate
to faster charge times and larger available output power.
Tie the FB pin to GND to operate the LT3751 as a capacitor
charger. In this mode, the LT3751 charges the output at
peak primary current in boundary mode operation. This
constitutes maximum power delivery and yields the fast-
est charge times. Power delivery is halted once the output
reaches the desired output voltage set by the RV
RBG pins.
Note that drastically reducing N below the V /V
OUT TRANS
ratio will increase the flyback voltage on the drain of the
NMOS and increase the current through the output diode.
and
OUT
A good choice is to select N equal to V /V
.
OUT TRANS
VOUT
VTRANS
N≤
Tie a resistor divider from the FB pin to V
and GND
OUT
to operate the LT3751 as a low noise voltage regulator
(refer to Low Noise regulation section for proper design
procedures). The LT3751 operates as a voltage regulator
using both peak current and duty cycle modulation to vary
output current during different loading conditions.
Choosing Capacitor Charger I
PK
When operating the LT3751 as capacitor charger, choose
based on the required capacitor charge time, t
I
PK
,
CHARGE
and the initial design inputs.
Selecting Component Parameters
2•N• VTRANS + VOUT •COUT • VOUT
(
)
IPK =
Most designs start with the initial selection of V
,
Efficiency • VTRANS • tCHARGE − td
(
)
TRANS
, (capacitor
V
, C , and either charge time, t
OUT OUT
charger) or P
CHARGE
Theconverterefficiencyvariesovertheoutputvoltagerange.
TheI equationisbasedontheaverageefficiencyoverthe
(regulator). These design inputs
OUT,MAX
PK
are then used to select the transformer ratio, N, the peak
primary current, I , and the primary inductance, L
entirechargingperiod.Severalfactorscancausethecharge
timetoincrease.Efficiencyisthemostdominantfactorand
is mainly affected by the transformer winding resistance,
core losses, leakage inductance, and transistor R . Most
applications have overall efficiencies above 70%.
.
PRI
PK
Figure7canbeusedasaroughguideformaximumpower
output for a given V and I .
TRANS
PK
DS
3751f
15
LT3751
APPLICATIONS INFORMATION
Thetotalpropagationdelay,t ,isthesecondmostdominant
d
factor that affects efficiency and is the summation of gate
driver on-off propagation delays and the discharge time
associatedwiththesecondarywindingcapacitance.There
are two effective methods to reduce the total propagation
delay. First, reduce the total capacitance on the secondary
winding, most notably the diode capacitance. Second,
reduce the total required NMOS gate charge. Figure 8
shows the effect of large secondary capacitance.
V
DRAIN
I
SEC
NO SEC.
CAPACITANCE
I
PRI
SEC. DISCHARGE
t
3751 F08
The energy stored in the secondary winding capacitance
2
Figure 8. Effect of Secondary Winding Capacitance
is ½ • C • V
. This energy is reflected to the primary
SEC
OUT
when the diode stops forward conduction. If the reflected
capacitance is greater than the total NMOS drain capaci-
tance, the drain of the NMOS power switch goes negative
and its intrinsic body diode conducts. It takes some time
for this energy to be dissipated and thus adds to the total
propagation delay.
ThepreviousequationguaranteesthattheV comparator
OUT
has enough time to sense the flyback waveform and trip
the DONE pin latch. Operating V
significantly higher
OUT
then that used to calculate L could result in a runaway
PRI
condition and overcharge the output capacitor.
The L equation is adequate for most regulator applica-
PRI
Choosing Regulator Maximum I
PK
tions.NotethatifbothI andNareincreasedsignificantly
PK
The I parameter in regulation mode is calculated based
for a given V
and V , the maximum I will not be
PK
TRANS
OUT PK
on the desired maximum output power instead of charge
time like that in a capacitor charger application.
reached within the refresh clock period. This will result in
a lower than expect maximum output power. To prevent
this from occurring, maintain the condition in the follow-
ing equation.
POUT(AVG)
Efficiency
⎛
⎞
1
N
VOUT
IPK = 2•
•
+
⎜
⎟
V
⎝
⎠
TRANS
38μs
1
VTRANS VOUT
LPRI
<
Note that the LT3751 regulation scheme varies the peak
current based on the output load current. The maximum
⎡
⎤
N
I •
+
⎢
⎣
⎥
⎦
PK
I
is only reached during charge mode or during heavy
PK
load conditions where output power is maximized.
The upper constraint on L can be reduced by increas-
PRI
ing V
and starting the design process over. The best
TRANS
Transformer Design
regulation occurs when operating the boundary-mode
frequency above 100kHz (refer to Operation section for
boundary-mode definition).
Thetransformer’sprimaryinductance,L ,isdetermined
PRI
by the desired V
and previously calculated N and I
OUT
PK
parameters. Use the following equation to select L
:
PRI
3μs• VOUT
IPK •N
LPRI
=
3751f
16
LT3751
APPLICATIONS INFORMATION
Table 1. Recommended Transformers
MANUFACTURER
PART NUMBER
MAXIMUM I (A)
L
(μH)
PRI
TURNS RATIO (PRI:SEC)
SIZE L × W × H (mm)
PRI
Coilcraft
www.coilcraft.com
DA2033-AL
DA2034-AL
GA3459-BL
GA3460-BL
5
10
1:10
1:10
1:10
1:10
17.4 × 24.1 × 10.2
20.6 × 30 × 11.3
32.65 × 26.75 × 14
32.65 × 26.75 × 14
10
20
50
10
5
2.5
Midcom
www.midcom.com
750032051
750032052
750310349
750310355
5
10
10
5
1:10
1:10
1:10
1:10
28.7 × 22 × 11.4
28.7 × 22 × 11.4
36.5 × 42 × 23
36.5 × 42 × 23
10
20
50
2.5
Sumida
www.sumida.com
C8117
5
10
10
5
1:10
1:10
1:10
1:10
23 × 18.6 × 10.8
32.2 × 27 × 14
32.5 × 26.5 × 13.5
32.5 × 26.5 × 13.5
C8119
10
20
50
PS07-299
PS07-300
2.5
TDK
www.tdk.com
DCT15EFD-U44S003
DCT20EFD-U32S003
DCT25EFD-U27S005
5
10
20
10
10
5
1:10
1:10
1:10
22.5 × 16.5 × 8.5
30 × 22 × 12
27.5 × 33 × 15.5
Figure 9 defines the maximum boundary-mode switching
frequency when operating at a desired output power level
10.000
1.000
0.100
0.010
f
f
f
= 50kHz
= 100kHz
= 200kHz
MAX
MAX
MAX
and is normalized to L /P
(ꢀH/Watt). The relation-
PRI OUT
ship of output power, boundary-mode frequency, I , and
PK
primary inductance can be used as a guide throughout
the design process.
RV
& R
Selection
TRANS
DCM
RV
sets the common-mode reference voltage for
TRANS
both the DCM comparator and V
comparator. Select
OUT
0.001
1
10
PEAK PRIMARY CURRENT (A)
100
RV
from the design guide in Figure 10.
TRANS
3751 F09
The RV
pin is connected to an internal 40μA current
TRANS
Figure 9. Maximum Switching Frequency
source. Pin current increases as the pin voltage is taken
higher than the internal 60V zener clamp. Choose 25k for
V
voltage below 12V. Choose 40k for V
voltage
TRANS
TRANS
voltage greater than
between 12V and 60V. For V
TRANS
150k
60V, choose RV
than 60V (i.e. 55V).
to limit RV
pin voltage to less
TRANS
TRANS
SUGGESTED
TRANS
RESISTANCE
125k
100k
75k
RV
VTRANS – 55V
RVTRANS
=
40μA
needstobeproperlydesignedinrelationtoRV
50k
R
.
TRANS
DCM
Improper selection of R
can lead to undesired switch-
DCM
25k
ing operation at low output voltages.
10 20 30 40 50 60 70 80
RDCM = 0.45•RVTRANS
V
(V)
TRANS
3751 F10
Figure 10. Suggested RVTRANS Resistance
3751f
17
LT3751
APPLICATIONS INFORMATION
RV
& RBG Selection
creases with output voltage, the average current though
the NMOS is greatest when the output is nearly charged
and is given by:
OUT
RV
should be selected based on V
comparator trip
OUT
OUT
current.RV currentshouldbedesignedbetween100μA
OUT
IPK • VOUT(PK)
and 4mA to maintain accuracy.
IAVG,M
=
2(VOUT(PK) +N• VTRANS
)
V
OUT,TRIP + VDIODE
⎛
⎝
⎞
⎠
+ VTRANS − 55V
⎜
⎟
See Table 2 for recommended external NMOS transistors.
N
RVOUT
=
400μA
Gate Driver Operation
R
sets the trip current and is directly related to the
BG
The LT3751 gate driver has an internal, selectable 10.5V
or 5.6V clamp with up to 2A current capability (using
LVGATE). For 10.5V operation, tie CLAMP pin to ground,
selection of RV
.
OUT
0.98 •RVOUT
RBG
=
and for 5.6V operation, tie the CLAMP pin to the V pin.
CC
V
OUT,TRIP + VDIODE
⎛
⎞
⎛
⎝
⎞
⎟
RVOUT
RV
TRANS
− VTRANS
−1
Choose a clamp voltage that does not exceed the NMOS
⎜
⎟
⎜
N
⎠
⎝
⎠
manufacturer’s maximum V ratings. The 5.6V clamp
GS
can also be used to reduce LT3751 power dissipation
and increase efficiency when using logic-level FETs. The
typical gate driver overshoot voltage is 0.5V above the
clamp voltage.
NMOS Switch Selection
ChooseanexternalNMOSpowerswitchwithminimalgate
charge and on-resistance that satisfies current limit and
voltage break-down requirements. The gate is nominally
TheLT3751’sgatedriveralsoincorporatesaPMOSpull-up
deviceviatheLVGATEpin.ThePMOSpull-updrivershould
driven to V – 2V during each charge cycle. Ensure that
CC
this does not exceed the maximum gate to source voltage
rating of the NMOS but enhances the channel enough to
minimize the on-resistance.
onlybeusedforV applicationsof8Vorbelow.Operating
CC
LVGATE with V above 8V will cause permanent damage
CC
to the part. LVGATE is active when tied to HVGATE and
Similarly, the maximum drain-source voltage rating of the
allows rail-to-rail gate driver operation. This is especially
NMOS must exceed V
+ V /N or the magnitude
TRANS
OUT
useful for low V applications, allowing better NMOS
CC
of the leakage inductance spike, whichever is greater. The
maximuminstantaneousdraincurrentratingmustexceed
selected current limit. Because the switching period de-
drive capability. It also provides the fastest rise times,
given the larger 2A current capability verses 1.5A when
using only HVGATE.
Table 2. Recommended NMOS Transistors
MANUFACTURER
PART NUMBER
I (A)
D
V
(V)
R
(mΩ)
Q
(nC)
PACKAGE
DS(MAX)
DS(ON)
G(TOT)
Fairchild Semiconductor
www.fairchildsemi.com
FDS2582
FQB19N20L
FQP34N20L
4.1
21
31
150
200
200
66
140
75
11
27
55
SO-8
TO-252
TO-220
On Semiconductor
www.onsemi.com
MTD6N15T4G
NTD12N10T4G
NTB30N20T4G
NTB52N10T4G
6
150
100
200
100
300
165
81
15
14
75
72
DPAK
DPAK
12
30
52
2
D PAK
2
30
D PAK
Vishay
www.vishay.com
Si7820DN
2.6
3.4
33
200
150
200
240
135
60
12.1
20
53
1212-8
1212-8
TO-252
Si7818DN
SUP33N20-60P
3751f
18
LT3751
APPLICATIONS INFORMATION
Table 3. Recommended Output Diodes
MANUFACTURER
PART NUMBER
I
(A)
V
RRM
(V)
T (ns)
RR
PACKAGE
F(AV)
Central Semiconductor
www.centralsemi.com
CMR1U-10M
1
1000
100
SMA
Fairchild Semiconductor
www.fairchildsemi.com
ES3J
ES1G
ES1J
3
1
1
600
400
600
35
35
35
SMC
SMA
SMA
On Semiconductor
www.onsemi.com
MURS360
MURA260
MURA160
3
2
1
600
600
600
75
75
75
SMC
SMA
SMA
Vishay
www.vishay.com
USB260
US1G
2
1
1
5
600
400
1000
600
30
50
75
30
SMB
SMA
US1M
SMA
GURB5H60
TO-263AB
Output Diode Selection
Setting Current Limit
The output diode(s) are selected based on the maximum
repetitive reverse voltage (V ) and the average forward
Placing a sense resistor from the positive sense pin, CSP,
to the negative sense pin, CSN, sets the maximum peak
switch current. The maximum current limit is nominally
RRM
current (I
). The output diode’s V
should exceed
should exceed
F(AV)
RRM
V
PK
+ N • V
. The output diode’s I
106mV/R
. The power rating of the current sense
OUT
TRANS
F(AV)
SENSE
I /2N,theaverageshort-circuitcurrent.Theaveragediode
resistor must exceed:
I2 •RSENSE
current is also a function of the output voltage.
⎛
⎞
VOUT(PK)
VOUT(PK) +N• VTRANS
PK
PRSENSE
≥
⎜
⎟
IPK • VTRANS
2•(VOUT +N• VTRANS
3
⎝
⎠
IAVG
=
)
Additionally, there is approximately a 100ns propagation
delay from the time that peak current limit is detected to
when the gate transitions to the low state. This delay in-
The highest average diode current occurs at low output
voltages and decreases as the output voltage increases.
Reverse recovery time, reverse bias leakage and junc-
tion capacitance should also be considered. All affect
the overall charging efficiency. Excessive diode reverse
recovery times can cause appreciable discharging of the
output capacitor, thereby increasing charge time. Choose
a diode with a reverse recovery time of less than 100ns.
Diode leakage current under high reverse bias bleeds the
output capacitor of charge and increases charge time.
Choose a diode that has minimal reverse bias leakage
current. Diode junction capacitance is reflected back to
the primary, and energy is lost during the NMOS intrinsic
diode conduction. Choose a diode with minimal junction
capacitance. Table 3 recommends several output diodes
for various output voltages that have adequate reverse
recovery times.
creases the peak current limit by (V
)(100ns)/L
.
TRANS
PRI
Sense resistor inductance (L
) is another source of
RSENSE
current limit error. L
creates an input offset voltage
RSENSE
(V ) to the current comparator and causes the current
OS
comparator to trip early. V can be calculated as:
OS
⎛
⎞
LRSENSE
VOS = VTRANS
•
⎜
⎟
L
⎝
⎠
PRIMARY
ThechangeincurrentlimitbecomesV /R
.Theerror
OS SENSE
is more significant for applications using large di/dt ratios
in the transformer primary. It is recommended to use very
low inductance (< 2nH) sense resistors. Several resistors
can be placed in parallel to help reduce the inductance.
3751f
19
LT3751
APPLICATIONS INFORMATION
Care should also be taken in placement of the sense lines.
The negative return line, CSN, must be a dedicated trace
to the low side resistor terminal. Haphazardly routing the
CSN connection to the ground plane can cause inaccurate
current limit.
NMOS Snubber Design
The transformer leakage inductance causes a parasitic
voltage spike on the drain of the power NMOS switch dur-
ingtheturn-offtransition.Transformerleakageinductance
effects become more apparent at high peak primary cur-
rents. The worst-case magnitude of the voltage spike is
determinedbytheenergystoredintheleakageinductance
Under/Overvoltage Lockout
The LT3751 provides user-programmable under and
and the total capacitance on the V
node.
DRAIN
overvoltage lockouts for both V and V
. Use the
TRANS
CC
LLEAK •I2
CVDRAIN
equationsinthePinFunctionssectionforproperselection
of resistor values. When under/overvoltage lockout com-
parators are tripped, the master latch is disabled, power
delivery is halted, and the FAULT pin goes low. Adequate
supply bulk capacitors should be used to reduce power
supplyvoltageripplethatcouldcausefalsetrippingduring
normal switching operation.
PK
VD,LEAK
=
Two problems can arise from large V
. First, the
D,LEAK
magnitude of the spike may require an NMOS with an
unnecessarily high V which equates to a larger
(BR)DSS
. Secondly, the V
R
node will ring—possibly
DS(ON)
DRAIN
below ground—causing false tripping of the DCM com-
parator or damage to the NMOS switch (see Figure 12).
Both issues can be remedied using a snubber. If leakage
inductance causes issues, it is recommended to use a RC
snubber in parallel with the primary winding, as shown
The LT3751 provides internal zener clamping diodes to
protect itself in shutdown when V
is operated above
TRANS
55V. Supply voltages should only be applied to UVLO1,
UVLO2, OVLO1 and OVLO2 with series resistance such
thattheAbsoluteMaximumpincurrentsarenotexceeded.
Pin current can be calculated using:
in Figure 11. Size C
and R
based on the desired
SNUB
SNUB
leakage spike voltage, known leakage inductance, and an
RC time constant less than 1μs. Otherwise, the leakage
VAPPLIED − 55V
IPIN
=
voltage spike can cause false tripping of the V
parator and stop charging prematurely.
com-
OUT
RSERIES
Note that in shutdown, RV
, RV , R
, UVLO1,
TRANS
OUT DCM
UVLO2,OVLO1andOVLO2currentsincreasesignificantly
when operating V above the zener clamp voltages
TRANS
•
and are inversely proportional to the external series pin
L
PRI
R
SNUB
resistances.
•
C
SNUB
L
LEAK
C
VDRAIN
3751 F11
Figure 11. RC Snubber Circuit
3751f
20
LT3751
APPLICATIONS INFORMATION
R
, depending on output voltage and type used, may
FBH
V
DRAIN
require several smaller values placed in series. This will
reducetheriskofarcinganddamagetothefeedbackresis-
tors.Consultthemanufacturer’sratedvoltagespecification
for safe operation of the feedback resistors.
(WITHOUT
SNUBBER)
0V
NMOS DIODE
CONDUCTS
V
DRAIN
(WITH
SNUBBER)
The LT3751 has a minimum periodic refresh frequency
limitof23kHz.Thisdrasticallyreducesswitchingfrequency
components in the audio spectrum. The LT3751 can oper-
ate with no-load, but the regulation scheme switches to
overvoltage Burst Mode Operation and audible noise and
output voltage ripple increase. This can be avoided by
operating with a minimum load current.
0V
I
PRI
3751 F12
Figure 12. Effects of RC Snubber
Figure 12 shows the effect of the RC snubber resulting in
a lower voltage spike and faster settling time.
Minimum Load Current
Periodic refresh circuitry requires an average minimum
load current to avoid entering overvoltage burst mode.
Usually, the feedback resistors should be adequate to
provide this minimum load current.
LOW NOISE REGULATION
The LT3751 has the option to provide low noise regulated
output voltage when using a resistive voltage divider
from the output node to the FB pin. Refer to the Selecting
ComponentParameterssectiontodesignthetransformer,
NMOS power switch, output diode, and sense resistor.
Use the following equations to select the feedback resis-
tor values based on the power dissipation and desired
output voltage:
L
PRI •I2PK •23kHz
100 • VOUT
ILOAD(MIN)
≥
I
is the peak primary current at maximum power de-
PK
livery. The LT3751 will enter overvoltage burst mode if
the minimum load current is not met. Overvoltage burst
mode will prevent the application from entering a runaway
condition; however, the output voltage will increase 10%
over the nominal regulated voltage.
2
V
−1.22
PD
(
)
OUT
RFBH
=
=
; Top Feedback Resistor
⎛
⎞
1.22
−1.22
RFBL
•RFBH ; Bottom Feedback Resistor
⎜
⎟
V
⎝
⎠
OUT
3751f
21
LT3751
APPLICATIONS INFORMATION
Large Signal Stability
Small Signal Stability
Large signal stability can be an issue when audible noise
is a concern. Figure 13 shows that the problem originates
from the one-shot clock and the output voltage ripple. The
load must be constrained such that the output voltage
ripple does not exceed the regulation range of the error
amplifier within one clock period (approximately 6mV
referred to the FB pin).
The LT3751’s error amplifier is internally compensated to
increase its operating range but requires the converter’s
output node to be the dominant pole. Small signal stability
constraints become more prevalent during high-load-
ing conditions where the dominant output pole moves
to higher frequency and closer to the internal feedback
poles and zeros. The feedback loop requires the output
pole frequency to remain below 200Hz to guarantee small
The output capacitance should be increased if oscillations
occur or audible noise is present. Use Figure 14 to deter-
mine the maximum load for a given output capacitance to
maintain low audible noise operation. A small capacitor
can also be added from the FB pin to ground to lower the
ripple injected into FB pin.
signal stability. This allows smaller R
values then the
LOAD
large signal constraint. Thus, small signal issues should
not arise if the large signal constraint is met.
30
V
V
V
= 150V
= 300V
= 600V
OUT
OUT
OUT
25
20
15
10
5
LOAD
DROOP
V
OUT
I
PRI
26kHz
ONE-SHOT
CLK
0
0
50
100
150
200
OUTPUT POWER (W)
3751 F13
3751 F14
Figure 13. Voltage Ripple Stability Constraint
Figure 14. COUT(MIN) vs Output Power
3751f
22
LT3751
APPLICATIONS INFORMATION
Board Layout
4. Reduce the total node capacitance on the RV
and
OUT
R
pins by removing any ground or power planes
DCM
ThehighvoltageoperationoftheLT3751demandscarefulat-
tention to the board layout, observing the following points:
underneath the R
and R
pads and traces.
DCM
VOUT
Parasitic capacitance can cause unwanted behavior
on these pins.
1. Minimizetheareaofthehighvoltageendofthesecond-
ary winding.
5. Thermal vias should be added underneath the Exposed
Pad, Pin 21, to enhance the LT3751’s thermal perfor-
mance. These vias should go directly to a large area of
ground plane.
2. Provide sufficient spacing for all high voltage nodes
(NMOS drain, V
and secondary winding of the
OUT
transformer) in order to meet the breakdown voltage
requirements.
6. Isolated applications require galvanic separation of the
output-sidegroundandprimary-sideground.Adequate
spacing between both ground planes is needed to meet
voltage safety requirements.
3. KeeptheelectricalpathformedbyC
, theprimary
VTRANS
of T1, and the drain of the NMOS as short as possible.
Increasing the length of this path effectively increases
the leakage inductance of T1, potentially resulting in an
overvoltage condition on the drain of the NMOS.
3751f
23
LT3751
APPLICATIONS INFORMATION
Y
S E C O N D A R
P R I M A R
Y
3751f
24
LT3751
TYPICAL APPLICATIONS
42A Capacitor Charger
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
T1**
1:10
D1 D2***
V
V
OUT
500V
*M1, M2 REQUIRES PROPER
TRANS
12V TO 24V
HEATSINK/THERMAL DISSIPATION
C2
R6
C3
TO MEET MANUFACTURER’S SPECIFICATIONS
10μF
•
40.2k
1000μF
+
C4
1200μF
**THERMAL DISSIPATION OF T1 WILL LIMIT
THE CHARGE/DISCHARGE DUTY CYCLE OF C4
RV
CHARGE
CLAMP
TRANS
•
R7, 18.2k
R8, 40.2k
OFF ON
RDCM
***D2 MAY BE OMITTED FOR OUTPUT
VOLTAGE OPERATION BELOW 300V
V
CC
V
LT3751
CC
12V TO 24V
RV
C1
10μF
OUT
R11, 100k
DONE
R12, 100k
R1, 191k
HVGATE
LVGATE
CSP
M1, M2*
V
FAULT
UVLO1
OVLO1
UVLO2
CC
C1: 25V X5R OR X7R CERAMIC CAPACITOR
C2: 25V X5R OR X7R CERAMIC CAPACITOR
R5
2.5mꢁ
C3: 25V ELECTROLYTIC
V
TRANS
R2, 475k
R3, 191k
C4: HITACHI FX22L122Y 1200μF, 550V ELECTROLYTIC
D1, D2: VISHAY GURB5H60 600V, 5A ULTRAFAST RECTIFIER
M1, M2: 2 PARALLEL VISHAY SUD33N20-60P 200V, 33A NMOS
R1 THRU R4: USE 1% RESISTORS
CSN
FB
V
CC
R4, 475k
R6 THRU R8: USE 1% 0805 RESISTORS
R5: USE 2 PARALLEL 5mΩ IRC LR SERIES 2512 RESISTORS
T1: COILCRAFT GA-3460-BL 50A SURACE MOUNT TRANSFORMER
OVLO2
GND RBG
3751 TA02
R9
787Ω
FOR ANY V
VOLTAGE BETWEEN
OUT
50V AND 500V SELECT R9 ACCORDING TO:
ꢁ
ꢄ
40.2kꢀ
+ VDIODE
R9 = 0.98 •N•
ꢃ
ꢆ
V
ꢂ
ꢅ
OUT
Charging Efficiency
vs Output Voltage
Output Capacitor Charge Times
vs Capacitance
Charging Waveform
85
80
75
70
65
1200
800
400
0
V
V
V
V
V
V
V
V
= 500V, V
= 500V, V
= 300V, V
= 300V, V
= 100V,
= 24V
= 12V
= 24V
= 12V
OUT
OUT
OUT
OUT
TRANS
TRANS
TRANS
TRANS
V
V
= 500V
TRANS
C4 = 1200μF
OUT
= 24V
OUT
= 24V
TRANS
= 100V,
OUT
= 12V
TRANS
V
OUT
100V/DIV
AVERAGE
INPUT
CURRENT
5A/DIV
V
V
= 12V
= 24V
TRANS
TRANS
3751 TA02d
50
150
250
350
450
200
400
600
800
1000
1200
100ms/DIV
OUTPUT VOLTAGE (V)
OUTPUT CAPACITANCE (μF)
3751 TA02b
3751 TA02c
3751f
25
LT3751
TYPICAL APPLICATIONS
18A Non-Isolated, High-Voltage Regulator
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
T1
1:10
D1
V
V
OUT
TRANS
50V TO 500V
5V TO 24V
C2
C3
C5
0.47μF
R6
•
5× 2.2μF
680μF
40.2k
*M1 REQUIRES PROPER
+
C4***
100μF
HEATSINK/THERMAL DISSIPATION
•
TO MEET MANUFACTURER’S SPECIFICATIONS
RV
TRANS
R7, 18.2k
R8, 40.2k
OFF ON
CHARGE
CLAMP
RDCM
**DEPENDING ON DESIRED OUTPUT VOLTAGES,
R10 MUST BE SPLIT INTO MULTIPLE RESISTORS,
TO MEET MANUFACTURER’S VOLTAGE SPECIFICATION.
LT3751
V
CC
V
RV
OUT
CC
5V TO 24V
C1
10μF
***C4 MUST BE SIZED TO MEET LARGE SIGNAL
STABILITY CRITERIA DESCRIBED IN THE
APPLICATIONS INFORMATION SECTION
DONE
TO
MICRO
HVGATE
LVGATE
CSP
M1*
V
FAULT
UVLO1
OVLO1
UVLO2
OVLO2
CC
R1, 475k
R5
6mΩ
C1: 25V X5R OR X7R CERAMIC
C2: 25V X5R OR X7R CERAMIC
C3: 25V ELECTROLYTIC
V
TRANS
R2, 69.8k
R3, 475k
CSN
FB
R10**
R11
C5: TDK CKG57NX7R2J474M
D1: VISHAY US1M 1000V
V
CC
R4, 69.8k
M1: FAIRCHILD FQP34N20L
C6
10nF
R1 THRU R4, R6 THRU R9, R11: USE 1% 0805
R5: IRC LR SERIES 2512 RESISTORS
R10A, R10B, R10C USE: 200V 1206 RESISTORS
T1: COILCRAFT GA3459-AL
GND RBG
3751 TA04
R9
Steady-State Operation with
1.1mA Load Current
Suggested Component Values
V
(V)
R9 (kΩ)
3.32
R11(kΩ)
R10(kΩ)
30.9
124
OUT
V
OUT
100
200
300
400
0.383
0.768
1.13
AC COUPLED
2V/DIV
1.65
1.10
274
V
SW
50V/DIV
0.825
1.54
499
I
†
PRI
500
Tie to GND
1.74
715
10A/DIV
†
Transformer primary inductance limits V
comparator operation
OUT
3751 TA03b
to V
operating V
= 400V
. RV
and R should be tied to ground when
OUT BG
10μs/DIV
OUT
MAX
above 400V.
OUT
Regulation Efficiency
vs Load Current (VOUT = 500V)
Steady-State Operation with
100mA Load Current
VOUT vs Load Current
90
85
80
75
70
65
60
515
510
505
500
495
V
OUT
V
V
V
= 24V
= 12V
= 5V
TRANS
TRANS
TRANS
COUPLED
2V/DIV
V
SW
50V/DIV
I
PRI
10A/DIV
3751 TA03e
10μs/DIV
V
V
V
= 24V
= 12V
= 5V
TRANS
TRANS
TRANS
0
50
100
150
200
0
50
100
(mA)
150
200
OUTPUT VOLTAGE (V)
I
LOAD
3751 TA03c
3751 TA03d
3751f
26
LT3751
PACKAGE DESCRIPTION
UFD Package
20-Pin Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1711 Rev B)
0.70 0.05
2.65 0.05
4.50 0.05
3.10 0.05
1.50 REF
3.65 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
2.50 REF
4.10 0.05
5.50 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.20 OR
C = 0.35
0.75 0.05
1.50 REF
19
4.00 0.10
(2 SIDES)
R = 0.05 TYP
20
0.40 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 0.10
(2 SIDES)
2.50 REF
3.65 0.10
2.65 0.10
(UFD20) QFN 0506 REV B
0.25 0.05
0.50 BSC
0.200 REF
R = 0.115
TYP
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3751f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LT3751
TYPICAL APPLICATION
300V Regulated Power Supply
T1
D1
1:10
V
V
TRANS
24V
OUT
300V
C2
C3
R6
0mA TO 270mA
•
5× 2.2μF
+
680μF
40.2k
C4
20μF
•
RV
CHARGE
TRANS
R7
18.2k
OFF ON
RDCM
RV
CLAMP
OUT
V
CC
V
CC
24V
C1
10μF
R8
274k
M1
R5
HVGATE
LVGATE
CSP
DONE
FAULT
TO
V
MICRO
CC
R1
432k
UVLO1
OVLO1
UVLO2
OVLO2
6mꢁ
V
R2
TRANS
LT3751
475k
CSN
FB
R3
432k
C5
10nF
V
R4
475k
CC
R9
1.13k
GND RBG
3751 TA05
C1: 25V X5R OR X7R CERAMIC CAPACITOR
C2: 25V X5R OR X7R CERAMIC CAPACITOR
C3: 25V ELECTROLYTIC
C4: 330V RUBYCON PHOTOFLASH CAPACITOR
D1: VISHAY USIM 1000V
M1: FAIRCHILD FQP34N20L
R1 THROUGH R4: USE 1% 0805 RESISTORS
R5: USE TWO PARALLEL 5mΩ IRC LR SERIES 2512 RESISTORS
T1: SUMIDA PS07-299, 20A TRANSFORMER
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
V : 2.75V to 5.5V, Charges Two Supercapacitors in Series to 4.8V or 5.3V
LTC3225
150mA Supercapacitor Charger
IN
LT3420/LT3420-1
1.4A/1A, Photoflash Capacitor Charger
with Automatic Top-Off
Charges 220μF to 320V in 3.7 Seconds from 5V, V : 2.2V to 16V, I < 1μA,
IN SD
10-Lead MS Package
LT3468/LT3468-1
LT3468-2
1.4A, 1A, 0.7A, Photoflash Capacitor Charger V : 2.5V to 16V, Charge Time: 4.6 Seconds for LT3468 (0V to 320V, 100μF,
IN
V
= 3.6V), I < 1μA, ThinSOT™ Package
SD
IN
LT3484-0/LT3484-1
LT3484-2
1.4A, 0.7A, 1A Photoflash Capacitor Charger
V : 1.8V to 16V, Charge Time: 4.6 Seconds for LT3484-0 (0V to 320V, 100μF,
IN
IN
V
= 3.6V), I < 1μA, 2mm × 3mm 6-Lead DFN Package
SD
LT3485-0/LT3485-1
LT3485-2/LT3485-3
1.4A, 0.7A, 1A, 2A Photoflash Capacitor
Charger with Output Voltage Monitor and
Integrated IGBT
V : 1.8V to 10V, Charge Time: 3.7 Seconds for LT3485-0 (0V to 320V, 100μF,
IN
IN
V
= 3.6V), I < 1μA, 3mm × 3mm 10-Lead DFN Package
SD
LT3585-0/LT3585-1
LT3585-2/LT3585-3
1.2A, 0.55A, 0.85A, 1.7A Photoflash
Capacitor Charger with Adjustable Input
Current and IGBT Drivers
V : 1.5V to 16V, Charge Time: 3.3 Seconds for LT3585-3 (0V to 320V, 100μF,
IN
IN
V
= 3.6V), I < 1μA, 3mm × 2mm DFN-10 Package
SD
LT3750
Capacitor Charger Controller
V : 3V to 24V, Charge Time: 300ms for (0V to 300V, 100μF) MSOP-10 Package
IN
ThinSOT is a trademark of Linear Technology Corporation.
3751f
LT 1108 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
© LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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