LT3758AEMSE#TRPBF [Linear]
LT3758 - High Input Voltage, Boost, Flyback, SEPIC and Inverting Controller; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C;
| 型号： | LT3758AEMSE#TRPBF |
| 厂家： | 
Linear |
| 描述： | LT3758 - High Input Voltage, Boost, Flyback, SEPIC and Inverting Controller; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C 开关 光电二极管 |
| 文件： | 总38页 (文件大小：1362K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3758/LT3758A
High Input Voltage,
Boost, Flyback, SEPIC and
Inverting Controller
FEATURES
DESCRIPTION
The LT®3758/LT3758A are wide input range, current
mode, DC/DC controllers which are capable of generating
either positive or negative output voltages. They can be
configured as either a boost, flyback, SEPIC or inverting
converter. The LT3758/LT3758A drive a low side external
N-channel power MOSFET from an internal regulated 7.2V
supply. The fixed frequency, current-mode architecture
results in stable operation over a wide range of supply
and output voltages.
n
Wide Input Voltage Range: 5.5V to 100V
n
Positive or Negative Output Voltage Programming
with a Single Feedback Pin
n
Current Mode Control Provides Excellent Transient
Response
n
Programmable Operating Frequency (100kHz to
1MHz) with One External Resistor
n
Synchronizable to an External Clock
n
Low Shutdown Current < 1µA
n
Internal 7.2V Low Dropout Voltage Regulator
The operating frequency of LT3758/LT3758A can be set
with an external resistor over a 100kHz to 1MHz range,
and can be synchronized to an external clock using the
SYNC pin. A minimum operating supply voltage of 5.5V,
and a low shutdown quiescent current of less than 1µA,
make the LT3758/LT3758A ideally suited for battery-
powered systems.
n
Programmable Input Undervoltage Lockout with
Hysteresis
Programmable Soft-Start
Small 10-Lead DFN (3mm × 3mm) and
MSOPE Packages
n
n
APPLICATIONS
The LT3758/LT3758A feature soft-start and frequency
foldback functions to limit inductor current during start-
up and output short-circuit. The LT3758A has improved
load transient performance compared to the LT3758.
n
Automotive
n
Telecom
n
Industrial
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
12V Output Nonisolated Flyback Power Supply
D1
V
V
12V
1.2A
IN
OUT
36V TO
72V
0.022µF
100V
C
IN
6.2k
2.2µF
100V
X7R
1M
T1
1,2,3
(SERIES)
4,5,6
(PARALLEL)
V
IN
D
SN
SHDN/UVLO
44.2k
SW
LT3758
105k
1%
SYNC
GATE
M1
SENSE
RT
SS
FBX
63.4k
200kHz
V
GND INTV
CC
C
1N4148
5.1Ω
0.47µF
C
4.7µF
10V
VCC
10k
10nF
C
47µF
X5R
OUT
15.8k
1%
100pF
0.030Ω
X5R
3758 TA01
Rev F
1
Document Feedback
For more information www.analog.com
LT3758/LT3758A
ABSOLUTE MAXIMUM RATINGS (Note 1)
V , SHDN/UVLO (Note 7) ......................................100V
Operating Junction Temperature Range (Notes 2, 8)
LT3758E/LT3758AE........................... –40°C to 125°C
LT3758I/LT3758AI............................. –40°C to 125°C
LT3758H/LT3758AH .......................... –40°C to 150°C
LT3758MP/LT3758AMP..................... –55°C to 150°C
Storage Temperature Range
IN
INTV ....................................................V + 0.3V, 20V
CC
IN
GATE ........................................................ INTV + 0.3V
CC
SYNC ..........................................................................8V
V , SS.........................................................................3V
C
RT
1.5V
...............................................................................................
SENSE.................................................................... 0.3V
FBX ................................................................. –6V to 6V
DFN.................................................... –65°C to 125°C
MSOP ................................................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec) MSOP........300°C
PIN CONFIGURATION
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Rꢊ
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ꢂ
ꢃ
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ꢎ
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ꢆ
Fꢡꢘ
ꢔꢔ
SHDNꢟꢠꢃꢏꢁ
SHDNꢓꢔꢅꢕꢖ
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ꢡ ꢀꢄꢍꢢꢆꢣ θ ꢡ ꢃꢍꢢꢆꢓꢛ
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ꢖꢗꢈꢘ
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
LDNK
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3758EDD#PBF
LT3758EDD#TRPBF
LT3758IDD#TRPBF
LT3758EMSE#TRPBF
LT3758IMSE#TRPBF
LT3758HMSE#TRPBF
LT3758MPMSE#TRPBF
LT3758AEDD#TRPBF
LT3758AIDD#TRPBF
LT3758AEMSE#TRPBF
LT3758AIMSE#TRPBF
LT3758AHMSE#TRPBF
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic MSOP
10-Lead (3mm × 3mm) Plastic MSOP
10-Lead (3mm × 3mm) Plastic MSOP
10-Lead (3mm × 3mm) Plastic MSOP
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic MSOP
10-Lead (3mm × 3mm) Plastic MSOP
10-Lead (3mm × 3mm) Plastic MSOP
10-Lead (3mm × 3mm) Plastic MSOP
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–55°C to 150°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–55°C to 150°C
LT3758IDD#PBF
LDNK
LT3758EMSE#PBF
LT3758IMSE #PBF
LT3758HMSE#PBF
LT3758MPMSE #PBF
LT3758AEDD#PBF
LT3758AIDD#PBF
LT3758AEMSE#PBF
LT3758AIMSE#PBF
LT3758AHMSE#PBF
LT3758AMPMSE#PBF
LTDNM
LTDNM
LTDNM
LTDNM
LGGS
LGGS
LTGGK
LTGGK
LTGGK
LT3758AMPMSE#TRPBF LTGGK
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Rev F
2
For more information www.analog.com
LT3758/LT3758A
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 24V, SHDN/UVLO = 24V, SENSE = 0V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Operating Range
5.5
100
V
IN
IN
V
Shutdown I
SHDN/UVLO = 0V
SHDN/UVLO = 1.15V
0.1
1
6
µA
µA
Q
V
V
Operating I
V = 0.3V, R = 41.2k
1.75
350
110
–65
2.2
400
120
mA
µA
IN
Q
C
T
Operating I with Internal LDO Disabled
V = 0.3V, R = 41.2k, INTV = 7.5V
C T CC
IN
Q
l
SENSE Current Limit Threshold
SENSE Input Bias Current
Error Amplifier
100
mV
µA
Current Out of Pin
l
l
FBX Regulation Voltage (V
FBX Overvoltage Lockout
FBX Pin Input Current
)
FBX > 0V (Note 3)
FBX < 0V (Note 3)
1.569
1.6
1.631
V
V
FBX(REG)
–0.816 –0.800 –0.784
FBX > 0V (Note 4)
FBX < 0V (Note 4)
6
7
8
11
10
14
%
%
FBX = 1.6V (Note 3)
FBX = –0.8V (Note 3)
70
100
10
nA
nA
–10
Transconductance g (∆I /∆FBX)
(Note 3)
(Note 3)
230
5
µS
m
VC
V Output Impedance
C
MΩ
V
Line Regulation (∆V /[∆V • V
])
FBX > 0V, 5.5V < V < 100V (Notes 3, 6)
0.006
0.005
0.025
0.03
%/V
%/V
FBX
FBX
IN
FBX(REG)
IN
FBX < 0V, 5.5V < V < 100V (Notes 3, 6)
IN
V Current Mode Gain (∆V /∆V
)
5.5
V/V
µA
C
VC
SENSE
V Source Current
C
V = 1.5V
C
–15
V Sink Current
C
FBX = 1.7V
FBX = –0.85V
12
11
µA
µA
Oscillator
Switching Frequency
R = 41.2k to GND, FBX = 1.6V
270
300
100
330
0.4
kHz
kHz
kHz
T
R = 140k to GND, FBX = 1.6V
T
R = 10.5k to GND, FBX = 1.6V
1000
T
RT Voltage
FBX = 1.6V
1.2
220
220
V
ns
ns
Minimum Off-Time
Minimum On-Time
SYNC Input Low
SYNC Input High
SS Pull-Up Current
Low Dropout Regulator
1.5
SS = 0V, Current Out of Pin
–10
7.2
µA
V
l
INTV Regulation Voltage
7
7.4
4.7
CC
INTV Undervoltage Lockout Threshold
Falling INTV
4.3
4.5
0.5
V
V
CC
CC
UVLO Hysteresis
INTV Overvoltage Lockout Threshold
17.5
V
CC
INTV Current Limit
V
V
= 100V
= 20V
11
–1
16
50
22
mA
mA
CC
IN
IN
INTV Load Regulation (∆V
/V
)
0 < I
< 10mA, V = 8V
–0.4
0.005
500
%
%/V
mV
CC
INTVCC INTVCC
INTVCC
IN
INTV Line Regulation (∆V
/[∆V • V
]) 8V < V < 100V
0.02
CC
INTVCC
IN
INTVCC
IN
Dropout Voltage (V – V
)
V
IN
= 6V, I
= 10mA
INTVCC
IN
INTVCC
Rev F
3
For more information www.analog.com
LT3758/LT3758A
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 24V, SHDN/UVLO = 24V, SENSE = 0V, unless otherwise noted.
PARAMETER
INTV Current in Shutdown
CONDITIONS
SHDN/UVLO = 0V, INTV = 8V
MIN
TYP
MAX
UNITS
µA
16
CC
CC
INTV Voltage to Bypass Internal LDO
7.5
V
CC
Logic Inputs
l
SHDN/UVLO Threshold Voltage Falling
SHDN/UVLO Input Low Voltage
SHDN/UVLO Pin Bias Current Low
SHDN/UVLO Pin Bias Current High
Gate Driver
V
= INTV = 8V
1.17
1.7
1.22
1.27
0.4
V
V
IN
CC
I
Drops Below 1µA
VIN
SHDN/UVLO = 1.15V
SHDN/UVLO = 1.33V
2
2.5
µA
nA
10
100
t Gate Driver Output Rise Time
C = 3300pF (Note 5), INTV = 7.5V
22
20
ns
ns
V
r
L
CC
t Gate Driver Output Fall Time
f
C = 3300pF (Note 5), INTV = 7.5V
L CC
Gate Output Low (V
)
OL
0.05
Gate Output High (V
)
INTV
V
OH
CC
–0.05
Note 3: The LT3758/LT3758A are tested in a feedback loop which servos
to the reference voltages (1.6V and –0.8V) with the V pin forced
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
V
FBX
C
to 1.3V.
Note 4: FBX overvoltage lockout is measured at V
relative
FBX(OVERVOLTAGE)
Note 2: The LT3758E/LT3758AE are guaranteed to meet performance
specifications from the 0°C to 125°C junction temperature. Specifications
over the –40°C to 125°C operating junction temperature range are
assured by design, characterization and correlation with statistical process
controls. The LT3758I/LT3758AI are guaranteed over the full –40°C to
125°C operating junction temperature range. The LT3758H/LT3758AH are
guaranteed over the full –40°C to 150°C operating junction temperature
range. High junction temperatures degrade operating lifetimes. Operating
lifetime is derated at junction temperatures greater than 125°C. The
LT3758MP/LT3758AMP are 100% tested and guaranteed over the full
–55°C to 150°C operating junction temperature range.
to regulated V
.
FBX(REG)
Note 5: Rise and fall times are measured at 10% and 90% levels.
Note 6: SHDN/UVLO = 1.33V when V = 5.5V.
IN
Note 7: For V below 6V, the SHDN/UVLO pin must not exceed V .
IN
IN
Note 8: The LT3758/LT3758A include overtemperature protection that
is intended to protect the device during momentary overload conditions.
Junction temperature will exceed the maximum operating junction
temperature when overtemperature protection is active. Continuous
operation above the specified maximum operating junction temperature
may impair device reliability.
Rev F
4
For more information www.analog.com
LT3758/LT3758A
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
Positive Feedback Voltage
vs Temperature, VIN
Negative Feedback Voltage
vs Temperature, VIN
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ꢒꢖꢗꢘ
ꢒꢖꢗꢙ
ꢒꢖꢗꢓ
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ꢒꢓꢔꢕ
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ꢛꢜ
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ꢛꢜ
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ꢕ
ꢝ ꢏꢕ
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ꢝꢞ
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ꢝ ꢛꢜꢀꢕ ꢝ ꢌꢟꢌꢕ
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SHDNꢠꢅꢕꢑꢖ ꢝ ꢎꢟꢚꢚꢕ
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ꢚꢋꢌꢏ ꢐꢍꢎ
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Quiescent Current
vs Temperature, VIN
Dynamic Quiescent Current
vs Switching Frequency
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ꢅꢐꢘ
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ꢅꢐꢂ
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ꢐ
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ꢙꢁꢂꢘ ꢚꢃꢙ
ꢖꢘꢔꢛ ꢇꢐꢙ
Normalized Switching
Frequency vs FBX
RT vs Switching Frequency
ꢜꢙꢌ
ꢜꢌꢌ
ꢎꢌ
ꢛꢌ
ꢚꢌ
ꢙꢌ
ꢌ
1000
100
10
ꢋꢌꢍꢎ
ꢌ
ꢌꢍꢚ
ꢌꢍꢎ
ꢜꢍꢙ
ꢜꢍꢛ
ꢋꢌꢍꢚ
0
300 400 500 600 700 800 900 1000
100 200
Fꢀꢁ ꢂꢃꢄꢅꢆꢇꢈ ꢉꢂꢊ
SWITCHING FREQUENCY (kHz)
3758 G05
ꢝꢞꢟꢎ ꢇꢌꢛ
Rev F
5
For more information www.analog.com
LT3758/LT3758A
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
Switching Frequency
vs Temperature
SENSE Current Limit Threshold
vs Temperature
ꢅꢄꢃ
ꢅꢅꢂ
ꢅꢅꢃ
ꢅꢃꢂ
ꢅꢃꢃ
ꢜꢜꢃ
ꢜꢄꢃ
ꢜꢅꢃ
ꢜꢃꢃ
ꢄꢛꢃ
ꢄꢚꢃ
ꢄꢁꢃ
R
ꢝ ꢞꢅꢟꢄꢠ
ꢆ
ꢀꢁꢂ ꢀꢂꢃ ꢀꢄꢂ
ꢃ
ꢄꢂ ꢂꢃ ꢁꢂ ꢅꢃꢃ ꢅꢄꢂ ꢅꢂꢃ
ꢀꢁꢂ ꢀꢂꢃ ꢀꢄꢂ
ꢃ
ꢄꢂ ꢂꢃ ꢁꢂ ꢅꢃꢃ ꢅꢄꢂ ꢅꢂꢃ
ꢆꢇꢈꢉꢇRꢊꢆꢋRꢇ ꢌꢍꢎꢏ
ꢆꢇꢈꢉꢇRꢊꢆꢋRꢇ ꢌꢍꢎꢏ
ꢘꢁꢂꢙ ꢚꢃꢙ
ꢜꢁꢂꢚ ꢕꢃꢁ
SENSE Current Limit Threshold
vs Duty Cycle
SHDN/UVLO Threshold
vs Temperature
ꢅꢐꢄꢑ
ꢅꢐꢄꢘ
ꢅꢐꢄꢗ
ꢅꢐꢄꢄ
ꢅꢐꢄꢃ
ꢅꢐꢅꢑ
ꢓꢓꢌ
ꢓꢓꢊ
ꢓꢊꢌ
ꢓꢊꢊ
ꢋꢌ
SHDNꢒꢋꢓꢔꢕ Rꢚꢜꢚꢛꢖ
SHDNꢒꢋꢓꢔꢕ Fꢊꢔꢔꢚꢛꢖ
ꢊ
ꢔꢊ
ꢕꢊ
ꢗꢊ
ꢖꢊ
ꢓꢊꢊ
ꢀꢁꢂ ꢀꢂꢃ ꢀꢄꢂ
ꢃ
ꢄꢂ ꢂꢃ ꢁꢂ ꢅꢃꢃ ꢅꢄꢂ ꢅꢂꢃ
ꢀꢁꢂꢃ ꢄꢃꢄꢅꢆ ꢇꢈꢉ
ꢆꢇꢈꢉꢇRꢊꢆꢋRꢇ ꢌꢍꢎꢏ
ꢙꢁꢂꢑ ꢖꢅꢃ
ꢘꢙꢌꢖ ꢚꢊꢋ
SHDN/UVLO Hysteresis Current
vs Temperature
SHDN/UVLO Current vs Voltage
ꢄꢐꢙ
ꢄꢐꢄ
ꢄꢐꢃ
ꢅꢐꢘ
ꢅꢐꢑ
ꢓꢋ
ꢑꢋ
ꢕꢋ
ꢏꢋ
ꢔꢋ
ꢋ
ꢀꢁꢂ ꢀꢂꢃ ꢀꢄꢂ
ꢃ
ꢄꢂ ꢂꢃ ꢁꢂ ꢅꢃꢃ ꢅꢄꢂ ꢅꢂꢃ
ꢋ
ꢏꢋ
ꢑꢋ
ꢐꢋ
ꢒꢋ
ꢔꢋꢋ
ꢆꢇꢈꢉꢇRꢊꢆꢋRꢇ ꢌꢍꢎꢏ
SHDNꢀꢁꢂꢃꢄ ꢂꢄꢃꢅꢆꢇꢈ ꢉꢂꢊ
ꢚꢁꢂꢘ ꢛꢅꢄ
ꢕꢖꢓꢒ ꢇꢔꢔ
Rev F
6
For more information www.analog.com
LT3758/LT3758A
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
INTVCC Minimum Output
Current vs VIN
INTVCC vs Temperature
INTVCC Load Regulation
ꢁꢐꢕ
ꢁꢐꢔ
ꢁꢐꢄ
ꢁꢐꢅ
ꢁꢐꢃ
ꢐꢎꢓ
ꢐꢎꢒ
45
40
35
30
25
20
15
10
5
ꢀ ꢂ ꢃꢄꢅꢆꢇ
ꢁ
ꢃ
ꢘ ꢏꢃ
ꢀꢁ
ꢐꢎꢑ
ꢐ
ꢉꢊꢀꢈ ꢂ ꢑꢗꢎꢈ
ꢇꢇ
ꢍꢎꢕ
ꢍꢎꢏ
ꢉꢊꢀꢈ ꢂ ꢖꢈ
ꢇꢇ
0
1
10
100
ꢌ
ꢑꢌ
ꢑꢔ
ꢒꢌ
ꢒꢔ
ꢀꢁꢂ ꢀꢂꢃ ꢀꢄꢂ
ꢃ
ꢄꢂ ꢂꢃ ꢁꢂ ꢅꢃꢃ ꢅꢄꢂ ꢅꢂꢃ
ꢔ
ꢈ
ꢋꢈꢌ
ꢆꢇꢈꢉꢇRꢊꢆꢋRꢇ ꢌꢍꢎꢏ
ꢉꢊ
ꢀꢁꢂꢃ ꢅꢆꢇꢈ ꢉꢊꢇꢋ
ꢄꢄ
ꢔꢁꢂꢖ ꢗꢅꢔ
ꢍꢎꢄꢏ ꢐꢃꢑ
ꢓꢐꢔꢏ ꢖꢑꢔ
INTVCC Dropout Voltage
vs Current, Temperature
Gate Drive Rise
and Fall Time vs CL
INTVCC Line Regulation
ꢎꢏꢒꢅ
ꢎꢏꢐꢑ
ꢎꢏꢐꢅ
ꢎꢏꢓꢑ
ꢎꢏꢓꢅ
ꢅꢀꢀꢀ
ꢘꢀꢀ
ꢄꢀꢀ
ꢙꢀꢀ
ꢃꢀꢀ
ꢖꢀꢀ
ꢁꢀꢀ
ꢗꢀꢀ
ꢂꢀꢀ
ꢅꢀꢀ
ꢀ
ꢓꢅ
ꢍꢅ
ꢌꢅ
ꢋꢅ
ꢎꢅ
ꢏꢅ
ꢒꢅ
ꢑꢅ
ꢐꢅ
ꢅ
ꢉ
ꢜ ꢃꢉ
ꢇꢖꢆꢗ ꢘ ꢌꢙꢑꢗ
ꢀꢀ
ꢆꢇ
ꢅꢖꢀꢚꢊ
ꢅꢂꢖꢚꢊ
ꢙꢖꢚꢊ
ꢂꢖꢚꢊ
Rꢇꢕꢉ ꢆꢇꢈꢉ
Fꢚꢁꢁ ꢆꢇꢈꢉ
ꢀꢚꢊ
ꢛꢖꢖꢚꢊ
ꢅ
ꢓꢅ ꢐꢅ ꢒꢅ ꢔꢅ ꢑꢅ ꢕꢅ ꢎꢅ ꢖꢅ ꢍꢅ ꢓꢅꢅ
ꢃꢀꢄ
ꢅ
ꢎ
ꢐꢅ
ꢐꢎ
ꢂꢃFꢄ
ꢑꢅ
ꢑꢎ
ꢒꢅ
ꢀ
ꢂ
ꢁ
ꢃ
ꢄ
ꢅꢀ
ꢀ
ꢆꢇꢈꢉ ꢋꢌꢍꢎ ꢏꢐꢍꢑ
ꢀ
ꢁꢂ
ꢊꢊ
ꢁ
ꢒꢎꢑꢖ ꢋꢓꢕ
ꢗꢙꢖꢄ ꢔꢅꢙ
ꢒꢌꢎꢍ ꢔꢐꢍ
Gate Drive Rise
and Fall Time vs INTVCC
FBX Frequency Foldback
Waveforms During Overcurrent
Typical Start-Up Waveforms
ꢇꢍ
ꢌꢎ
ꢌꢍ
ꢏꢎ
ꢏꢍ
ꢎ
ꢄ
ꢖ ꢇꢇꢍꢍꢗF
ꢆ ꢞ ꢗꢓꢆ
ꢅꢐ
ꢇ
ꢘ ꢙꢕꢇ
ꢕ
ꢆꢗ
ꢇ
ꢈꢉꢊ
ꢋꢁꢇꢄꢅꢆꢇ
Rꢀꢘꢉ ꢂꢀꢈꢉ
ꢆ
ꢇ
ꢏꢕꢉ
ꢌꢍ
Fꢙꢕꢕ ꢂꢀꢈꢉ
ꢒꢘꢆꢃꢄꢅꢆ
ꢀꢁꢇꢄꢅꢆꢇ
ꢅ
ꢙ ꢅ
ꢎꢒꢍ ꢎꢒꢚ
ꢆ
ꢑ ꢆ
ꢎꢏꢐ ꢎꢏꢒ
ꢒꢍꢃꢄꢅꢆ
ꢋꢐꢄꢅꢆꢇ
ꢛꢔꢜꢓ ꢝꢀꢘ
ꢓꢔꢀꢕ ꢖꢋꢏ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆꢇ
ꢇꢈꢈ ꢉꢊꢋꢅꢌꢍꢎ ꢍꢋꢋꢎꢅꢌꢍꢉꢅꢏꢐꢑ ꢒꢓꢆ ꢉꢏ ꢔꢀꢆ ꢅꢐꢋꢕ ꢖ
ꢀꢗꢆ ꢏꢕꢉꢋꢕꢉ ꢇꢈꢋꢅꢌ ꢌꢏꢐꢆꢈRꢉꢈR
ꢌꢚꢚ ꢊꢛꢜꢆꢝꢐꢎ ꢐꢜꢜꢎꢆꢝꢐꢊꢆꢈꢗꢞ ꢏꢕꢇ ꢊꢈ ꢔꢋꢇ ꢆꢗꢜꢉ ꢟ
ꢋꢙꢇ ꢈꢉꢊꢜꢉꢊ ꢌꢚꢜꢆꢝ ꢝꢈꢗꢇꢚRꢊꢚR
ꢍ
ꢐ
ꢏꢌ
ꢏꢎ
ꢇ
ꢑ
ꢀꢁꢂꢃ ꢅꢃꢆ
ꢄꢄ
ꢇꢒꢎꢓ ꢔꢏꢐ
Rev F
7
For more information www.analog.com
LT3758/LT3758A
PIN FUNCTIONS
V (Pin 1): Error Amplifier Compensation Pin. Used to
GATE (Pin 7): N-Channel MOSFET Gate Driver Output.
Switches between INTV and GND. Driven to GND when
C
stabilize the voltage loop with an external RC network.
CC
IC is shut down, during thermal lockout or when INTV
CC
FBX (Pin 2): Positive and Negative Feedback Pin.
Receives the feedback voltage from the external resistor
divider across the output. Also modulates the switching
frequency during start-up and fault conditions when FBX
is close to GND.
is above or below the overvoltage or UV thresholds,
respectively.
INTV (Pin 8): Regulated Supply for Internal Loads and
CC
Gate Driver. Supplied from VIN and regulated to 7.2V (typi-
cal). INTV must be bypassed with a minimum of 4.7µF
CC
SS (Pin 3): Soft-Start Pin. This pin modulates compensa-
capacitor placed close to pin. INTV can be connected
CC
tion pin voltage (V ) clamp. The soft-start interval is set
C
directly to V , if V is less than 17.5V. INTV can also
IN
IN
CC
with an external capacitor. The pin has a 10µA (typical)
pull-up current source to an internal 2.5V rail. The soft-
start pin is reset to GND by an undervoltage condition
be connected to a power supply whose voltage is higher
than 7.5V, and lower than V , provided that supply does
IN
not exceed 17.5V.
at SHDN/UVLO, an INTV undervoltage or overvoltage
CC
condition or an internal thermal lockout.
SHDN/UVLO (Pin 9): Shutdown and Undervoltage Detect
Pin. An accurate 1.22V (nominal) falling threshold with
externally programmable hysteresis detects when power
is okay to enable switching. Rising hysteresis is generated
by the external resistor divider and an accurate internal
2µA pull-down current. An undervoltage condition resets
sort-start. Tie to 0.4V, or less, to disable the device and
RT (Pin 4): Switching Frequency Adjustment Pin. Set the
frequency using a resistor to GND. Do not leave this pin
open.
SYNC (Pin 5): Frequency Synchronization Pin. Used to
synchronize the switching frequency to an outside clock.
If this feature is used, an R resistor should be chosen
reduce V quiescent current below 1µA.
T
IN
to program a switching frequency 20% slower than the
SYNC pulse frequency. Tie the SYNC pin to GND if this
feature is not used. SYNC is bypassed when FBX is close
to GND.
V (Pin 10): Input Supply Pin. Must be locally bypassed
IN
with a 0.22µF, or larger, capacitor placed close to the pin.
Exposed Pad (Pin 11): Ground. This pin also serves as
the negative terminal of the current sense resistor. The
exposed pad must be soldered directly to the local ground
plane.
SENSE (Pin 6): The Current Sense Input for the Control
Loop. Kelvin connect this pin to the positive terminal of
the switch current sense resistor in the source of the
NFET. The negative terminal of the current sense resis-
tor should be connected to GND plane close to the IC.
Rev F
8
For more information www.analog.com
LT3758/LT3758A
BLOCK DIAGRAM
C
DC
L1
D1
V
IN
V
OUT
R4
R3
+
C
IN
L2
C
OUT1
C
R2
R1
OUT2
+
•
FBX
9
10
V
IN
SHDN/UVLO
A10
–
+
I
S1
2.5V
2µA
1.22V
2.5V
INTERNAL
REGULATOR
AND UVLO
I
S3
CURRENT
LIMIT
I
S2
17.5V
V
C
10µA
+
–
UVLO
A9
1
7.2V LDO
INTV
Q3
CC
C
VCC
C
C2
8
7
G4
G3
A8
R
C
+
–
C
C1
5V UP
A11
A12
1.72V
4.5V DOWN
–
+
TSD
165˚C
DRIVER
G6
SR1
V
C
–
+
GATE
–
+
G5
G2
A7
R
O
M1
–0.88V
S
Q2
PWM
COMPARATOR
110mV
–
+
1.6V
+
–
A6
A5
A1
SLOPE
RAMP
V
ISENSE
FBX
SENSE
FBX
2
6
+
–
+
–
A2
RAMP
R
SENSE
GND
–0.8V
GENERATOR
1.28V
–
+
11
A3
100kHz-1MHz
OSCILLATOR
G1
1.2V
+
FREQUENCY
FOLDBACK
+
A4
Q1
–
R5
8k
FREQ
PROG
D3
D2
SS
3
SYNC
RT
5
4
3758 F01
C
R
T
SS
Figure 1. LT3758 Block Diagram Working as a SEPIC Converter
Rev F
9
For more information www.analog.com
LT3758/LT3758A
APPLICATIONS INFORMATION
Main Control Loop
The LT3758 has overvoltage protection functions to pro-
tect the converter from excessive output voltage over-
shoot during start-up or recovery from a short-circuit
condition. An overvoltage comparator A11 (with 20mV
hysteresis) senses when the FBX pin voltage exceeds the
positive regulated voltage (1.6V) by 8% and provides a
reset pulse. Similarly, an overvoltage comparator A12
(with 10mV hysteresis) senses when the FBX pin voltage
exceeds the negative regulated voltage (–0.8V) by 11%
and provides a reset pulse. Both reset pulses are sent to
the main RS latch (SR1) through G6 and G5. The power
MOSFET switch M1 is actively held off for the duration of
an output overvoltage condition.
The LT3758 uses a fixed frequency, current mode con-
trol scheme to provide excellent line and load regulation.
Operation can be best understood by referring to the
Block Diagram in Figure 1.
The start of each oscillator cycle sets the SR latch (SR1)
and turns on the external power MOSFET switch M1
through driver G2. The switch current flows through the
external current sensing resistor R
and generates a
SENSE
voltage proportional to the switch current. This current
sense voltage VISENSE (amplified by A5) is added to a
stabilizing slope compensation ramp and the resulting
sum (SLOPE) is fed into the positive terminal of the PWM
comparator A7. When SLOPE exceeds the level at the
Programming Turn-On and Turn-Off Thresholds with
the SHDN/UVLO Pin
negative input of A7 (V pin), SR1 is reset, turning off the
C
power switch. The level at the negative input of A7 is set
by the error amplifier A1 (or A2) and is an amplified ver-
sion of the difference between the feedback voltage (FBX
pin) and the reference voltage (1.6V or –0.8V, depending
on the configuration). In this manner, the error ampli-
fier sets the correct peak switch current level to keep the
output in regulation.
The SHDN/UVLO pin controls whether the LT3758 is
enabled or is in shutdown state. A micropower 1.22V
reference, a comparator A10 and a controllable current
source IS1 allow the user to accurately program the supply
voltage at which the IC turns on and off. The falling value
can be accurately set by the resistor dividers R3 and R4.
When SHDN/UVLO is above 0.4V, and below the 1.22V
threshold, the small pull-down current source IS1 (typical
2µA) is active.
The LT3758 has a switch current limit function. The cur-
rent sense voltage is input to the current limit compara-
tor A6. If the SENSE pin voltage is higher than the sense
The purpose of this current is to allow the user to program
the rising hysteresis. The Block Diagram of the compara-
tor and the external resistors is shown in Figure 1. The
typical falling threshold voltage and rising threshold volt-
age can be calculated by the following equations:
current limit threshold V
(110mV, typical), A6
SENSE(MAX)
will reset SR1 and turn off M1 immediately.
The LT3758 is capable of generating either positive or
negative output voltage with a single FBX pin. It can be
configured as a boost, flyback or SEPIC converter to gen-
erate positive output voltage, or as an inverting converter
to generate negative output voltage. When configured as
a SEPIC converter, as shown in Figure 1, the FBX pin is
pulled up to the internal bias voltage of 1.6V by a volt-
(R3+R4)
V
V
= 1.22 •
VIN,FALLING
R4
= 2µA •R3+ V
VIN,RISING
IN,FALLING
For applications where the SHDN/UVLO pin is only used
as a logic input, the SHDN/UVLO pin can be connected
age divider (R1 and R2) connected from V
to GND.
OUT
Comparator A2 becomes inactive and comparator A1 per
-
directly to the input voltage V through a 1k resistor for
IN
forms the inverting amplification from FBX to V . When
C
always-on operation.
the LT3758 is in an inverting configuration, the FBX pin
is pulled down to –0.8V by a voltage divider connected
from V
to GND. Comparator A1 becomes inactive and
OUT
comparator A2 performs the noninverting amplification
from FBX to V .
C
Rev F
10
For more information www.analog.com
LT3758/LT3758A
APPLICATIONS INFORMATION
INTV Regulator Bypassing and Operation
Q = power MOSFET total gate charge
G
CC
An internal, low dropout (LDO) voltage regulator produces
The LT3758 uses packages with an Exposed Pad for
enhanced thermal conduction. With proper soldering to
the Exposed Pad on the underside of the package and a
full copper plane underneath the device, thermal resis-
the 7.2V INTV supply which powers the gate driver, as
CC
shown in Figure 1. The LT3758 contains an undervoltage
lockout comparator A8 and an overvoltage lockout com-
parator A9 for the INTVCC supply. The INTVCC undervoltage
(UV) threshold is 4.5V (typical), with 0.5V hysteresis, to
ensure that the MOSFETs have sufficient gate drive voltage
before turning on. The logic circuitry within the LT3758 is
tance (θ ) will be about 43°C/W for the DD package and
JA
40°C/W for the MSE package. For an ambient board tem-
perature of TA = 70°C and maximum junction temperature
of 125°C, the maximum I
(I
) of the DD
DRIVE DRIVE(MAX)
package can be calculated as:
also powered from the internal INTV supply.
CC
The INTVCC overvoltage threshold is set to be 17.5V
(typical) to protect the gate of the power MOSFET. When
(T − T )
1.28W
J
A
I
=
−I =
−1.6mA
current limit
DRIVE(MAX)
Q
(θ • V )
V
IN
JA
IN
INTV is below the UV threshold, or above the overvolt-
CC
The LT3758 has an internal INTV
I
CC DRIVE
age threshold, the GATE pin will be forced to GND and the
soft-start operation will be triggered.
function to protect the IC from excessive on-chip power
dissipation. The I
current limit decreases as the V
DRIVE
IN
IN
The INTV regulator must be bypassed to ground imme-
CC
increases (see the INTV Minimum Output Current vs V
graph in the Typical PerCfoCrmance Characteristics section).
diately adjacent to the IC pins with a minimum of 4.7µF
ceramic capacitor. Good bypassing is necessary to sup-
ply the high transient currents required by the MOSFET
gate driver.
If I
reaches the current limit, INTV voltage will fall
and may trigger the soft-start.
DRIVE
CC
Based on the preceding equation and the INTVCC Minimum
In an actual application, most of the IC supply current is
used to drive the gate capacitance of the power MOSFET.
The on-chip power dissipation can be a significant con-
cern when a large power MOSFET is being driven at a
Output Current vs V graph, the user can calculate the
IN
maximum MOSFET gate charge the LT3758 can drive at
a given V and switch frequency. A plot of the maximum
IN
Q vs V at different frequencies to guarantee a minimum
4.7V INITNV is shown in Figure 2.
G
high frequency and the V voltage is high. It is impor-
IN
CC
tant to limit the power dissipation through selection of
MOSFET and/or operating frequency so the LT3758 does
not exceed its maximum junction temperature rating. The
140
ꢋꢊꢊꢐꢑꢒ
120
junction temperature T can be estimated using the fol-
J
100
80
lowing equations:
T = T + P • θ
JA
J
A
IC
60
T = ambient temperature
A
ꢅꢓꢑꢒ
40
20
0
θ
= junction-to-ambient thermal resistance
JA
P = IC power consumption
IC
ꢅꢊ
ꢃꢀꢄ
ꢅꢊꢊ
ꢅ
= V • (I + I )
DRIVE
IN
Q
ꢀ
ꢁꢂ
ꢋꢌꢍꢎ Fꢊꢏ
I = V operation I = 1.6mA
Q
IN
Q
Figure 2. Recommended Maximum QG vs VIN at Different
Frequencies to Ensure INTVCC Higher Than 4.7V
I
= average gate drive current = f • Q
G
DRIVE
f = switching frequency
Rev F
11
For more information www.analog.com
LT3758/LT3758A
APPLICATIONS INFORMATION
As illustrated in Figure 2, a trade-off between the operat-
ing frequency and the size of the power MOSFET may be
needed in order to maintain a reliable IC junction tempera-
ture. Prior to lowering the operating frequency, however,
be sure to check with power MOSFET manufacturers for
A resistor R
can be connected, as shown in Figure 3, to
VCC
limit the inrush current from VOUT. Regardless of whether
or not the INTV pin is connected to an external voltage
CC
source, it is always necessary to have the driver circuitry
bypassed with a 4.7µF low ESR ceramic capacitor to
their most recent low Q , low R
devices. Power
ground immediately adjacent to the INTV and GND pins.
MOSFET manufacturingGtechnolDoSg(iOeNs) are continually
improving, with newer and better performance devices
being introduced almost yearly.
CC
Operating Frequency and Synchronization
The choice of operating frequency may be determined
by on-chip power dissipation, otherwise it is a trade-off
between efficiency and component size. Low frequency
operation improves efficiency by reducing gate drive cur-
rent and MOSFET and diode switching losses. However,
lower frequency operation requires a physically larger
inductor. Switching frequency also has implications
for loop compensation. The LT3758 uses a constant-
frequency architecture that can be programmed over a
100kHz to 1000kHz range with a single external resistor
from the RT pin to ground, as shown in Figure 1. The
RT pin must have an external resistor to GND for proper
operation of the LT3758. A table for selecting the value
An effective approach to reduce the power consumption
of the internal LDO for gate drive is to tie the INTV pin
CC
to an external voltage source high enough to turn off the
internal LDO regulator.
If the input voltage VIN does not exceed the absolute maxi-
mum rating of both the power MOSFET gate-source volt-
age (V ) and the INTV overvoltage lockout threshold
GS
CC
voltage (17.5V), the INTV pin can be shorted directly
CC
to the V pin. In this condition, the internal LDO will be
IN
turned off and the gate driver will be powered directly
from the input voltage VIN. With the INTVCC pin shorted to
V , however, a small current (around 16µA) will load the
IN
of R for a given operating frequency is shown in Table 1.
T
INTV in shutdown mode. For applications that require
CC
Table 1. Timing Resistor (RT) Value
the lowest shutdown mode input supply current, do not
connect the INTV pin to V .
SWITCHING FREQUENCY (kHz)
R (kΩ)
T
CC
IN
100
200
300
400
500
600
700
800
900
1000
140
63.4
41.2
30.9
24.3
19.6
16.5
14
In SEPIC or flyback applications, the INTV pin can be
CC
connected to the output voltage V
through a blocking
OUT
diode, as shown in Figure 3, if V
conditions:
meets the following
OUT
1. V
2. V
3. V
< V (pin voltage)
OUT
OUT
OUT
IN
< 17.5V
< maximum V rating of power MOSFET
GS
12.1
10.5
ꢑꢈꢉꢄꢊꢋ
ꢍꢎꢈꢁ
ꢐ
ꢁꢀꢀ
R
ꢁꢀꢀ
ꢁ
ꢆꢇꢈ
ꢀꢀ
The operating frequency of the LT3758 can be synchronized
to an external clock source. By providing a digital clock
signal into the SYNC pin, the LT3758 will operate at the
SYNC clock frequency. If this feature is used, an R resistor
should be chosen to program a switching frequeTncy 20%
slower than SYNC pulse frequency. It is recommended the
SYNC pulse have a minimum pulse width of 200ns. Tie the
SYNC pin to GND if this feature is not used.
ꢀ
ꢁꢀꢀ
ꢂꢃꢄꢅF
ꢏꢎꢐ
ꢉꢄꢊꢋ Fꢌꢉ
Figure 3. Connecting INTVCC to VOUT
Rev F
12
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LT3758/LT3758A
APPLICATIONS INFORMATION
Duty Cycle Consideration
Soft-Start
Switching duty cycle is a key variable defining con-
verter operation. As such, its limits must be considered.
Minimum on-time is the smallest time duration that the
LT3758 is capable of turning on the power MOSFET. This
time is generally about 220ns (typical) (see Minimum
On-Time in the Electrical Characteristics table). In each
switching cycle, the LT3758 keeps the power switch off
for at least 220ns (typical) (see Minimum Off-Time in the
Electrical Characteristics table).
The LT3758 contains several features to limit peak switch
currents and output voltage (VOUT) overshoot during
start-up or recovery from a fault condition. The primary
purpose of these features is to prevent damage to external
components or the load.
High peak switch currents during start-up may occur
in switching regulators. Since V
is far from its final
value, the feedback loop is satuOraUtTed and the regulator
tries to charge the output capacitor as quickly as possible,
resulting in large peak currents. A large surge current may
cause inductor saturation or power switch failure.
The minimum on-time and minimum off-time and the
switching frequency define the minimum and maximum
switching duty cycles a converter is able to generate:
The LT3758 addresses this mechanism with the SS pin.
As shown in Figure 1, the SS pin reduces the power
MOSFET current by pulling down the VC pin through
Q2. In this way the SS allows the output capacitor to
charge gradually toward its final value while limiting the
start-up peak currents. The typical start-up waveforms are
shown in the Typical Performance Characteristics section.
Minimum duty cycle = minimum on-time • frequency
Maximum duty cycle = 1 – (minimum off-time • frequency)
Programming the Output Voltage
The output voltage V
is set by a resistor divider, as
OUT
shown in Figure 1. The positive and negative V
are set
OUT
The inductor current I slewing rate is limited by the soft-
L
by the following equations:
start function.
⎛
⎞
⎟
⎠
R2
R1
Besides start-up (with SHDN/UVLO), soft-start can also
V
V
= 1.6V • 1+
⎜
OUT,POSITIVE
⎝
⎛
be triggered by the following faults:
⎞
⎟
⎠
R2
R1
1. INTV > 17.5V
CC
= –0.8V • 1+
⎜
OUT,NEGATIVE
⎝
2. INTV < 4.5V
CC
The resistors R1 and R2 are typically chosen so that
the error caused by the current flowing into the FBX pin
during normal operation is less than 1% (this translates
to a maximum value of R1 at about 158k).
3. Thermal lockout
Any of these three faults will cause the LT3758 to stop
switching immediately. The SS pin will be discharged by
Q3. When all faults are cleared and the SS pin has been
discharged below 0.2V, a 10µA current source I starts
charging the SS pin, initiating a soft-start operation.
In the applications where V
is pulled up by an exter-
OUT
S2
nal positive power supply, the FBX pin is also pulled up
through the R2 and R1 network. Make sure the FBX does
not exceed its absolute maximum rating (6V). The R5, D2,
and D3 in Figure 1 provide a resistive clamp in the positive
direction. To ensure FBX is lower than 6V, choose suf-
ficiently large R1 and R2 to meet the following condition:
The soft-start interval is set by the soft-start capacitor
selection according to the equation:
1.25V
T
= C
•
SS
SS
10µA
⎛
⎞
⎟
⎠
R2
R1
R2
6V • 1+
+ 3.5V •
> V
OUT(MAX)
⎜
⎝
8kΩ
where V
is the maximum V
that is pulled up
OUT(MAX)
by an external power supply.
OUT
Rev F
13
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LT3758/LT3758A
APPLICATIONS INFORMATION
FBX Frequency Foldback
load transient response, when compared to the LT3758.
New internal circuits ensure that the transient from not
switching to switching at high current can be made in
a few cycles. The optimum values depend on the con-
verter topology, the component values and the operat-
ing conditions (including the input voltage, load current,
etc.). To compensate the feedback loop of the LT3758/
LT3758A, a series resistor-capacitor network is usually
When VOUT is very low during start-up or a GND fault
on the output, the switching regulator must operate at
low duty cycles to maintain the power switch current
within the current limit range, since the inductor cur-
rent decay rate is very low during switch off time. The
minimum on-time limitation may prevent the switcher
from attaining a sufficiently low duty cycle at the pro-
grammed switching frequency. So, the switch current
will keep increasing through each switch cycle, exceed-
ing the programmed current limit. To prevent the switch
peak currents from exceeding the programmed value, the
LT3758 contains a frequency foldback function to reduce
the switching frequency when the FBX voltage is low (see
the Normalized Switching Frequency vs FBX graph in the
Typical Performance Characteristics section).
connected from the V pin to GND. Figure 1 shows the
C
typical V compensation network. For most applications,
C
the capacitor should be in the range of 470pF to 22nF,
and the resistor should be in the range of 5k to 50k. A
small capacitor is often connected in parallel with the RC
compensation network to attenuate the V voltage ripple
C
induced from the output voltage ripple through the inter-
nal error amplifier. The parallel capacitor usually ranges in
value from 10pF to 100pF. A practical approach to design
the compensation network is to start with one of the cir-
cuits in this data sheet that is similar to your applica-
tion, and tune the compensation network to optimize the
performance. Stability should then be checked across all
operating conditions, including load current, input voltage
and temperature.
During frequency foldback, external clock synchroniza
tion is disabled to prevent interference with frequency
reducing operation.
-
Thermal Lockout
If LT3758 die temperature reaches 165°C (typical), the
part will go into thermal lockout. The power switch will
be turned off. A soft-start operation will be triggered. The
part will be enabled again when the die temperature has
dropped by 5°C (nominal).
SENSE Pin Programming
For control and protection, the LT3758 measures the
power MOSFET current by using a sense resistor (RSENSE
)
between GND and the MOSFET source. Figure 4 shows a
typical waveform of the sense voltage (V ) across the
Loop Compensation
SENSE
sense resistor. It is important to use Kelvin traces between
Loop compensation determines the stability and transient
performance. The LT3758/LT3758A use current mode
control to regulate the output which simplifies loop com-
pensation. The LT3758A improves the no-load to heavy
the SENSE pin and R
, and to place the IC GND as
SENSE
close as possible to the GND terminal of the R
proper operation.
for
SENSE
ꢆ
ꢇꢈꢉꢇꢈ
∆ꢆ
ꢆ
ꢇꢈꢉꢇꢈ ꢏ χ • ꢇꢈꢉꢇꢈꢊꢐꢌꢑꢎ
ꢆ
ꢆ
ꢇꢈꢉꢇꢈꢊꢋꢈꢌꢍꢎ
ꢇꢈꢉꢇꢈꢊꢐꢌꢑꢎ
ꢒ
ꢓꢔ
ꢇ
ꢔ
ꢇ
ꢀꢁꢂꢃ Fꢄꢅ
Figure 4. The Sense Voltage During a Switching Cycle
Rev F
14
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LT3758/LT3758A
APPLICATIONS INFORMATION
Due to the current limit function of the SENSE pin,
APPLICATION CIRCUITS
R
SENSE should be selected to guarantee that the peak
The LT3758 can be configured as different topologies. The
first topology to be analyzed will be the boost converter,
followed by the flyback, SEPIC and inverting converters.
current sense voltage VSENSE(PEAK) during steady state
normal operation is lower than the SENSE current limit
threshold (see the Electrical Characteristics table). Given
a 20% margin, VSENSE(PEAK) is set to be 80mV. Then,
the maximum switch ripple current percentage can be
calculated using the following equation:
Boost Converter: Switch Duty Cycle and Frequency
The LT3758 can be configured as a boost converter for
the applications where the converter output voltage is
higher than the input voltage. Remember that boost con-
verters are not short-circuit protected. Under a shorted
output condition, the inductor current is limited only by
the input supply capability. For applications requiring a
step-up converter that is short-circuit protected, please
refer to the Applications Information section covering
SEPIC converters.
ΔV
SENSE
80mV −0.5 • ΔV
c =
SENSE
c
is used in subsequent design examples to calculate
inductor value. ∆VSENSE is the ripple voltage across
SENSE
R
.
The LT3758 switching controller incorporates 100ns
timing interval to blank the ringing on the current sense
signal immediately after M1 is turned on. This ringing is
caused by the parasitic inductance and capacitance of the
PCB trace, the sense resistor, the diode, and the MOSFET.
The 100ns timing interval is adequate for most of the
LT3758 applications. In the applications that have very
large and long ringing on the current sense signal, a small
RC filter can be added to filter out the excess ringing.
Figure 5 shows the RC filter on the SENSE pin. It is usually
The conversion ratio as a function of duty cycle is:
V
1
OUT
=
V
1−D
IN
in continuous conduction mode (CCM).
For a boost converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
voltage (V ) and the input voltage (V ). The maximum
OUT
IN
sufficient to choose 22Ω for R and 2.2nF to 10nF for
FLT
duty cycle (DMAX) occurs when the converter has the
C
FLT
. Keep R ’s resistance low. Remember that there is
FLT
minimum input voltage:
65µA (typical) flowing out of the SENSE pin. Adding R
will affect the SENSE current limit threshold:
FLT
V
− V
IN(MIN)
OUT
D
=
MAX
V
OUT
V
= 110mV – 65µA • R
SENSE_ILIM
FLT
Discontinuous conduction mode (DCM) provides higher
conversion ratios at a given frequency at the cost of
reduced efficiencies and higher switching currents.
ꢋ
ꢌ
ꢍꢎꢂꢉ
ꢁꢂꢃꢄꢅꢆ
R
Boost Converter: Inductor and Sense Resistor Selection
Fꢁꢂ
ꢈꢉꢊꢈꢉ
For the boost topology, the maximum average inductor
current is:
ꢍꢊꢏ
ꢀ
Fꢁꢂ
R
ꢈꢉꢊꢈꢉ
1
ꢃꢄꢅꢆ Fꢇꢅ
I
= I
•
O(MAX)
L(MAX)
1−D
MAX
Figure 5. The RC Filter on the SENSE Pin
Then, the ripple current can be calculated by:
1
ΔI = c •I
= c •I
L(MAX)
•
O(MAX)
L
1−D
MAX
Rev F
15
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LT3758/LT3758A
APPLICATIONS INFORMATION
c
The constant in the preceding equation represents the
(V
), the on-resistance (R
), the gate to source
DS(ON)
GS(TH)
percentage peak-to-peak ripple current in the inductor,
and gate to drain charges (Q and Q ), the maximum
GD
relative to I
.
drain current (ID(MAX)) anGdS the MOSFET’s thermal
resistances (R and R ).
L(MAX)
θJC
θJA
The inductor ripple current has a direct effect on the
choice of the inductor value. Choosing smaller values of
The power MOSFET will see full output voltage, plus a
diode forward voltage, and any additional ringing across
its drain-to-source during its off-time. It is recommended
∆I requires large inductances and reduces the current
L
loop gain (the converter will approach voltage mode).
Accepting larger values of ∆IL provides fast transient
response and allows the use of low inductances, but
results in higher input current ripple, greater core
losses, and in some cases, subharmonic oscillation. A
to choose a MOSFET whose B
is higher than V
by
VDSS
OUT
a safety margin (a 10V safety margin is usually sufficient).
The power dissipated by the MOSFET in a boost converter is:
PFET = I2L(MAX) • RDS(ON) • DMAX + 2 • V2OUT • IL(MAX)
c
good starting point for is 0.2 and careful evaluation
• C
• f/1A
of system stability should be made to ensure adequate
design margin.
RSS
The first term in the preceding equation represents the
conduction losses in the device, and the second term, the
switching loss. C
which is usually specified in the MOSFET characteristics.
Given an operating input voltage range, and having cho-
sen the operating frequency and ripple current in the
inductor, the inductor value of the boost converter can
be determined using the following equation:
is the reverse transfer capacitance,
RSS
For maximum efficiency, RDS(ON) and CRSS should be
minimized. From a known power dissipated in the power
MOSFET, its junction temperature can be obtained using
the following equation:
V
IN(MIN)
L =
•D
MAX
ΔI • f
L
The peak and RMS inductor current are:
T = T + P • θ = T + P • (θ + θ )
J
A
FET
JA
A
FET
JC
CA
⎛
⎞
⎟
⎠
c
TJ must not exceed the MOSFET maximum junction
temperature rating. It is recommended to measure the
MOSFET temperature in steady state to ensure that abso-
lute maximum ratings are not exceeded.
I
I
= I
• 1+
⎜
L(PEAK) L(MAX)
⎝
2
2
c
=I
• 1+
L(MAX)
L(RMS)
12
Boost Converter: Output Diode Selection
Based on these equations, the user should choose the
inductors having sufficient saturation and RMS current
ratings.
To maximize efficiency, a fast switching diode with low
forward drop and low reverse leakage is desirable. The
peak reverse voltage that the diode must withstand is
equal to the regulator output voltage plus any additional
ringing across its anode-to-cathode during the on-time.
The average forward current in normal operation is equal
to the output current, and the peak current is equal to:
Set the sense voltage at I
to be the minimum of the
L(PEAK)
SENSE current limit threshold with a 20% margin. The
sense resistor value can then be calculated to be:
80mV
R
=
SENSE
I
L(PEAK)
⎛
⎞
⎟
⎠
c
I
=I
= 1+
•I
L(MAX)
⎜
D(PEAK) L(PEAK)
⎝
2
Boost Converter: Power MOSFET Selection
It is recommended that the peak repetitive reverse voltage
rating V is higher than V by a safety margin (a 10V
Important parameters for the power MOSFET include the
drain-source voltage rating (V ), the threshold voltage
RRM
OUT
DS
safety margin is usually sufficient).
Rev F
16
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LT3758/LT3758A
APPLICATIONS INFORMATION
The power dissipated by the diode is:
For the bulk C component, which also contributes 1% to
the total ripple:
P = I
D
• V
D
O(MAX)
I
O(MAX)
and the diode junction temperature is:
T = T + P • R
C
≥
OUT
0.01• V
• f
OUT
J
A
D
θJA
The output capacitor in a boost regulator experiences
high RMS ripple currents, as shown in Figure 6. The RMS
ripple current rating of the output capacitor can be deter-
mined using the following equation:
The R to be used in this equation normally includes the
θJC
R
fθoJrAthe device plus the thermal resistance from the
board to the ambient temperature in the enclosure. T must
J
not exceed the diode maximum junction temperature rating.
D
MAX
I
≥I
•
Boost Converter: Output Capacitor Selection
RMS(COUT) O(MAX)
1−D
MAX
Contributions of ESR (equivalent series resistance), ESL
(equivalent series inductance) and the bulk capacitance
Multiple capacitors are often paralleled to meet ESR
requirements. Typically, once the ESR requirement is sat-
isfied, the capacitance is adequate for filtering and has the
required RMS current rating. Additional ceramic capaci-
tors in parallel are commonly used to reduce the effect of
parasitic inductance in the output capacitor, which reduces
high frequency switching noise on the converter output.
ꢈ
ꢈ
ꢁFF
ꢁꢉ
∆ꢀ
ꢆꢁꢂꢃ
ꢀ
ꢁꢂꢃ
ꢄꢅꢆꢇ
Rꢌꢉꢍꢌꢉꢍ ꢎꢂꢊ ꢃꢁ
ꢃꢁꢃꢅꢏ ꢌꢉꢎꢂꢆꢃꢅꢉꢆꢊ
ꢄꢐꢁꢅRꢎ ꢑ ꢆꢅꢒꢇ
∆ꢀ
ꢊꢋR
ꢓꢔꢕꢖ Fꢗꢘ
Boost Converter: Input Capacitor Selection
Figure 6. The Output Ripple Waveform of a Boost Converter
The input capacitor of a boost converter is less critical
than the output capacitor, due to the fact that the inductor
is in series with the input, and the input current wave-
form is continuous. The input voltage source impedance
determines the size of the input capacitor, which is typi-
cally in the range of 10µF to 100µF. A low ESR capacitor
is recommended, although it is not as critical as for the
output capacitor.
must be considered when choosing the correct output
capacitors for a given output ripple voltage. The effect of
these three parameters (ESR, ESL and bulk C) on the out-
put voltage ripple waveform for a typical boost converter
is illustrated in Figure 6.
The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
The RMS input capacitor ripple current for a boost con-
verter is:
between the ESR step ∆V
and the charging/discharg-
ESR
ing ∆V
. For the purpose of simplicity, we will choose
COUT
I
= 0.3 • ∆I
L
RMS(CIN)
2% for the maximum output ripple, to be divided equally
between ∆V and ∆V . This percentage ripple will
ESR
COUT
change, depending on the requirements of the applica-
tion, and the following equations can easily be modified.
For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor can be determined using the fol-
lowing equation:
FLYBACK CONVERTER APPLICATIONS
The LT3758 can be configured as a flyback converter for
the applications where the converters have multiple out-
puts, high output voltages or isolated outputs. Figure 7
shows a simplified flyback converter.
0.01• V
I
OUT
The flyback converter has a very low parts count for mul-
tiple outputs, and with prudent selection of turns ratio,
can have high output/input voltage conversion ratios with
ESR
≤
COUT
D(PEAK)
Rev F
17
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LT3758/LT3758A
APPLICATIONS INFORMATION
a desirable duty cycle. However, it has low efficiency due
to the high peak currents, high peak voltages and con-
sequent power loss. The flyback converter is commonly
used for an output power of less than 50W.
ꢈ
ꢉꢆ
ꢅ
ꢆꢇ
The flyback converter can be designed to operate either
in continuous or discontinuous mode. Compared to con-
tinuous mode, discontinuous mode has the advantage of
smaller transformer inductances and easy loop compen-
sation, and the disadvantage of higher peak-to-average
current and lower efficiency.
ꢅ
ꢆꢇꢍꢎꢏꢐꢑ
ꢅ
ꢉ
ꢅ
ꢉꢍꢎꢏꢐꢑ
ꢉꢋ
ꢀꢊꢋꢋꢁꢀꢌꢁꢉ
Rꢇꢉ ꢀꢂꢊꢍꢍꢁR
ꢉꢌꢋ
ꢉꢀꢋ
ꢆ
ꢊ
ꢆ
ꢆ
ꢉ
ꢂ ꢄꢂ
ꢃ
ꢀ
ꢋ
ꢅ
ꢆ
ꢆꢂ
ꢀꢁꢂꢃ Fꢄꢃ
ꢖ
ꢖ
ꢗ
ꢖ
ꢅꢀꢖꢂ
ꢘꢊꢌ
ꢇ
ꢆ
ꢉ
ꢇ
R
ꢀꢂ
ꢆꢂ
ꢀꢂ
Figure 8. Waveforms of the Flyback Converter
in Discontinuous Mode Operation
ꢇ
ꢈ
ꢈ
ꢀ
ꢃ
ꢗ
ꢉ
ꢀꢂ
According to the preceding equations, the user has rela-
tive freedom in selecting the switch duty cycle or turns
ratio to suit a given application. The selections of the
duty cycle and the turns ratio are somewhat iterative pro-
cesses, due to the number of variables involved. The user
can choose either a duty cycle or a turns ratio as the start
point. The following trade-offs should be considered when
selecting the switch duty cycle or turns ratio, to optimize
the converter performance. A higher duty cycle affects the
flyback converter in the following aspects:
ꢆ
ꢀꢎ
ꢈꢌꢏꢐꢑꢒ
ꢋꢔꢌꢁ
ꢖ
ꢕ
ꢅ
ꢗꢉꢀ
ꢀꢁꢂꢀꢁ
R
ꢀꢁꢂꢀꢁ
ꢋꢂꢉ
ꢏꢐꢑꢒ Fꢓꢐ
Figure 7. A Simplified Flyback Converter
Flyback Converter: Switch Duty Cycle and Turns Ratio
•
Lower MOSFET RMS current I
, but higher
SW(RMS)
The flyback converter conversion ratio in the continuous
mode operation is:
MOSFET V peak voltage
DS
•
Lower diode peak reverse voltage, but higher diode
RMS current I
V
N
N
D
OUT
S
P
=
•
D(RMS)
V
1−D
IN
•
Higher transformer turns ratio (N /N )
P S
Where N /N is the second to primary turns ratio.
S
P
The choice,
Figure 8 shows the waveforms of the flyback converter
in discontinuous mode operation. During each switching
D
1
3
=
D+D2
period T , three subintervals occur: DT , D2T , D3T .
S
S
During DTS, M is on, and D is reverse-SbiasedS. During
(for discontinuous mode operation with a given D3) gives
the power MOSFET the lowest power stress (the product
of RMS current and peak voltage). The choice,
D2T , M is off, and L is conducting current. Both L and
S
S
P
L currents are zero during D3T .
S
S
The flyback converter conversion ratio in the discontinu-
ous mode operation is:
D
2
3
=
D+D2
(for discontinuous mode operation with a given D3)
gives the diode the lowest power stress (the product of
Rev F
V
N
N
D
OUT
S
P
=
•
V
D2
IN
18
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LT3758/LT3758A
APPLICATIONS INFORMATION
RMS current and peak voltage). An extreme high or low
duty cycle results in high power stress on the MOSFET
or diode, and reduces efficiency. It is recommended to
choose a duty cycle between 20% and 80%.
According to Figure 8, the primary and secondary peak
currents are:
I
I
= I
= I
= 2 • I
SW(PEAK) LP(MAX)
LP(PEAK)
LS(PEAK)
= 2 • I
D(PEAK)
LS(MAX)
Flyback Converter: Transformer Design for
Discontinuous Mode Operation
The primary and second inductor values of the flyback
converter transformer can be determined using the fol-
lowing equations:
The transformer design for discontinuous mode of opera-
tion is chosen as presented here. According to Figure 8,
the minimum D3 (D3 ) occurs when the the converter
2
2
D
• V
• h
IN(MIN)
MAX
has the minimum V MIaNnd the maximum output power
L =
P
IN
2 •P
• f
OUT(MAX)
(P ). Choose D3
to be equal to or higher than 10%
toOgUuTarantee the cMoInNverter is always in discontinuous
mode operation. Choosing higher D3 allows the use of
low inductances but results in higher switch peak current.
2
D2 •(V
+ V )
D
OUT
L =
S
2 •I
• f
OUT(MAX)
The primary to second turns ratio is:
The user can choose a D
as the start point. Then, the
MAX
maximum average primary currents can be calculated by
the following equation:
N
N
L
L
P
S
P
S
=
P
OUT(MAX)
I
=I
=
SW(MAX)
LP(MAX)
Flyback Converter: Snubber Design
D
• V
• h
MAX
IN(MIN)
Transformer leakage inductance (on either the primary
or secondary) causes a voltage spike to occur after the
MOSFET turn-off. This is increasingly prominent at higher
load currents, where more stored energy must be dis-
sipated. In some cases a snubber circuit will be required
to avoid overvoltage breakdown at the MOSFET’s drain
node. There are different snubber circuits, and Application
Note 19 is a good reference on snubber design. An RCD
snubber is shown in Figure 7.
where h is the converter efficiency.
If the flyback converter has multiple outputs, P
is the sum of all the output power.
OUT(MAX)
The maximum average secondary current is:
I
OUT(MAX)
I
= I
=
D(MAX)
LS(MAX)
D2
where
The snubber resistor value (R ) can be calculated by the
D2 = 1 – D
– D3
SN
MAX
following equation:
the primary and secondary RMS currents are:
N
N
2
P
S
V
− V • V
•
OUT
SN
SN
D
MAX
I
I
= 2 •I
•
•
LP(MAX)
LS(MAX)
LP(RMS)
LS(RMS)
R
= 2 •
SN
3
2
I
•L • f
LK
SW(PEAK)
D2
3
= 2 •I
where VSN is the snubber capacitor voltage. A smaller
results in a larger snubber loss. A reasonable V is
V
SN
SN
2 to 2.5 times of:
V
•N
P
OUT
N
S
Rev F
19
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LT3758/LT3758A
APPLICATIONS INFORMATION
LLK is the leakage inductance of the primary winding,
which is usually specified in the transformer character-
istics. LLK can be obtained by measuring the primary
inductance with the secondary windings shorted. The
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
equation:
T = T + P • θ = T + P • (θ + θ )
J
A
FET
JA
A
FET
JC
CA
snubber capacitor value (C ) can be determined using
CN
TJ must not exceed the MOSFET maximum junction
temperature rating. It is recommended to measure the
MOSFET temperature in steady state to ensure that abso-
lute maximum ratings are not exceeded.
the following equation:
V
SN
C
=
CN
ΔV •R • f
SN
CN
where ∆V is the voltage ripple across C . A reasonable
CN
∆V is 5S%N to 10% of V . The reverse voltage rating of
Flyback Converter: Output Diode Selection
SN
SN
D
should be higher than the sum of V and V
.
The output diode in a flyback converter is subject to large
RMS current and peak reverse voltage stresses. A fast
switching diode with a low forward drop and a low reverse
leakage is desired. Schottky diodes are recommended if
the output voltage is below 100V.
SN
SN
IN(MAX)
Flyback Converter: Sense Resistor Selection
In a flyback converter, when the power switch is turned on,
the current flowing through the sense resistor (I ) is:
SENSE
Approximate the required peak repetitive reverse voltage
I
= I
LP
SENSE
rating V
using:
RRM
Set the sense voltage at I
the SENSE current limit threshold with a 20% margin. The
sense resistor value can then be calculated to be:
to be the minimum of
LP(PEAK)
N
S
V
>
• V
+ V
IN(MAX)
OUT
RRM
N
P
80mV
The power dissipated by the diode is:
P = I • V
R
=
SENSE
I
LP(PEAK)
D
O(MAX)
D
Flyback Converter: Power MOSFET Selection
and the diode junction temperature is:
T = T + P • R
For the flyback configuration, the MOSFET is selected
with a VDC rating high enough to handle the maximum
J
A
D
θJA
The R to be used in this equation normally includes the
θJA
V , the reflected secondary voltage and the voltage spike
IN
RθJC for the device, plus the thermal resistance from the
due to the leakage inductance. Approximate the required
board to the ambient temperature in the enclosure. T must
J
MOSFET V rating using:
DC
not exceed the diode maximum junction temperature rating.
BV
> V
DSS
DS(PEAK)
Flyback Converter: Output Capacitor Selection
where
The output capacitor of the flyback converter has a similar
operation condition as that of the boost converter. Refer to
the Boost Converter: Output Capacitor Selection section
V
= V
+ V
DS(PEAK)
IN(MAX) SN
The power dissipated by the MOSFET in a flyback con-
verter is:
for the calculation of C
and ESR
.
OUT
COUT
2
2
P
C
= I
• R
+ 2 • V
• I
•
The RMS ripple current rating of the output capacitors
in discontinuous operation can be determined using the
following equation:
FET
RSS
M(RMS)
• f/1A
DS(ON)
DS(PEAK) L(MAX)
The first term in this equation represents the conduction
losses in the device, and the second term, the switching
4−(3 •D2)
I
≥ I
•
O(MAX)
loss. C
is the reverse transfer capacitance, which is
RMS(COUT),DISCONTINUOUS
RSS
3 •D2
usually specified in the MOSFET characteristics.
Rev F
20
For more information www.analog.com
LT3758/LT3758A
APPLICATIONS INFORMATION
Flyback Converter: Input Capacitor Selection
The maximum duty cycle (D
) occurs when the con-
MAX
verter has the minimum input voltage:
The input capacitor in a flyback converter is subject to
a large RMS current due to the discontinuous primary
current. To prevent large voltage transients, use a low
ESR input capacitor sized for the maximum RMS current.
The RMS ripple current rating of the input capacitors in
discontinuous operation can be determined using the fol-
lowing equation:
V
+ V
D
OUT
D
=
MAX
V
+ V
+ V
D
OUT
IN(MIN)
SEPIC Converter: Inductor and Sense Resistor Selection
As shown in Figure 1, the SEPIC converter contains two
inductors: L1 and L2. L1 and L2 can be independent, but can
also be wound on the same core, since identical voltages
are applied to L1 and L2 throughout the switching cycle.
P
V
4−(3 •D
)
OUT(MAX)
MAX
I
≥
•
RMS(CIN),DISCONTINUOUS
• h
3 •D
IN(MIN)
MAX
For the SEPIC topology, the current through L1 is the
converter input current. Based on the fact that, ideally, the
output power is equal to the input power, the maximum
average inductor currents of L1 and L2 are:
SEPIC CONVERTER APPLICATIONS
The LT3758 can be configured as a SEPIC (single-ended
primary inductance converter), as shown in Figure 1. This
topology allows for the input to be higher, equal, or lower
than the desired output voltage. The conversion ratio as
a function of duty cycle is:
D
MAX
I
I
=I
=I
•
O(MAX)
L1(MAX) IN(MAX)
1−D
MAX
=I
L2(MAX)
O(MAX)
V
+ V
D
D
OUT
V
=
In a SEPIC converter, the switch current is equal to I
L2
average switch current is defined as:
+
1−D
L1
IN
I
when the power switch is on, therefore, the maximum
in continuous conduction mode (CCM).
In a SEPIC converter, no DC path exists between the input
and output. This is an advantage over the boost converter
for applications requiring the output to be disconnected
from the input source when the circuit is in shutdown.
1
I
=I
+I
=I
•
O(MAX)
L1(MAX) L2(MAX)
SW(MAX)
1−D
MAX
and the peak switch current is:
Compared to the flyback converter, the SEPIC converter
has the advantage that both the power MOSFET and the
⎛
⎞
⎟
⎠
c
1
I
= 1+
•I
•
O(MAX)
⎜
SW(PEAK)
⎝
2
1−D
MAX
output diode voltages are clamped by the capacitors (C ,
IN
C
and C ), therefore, there is less voltage ringing
DC
OUT
c
The constant in the preceding equations represents the
percentage peak-to-peak ripple current in the switch, rela-
across the power MOSFET and the output diodes. The
SEPIC converter requires much smaller input capacitors
than those of the flyback converter. This is due to the fact
that, in the SEPIC converter, the inductor L1 is in series
with the input, and the ripple current flowing through the
input capacitor is continuous.
tive to I
, as shown in Figure 9. Then, the switch
SW(MAX)
ripple current ∆I can be calculated by:
SW
c
∆I
=
• I
SW(MAX)
SW
The inductor ripple currents ∆I and ∆I are identical:
L1
L2
SEPIC Converter: Switch Duty Cycle and Frequency
∆I = ∆I = 0.5 • ∆I
SW
L1
L2
For a SEPIC converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
The inductor ripple current has a direct effect on the
choice of the inductor value. Choosing smaller values of
∆IL requires large inductances and reduces the current
loop gain (the converter will approach voltage mode).
Rev F
voltage (V ), the input voltage (V ) and the diode for-
OUT
IN
ward voltage (V ).
D
21
For more information www.analog.com
LT3758/LT3758A
APPLICATIONS INFORMATION
where
Accepting larger values of ∆IL allows the use of low induc-
tances, but results in higher input current ripple, greater
core losses, and in some cases, subharmonic oscillation.
ΔI
L1
c
=
L1
I
c
L1(MAX)
A good starting point for is 0.2 and careful evaluation
of system stability should be made to ensure adequate
design margin.
2
c
L2
I
=I
• 1+
L2(MAX)
L2(RMS)
12
where
ꢆ
ꢇꢈ
∆ꢆ
ꢆ
ꢇꢈ ꢉ χ • ꢇꢈꢊꢋꢌꢍꢎ
ΔI
L2
c
=
L2
ꢆ
ꢇꢈꢊꢋꢌꢍꢎ
I
L2 (MAX)
ꢏ
ꢐꢑ
ꢇ
Based on the preceding equations, the user should choose
the inductors having sufficient saturation and RMS cur-
rent ratings.
ꢑ
ꢇ
ꢀꢁꢂꢃ Fꢄꢅ
Figure 9. The Switch Current Waveform of the SEPIC Converter
In a SEPIC converter, when the power switch is turned on,
the current flowing through the sense resistor (I
the switch current.
) is
SENSE
Given an operating input voltage range, and having cho-
sen the operating frequency and ripple current in the
inductor, the inductor value (L1 and L2 are independent)
of the SEPIC converter can be determined using the fol-
lowing equation:
Set the sense voltage at I
to be the minimum
SENSE(PEAK)
of the SENSE current limit threshold with a 20% margin.
The sense resistor value can then be calculated to be:
80 mV
V
R
=
IN(MIN)
SENSE
L1=L2 =
•D
MAX
I
SW(PEAK)
0.5 • ΔI • f
SW
For most SEPIC applications, the equal inductor values
will fall in the range of 1µH to 100µH.
SEPIC Converter: Power MOSFET Selection
For the SEPIC configuration, choose a MOSFET with a
By making L1 = L2, and winding them on the same core,
the value of inductance in the preceding equation is
replaced by 2L, due to mutual inductance:
V
DC
rating higher than the sum of the output voltage and
input voltage by a safety margin (a 10V safety margin is
usually sufficient).
V
The power dissipated by the MOSFET in a SEPIC con-
verter is:
IN(MIN)
L =
•D
MAX
ΔI • f
SW
2
P
= I
• R
• D
MAX
FET
SW(MAX)
DS(ON)
2
This maintains the same ripple current and energy storage
in the inductors. The peak inductor currents are:
+ 2 • (V
+ V ) • I
• C
• f/1A
IN(MIN)
OUT
L(MAX)
RSS
I
I
= I
= I
+ 0.5 • ∆I
+ 0.5 • ∆I
L1(PEAK)
L2(PEAK)
L1(MAX)
L2(MAX)
L1
L2
The first term in this equation represents the conduction
losses in the device, and the second term, the switching
loss. C
is the reverse transfer capacitance, which is
RSS
The RMS inductor currents are:
usually specified in the MOSFET characteristics.
For maximum efficiency, RDS(ON) and CRSS should be
minimized. From a known power dissipated in the power
2
c
L1
I
=I
• 1+
L1(MAX)
L1(RMS)
12
Rev F
22
For more information www.analog.com
LT3758/LT3758A
APPLICATIONS INFORMATION
MOSFET, its junction temperature can be obtained using
the following equation:
C
has nearly a rectangular current waveform. During
DC
the switch off-time, the current through C is I , while
approximately –IO flows during the on-tiDmCe. TIhNe RMS
rating of the coupling capacitor is determined by the fol-
lowing equation:
T = T + P • θ = T + P • (θ + θ )
J
A
FET
JA
A
FET
JC
CA
TJ must not exceed the MOSFET maximum junction
temperature rating. It is recommended to measure the
MOSFET temperature in steady state to ensure that abso-
lute maximum ratings are not exceeded.
V
+ V
D
OUT
I
>I
•
RMS(CDC) O(MAX)
V
IN(MIN)
SEPIC Converter: Output Diode Selection
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for C .
To maximize efficiency, a fast switching diode with a low
forward drop and low reverse leakage is desirable. The
average forward current in normal operation is equal to
the output current, and the peak current is equal to:
DC
INVERTING CONVERTER APPLICATIONS
The LT3758 can be configured as a dual-inductor inverting
⎛
⎞
⎟
⎠
c
1
topology, as shown in Figure 10. The V
to V ratio is:
OUT
IN
I
= 1+
•I
•
O(MAX)
⎜
D(PEAK)
⎝
2
1−D
MAX
V
− V
D
D
OUT
V
= −
1−D
IN
It is recommended that the peak repetitive reverse voltage
rating V is higher than V + V by a safety
RRM
OUT
IN(MAX)
in continuous conduction mode (CCM).
margin (a 10V safety margin is usually sufficient).
ꢃ
ꢑ ꢄꢃ
ꢇꢈ
ꢇꢔ
The power dissipated by the diode is:
ꢖ
ꢅ
ꢆꢂ
ꢑ
ꢖ
P = I
• V
D
D
O(MAX)
ꢃ
ꢆꢂ
ꢃ
ꢅ
ꢉꢊꢋ
ꢉꢊꢋ ꢑ
and the diode junction temperature is:
T = T + P • R
ꢇꢋꢌꢍꢎꢏ
ꢒꢓꢋꢁ
ꢄꢈ
ꢕꢈ
R
J
A
D
θJA
ꢀꢁꢂꢀꢁ
The R used in this equation normally includes the R
θJA
θJC
for the device, plus the thermal resistance from the board,
ꢀꢁꢂꢀꢁ
ꢑ
ꢒꢂꢄ
to the ambient temperature in the enclosure. T must not
ꢌꢍꢎꢏ Fꢈꢐ
J
exceed the diode maximum junction temperature rating.
Figure 10. A Simplified Inverting Converter
SEPIC Converter: Output and Input Capacitor Selection
The selections of the output and input capacitors of
the SEPIC converter are similar to those of the boost
converter. Please refer to the Boost Converter: Output
Capacitor Selection and Boost Converter: Input Capacitor
Selection sections.
Inverting Converter: Switch Duty Cycle and Frequency
For an inverting converter operating in CCM, the duty
cycle of the main switch can be calculated based on the
negative output voltage (VOUT) and the input voltage (VIN).
The maximum duty cycle (D
) occurs when the con-
MAX
SEPIC Converter: Selecting the DC Coupling Capacitor
verter has the minimum input voltage:
The DC voltage rating of the DC coupling capacitor (C ,
DC
V
− V
D
OUT
as shown in Figure 1) should be larger than the maximum
input voltage:
D
=
MAX
V
− V − V
D IN(MIN)
OUT
V
CDC
> V
IN(MAX)
Rev F
23
For more information www.analog.com
LT3758/LT3758A
APPLICATIONS INFORMATION
Inverting Converter: Inductor, Sense Resistor, Power
MOSFET, Output Diode and Input Capacitor Selections
C
has nearly a rectangular current waveform. During
DC
the switch off-time, the current through C is I , while
approximately –IO flows during the on-tiDmCe. TIhNe RMS
rating of the coupling capacitor is determined by the fol-
lowing equation:
The selections of the inductor, sense resistor, power
MOSFET, output diode and input capacitor of an invert-
ing converter are similar to those of the SEPIC converter.
Please refer to the corresponding SEPIC converter
sections.
D
MAX
I
>I
•
RMS(CDC) O(MAX)
1−D
MAX
Inverting Converter: Output Capacitor Selection
A low ESR and ESL, X5R or X7R ceramic capacitor works
The inverting converter requires much smaller output
capacitors than those of the boost, flyback and SEPIC
converters for similar output ripples. This is due to the
fact that, in the inverting converter, the inductor L2 is
in series with the output, and the ripple current flowing
through the output capacitors are continuous. The output
ripple voltage is produced by the ripple current of L2 flow-
ing through the ESR and bulk capacitance of the output
capacitor:
well for C .
DC
Board Layout
The high speed operation of the LT3758 demands careful
attention to board layout and component placement. The
Exposed Pad of the package is the only GND terminal of
the IC, and is important for thermal management of the
IC. Therefore, it is crucial to achieve a good electrical and
thermal contact between the Exposed Pad and the ground
plane of the board. For the LT3758 to deliver its full output
power, it is imperative that a good thermal path be pro-
vided to dissipate the heat generated within the package.
It is recommended that multiple vias in the printed circuit
board be used to conduct heat away from the IC and into
a copper plane with as much area as possible.
⎛
⎞
⎟
⎠
1
ΔV
= ΔI • ESR
+
COUT
⎜
L2
OUT(P–P)
8 • f •C
⎝
OUT
After specifying the maximum output ripple, the user can
select the output capacitors according to the preceding
equation.
To prevent radiation and high frequency resonance prob-
lems, proper layout of the components connected to the
IC is essential, especially the power paths with higher di/
dt. The following high di/dt loops of different topologies
should be kept as tight as possible to reduce inductive
ringing:
The ESR can be minimized by using high quality X5R or
X7R dielectric ceramic capacitors. In many applications,
ceramic capacitors are sufficient to limit the output volt-
age ripple.
The RMS ripple current rating of the output capacitor
needs to be greater than:
•
In boost configuration, the high di/dt loop contains
the output capacitor, the sensing resistor, the power
MOSFET and the Schottky diode.
I
> 0.3 • ∆I
L2
RMS(COUT)
Inverting Converter: Selecting the DC Coupling Capacitor
•
In flyback configuration, the high di/dt primary loop
contains the input capacitor, the primary winding, the
power MOSFET and the sensing resistor. The high di/
dt secondary loop contains the output capacitor, the
secondary winding and the output diode.
The DC voltage rating of the DC coupling capacitor (C ,
DC
as shown in Figure 10) should be larger than the maxi-
mum input voltage minus the output voltage (negative
voltage):
V
CDC
> V
– V
•
In SEPIC configuration, the high di/dt loop contains
the power MOSFET, sense resistor, output capacitor,
Schottky diode and the coupling capacitor.
IN(MAX) OUT
Rev F
24
For more information www.analog.com
LT3758/LT3758A
APPLICATIONS INFORMATION
•
In inverting configuration, the high di/dt loop contains
power MOSFET, sense resistor, Schottky diode and the
coupling capacitor.
The small-signal components should be placed away
from high frequency switching nodes. For optimum load
regulation and true remote sensing, the top of the output
voltage sensing resistor divider should connect indepen-
dently to the top of the output capacitor (Kelvin connec-
tion), staying away from any high dV/dt traces. Place the
divider resistors near the LT3758 in order to keep the high
impedance FBX node short.
Check the stress on the power MOSFET by measuring its
drain-to-source voltage directly across the device termi-
nals (reference the ground of a single scope probe directly
to the source pad on the PC board). Beware of inductive
ringing, which can exceed the maximum specified voltage
rating of the MOSFET. If this ringing cannot be avoided,
and exceeds the maximum rating of the device, either
choose a higher voltage device or specify an avalanche-
rated power MOSFET.
Figure 11 shows the suggested layout of the 10V to
40V input, 48V output boost converter in the Typical
Applications section.
ꢒ
ꢁꢂ
ꢀ
ꢁꢂ
ꢒ
ꢒ
ꢒꢇ
ꢒꢓ
ꢋꢇ
Rꢃ
R
ꢒ
Rꢇ
Rꢓ
ꢒ
1
2
3
4
5
10
LT3758
9
8
7
6
ꢒ
ꢍꢍ
ꢀꢒꢒ
R
ꢊ
1
2
3
4
8
7
6
5
M1
R
ꢍ
ꢀꢁꢌꢍ ꢊꢈ ꢎRꢈꢉꢂꢏ
ꢐꢋꢌꢂꢑ
ꢏꢇ
ꢒ
ꢒ
ꢈꢉꢊꢇ
ꢈꢉꢊꢓ
ꢀ
ꢈꢉꢊ
ꢃꢄꢅꢆ Fꢇꢇ
Figure 11. Suggested Layout of the 10V to 40V Input, 48V Output
Boost Converter in the Typical Applications Section
Rev F
25
For more information www.analog.com
LT3758/LT3758A
APPLICATIONS INFORMATION
Recommended Component Manufacturers
Some of the recommended component manufacturers
are listed in Table 2.
Table 2. Recommended Component Manufacturers
VENDOR
AVX
COMPONENTS
WEB ADDRESS
avx.com
Capacitors
BH Electronics
Inductors,
Transformers
bhelectronics.com
Coilcraft
Inductors
Inductors
Diodes
coilcraft.com
bussmann.com
diodes.com
Cooper Bussmann
Diodes, Inc
Fairchild
MOSFETs
Diodes
fairchildsemi.com
General Semiconductor
generalsemiconductor.
com
International Rectifier
IRC
MOSFETs, Diodes
Sense Resistors
Tantalum Capacitors
Toroid Cores
Diodes
irf.com
irctt.com
Kemet
kemet.com
Magnetics Inc
Microsemi
Murata-Erie
Nichicon
mag-inc.com
microsemi.com
murata.co.jp
nichicon.com
onsemi.com
panasonic.com
pulseeng.com
sanyo.co.jp
Inductors, Capacitors
Capacitors
On Semiconductor
Panasonic
Pulse
Diodes
Capacitors
Inductors
Sanyo
Capacitors
Sumida
Inductors
sumida.com
t-yuden.com
Taiyo Yuden
TDK
Capacitors
Capacitors, Inductors component.tdk.com
Thermalloy
Tokin
Heat Sinks
Capacitors
aavidthermalloy.com
nec-tokinamerica.com
tokoam.com
Toko
Inductors
United Chemi-Con
Vishay/Dale
Vishay/Siliconix
Würth Elektronik
Vishay/Sprague
Zetex
Capacitors
chemi-com.com
vishay.com
Resistors
MOSFETs
vishay.com
Inductors
we-online.com
vishay.com
Capacitors
Small-Signal Discretes
zetex.com
Rev F
26
For more information www.analog.com
LT3758/LT3758A
TYPICAL APPLICATIONS
10V to 40V Input, 48V Output Boost Converter
V
IN
10V TO 40V
C
IN
L1
18.7µH
R3
200k
4.7µF
50V
X7R
×2
V
IN
D1
SHDN/UVLO
V
OUT
R4
48V
1A
32.4k
LT3758
R2
464k
M1
SYNC
GATE
SENSE
RT
SS
C
+
OUT1
FBX
R
100µF
63V
T
V
GND INTV
CC
C
41.2k
C
300kHz
OUT2
R1
15.8k
C
4.7µF
10V
C
SS
VCC
4.7µF
R
C
10k
R
S
0.68µF
50V
X7R
×4
0.012Ω
C
C
C1
10nF
C2
X5R
100pF
3758 TA02a
C
C
, C
OUT1
: MURATA GRM32ER71H475KA88L
: PANASONIC ECG EEV-TG1J101UP
D1: VISHAY SILICONIX 30BQ060
L1: PULSE PB2020.223
M1: VISHAY SILICONIX SI7460DP
IN OUT2
Efficiency vs Output Current
Start-Up Waveforms
ꢌꢊꢊ
ꢆ
ꢔ ꢊꢕꢆ
ꢅꢓ
ꢗꢊ
ꢖꢊ
ꢕꢊ
ꢔꢊ
ꢙ
ꢚ ꢑꢊꢙ
ꢍꢆ
ꢆ
ꢇꢈꢉ
ꢙ
ꢚ ꢓꢑꢙ
ꢍꢆ
ꢊꢋꢆꢃꢄꢅꢆ
ꢐꢊ
ꢅ
ꢑꢊ
ꢒꢊ
ꢓꢊ
ꢌꢊ
ꢌꢍ
ꢊꢎꢃꢄꢅꢆ
ꢏꢐꢀꢑ ꢉꢎꢋꢊꢒ
ꢙ
ꢚ ꢌꢊꢙ
ꢍꢆ
ꢀꢁꢂꢃꢄꢅꢆ
ꢊꢋꢊꢊꢌ
ꢊꢋꢌ
ꢊꢋꢊꢌ
ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇꢈꢉ
ꢌ
ꢒꢕꢐꢖ ꢂꢈꢊꢓꢘ
Rev F
27
For more information www.analog.com
LT3758/LT3758A
TYPICAL APPLICATIONS
10V to 40V Input, 48V/2.5A Output Boost Converter
V
IN
10V TO 40V
C
IN2
L1
10µH
+
C
33µF
63V
R3
1M
IN1
4.7µF
100V
X5R
×3
V
IN
D1
SHDN/UVLO
V
OUT
R4
48V
2.5A
191k
LT3758A
R2
580k
M1
M2
SYNC
GATE
RT
SS
SENSE
FBX
GND INTV
CC
C
56µF
63V
+
OUT1
R
63.4k
T
V
C
C
200kHz
OUT2
R1
20.0k
C
4.7µF
10V
C
0.1µF
VCC
4.7µF
SS
R
10k
R
C
S
100V
X5R
×3
0.004Ω
1W
C
C
C1
10nF
C2
X5R
100pF
3758 TA03a
C
C
, SUN ELEC. 63HVH33M
D1: DIODES SBRT10U60D1
L1: WURTH ELEC. WE-7443641000
M1, M2: INFINEON BSC066N06NS
IN1
: SUN ELEC. 63HVH56M
OUT1
Efficiency vs Output Current
Load Step Response at VIN=24V
ꢄꢅꢅ
ꢔꢅ
ꢘꢅ
ꢕꢅ
ꢙꢅ
ꢖꢅ
ꢆꢅ
ꢗꢅ
ꢇꢅ
ꢄꢅ
ꢅ
ꢀ
ꢃ ꢄꢅꢀ
ꢁꢂ
ꢀ
ꢃ ꢆꢅꢀ
ꢇ
ꢁꢂ
ꢈꢉꢊ
ꢋꢇꢄꢅꢆꢇ
ꢌꢍꢎꢍꢈꢉꢏꢐꢑꢅ
ꢀ
ꢃ ꢇꢆꢀ
ꢁꢂ
ꢋꢓꢁꢌ
ꢆ
ꢈꢉꢊ
ꢒꢌꢄꢅꢆꢇ
ꢁꢓꢀꢌ
ꢔꢕꢀꢖ ꢊꢌꢁꢔꢗ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
ꢅꢑꢅꢄ
ꢅꢑꢄ
ꢄ
ꢄꢅ
ꢈꢉꢊꢋꢉꢊ ꢌꢉRRꢍꢂꢊ ꢎꢏꢐ
ꢗꢕꢖꢘ ꢊꢏꢅꢗꢚ
Rev F
28
For more information www.analog.com
LT3758/LT3758A
TYPICAL APPLICATIONS
36V to 72V Input, 90V/1.8A Output Boost Converter
V
IN
36V TO 72V
C
IN
L1
33µH
R3
1M
4.7µF
100V
X5R
×2
V
IN
D1
SHDN/UVLO
V
90V
OUT
R4
37.4k
1.8A
LT3758A
R2
549k
M1
SYNC
GATE
SENSE
RT
SS
C
10µF
100V
+
OUT1
FBX
R
T
V
GND INTV
CC
C
49.9k
C
250kHz
OUT2
R1
10.0k
C
4.7µF
10V
C
SS
VCC
4.7µF
R
C
R
S
0.1µF
100V
X5R
×3
16.2k
0.010Ω
C
C
C1
10nF
C2
X5R
100pF
3758 TA04a
C
: SUN ELEC. 100HVH10M
L1: WURTH ELEC. WE-7443643300
M1: INFINEON BSC190N12NS3
OUT1
D1: DIODES SBR8M100P5
Efficiency vs Output Current
Load Step Response at VIN=48V
ꢕꢓꢓ
ꢘꢓ
ꢇꢓ
ꢄꢓ
ꢉꢓ
ꢙꢓ
ꢆꢓ
ꢈꢓ
ꢅꢓ
ꢕꢓ
ꢓ
ꢀ
ꢃ ꢄꢅꢀ
ꢁꢂ
ꢇ
ꢈꢉꢊ
ꢋꢇꢄꢅꢆꢇ
ꢌꢍꢎꢍꢈꢉꢏꢐꢑꢅ
ꢀ
ꢃ ꢆꢇꢀ
ꢁꢂ
ꢀ
ꢃ ꢈꢉꢀ
ꢁꢂ
ꢒꢓꢀꢌ
ꢆ
ꢈꢉꢊ
ꢒꢌꢄꢅꢆꢇ
ꢁꢓꢔꢌ
ꢕꢔꢀꢖ ꢊꢌꢁꢗꢘ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
ꢓꢔꢓꢕ
ꢓꢔꢕ
ꢕ
ꢕꢓ
ꢊꢋꢌꢍꢋꢌ ꢎꢋRRꢏꢂꢌ ꢐꢑꢒ
ꢈꢄꢙꢇ ꢌꢑꢓꢆꢚ
Rev F
29
For more information www.analog.com
LT3758/LT3758A
TYPICAL APPLICATIONS
12V Output Nonisolated Flyback Power Supply
D1
V
12V
1.2A
OUT
V
IN
36V TO 72V
0.022µF
6.2k
C
IN
100V
1M
2.2µF
100V
X7R
T1
1,2,3
4,5,6
(PARALLEL)
V
IN
(SERIES)
D
SN
SHDN/UVLO
44.2k
SW
LT3758
105k
1%
SYNC
GATE
M1
SENSE
RT
SS
FBX
V
C
GND INTV
CC
63.4k
200kHz
1N4148
5.1Ω
0.47µF
100pF
C
4.7µF
10V
VCC
10k
10nF
C
47µF
X5R
OUT
15.8k
1%
0.030Ω
X5R
3758 TA05a
C
: MURATA GRM32ER72A225KA35L
D1: ON SEMICONDUCTOR MBRS360T3G
IN
T1: COILTRONICS VP2-0066
M1: VISHAY SILICONIX SI4848DY
D
: VISHAY SILICONIX ES1D
: MURATA GRM32ER61C476ME15L
SN
C
OUT
Efficiency vs Output Current
Start-Up Waveform
ꢌꢊꢊ
ꢗꢊ
ꢖꢊ
ꢕꢊ
ꢔꢊ
ꢑꢊ
ꢆ
ꢑ ꢒꢌꢆ
ꢅꢐ
ꢙ
ꢚ ꢒꢖꢙ
ꢍꢆ
ꢆ
ꢇꢈꢉ
ꢀꢆꢃꢄꢅꢆ
ꢒꢊ
ꢓꢊ
ꢊꢋꢀꢌ ꢉꢍꢎꢀꢏ
ꢀꢁꢂꢃꢄꢅꢆ
ꢐꢊ
ꢊꢋꢊꢌ
ꢊꢋꢌ
ꢌ
ꢌꢊ
ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇꢈꢉ
ꢓꢕꢑꢖ ꢂꢈꢊꢑꢘ
Frequency Foldback Waveforms
When Output Short-Circuit
ꢇ
ꢔ ꢕꢐꢇ
ꢆꢓ
ꢇ
ꢈꢉꢊ
ꢋꢇꢄꢅꢆꢇ
ꢇ
ꢌꢍ
ꢋꢁꢇꢄꢅꢆꢇ
ꢎꢏꢋꢐ ꢊꢑꢁꢋꢒ
ꢀꢁꢂꢃꢄꢅꢆꢇ
Rev F
30
For more information www.analog.com
LT3758/LT3758A
TYPICAL APPLICATIONS
VFD (Vacuum Fluorescent Display) Flyback Power Supply
D1
V
96V
80mA
OUT
C
OUT2
2.2µF
100V
X7R
4
5
V
IN
D2
V
64V
OUT2
9V TO 16V
C
22µF
25V
IN
T1
1, 2, 3
40mA
178k
V
IN
C
1µF
OUT1
22Ω
SHDN/UVLO
100V
X7R
220pF
32.4k
95.3k
M1 SW
LT3758
SYNC
GATE
6
SENSE
RT
SS
FBX
V
GND INTV
CC
C
0.47µF
63.4k
200kHz
C
4.7µF
10V
VCC
10k
10nF
0.019Ω
0.5W
47pF
1.62k
X5R
3758 TA06a
C
C
C
: MURATA GRM32ER61E226KE15L
D2: VISHAY SILICONIX ES1C
M1: VISHAY SILICONIX Si4100DY
T1: COILTRONICS VP1-0102
IN
: MURATA GRM31CR72A105K01L
: MURATA GRM32ER72A225KA35L
OUT1
OUT2
D1: VISHAY SILICONIX ES1D
(*PRIMARY = 3 WINDINGS IN PARALLEL)
Start-Up Waveforms
Switching Waveforms
ꢇ
ꢕ ꢀꢌꢇ
ꢇ
ꢇ
ꢆꢔ
ꢈꢉꢊꢀ
ꢈꢉꢊꢌ
ꢆ
ꢋꢌꢍꢎ
ꢎꢆꢃꢄꢅꢆ
ꢏꢐꢑꢒ
ꢆ
ꢋꢌꢍꢀ
ꢎꢆꢃꢄꢅꢆ
ꢏꢐꢑꢒ
ꢆ
ꢇ
ꢋ
ꢇꢈ
ꢈꢉꢊꢀ
ꢉꢊꢆꢃꢄꢅꢆ
ꢇ
ꢈꢉꢊꢌ
ꢌꢁꢇꢄꢅꢆꢇ
ꢓꢔꢉꢕ ꢍꢐꢊꢖꢗ
ꢍꢎꢏꢐ ꢊꢑꢁꢒꢓ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆꢇ
Rev F
31
For more information www.analog.com
LT3758/LT3758A
TYPICAL APPLICATIONS
36V to 72V Input, 3.3V Output Isolated Telecom Power Supply
PA1277NL
4
+
-
V
3.3V
3A
OUT
5
6
V
IN
36V TO 72V
0.022µF
100V
C
C
OUT
5.6k
IN
100µF
6.3V
×3
2.2µF
100V
X7R
BAV21W
UPS840
7
8
3
V
OUT
1M
V
IN
FDC2512
GATE
BAS516
10Ω
2
SHDN/UVLO
SENSE
44.2k
4.7µF
25V
X5R
0.03Ω
LT3758
100pF
BAT54CWTIG
100k
47pF
SYNC
INTV
CC
1
4.7µF
25V
X5R
FBX
RT
16k
274Ω
V
BAS516
SS
C
GND
63.4k
200kHz
LT4430
PS2801-1
0.47µF
47nF
0.47µF
V
OPTO
IN
2k
2200pF
250VAC
GND COMP
OC 0.5V FB
1µF
22.1k
3758 TA07a
Efficiency vs Output Current
ꢌꢊꢊ
ꢗꢊ
ꢖꢊ
ꢕꢊ
ꢔꢊ
ꢑꢊ
ꢙ
ꢚ ꢓꢔꢙ
ꢙ
ꢚ ꢕꢐꢙ
ꢍꢆ
ꢍꢆ
ꢙ
ꢚ ꢒꢖꢙ
ꢍꢆ
ꢒꢊ
ꢓꢊ
ꢐꢊ
ꢊꢋꢊꢌ
ꢊꢋꢌ
ꢌ
ꢌꢊ
ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇꢈꢉ
ꢓꢕꢑꢖ ꢂꢈꢊꢕꢘ
Rev F
32
For more information www.analog.com
LT3758/LT3758A
TYPICAL APPLICATIONS
18V to 72V Input, 24V Output SEPIC Converter
V
IN
18V TO 72V
C
C
IN2
C
10µF
100V
DC
+
IN1
•
2.2µF
100V
X7R
2.2µF
232k
20k
V
L1A
IN
100V
X7R, ×2
SHDN/UVLO
D1
V
OUT
24V
1A
LT3758A
SYNC
GATE
M1
L1B
280k
1%
•
SENSE
0.025Ω
RT
SS
FBX
V
C
GND INTV
CC
C
33µF
41.2k
300kHz
OUT1
+
20k
1%
35V
C
10k
10nF
0.47µF
OUT1
×2
C
4.7µF
10V
VCC
10µF
25V
X5R
×4
X5R
3758 TA08a
C
C
C
C
: PANASONIC EEE2AA100UP
L1A, L1B: COILTRONICS DRQ127-470
M1: FAIRCHILD SEMICONDUCTOR FDMS2572
D1: ON SEMICONDUCTOR MBRS3100T3G
IN1
, C : TAIYO YUDEN HMK325B7225KN-T
IN2 DC
: MURATA GRM31CR61E106KA12L
: KEMET T495X336K035AS
OUT1
OUT2
Efficiency vs Output Current
Load Step Waveform
ꢌꢊꢊ
ꢗꢊ
ꢇ
ꢘ ꢙꢕꢇ
ꢆꢗ
ꢙ
ꢚ ꢌꢖꢙ
ꢍꢆ
ꢇ
ꢈꢉꢊ
ꢖꢊ
ꢕꢊ
ꢋꢇꢄꢅꢆꢇ
ꢌꢍꢎꢍꢈꢉꢏꢐꢑꢅ
ꢙ
ꢚ ꢕꢑꢙ
ꢍꢆ
ꢙ
ꢚ ꢒꢖꢙ
ꢍꢆ
ꢔꢊ
ꢓꢊ
ꢒꢊ
ꢒꢌ
ꢆ
ꢈꢉꢊ
ꢒꢌꢄꢅꢆꢇ
ꢁꢌ
ꢐꢊ
ꢑꢊ
ꢌꢊ
ꢓꢔꢀꢕ ꢊꢌꢁꢕꢖ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
ꢊꢋꢊꢊꢌ
ꢊꢋꢌ
ꢊꢋꢊꢌ
ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇꢈꢉ
ꢌ
ꢐꢕꢓꢖ ꢂꢈꢊꢖꢘ
Frequency Foldback Waveforms
When Output Short-Circuit
Start-Up Waveform
ꢇ
ꢗ ꢘꢕꢇ
ꢆ
ꢖ ꢗꢓꢆ
ꢆꢖ
ꢅꢕ
ꢇ
ꢊꢋꢌ
ꢍꢁꢇꢄꢅꢆꢇ
ꢆ
ꢇ
ꢇꢈꢉ
ꢈꢉ
ꢊꢋꢆꢃꢄꢅꢆ
ꢀꢁꢇꢄꢅꢆꢇ
ꢅꢌ
ꢅꢌ
ꢆꢎ
ꢆꢎ
ꢊꢍ ꢎ ꢊꢏ
ꢏꢐ ꢑ ꢏꢒ
ꢊꢍꢃꢄꢅꢆ
ꢍꢐꢄꢅꢆꢇ
ꢐꢑꢒꢓ ꢉꢍꢋꢓꢔ
ꢓꢔꢀꢕ ꢌꢐꢁꢕe
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆꢇ
Rev F
33
For more information www.analog.com
LT3758/LT3758A
TYPICAL APPLICATIONS
10V to 40V Input, –12V Output Inverting Converter
V
IN
10V TO 40V
C
C
IN2
C
DC
+
IN1
•
R1
200k
4.7µF
50V
X7R
×2
2.2µF
4.7µF
50V
×2
V
L1A
IN
100V
X7R, ×2
L1B
SHDN/UVLO
V
OUT
R2
32.4k
–12V
2A
LT3758A
SYNC
GATE
M1
D1
SENSE
105k
7.5k
0.015Ω
RT
SS
FBX
GND INTV
CC
V
C
C
41.2k
300kHz
OUT2
47µF
+
20V
10k
6.8nF
0.47µF
C
×2
C
4.7µF
10V
OUT1
VCC
22µF
16V
X5R
×4
X5R
3758 TA09a
C
C
C
C
: KEMET T495X475K050AS
D1: VISHAY SILICONIX 30BQ060
L1A, L1B: COILTRONICS DRQ127-150
M1: VISHAY SILICONIX SI7850DP
IN1
, C : MURATA GRM32ER71H475KA88L
IN2 DC
: MURATA GRM32ER61C226KE20
: KEMET T495X476K020AS
OUT1
OUT2
Efficiency vs Output Current
Load Step Waveforms
ꢌꢊꢊ
ꢗꢊ
ꢇ
ꢘ ꢙꢚꢇ
ꢆꢗ
ꢙ
ꢚ ꢌꢊꢙ
ꢍꢆ
ꢇ
ꢈꢉꢊ
ꢋꢇꢄꢅꢆꢇ
ꢙ
ꢚ ꢑꢒꢙ
ꢖꢊ
ꢕꢊ
ꢍꢆ
ꢙ
ꢚ ꢒꢊꢙ
ꢌꢍꢎꢍꢈꢉꢏꢐꢑꢅ
ꢍꢆ
ꢔꢊ
ꢓꢊ
ꢒꢊ
ꢋꢌ
ꢆ
ꢈꢉꢊ
ꢋꢌꢄꢅꢆꢇ
ꢁꢌ
ꢐꢊ
ꢑꢊ
ꢌꢊ
ꢒꢓꢀꢔ ꢊꢌꢁꢕꢖ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
ꢊꢋꢊꢊꢌ
ꢊꢋꢌ
ꢌ
ꢌꢊ
ꢊꢋꢊꢌ
ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇꢈꢉ
ꢐꢕꢓꢖ ꢂꢈꢊꢗꢘ
Frequency Foldback Waveforms
When Output Short-Circuit
Start-Up Waveforms
ꢆ
ꢗ ꢏꢘꢆ
ꢇ
ꢘ ꢊꢙꢇ
ꢅꢖ
ꢆꢗ
ꢇ
ꢆ
ꢋꢌꢍ
ꢇꢈꢉ
ꢎꢁꢇꢄꢅꢆꢇ
ꢀꢆꢃꢄꢅꢆ
ꢇ
ꢈꢉ
ꢊꢁꢇꢄꢅꢆꢇ
ꢅꢊ
ꢅꢊ
ꢋꢌ ꢍ ꢋꢎ
ꢏꢌꢃꢄꢅꢆ
ꢆꢏ
ꢆꢏ
ꢎꢐ ꢑ ꢎꢒ
ꢐꢑꢀꢒ ꢉꢌꢓꢔꢕ
ꢓꢔꢀꢕ ꢍꢐꢁꢖe
ꢀꢐꢄꢅꢆꢇ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆꢇ
Rev F
34
For more information www.analog.com
LT3758/LT3758A
PACKAGE DESCRIPTION
DD Package
10-Lead Plastic DFN (3mm × 3mm)
ꢄReꢪeꢫeꢬꢭe ꢙꢍꢕ ꢈꢐꢑ ꢮ ꢂꢡꢚꢂꢨꢚꢃꢤꢜꢜ Rev ꢕꢊ
ꢂꢁꢦꢂ ±ꢂꢁꢂꢡ
ꢀꢁꢡꢡ ±ꢂꢁꢂꢡ
ꢛꢁꢃꢡ ±ꢂꢁꢂꢡ ꢄꢛ ꢆꢇꢈꢉꢆꢊ
ꢃꢁꢤꢡ ±ꢂꢁꢂꢡ
ꢖꢏꢕꢗꢏꢑꢉ
ꢌꢘꢍꢙꢇꢋꢉ
ꢂꢁꢛꢡ ± ꢂꢁꢂꢡ
ꢂꢁꢡꢂ
ꢒꢆꢕ
ꢛꢁꢀꢨ ±ꢂꢁꢂꢡ
ꢄꢛ ꢆꢇꢈꢉꢆꢊ
RECOMMENDED ꢆꢌꢙꢈꢉR ꢖꢏꢈ ꢖꢇꢍꢕꢞ ꢏꢋꢈ ꢈꢇꢓꢉꢋꢆꢇꢌꢋꢆ
R ꢧ ꢂꢁꢃꢛꢡ
ꢂꢁꢅꢂ ± ꢂꢁꢃꢂ
ꢍꢣꢖ
ꢤ
ꢃꢂ
ꢀꢁꢂꢂ ±ꢂꢁꢃꢂ
ꢄꢅ ꢆꢇꢈꢉꢆꢊ
ꢃꢁꢤꢡ ± ꢂꢁꢃꢂ
ꢄꢛ ꢆꢇꢈꢉꢆꢊ
ꢖꢇꢋ ꢃ ꢋꢌꢍꢕꢞ
R ꢧ ꢂꢁꢛꢂ ꢌR
ꢂꢁꢀꢡ × ꢅꢡ°
ꢖꢇꢋ ꢃ
ꢍꢌꢖ ꢓꢏRꢗ
ꢄꢆꢉꢉ ꢋꢌꢍꢉ ꢤꢊ
ꢕꢞꢏꢓFꢉR
ꢄꢈꢈꢊ ꢈFꢋ Rꢉꢝ ꢕ ꢂꢀꢃꢂ
ꢡ
ꢃ
ꢂꢁꢛꢡ ± ꢂꢁꢂꢡ
ꢂꢁꢡꢂ ꢒꢆꢕ
ꢂꢁꢦꢡ ±ꢂꢁꢂꢡ
ꢂꢁꢛꢂꢂ RꢉF
ꢛꢁꢀꢨ ±ꢂꢁꢃꢂ
ꢄꢛ ꢆꢇꢈꢉꢆꢊ
ꢂꢁꢂꢂ ꢩ ꢂꢁꢂꢡ
ꢒꢌꢍꢍꢌꢓ ꢝꢇꢉꢐꢥꢉꢟꢖꢌꢆꢉꢈ ꢖꢏꢈ
ꢋꢌꢍꢉꢎ
ꢃꢁ ꢈRꢏꢐꢇꢋꢑ ꢍꢌ ꢒꢉ ꢓꢏꢈꢉ ꢏ ꢔꢉꢈꢉꢕ ꢖꢏꢕꢗꢏꢑꢉ ꢌꢘꢍꢙꢇꢋꢉ ꢓꢂꢚꢛꢛꢜ ꢝꢏRꢇꢏꢍꢇꢌꢋ ꢌF ꢄꢐꢉꢉꢈꢚꢛꢊꢁ
ꢕꢞꢉꢕꢗ ꢍꢞꢉ ꢙꢍꢕ ꢐꢉꢒꢆꢇꢍꢉ ꢈꢏꢍꢏ ꢆꢞꢉꢉꢍ FꢌR ꢕꢘRRꢉꢋꢍ ꢆꢍꢏꢍꢘꢆ ꢌF ꢝꢏRꢇꢏꢍꢇꢌꢋ ꢏꢆꢆꢇꢑꢋꢓꢉꢋꢍ
ꢛꢁ ꢈRꢏꢐꢇꢋꢑ ꢋꢌꢍ ꢍꢌ ꢆꢕꢏꢙꢉ
ꢀꢁ ꢏꢙꢙ ꢈꢇꢓꢉꢋꢆꢇꢌꢋꢆ ꢏRꢉ ꢇꢋ ꢓꢇꢙꢙꢇꢓꢉꢍꢉRꢆ
ꢅꢁ ꢈꢇꢓꢉꢋꢆꢇꢌꢋꢆ ꢌF ꢉꢟꢖꢌꢆꢉꢈ ꢖꢏꢈ ꢌꢋ ꢒꢌꢍꢍꢌꢓ ꢌF ꢖꢏꢕꢗꢏꢑꢉ ꢈꢌ ꢋꢌꢍ ꢇꢋꢕꢙꢘꢈꢉ
ꢓꢌꢙꢈ Fꢙꢏꢆꢞꢁ ꢓꢌꢙꢈ Fꢙꢏꢆꢞꢠ ꢇF ꢖRꢉꢆꢉꢋꢍꢠ ꢆꢞꢏꢙꢙ ꢋꢌꢍ ꢉꢟꢕꢉꢉꢈ ꢂꢁꢃꢡꢢꢢ ꢌꢋ ꢏꢋꢣ ꢆꢇꢈꢉ
ꢡꢁ ꢉꢟꢖꢌꢆꢉꢈ ꢖꢏꢈ ꢆꢞꢏꢙꢙ ꢒꢉ ꢆꢌꢙꢈꢉR ꢖꢙꢏꢍꢉꢈ
ꢤꢁ ꢆꢞꢏꢈꢉꢈ ꢏRꢉꢏ ꢇꢆ ꢌꢋꢙꢣ ꢏ RꢉFꢉRꢉꢋꢕꢉ FꢌR ꢖꢇꢋ ꢃ ꢙꢌꢕꢏꢍꢇꢌꢋ ꢌꢋ ꢍꢞꢉ
ꢍꢌꢖ ꢏꢋꢈ ꢒꢌꢍꢍꢌꢓ ꢌF ꢖꢏꢕꢗꢏꢑꢉ
Rev F
35
For more information www.analog.com
LT3758/LT3758A
PACKAGE DESCRIPTION
MSE Package
10-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1664 Rev I)
BOTTOM VIEW OF
EXPOSED PAD OPTION
1.88
(.074)
1.88 ±0.102
(.074 ±.004)
0.889 ±0.127
(.035 ±.005)
1
0.29
REF
1.68
(.066)
0.05 REF
5.10
(.201)
MIN
1.68 ±0.102
3.20 – 3.45
DETAIL “B”
(.066 ±.004) (.126 – .136)
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
DETAIL “B”
10
NO MEASUREMENT PURPOSE
0.50
(.0197)
BSC
0.305 ± 0.038
(.0120 ±.0015)
TYP
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
0.497 ±0.076
(.0196 ±.003)
10 9
8
7 6
RECOMMENDED SOLDER PAD LAYOUT
REF
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
DETAIL “A”
0° – 6° TYP
0.254
(.010)
1
2
3
4 5
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 ±0.0508
(.004 ±.002)
0.50
(.0197)
BSC
MSOP (MSE) 0213 REV I
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD
SHALL NOT EXCEED 0.254mm (.010") PER SIDE.
Rev F
36
For more information www.analog.com
LT3758/LT3758A
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
3/10
Deleted Bullet from Features and Last Line of Description
Updated All Sections to Include H-Grade and Military Grade
Deleted Vendor Telephone Information from Table 2 in Applications Information Section
Revised TA04 and TA04c in Typical Applications
Replaced Related Parts List
1
2 to 7
26
29
36
8
B
5/10
5/11
Revised last sentence of SYNC Pin description
Updated Block Diagram
9
Revised value in last sentence of Programming Turn-on and Turn-off Thresholds in the SHDN/UVLO Pin Section
Revised penultimate sentence of Operating Frequency and Synchronization section
Revised MP-grade temperature range in Absolute Maximum Ratings and Order Information
Revised Note 2
10
13
C
D
2
4
19
Revised formula in Applications Information
07/12 Added LT3758A version
Updated Block Diagram
Throughout
9
Updated Programming the Output Voltage section
13
Updated Loop Compensation section
14
Updated the schematic and Load Step Waveforms in the Typical Applications section
Text Clarification
31, 32
16, 22
E
F
6/17
01/19 Added New Boost Circuits & Graphs
28, 29
38
Updated Related Parts Section with LT8361/LT8362/LT8364 Boost Converters
Rev F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
37
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LT3758/LT3758A
TYPICAL APPLICATION
8V to 72V Input, 12V Output SEPIC Converter
Efficiency vs Output Current
V
IN
8V TO 72V
ꢎꢏꢏ
ꢘꢏ
C
DC
•
C
IN
2.2µF
100V
154k
V
2.2µF
100V
X7R
×2
L1A
IN
ꢀ
ꢃ ꢄꢀ
ꢁꢂ
D1
X7R, ×2
MBRS3100T3G
SHDN/UVLO
ꢄꢏ
ꢗꢏ
V
12V
2A
OUT
ꢀ
ꢁꢂ
ꢃ ꢔꢓꢀ
32.4k
LT3758
ꢀ
ꢃ ꢗꢓꢀ
ꢁꢂ
SYNC
GATE
M1
Si7456DP
C
OUT1
ꢖꢏ
ꢕꢏ
ꢔꢏ
L1B
+
47µF
20V
×2
105k
•
SENSE
1%
0.012Ω
RT
SS
FBX
ꢒꢏ
ꢓꢏ
ꢎꢏ
V
GND INTV
CC
C
41.2k
300kHz
15.8k
1%
C
OUT2
10µF
16V
X5R
×4
ꢏꢚꢏꢏꢎ
ꢏꢚꢏꢎ
ꢏꢚꢎ
ꢎ
ꢎꢏ
10k
10nF
C
0.47µF
VCC
ꢅꢆꢇꢈꢆꢇ ꢉꢆRRꢊꢂꢇ ꢋꢌꢍ
4.7µF
10V
ꢒꢗꢕꢄ ꢇꢌꢎꢏꢙ
X5R
3758 TA10a
L1A, L1B: COILTRONICS DRQ127-220
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
2.9V ≤ V ≤ 40V, with Small Packages and Powerful Gate Drive
LT3757A
40V Flyback, Boost, SEPIC and Inverting Controllers
IN
LT3759
40V Flyback, Boost, SEPIC and Inverting Controller
100V Isolated Flyback Converters in SOT-23
100V Isolated Flyback Converter
1.6V ≤ V ≤ 42V, with Small Package and Powerful Gate Drive
IN
LT8300/LT8303
LT8304/LT8304-1
LT3748
Monolithic No-Opto Flybacks with Integrated 240mA/500mA Switch
Monolithic No-Opto Flyback with Integrated 2A Switch, SO-8 Package
100V Isolated Flyback Controller
5V ≤ V ≤ 100V, No-Opto Flyback, MSOP-16 with High Voltage Spacing
IN
LT8301/LT8302
LT3798
42V Isolated Flyback Converters
Monolithic No-Opto Flybacks with Integrated 1.2A/3.6A, 65V Switch
Offline Isolated No Opto-Coupler Flyback Controller with
Active PFC
V
IN
and V
Limited Only by External Components
OUT
LT3799/LT3799-1
LT3957A
Offline Isolated Flyback LED Controllers with Active PFC
V
and V
Limited Only by External Components
IN
OUT
Boost, Flyback, SEPIC and Inverting Converter with 5A, 3V ≤ V ≤ 40V, 100kHz to 1MHz Programmable Operation Frequency,
40V Switch
IN
5mm × 6mm QFN Package
LT3958
LT8361
LT8362
LT8364
Boost, Flyback, SEPIC and Inverting Converter with 3.3A, 5V ≤ V ≤ 80V, 100kHz to 1MHz Programmable Operation Frequency,
IN
84V Switch
100V, 2A, Low I Boost/SEPIC/Inverting Converter
5mm × 6mm QFN Package
V
= 2.8V to 60V, V
= 100V, I = 6µA (Burst Mode Operation),
Q
Q
IN
OUT(MAX)
MSOP-16(12)E, 3mm × 3mm DFN-10 Packages
V = 2.8V to 60V, V = 60V, I = 9µA (Burst Mode Operation),
IN
60V, 2A, Low I Boost/SEPIC/Inverting Converter
Q
OUT(MAX)
Q
MSOP-16(12)E Package
60V, 4A, Low I Boost/SEPIC/Inverting Converter
V
= 2.8V to 60V, V
= 60V, I = 9µA (Burst Mode Operation),
OUT(MAX) Q
Q
IN
MSOP-16(12)E, 4mm × 3mm DFN-12 Packages
Rev F
01/19
www.analog.com
ANALOG DEVICES, INC. 2009-2019
38
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