LT3761HMSE [Linear]
60VIN LED Controller with Internal PWM Generator; 60VIN LED控制器，内置PWM发生器
| 型号： | LT3761HMSE |
| 厂家： | 
Linear |
| 描述： | 60VIN LED Controller with Internal PWM Generator |
| 文件： | 总28页 (文件大小：393K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3761
60V LED Controller with
IN
Internal PWM Generator
FeaTures
DescripTion
n
3000:1 True Color PWM™ Dimming for LEDs
The LT®3761 is a DC/DC controller designed to operate as
a constant-current source and constant-voltage regulator.
ItfeaturesaprogrammableinternalPWMdimmingsignal.
The LT3761 is ideally suited for driving high current LEDs,
but also has features to make it suitable for charging bat-
teries and supercapacitors. The fixed frequency, current
mode architecture results in stable operation over a wide
range of supply and output voltages. A voltage feedback
pinservesastheinputforseveralLEDprotectionfeatures,
and also makes it possible for the converter to operate
as a constant-voltage source. A frequency adjust pin
allows the user to program the frequency from 100kHz
to 1MHz to optimize efficiency, performance or external
component size.
n
Wide V Range: 4.5V to 60V
IN
n
n
n
Rail-to-Rail Current Sense Range: 0V to 80V
Programmable PWM Dimming Signal Generator
Constant Current ( 3%ꢀ and Constant-Voltage
( 2%ꢀ Regulation
n
n
Analog Dimming
Drives LEDs in Boost, SEPIC, Inverting, Buck Mode,
Buck-Boost Mode, or Flyback Configuration
Output Short-Circuit Protected Boost
Open LED Protection and Reporting
n
n
n
n
n
n
n
Adjustable Switching Frequency: 100kHz to 1MHz
Programmable V UVLO with Hysteresis
C/10 Indication for Battery Chargers
Low Shutdown Current: <1µA
Thermally Enhanced 16-Lead MSOP Package
IN
TheLT3761sensesoutputcurrentatthehighsideoratthe
low side of the load. The PWM input can be configured to
self-oscillate at fixed frequency with duty ratio program-
mable from 4% to 96%. When driven by an external
signal, the PWM input provides LED dimming ratios of
up to 3000:1. The CTRL input provides additional analog
dimming capability.
applicaTions
n
High Voltage LED Strings >100V with Ground
Referred Current Sense
n
Grounded Anode LEDs
Battery and SuperCap Chargers
Accurate Current Limited Voltage Regulators
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
True Color PWM is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents including 7199560, 7321203.
n
Typical applicaTion
94% Efficient Boost LED Driver for Automotive
Headlamp with 25:1 Internal PWM Dimming
10µH
V
IN
8V TO
60V
PWM Dimming Waveforms at
Various DIM Voltage Settings
2.2µF
×2
499k
V
IN
1M
2.2µF
×4
0.25Ω
1A
GATE
EN/UVLO
V
REF
SENSE
90.9k
V
= 7.7V
PWM
DIM
DC
1M
= 96%
LT3761
10mΩ
16.9k
CTRL
V
= 4V
PWM
DIM
DC
GND
INTV
CC
140k
= 50%
I
LED
1A/DIV
100k
FB
ISP
ISN
V
= 1.5V
PWM
DIM
DC
= 10%
60W
OPENLED
DIM/SS
PWM
LED
DIM
STRING
V
DIM
DC
= 0.4V
124k
0.01µF
PWMOUT
= 4.3%
PWM
V
RT INTV
C
CC
3761 TA01b
0.5ms/DIV
47nF
300Hz
28.7k
350kHz
5.1k
4.7nF
INTV
CC
1µF
3761 TA01a
3761f
1
LT3761
absoluTe maximum raTings
pin conFiguraTion
(Note 1ꢀ
TOP VIEW
V , EN/UVLO............................................................60V
IN
1
2
3
4
5
6
7
8
PWMOUT
FB
16 GATE
15 SENSE
ISP, ISN.....................................................................80V
ISN
14 V
IN
ISP
13 INTV
CC
17
GND
INTV ...................................................V + 0.3V, 9.6V
CC
IN
V
C
12 EN/UVLO
11 RT
CTRL
GATE, PWMOUT ................................................ (Note 2)
CTRL, OPENLED........................................................15V
FB, PWM..................................................................9.6V
V
10 DIM/SS
REF
PWM
9
OPENLED
MSE PACKAGE
16-LEAD PLASTIC MSOP
V , V ......................................................................3V
C
REF
T
= 125°C (E-, I-GRADES), T
= 150°C (H-GRADE),
JMAX
JMAX
θ
= 43°C/W, θ = 4°C/W
JA
JC
RT, DIM/SS..............................................................1.5V
SENSE......................................................................0.5V
Operating Ambient Temperature Range (Notes 3, 4)
LT3761E.................................................–40 to 125°C
LT3761I..................................................–40 to 125°C
LT3761H ................................................–40 to 150°C
Storage Temperature Range .................. –65°C to 150°C
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
orDer inFormaTion
LEAD FREE FINISH
LT3761EMSE#PBF
LT3761IMSE#PBF
LT3761HMSE#PBF
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3761EMSE#TRPBF
LT3761IMSE#TRPBF
LT3761HMSE#TRPBF
3761
3761
3761
16-Lead Plastic MSOP
16-Lead Plastic MSOP
16-Lead Plastic MSOP
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 24V, EN/UVLO = 24V, CTRL = 2V, PWM = 5V, unless otherwise noted.
PARAMETER
CONDITIONS
Tied to INTV
CC
MIN
TYP
MAX
UNITS
l
V
IN
IN
Minimum Operating Voltage
V
4.5
V
IN
V
Shutdown I
EN/UVLO = 0V, PWM = 0V
EN/UVLO = 1.15V, PWM = 0V
0.1
1
6
µA
µA
Q
V
V
V
V
Operating I (Not Switching)
PWM = 0V
1.8
2.02
0.001
185
105
40
2.2
mA
V
IN
Q
l
Voltage
–100µA ≤ I
≤ 0µA
1.955
2.05
REF
REF
REF
VREF
Line Regulation
Pull-Up Current
4.5V ≤ V ≤ 60V
%/V
µA
mV
µA
µA
V
IN
l
l
V
REF
= 0V
150
98
210
118
SENSE Current Limit Threshold
SENSE Input Bias Current
DIM/SS Pull-Up Current
DIM/SS Voltage Clamp
Current Out of Pin, SENSE = 0V
Current Out of Pin, DIM/SS = 0V
l
10
12
14
I
= 0µA
1.2
DIM/SS
3761f
2
LT3761
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 24V, EN/UVLO = 24V, CTRL = 2V, PWM = 5V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Error Amplifier
l
l
Full-Scale ISP/ISN Current Sense Threshold
ISP-ISN
CTRL ≥ 1.2V, ISP = 48V
CTRL ≥ 1.2V, ISN = 0V
242
243
250
257
258
268
mV
mV
(V
)
l
l
1/10th Scale ISP/ISN Current Sense Threshold
(V
CTRL = 0.2V, ISP = 48V
CTRL = 0.2V, ISN = 0V
21
20
25
28
30
36
mV
mV
)
ISP-ISN
l
l
Mid-Scale ISP/ISN Current Sense Threshold
(V
CTRL = 0.5V, ISP = 48V
CTRL = 0.5V, ISN = 0V
96
95
100
105
104
115
mV
mV
)
ISP-ISN
ISP/ISN Overcurrent Threshold
600
mV
V
ISP/ISN Current Sense Amplifier Input Common Mode
0
0
80
Range (V
)
ISN
ISP/ISN Input Bias Current High Side Sensing (Combined) PWM = 5V (Active), ISP = ISN = 48V
PWM = 0V (Standby), ISP = ISN = 48V
100
0.1
µA
µA
ISP/ISN Input Bias Current Low Side Sensing (Combined) PWM = 5V, ISP = ISN = 0V
–230
120
70
µA
µS
µS
V
ISP/ISN Current Sense Amplifier g (High Side Sensing)
V
V
= 250mV, ISP = 48V
= 250mV, ISN = 0V
m
ISP-ISN
ISP-ISN
ISP/ISN Current Sense Amplifier g (Low Side Sensing)
m
l
CTRL Pin Range for Linear Current Sense Threshold
Adjustment
1.0
CTRL Input Bias Current
Current Out of Pin
50
15
100
nA
MΩ
nA
V
V Output Impedance
C
0.9V ≤ V ≤ 1.5V
C
V Standby Input Bias Current
C
PWM = 0V
–20
20
l
l
FB Regulation Voltage (V
)
FB
ISP = ISN = 48V, 0V
1.225
1.255
500
40
1.275
FB Amplifier g
FB = V , ISP = ISN = 48V
µS
nA
V
m
FB
FB Pin Input Bias Current
FB Open LED Threshold
Current Out of Pin, FB = V
100
FB
OPENLED Falling, ISP Tied to ISN
V
–
V
–
V
–
FB
FB
FB
65mV
50mV
40mV
C/10 Inhibit for OPENLED Assertion (V
)
FB = V , ISN = 48V, 0V
14
25
39
mV
V
ISP-ISN
FB
FB Overvoltage Threshold
PWMOUT Falling
V
FB
+
V
+
V
+
FB
FB
50mV
60mV
70mV
4
V/V
V Current Mode Gain (∆V /∆V
)
C
VC
SENSE
Oscillator
l
Switching Frequency
R = 95.3kΩ
T
85
925
100
1000
115
1050
kHz
kHz
T
R = 8.87kΩ
GATE Minimum Off-Time
GATE Minimum On-Time
Linear Regulator
C
= 2200pF
= 2200pF
160
180
ns
ns
GATE
GATE
C
l
INTV Regulation Voltage
10V ≤ V ≤ 60V
7.6
8.1
7.85
8.05
4.5
V
V
CC
IN
INTV Maximum Operating Voltage
CC
INTV Minimum Operating Voltage
V
CC
Dropout (V – INTV
)
I
= –10mA, V = 7V
390
4.1
36
8
mV
V
IN
CC
INTVCC
IN
l
INTV Undervoltage Lockout
3.9
30
4.4
42
13
CC
INTV Current Limit
INTV = 6V, 8V ≤ V ≤ 60V
mA
µA
CC
CC
IN
INTV Current in Shutdown
EN/UVLO = 0V, INTV = 8V
CC
CC
3761f
3
LT3761
elecTrical characTerisTics The ldenotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 24V, EN/UVLO = 24V, CTRL = 2V, PWM = 5V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Logic Inputs/Outputs
l
l
EN/UVLO Threshold Voltage Falling
EN/UVLO Rising Hysteresis
EN/UVLO Input Low Voltage
EN/UVLO Pin Bias Current Low
EN/UVLO Pin Bias Current High
OPENLED Output Low
1.18
1.220
20
1.26
V
mV
V
I
Drops Below 1µA
0.4
2.7
VIN
EN/UVLO = 1.15V
EN/UVLO = 1.33V
1.7
2.3
10
µA
nA
mV
100
200
I
= 1mA
OPENLED
PWM Pin Signal Generator
PWM Falling Threshold
l
0.78
0.35
6
0.83
0.4
7.5
88
0.88
0.6
9
V
V
PWM Threshold Hysteresis (V
)
I
= 0µA
DIM/SS
PWMHYS
PWM Pull-Up Current (I
)
PWM = 0.7V, I
PWM = 1.5V, I
= 0µA
= 0µA
µA
µA
mA
PWMUP
DIM/SS
DIM/SS
PWM Pull-Down Current (I
)
68
110
PWMDN
PWM Fault Mode Pull-Down Current
INTV = 3.8V
1.5
CC
PWMOUT Duty Ratio for PWM Signal Generator (Note 5)
I
I
I
I
= –6.5µA
3.1
6.8
40
4.1
7.9
47.8
96.5
5.2
9.2
56
%
%
%
%
DIM/SS
DIM/SS
DIM/SS
DIM/SS
= 0µA
= 21.5µA
= 52µA
95
98
PWMOUT Signal Generator Frequency
PWM = 47nF to GND, I
= 0µA
215
300
435
Hz
DIM/SS
PWMOUT, Gate Pin Drivers
PWMOUT Driver Output Rise Time (t )
C = 560pF
35
35
ns
ns
V
r
L
PWMOUT Driver Output Fall Time (t )
C = 560pF
L
f
PWMOUT Output Low (V
)
OL
PWM = 0V
0.05
PWMOUT Output High (V
)
INTV
–
–
V
OH
CC
0.05
GATE Output Rise Time (t )
C = 3300pF
25
25
ns
ns
V
r
L
GATE Output Fall Time (t )
C = 3300pF
L
f
GATE Output Low (V
)
OL
0.1
GATE Output High (V
)
OH
INTV
0.05
V
CC
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Do not apply a positive or negative voltage or current source to
GATE or PWMOUT pins, otherwise permanent damage may occur.
Note 3: The LT3761E is guaranteed to meet performance specifications
from the 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3761I is guaranteed over the full –40°C to 125°C operating junction
temperature range. The LT3761H is guaranteed over the full –40°C to
150°C operating junction temperature range. Operating lifetime is derated
at junction temperatures greater than 125°C.
Note 4: The LT3761 includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed the maximum operating junction temperature
when overtemperature protection is active. Continuous operation above
the specified maximum junction temperature may impair device reliability.
Note 5: PWMOUT Duty Ratio is calculated:
Duty = I
/(I
+ I
PWMDN
)
PWMUP PWMUP
3761f
4
LT3761
Typical perFormance characTerisTics TA = 25°C, unless otherwise noted.
V
ISP-ISN Threshold
VISP-ISN Threshold
vs ISP Voltage
Full-Scale VISP-ISN Threshold
vs Temperature
vs CTRL Voltage
260
258
256
254
252
250
248
246
244
300
250
200
150
100
50
260
255
250
245
240
CTRL = 2V
ISN = 0
ISP = 48V
0
–50
0
0.5
1
1.5
2
0
20
40
60
80
–50 –25
0
25 50 75 100 125 150
CTRL VOLTAGE (V)
ISP VOLTAGE (V)
TEMPERATURE (°C)
3761 G02
3761 G03
3761 G01
FB Regulation Voltage (VFB
vs Temperature
ꢀ
VREF Source Current
vs Temperature
VISP-ISN Threshold vs FB Voltage
1.270
1.265
1.260
1.255
1.250
1.245
1.240
200
190
180
170
160
150
300
250
200
150
100
50
CTRL = 2V
CTRL = 0.5V
0
–50
0
25 50 75 100 125 150
–50 –25
0
25 50 75 100 125 150
–25
1.20 1.21 1.22 1.23 1.24 1.25 1.26
TEMPERATURE (°C)
TEMPERATURE (°C)
FB VOLTAGE (V)
3761 G04
3761 G06
3761 G05
Switching Frequency
vs Temperature
VREF Voltage vs Temperature
Switching Frequency vs RT
2.06
2.05
2.04
2.03
2.02
2.01
2.00
1.99
1.98
1000
420
415
410
405
400
395
390
385
380
R
T
= 25.5k
900
800
700
600
500
400
300
200
100
10
100
–50
0
25 50 75 100 125 150
–50
0
25 50 75 100 125 150
–25
–25
R
T
(kΩ)
TEMPERATURE (°C)
TEMPERATURE (°C)
3761 G07
3761 G09
3761 G08
3761f
5
LT3761
Typical perFormance characTerisTics TA = 25°C, unless otherwise noted.
SENSE Current Limit Threshold
vs Temperature
EN/UVLO Hysteresis Current
vs Temperature
EN/UVLO Threshold
vs Temperature
110
105
100
95
2.8
2.6
2.4
2.2
2.0
1.8
1.27
1.25
1.23
1.21
1.19
RISING
FALLING
90
–50 –25
0
25 50 75 100 125 150
–50
0
25 50 75 100 125 150
TEMPERATURE (°C)
3761 G10
–25
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3761 G12
TEMPERATURE (°C)
3761 G11
INTVCC Current Limit vs
vs Temperature
INTVCC Dropout Voltage
vs Current, Temperature
VISP-ISN C/10 Threshold
vs Temperature
40
38
36
34
32
30
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
–1.8
35
30
25
20
15
10
ISP = 24V
T
= –45°C
A
T
= 25°C
A
ISN = 0V
T
= 130°C
A
V
= 7V
5
IN
–50
0
25 50 75 100 125 150
–25
–50 –25
0
25 50 75 100 125 150
0
10
15
20
25
30
TEMPERATURE (°C)
LDO CURRENT (mA)
TEMPERATURE (°C)
3761 G15
3761 G14
3761 G13
PWM Signal Generator Duty Ratio
vs DIM/SS Current
PWM Signal Generator Frequency
vs Duty Ratio
PWMOUT Waveform
100
80
60
40
20
0
340
320
300
280
260
C
= 2.2nF
C
= 47nF
PWMOUT
PWM
PWM
INPUT
PWMOUT
5V/DIV
3761 G18
200ns/DIV
–10
0
10
20
30
40
50
0
20
40
60
80
100
DIM/SS CURRENT (µA)
DUTY RATIO (%)
3761 G16
3761 G17
3761f
6
LT3761
Typical perFormance characTerisTics TA = 25°C, unless otherwise noted.
DIM/SS Voltage
vs Current, Temperature
ISP/ISN Input Bias Current
vs CTRL Voltage, ISP = 48V
ISP/ISN Input Bias Current
vs CTRL Voltage, ISN = 0V
1.30
1.25
1.20
1.15
1.10
120
100
80
60
40
20
0
0
–40
ISP
ISN
ISP
T
= –45°C, 25°C
A
–80
T
= 130°C
A
–120
–160
–200
ISN
–10
0
10
20
30
40
50
0
0.5
1
1.5
2
0
0.5
1
1.5
2
DIM/SS CURRENT (µA)
CTRL (V)
CTRL (V)
3761 G20
3761 G21
3761 G19
PWMOUT Duty Ratio
vs Temperature, IDIM/SS = 0µA
PWMOUT Duty Ratio
vs Temperature, IDIM/SS = 21.5µA
VISP-ISN Overcurrent Threshold
vs Temperature
800
700
600
500
400
300
9.5
9.0
8.5
8.0
7.5
7.0
6.5
55
53
51
49
47
45
C
PWM
= 47nF
C
PWM
= 47nF
ISP = 24V
ISN = 0V
–50 –25
0
25 50 75 100 125 150
–50 –25
0
25 50 75 100 125 150
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3761 G24
3761 G22
3761 G23
3761f
7
LT3761
pin FuncTions
PWMOUT (Pin 1ꢀ: Buffered Version of PWM Signal for
Driving LED Load Disconnect NMOS or Level Shift. This
pin also serves in a protection function for the FB over-
voltage condition—will toggle if the FB input is greater
demand current state variable for the next PWM high
transition. Connect a capacitor between this pin and GND;
a resistor in series with the capacitor is recommended for
fast transient response.
than the FB regulation voltage (V ) plus 60mV (typical).
FB
CTRL (Pin 6ꢀ: Current Sense Threshold Adjustment Pin.
The PWMOUT pin is driven from INTV . Use of a FET
CC
Constant current regulation point V
is one-fourth
ISP-ISN
with gate cut-off voltage higher than 1V is recommended.
V
plus an offset for 0V ≤ CTRL ≤ 1V. For CTRL >
CTRL
1.2V the V
current regulation point is constant at
FB (Pin 2ꢀ: Voltage Loop Feedback Pin. FB is intended for
constant-voltageregulationorforLEDprotectionandopen
LEDdetection.Theinternaltransconductanceamplifierwith
ISP-ISN
the full-scale value of 250mV. For 1V ≤ CTRL ≤ 1.2V, the
dependence of V upon CTRL voltage transitions
ISP-ISN
fromalinearfunctiontoaconstantvalue, reaching98%of
full-scale value by CTRL = 1.1V. Do not leave this pin open.
output V will regulate FB to 1.25V (nominal) through the
C
DC/DC converter. If the FB input exceeds the regulation
voltage, V , minus 50mV and the voltage between ISP
FB
V
(Pin 7ꢀ: Voltage Reference Output Pin, Typically 2V.
REF
and ISN has dropped below the C/10 threshold of 25mV
(typical), the OPENLED pull-down is asserted. This action
may signal an open LED fault. If FB is driven above the FB
overvoltagethreshold,thePWMOUTandGATEpinswillbe
driven low to protect the LEDs from an overcurrent event.
Do not leave the FB pin open. If not used, connect to GND.
This pin drives a resistor divider for the CTRL pin, either
foranalogdimmingorfortemperaturelimit/compensation
of LED load. It can be bypassed with 10nF or greater, or
less than 50pF. Can supply up to 185µA (typical).
PWM (Pin 8ꢀ: A signal low turns off switcher, idles the
oscillator and disconnects the V pin from all internal
C
I
SN (Pin 3ꢀ: Connection Point for the Negative Terminal
of the Current Feedback Resistor. The constant output
current regulation can be programmed by I = 250mV/
loads. PWMOUT pin follows the PWM pin, except in fault
conditions. The PWM pin can be driven with a digital
signal to cause pulse width modulation (PWM) dimming
of an LED load. The digital signal should be capable of
sourcing or sinking 200μA at the high and low thresholds.
During start-up when DIM/SS is below 1V, the first rising
edge of PWM enables switching which continues until
LED
R
R
when CTRL > 1.2V or I
= (CTRL – 100mV)/(4 •
CC
LED
LED
). If ISN is greater than INTV , input bias current
LED
is typically 20μA flowing into the pin. Below INTV ,
CC
ISN bias current decreases until it flows out of the pin.
ISP (Pin 4ꢀ: Connection Point for the Positive Terminal of
V
≥ 25mV or SS ≥ 1V. Connecting a capacitor from
ISP-ISN
theCurrentFeedbackResistor. Inputbiascurrentdepends
PWM pin to GND invokes a self-driving oscillator where
internal pull-up and pull-down currents set a duty ratio
for the PWMOUT pin for dimming LEDs. The magnitude
of the pull-up/down currents is set by the current in the
DIM/SS pin. The capacitor on PWM sets the frequency of
the dimming signal. For hiccup mode response to output
short-circuit faults, connect this pin as shown in the ap-
plication titled Boost LED Driver with Output Short-Circuit
upon CTRL pin voltage. When it is greater than INTV
CC
it flows into the pin. Below INTV , ISP bias current
CC
decreases until it flows out of the pin. If the difference
between ISP and ISN exceeds 600mV (typical), then an
overcurrent event is detected. In response to this event,
the GATE and PWMOUT pins are driven low to protect
the switching regulator, a 1.5mA pulldown on PWM and
a 9mA pulldown on the DIM/SS pin are activated for 4µs.
Protection. If not used, connect the PWM pin to INTV .
CC
V (Pin 5ꢀ: Transconductance Error Amplifier Output Pin
C
OPENLED (Pin 9ꢀ: An open-drain pull-down on this pin
Used to Stabilize the Switching Regulator Control Loop
asserts if the FB input is greater than the FB regulation
with an RC Network. The V pin is high impedance when
C
voltage (V ) minus 50mV (typical) AND the difference
FB
PWM is low. This feature allows the V pin to store the
C
3761f
8
LT3761
pin FuncTions
between current sense inputs ISP and ISN is less than
25mV. To function, the pin requires an external pull-up
EN/UVLO (Pin 12ꢀ: Enable and Undervoltage Detect Pin.
An accurate 1.22V falling threshold with externally pro-
grammable hysteresis causes the switching regulator to
shut down when power is insufficient to maintain output
regulation.Abovethe1.24V(typical)risingenablethreshold
(but below 2.5V), EN/UVLO input bias current is sub-μA.
Below the 1.22V (typical) falling threshold, an accurate
2.3μA (typical) pull-down current is enabled so the user
can define the rising hysteresis with the external resistor
selection. An undervoltage condition causes the GATE
and PWMOUT pins to transition low and resets soft-start.
resistor, usually to INTV . When the PWM input is low
CC
and the DC/DC converter is idle, the OPENLED condition
is latched to the last valid state when the PWM input was
high. When PWM input goes high again, the OPENLED
pin will be updated. This pin may be used to report transi-
tion from constant current regulation to constant voltage
regulation modes, for instance in a charger or current
limited voltage supply.
DIM/SS(Pin10ꢀ:Soft-StartandPWMOUTDimmingSignal
Tie to 0.4V, or less, to disable the device and reduce V
quiescent current below 1μA.
IN
GeneratorProgrammingPin.Thispinmodulatesswitching
regulator frequency and compensation pin voltage (V )
C
clamp when it is below 1V. The soft-start interval is set
with an external capacitor and the DIM/SS pin charging
current. The pin has an internal 12μA (typical) pull-up
current source. The soft-start pin is reset to GND by an
undervoltage condition (detected at the EN/UVLO pin),
INTV (Pin13ꢀ:Currentlimited,lowdropoutlinearregula-
CC
tor regulates to 7.85V (typical) from V . Supplies internal
IN
loads,GATEandPWMOUTdrivers.Mustbebypassedwith
a 1µF ceramic capacitor placed close to the pin and to the
exposed pad GND of the IC.
INTV undervoltage, overcurrent event sensed at ISP/
CC
V (Pin 14ꢀ: Power Supply for Internal Loads and INTV
IN
CC
ISN, or thermal limit. After initial start-up with EN/UVLO,
DIM/SSisforcedlowuntilthefirstPWMrisingedge.When
DIM/SS reaches the steady-state voltage (~1.17V), the
charging current (sum of internal and external currents) is
sensedandusedtosetthePWMpincharginganddischarge
currents and threshold hysteresis. In this manner, the SS
chargingcurrentsetsthedutycycleofthePWMOUTsignal
generator associated with the PWM pin. This pin should
always have a capacitor to GND, minimum 560pF value,
when used with the PWMOUT signal generator function.
Place the PWM pin capacitor close to the IC.
Regulator. Must be locally bypassed with a 0.22µF (or
larger) low ESR capacitor placed close to the pin.
SENSE (Pin 15ꢀ: The Current Sense Input for the Switch
ControlLoop. KelvinconnecttheSENSEpintothepositive
terminal of the switch current sense resistor in the source
of the external power NFET. The negative terminal of the
switch current sense resistor should be Kelvin connected
to the exposed pad (GND) of the LT3761.
GATE(Pin16ꢀ:N-channelFETGateDriverOutput.Switches
betweenINTV andGND.DriventoGNDduringshutdown,
CC
fault or idle states.
RT (Pin 11ꢀ: Switching Frequency Adjustment Pin. Set the
frequency using a resistor to GND (for resistor values, see
the Typical Performance curve or Table 2). Do not leave
the RT pin open. Place the resistor close to the IC.
GND (Exposed Pad Pin 17ꢀ: Ground. This pin also serves
as current sense input for the control loop, sensing the
negative terminal of the current sense resistor. Solder the
exposed pad directly to the ground plane.
3761f
9
LT3761
block Diagram
PWMOUT
V
IN
–
+
185µA
FB
V
REF
LDO
–
+
1.3V
1.25V
OVFB
COMPARATOR
–
+
A8
INTV
7.85V
CC
A7
2.02V
0.8V + F3(I
)
–
+
DIM/SS
F1(I
)
DIM/SS
PWM
CTRL
S
–
+
PWMINT
R
Q
0.8V
F2(I
)
DIM/SS
PWM LATCH
+
GATE
1.5mA
FAULT
A2
R
Q
CTRL
100mV
DRIVER
–
S
BUFFER
10µA
×1/4
A3
1V
CLAMP
+
–
105mV
SENSE
GND
I
LED
I
ISP
ISN
A1
SWITCH
–
+
CURRENT MODE
COMPARATOR
10µA AT
g
m
+
–
+
–
A1 = A1
R
LED
A4
SENSE
R
SNS
I
CC EAMP
RAMP
A5
GENERATOR
1.25V
+
–
10µA AT
FB = 1.25V
g
m
FB
I
100kHz TO 1MHz
OSCILLATOR
DIM_SS
OPENLED
DETECT
CV EAMP
V
C
OPENLED
LOGIC
PWMINT
25mV
1V
+
+
–
EN/UVLO
1.22V
–
+
A6
FREQ
PROG
ISN
+
–
–
+
SHDN
ISP
FAULT
2.3µA
12µA
1.2V
FB
ISP > ISN + 0.6V
T > 165°C
BANDGAP
REFERENCE
FAULT
LOGIC
DIM/SS
RT
3761 BD
3761f
10
LT3761
operaTion
TheLT3761isaconstant-frequency,currentmodecontrol-
ler with a low side NMOS gate driver. The GATE pin and
PWMOUT pin drivers and other chip loads are powered
state of the PWM comparator. The difference between
ISP and ISN is monitored to determine if the output is in
a short-circuit condition. If the difference between ISP
and ISN is greater than 600mV (typical), the SR latch will
be reset regardless of the PWM comparator. The DIM/SS
pin will be pulled down and the PWMOUT and GATE pins
forced low for at least 4µs. These functions are intended
to protect the power switch as well as various external
components in the power path of the DC/DC converter.
from INTV , which is an internally regulated supply. In
CC
the discussion that follows it will be helpful to refer to
the Block Diagram of the IC. In normal operation with the
PWM pin low, the GATE and PWMOUT pins are driven to
GND, the V pin is high impedance to store the previous
C
switching state on the external compensation capacitor,
and the ISP and ISN pin bias currents are reduced to
leakage levels. When the PWM pin transitions high, the
PWMOUT pin transitions high after a short delay. At the
same time, the internal oscillator wakes up and gener-
ates a pulse to set the PWM latch, turning on the external
power MOSFET switch (GATE goes high). A voltage input
proportional to the switch current, sensed by an external
current sense resistor between the SENSE and GND input
pins, is added to a stabilizing slope compensation ramp
and the resulting switch current sense signal is fed into
the negative terminal of the PWM comparator. The current
in the external inductor increases steadily during the time
the switch is on. When the switch current sense voltage
In voltage feedback mode, the operation is similar to that
described above, except the voltage at the V pin is set by
C
the amplified difference of the internal reference of 1.25V
and the FB pin. If FB is lower than the reference voltage,
the switch current will increase; if FB is higher than the
referencevoltage,theswitchdemandcurrentwilldecrease.
The LED current sense feedback interacts with the FB
voltage feedback so that FB will not exceed the internal
reference and the voltage between ISP and ISN will not
exceed the threshold set by the CTRL pin. For accurate
currentorvoltageregulation,itisnecessarytobesurethat
under normal operating conditions the appropriate loop is
dominant. To deactivate the voltage loop entirely, FB can
be connected to GND. To deactivate the LED current loop
entirely, the ISP and ISN should be tied together and the
exceeds the output of the error amplifier, labeled V , the
C
latch is reset and the switch is turned off. During the
switch-off phase, the inductor current decreases. At the
completion of each oscillator cycle, internal signals such
as slope compensation return to their starting points and
a new cycle begins with the set pulse from the oscillator.
CTRL input tied to V
.
REF
Two LED specific functions featured on the LT3761 are
controlled by the voltage feedback pin. First, when the
FB pin exceeds a voltage 50mV lower (–4%) than the FB
regulationvoltage, andthedifferencevoltagebetweenISP
and ISN is below 25mV (typical), the pull-down driver on
the OPENLED pin is activated. This function provides a
status indicator that the load may be disconnected and
the constant-voltage feedback loop is taking control of the
switchingregulator.TheOPENLEDpinde-assertsonlywhen
PWM is high and FB drops below the voltage threshold. FB
overvoltage is the second protective function. When the
FB pin exceeds the FB regulation voltage by 60mV (plus
5% typical), the PWMOUT pin is driven low, ignoring the
state of the PWM input. In the case where the PWMOUT
pin drives a disconnect NFET, this action isolates the
LED load from GND, preventing excessive current from
damaging the LEDs.
Through this repetitive action, the PWM control algorithm
establishes a switch duty cycle to regulate a current or
voltage in the load. The V signal is integrated over many
C
switching cycles and is an amplified version of the differ-
ence between the LED current sense voltage, measured
between ISP and ISN, and the target difference voltage set
by the CTRL pin. In this manner, the error amplifier sets
the correct peak switch current level to keep the LED cur-
rent in regulation. If the error amplifier output increases,
more current is demanded in the switch; if it decreases,
lesscurrentisdemanded. Theswitchcurrentismonitored
during the on-phase and the voltage across the SENSE
pin is not allowed to exceed the current limit threshold of
105mV(typical).IftheSENSEpinexceedsthecurrentlimit
threshold, the SR latch is reset regardless of the output
3761f
11
LT3761
applicaTions inFormaTion
INTV Regulator Bypassing and Operation
is below the threshold. The purpose of this current is to
allow the user to program the rising hysteresis. The fol-
lowing equations should be used to determine the value
of the resistors:
CC
The INTV pin requires a capacitor for stable operation
CC
and to store the charge for the large GATE switching cur-
rents.Choosea10VratedlowESR,X7Rceramiccapacitor
for best performance. A 1μF capacitor will be adequate
for many applications. Place the capacitor close to the IC
R1+R2
VIN,FALLING =1.22•
R2
to minimize the trace length to the INTV pin and also
CC
VIN,RISING = 2.3µA•R1 + V
IN,FALLING
to the IC ground.
An internal current limit on the INTV output protects
V
CC
IN
the LT3761 from excessive on-chip power dissipation.
The minimum value of this current should be considered
when choosing the switching NMOS and the operating
frequency.
R1
LT3761
EN/UVLO
R2
3761 F01
I
can be calculated from the following equation:
INTVCC
Figure 1. Resistor Connection to Set
VIN Undervoltage Shutdown Threshold
I
= Q • f
OSC
INTVCC
G
CarefulchoiceofalowerQ FETwillallowhigherswitching
G
LED Current Programming
The LED current is programmed by placing an appropriate
value current sense resistor, R , in series with the LED
frequencies, leadingtosmallermagnetics. TheINTV pin
CC
has its own undervoltage disable set to 4.1V (typical) to
LED
protect the external FETs from excessive power dissipa-
string. The voltage drop across R
is (Kelvin) sensed
LED
tion caused by not being fully enhanced. If the INTV pin
CC
by the ISP and ISN pins. A half watt resistor is usually
a good choice. To give the best accuracy, sensing of the
current should be done at the top of the LED string. If this
option is not available then the current may be sensed
at the bottom of the string, or in the source of the PWM
disconnect NFET driven by the PWMOUT signal. A unique
case of GND sensing is the inverting converter shown in
the applications where the LED current is sensed in the
cathode of the power Schottky rectifier. This configuration
allows the LED anode to be grounded for heat sinking. In
this case, it is important to lowpass filter the discontinu-
ous current signal. Input bias currents for the ISP and ISN
inputsareshowninthetypicalperformancecharacteristics
andshouldbeconsideredwhenplacingaresistorinseries
with the ISP or ISN pins.
drops below the UVLO threshold, the GATE and PWMOUT
pins will be forced to 0V and the soft-start pin will be reset.
Iftheinputvoltage,V ,willnotexceed8V,thentheINTV
IN
CC
pin could be connected to the input supply. Be aware that
a small current (less than 13μA) will load the INTV
CC
in shutdown. This action allows the LT3761 to operate
from V as low as 4.5V. If V is normally above, but
IN
IN
occasionally drops below the INTV regulation voltage,
CC
then the minimum operating V will be close to 5V. This
IN
value is determined by the dropout voltage of the linear
regulator and the INTV undervoltage lockout threshold
CC
mentioned above.
Programming the Turn-On and Turn-Off Thresholds
with the EN/UVLO Pin
The CTRL pin should be tied to a voltage higher than 1.2V
to get the full-scale 250mV (typical) threshold across the
sense resistor. The CTRL pin can also be used to dim the
The power supply undervoltage lockout (UVLO) value can
beaccuratelysetbytheresistordividertotheEN/UVLOpin.
A small 2.3μA pull-down current is active when EN/UVLO
3761f
12
LT3761
applicaTions inFormaTion
LED current to zero, although relative accuracy decreases
with the decreasing voltage sense threshold. When the
CTRL pin voltage is less than 1V, the LED current is:
50mV should not cause mis-operation, but may lead to
noticeable offset between the current regulation and the
user-programmed value.
VCTRL −100mV
Programming Output Voltage (Constant Voltage
Regulationꢀ or Open LED/Overvoltage Threshold
ILED
=
RLED • 4
For a boost or SEPIC application, the output voltage can
be set by selecting the values of R3 and R4 (see Figure 2)
according to the following equation:
WhentheCTRLpinvoltageisbetween1Vand1.2VtheLED
current varies with CTRL, but departs from the previous
equation by an increasing amount as the CTRL voltage
increases. Ultimately, the LED current no longer varies for
R3+R4
VOUT = 1.25 •
R4
CTRL ≥ 1.2V. At CTRL = 1.1V, the value of I is ~98% of
LED
the equation’s estimate. Some values are listed in Table 1.
V
Table 1. (ISP-ISNꢀ Threshold vs CTRL
OUT
V
(Vꢀ
(ISP-ISNꢀ Threshold (mVꢀ
CRTL
R3
LT3761
1.0
225
236
FB
1.05
1.1
R4
244.5
248.5
250
3761 F02
1.15
1.2
Figure 2. Feedback Resistor Connection for
Boost or SEPIC LED Driver
When CTRL is higher than 1.2V, the LED current is regu-
lated to:
ForaboosttypeLEDdriver,settheresistorfromtheoutput
to the FB pin such that the expected voltage level during
normal operation will not exceed 1.17V. For an LED driver
of buck mode or a buck-boost mode configuration, the
output voltage is typically level-shifted to a signal with
respect to GND as illustrated in Figure 3. The output can
be expressed as:
250mV
RLED
ILED
=
The CTRL pin should not be left open (tie to V
if not
REF
used). The CTRL pin can also be used in conjunction with
R3
VOUT = VBE + 1.25 •
R4
a thermistor to provide overtemperature protection for
the LED load, or with a resistor divider to V to reduce
IN
output power and switching current when V is low.
IN
The presence of a time varying differential voltage signal
(ripple) across ISP and ISN at the switching frequency
is expected. The amplitude of this signal is increased by
high LED load current, low switching frequency and/or a
smaller value output filter capacitor. Some level of ripple
signal is acceptable: the compensation capacitor on the
+
R3
R
SEN(EXT)
V
C
OUT
OUT
LED
ARRAY
100k
–
LT3761
3761 F03
FB
R4
V pin filters the signal so the average difference between
C
ISP and ISN is regulated to the user-programmed value.
Ripple voltage amplitude (peak-to-peak) in excess of
Figure 3. Feedback Resistor Connection for
Buck Mode or Buck-Boost Mode LED Driver
3761f
13
LT3761
applicaTions inFormaTion
ISP/ISN Short-Circuit Protection Feature
prevent the ISP node from discharging during the PWM
signal low phase.
The ISP/ISN pins have a protection feature independent
of their LED current sense feature. The purpose of this
feature is to prevent the development of excessive cur-
rents that could damage the power components or the
The minimum PWM on or off time is affected by choice of
operatingfrequencyandexternalcomponentselection.The
data sheet application titled “Boost LED Driver for 30kHz
PWM Dimming” demonstrates regulated current pulses
as short as 3μs are achievable. The best overall combina-
tion of PWM and analog dimming capability is available if
the minimum PWM pulse is at least six switching cycles.
load. The action threshold (V
> 600mV, typical) is
ISP-ISN
above the default LED current sense threshold, so that
no interference will occur with current regulation. This
feature acts in the same manner as switch current limit:
it prevents switch turn-on until the ISP/ISN difference
falls below the threshold. Exceeding the threshold also
activates a pull-down on the SS and PWM pins and causes
the GATE and PWMOUT pins to be driven low for at least
4µs. If an overcurrent condition is sensed at ISP/ISN and
the PWM pin is configured either to make an internal
dimming signal, or for always-on operation as shown in
the application titled Boost LED Driver with Output Short
Protection, then the LT3761 will enter a hiccup mode of
operation. In this mode, after the initial response to the
fault, the PWMOUT pin re-enables the output switch at an
interval set by the capacitor on the PWM pin. If the fault
is still present, the PWMOUT pin will go low after a short
delay (typically 7µs) and turn off the output switch. This
fault-retry sequence continues until the fault is no longer
present in the output.
A low duty cycle PWM signal can cause excessive start-up
timesifitwereallowedtointerruptthesoft-startsequence.
Therefore, once start-up is initiated by PWM > 1.3V, it will
ignore a logical disable by the external PWM input signal.
The device will continue to soft-start with switching and
PWMOUT enabled until either the voltage at SS reaches
the 1V level, or the output current reaches one-tenth of
the full-scale current. At this point the device will begin
following the dimming control as designated by PWM.
Disconnect Switch Selection
An NMOS in series with the LED string at the cathode is
recommended in most LT3761 applications to improve
the PWM dimming. The NMOS BV
rating should be as
DSS
high as the open LED regulation voltage set by the FB pin,
whichistypicallythesameratingasthepowerswitchofthe
converter. ThemaximumcontinuousdraincurrentI
PWM Dimming Control
D(MAX)
rating should be higher than the maximum LED current.
There are two methods to control the current source for
dimming using the LT3761. One method uses the CTRL
pin to adjust the current regulated in the LEDs. A second
method uses the PWM pin to modulate the current source
between zero and full current to achieve a precisely pro-
grammed average current. To make PWM dimming more
A PMOS high side disconnect is needed for buck mode,
buck-boost mode or an output short circuit protected
boost. A level shift to drive the PMOS switch is shown
in the application schematic Boost LED Driver with Out-
put Short Circuit Protection. In the case of a high side
disconnect follow the same guidelines as for the NMOS
regarding voltage and current ratings. It is important to
include a bypass diode to GND at the drain of the PMOS
switch to ensure that the voltage rating of this switch is
not exceeded during transient fault events.
accurate, the switch demand current is stored on the V
C
node during the quiescent phase when PWM is low. This
feature minimizes recovery time when the PWM signal
goes high. To further improve the recovery time, a dis-
connect switch may be used in the LED current path to
3761f
14
LT3761
applicaTions inFormaTion
PWM Dimming Signal Generator
Programming the Switching Frequency
TheLT3761featuresaPWMdimmingsignalgeneratorwith
programmable duty cycle. The frequency of the square
The RT frequency adjust pin allows the user to program
the switching frequency (f ) from 100kHz to 1MHz to
SW
wave signal at PWMOUT is set by a capacitor C
from
optimize efficiency/performance or external component
size. Higher frequency operation yields smaller compo-
nent size but increases switching losses and gate driving
current, and may not allow sufficiently high or low duty
cycle operation. Lower frequency operation gives better
performance at the cost of larger external component
PWM
the PWM pin to GND according to the equation:
f
= 14kHz • nF/C
PWM
PWM
The duty cycle of the signal at PWMOUT is set by a µA
scale current into the DIM/SS pin (see Figure 4 and the
Typical Performance Characteristics).
size. For an appropriate R resistor value see Table 2. An
T
external resistor from the RT pin to GND is required—do
100
C
= 47nF
not leave this pin open.
PWM
80
60
40
20
0
Table 2. Switching Frequency (fSWꢀ vs RT Value
f
SW
(kHzꢀ
R (kΩꢀ
T
100
95.3
48.7
33.2
25.5
20.5
16.9
14.3
12.1
10.7
8.87
200
300
400
500
600
700
800
900
1000
0
2
4
6
8
DIM VOLTAGE (V)
3761 F04
Figure 4. PWMOUT Duty Ratio vs DIM Voltage for RDIM = 124k
Internally generated pull-up and pull-down currents on
the PWM pin are used to charge and discharge its capaci-
tor between the high and low thresholds to generate the
duty cycle signal. These current signals on the PWM pin
are small enough so they can be easily overdriven by a
digital signal from a microcontroller to obtain very high
dimming performance. The practical minimum duty cycle
using the internal signal generator is about 4% if the DIM/
SS pin is used to adjust the dimming ratio. Consult the
factory for techniques for and limitations of generating a
duty ratio less than 4% using the internal generator. For
always on operation, the PWM pin should be connected
as shown in the application Boost LED Driver with Output
Short Protection.
Duty Cycle Considerations
Switching duty cycle is a key variable defining converter
operation, therefore, its limits must be considered when
programming the switching frequency for a particular ap-
plication. The minimum duty cycle of the switch is limited
bythefixedminimumon-timeandtheswitchingfrequency
(f ). The maximum duty cycle of the switch is limited
SW
by the fixed minimum off-time and f . The following
SW
equations express the minimum/maximum duty cycle:
Min Duty Cycle = 220ns • f
SW
Max Duty Cycle = 1 – 170ns • f
SW
3761f
15
LT3761
applicaTions inFormaTion
300
ThemajorityofthepowerdissipationintheICcomesfrom
the supply current needed to drive the gate capacitance of
the external power MOSFET. This gate drive current can
be calculated as:
C
GATE
= 3300pF
250
200
150
100
50
MINIMUM ON-TIME
MINIMUM OFF-TIME
I
= f • Q
SW G
GATE
A low Q power MOSFET should always be used when
G
operating at high input voltages, and the switching fre-
quency should also be chosen carefully to ensure that
the IC does not exceed a safe junction temperature. The
internaljunctiontemperatureoftheICcanbeestimatedby:
0
–50
0
25 50 75 100 125 150
TEMPERATURE (°C)
–25
3761 F05
T = T + [V (I + f • Q ) • θ ]
J
A
IN
Q
SW
G
JA
Figure 5. Typical Minimum On and Off
GATE Pulse Width vs Temperature
where T is the ambient temperature, I is the quiescent
A
Q
currentofthepart(maximum2mA)andθ isthepackage
JA
Besides the limitation by the minimum off-time, it is
also recommended to choose the maximum duty cycle
below 95%.
thermal impedance (43°C/W for the MSE package). For
example, an application has T
= 85°C, V
=
A(MAX)
IN(MAX)
40V, f = 400kHz, and having a FET with Q = 20nC, the
SW
G
maximum IC junction temperature will be approximately:
VLED − V
IN
DBOOST
=
VLED
T = 85°C + [40V • (2mA + 400kHz • 20nC) • 43°C/W] =
J
102°C
VLED
DBUCK _MODE
=
=
The exposed pad on the bottom of the package must be
soldered to a ground plane. This ground should then be
connectedtoaninternalcoppergroundplanewiththermal
vias placed directly under the package to spread out the
heat dissipated by the IC.
V
IN
VLED
VLED + V
DSEPIC,DCUK
IN
Thermal Considerations
Open LED Reporting – Constant Voltage Regulation
Status Pin
The LT3761 is rated to a maximum input voltage of 60V.
Careful attention must be paid to the internal power dis-
sipation of the IC at higher input voltages to ensure that a
junction temperature of 125°C (150°C for H-grade) is not
exceeded. This junction limit is especially important when
operatingathighambienttemperatures.IfLT3761junction
temperature reaches 165°C, the GATE and PWMOUT pins
willbedriventoGNDandthesoft-start(DIM/SS)andPWM
pins will be discharged to GND. Switching will be enabled
after device temperature is reduced 10°C. This function is
intended to protect the device during momentary thermal
overload conditions.
The LT3761 provides an open-drain status pin, OPENLED,
that pulls low when the FB pin is within 50mV of its 1.25V
regulated voltage AND output current sensed by V
ISP-ISN
has reduced to 25mV, or 10% of the full-scale value. The
10%outputcurrentqualification(C/10)isuniqueforanLED
driver but fully compatible with open LED indication – the
qualificationisalwayssatisfiedsinceforanopenload,zero
current flows in the load. The C/10 feature is particularly
useful in the case where OPENLED is used to indicate the
end of a battery charging cycle and terminate charging or
transition to a float charge mode.
3761f
16
LT3761
applicaTions inFormaTion
For monitoring the LED string voltage, if the open LED
clamp voltage is programmed correctly using the FB
resistor divider then the FB pin should not exceed 1.18V
when LEDs are connected. If the OPENLED pulldown is
asserted and the PWM pin transitions low, the pulldown
will continue to be asserted until the next rising edge of
PWM even if FB falls below the OPENLED threshold.
Therefore, a 10μF capacitor is an appropriate selection
for a 400kHz boost regulator with 12V input, 48V output
and 1A load.
With the same V voltage ripple of 100mV, the input ca-
IN
pacitor for a buck converter can be estimated as follows:
µF
A •µs
CIN(µF) = ILED(A)• tSW(µs)• 4.7 •
I
LED
C10
COMPARATOR
ISP
ISN
A 10μF input capacitor is an appropriate selection for a
400kHz buck mode converter with a 1A load.
–
+
OPENLED
R
LED
25mV
In the buck mode configuration, the input capacitor has
large pulsed currents due to the current returned through
the Schottky diode when the switch is off. In this buck
convertercaseitisimportanttoplacethecapacitorasclose
as possible to the Schottky diode and to the GND return
of the switch (i.e., the sense resistor). It is also important
to consider the ripple current rating of the capacitor. For
best reliability, this capacitor should have low ESR and
ESL and have an adequate ripple current rating.
1mA
S
Q
R
1.2V
–
+
FB
OPEN LED
COMPARATOR
PWM
1. OPENLED ASSERTS WHEN V
ISP-ISN
2. OPENLED DE-ASSERTS WHEN FB < 1.19V, AND PWM LOGIC 1 = 1V
< 25mV AND FB > 1.2V, AND IS LATCHED
Table 3. Recommended Ceramic Capacitor Manufacturers
MANUFACTURER
TDK
WEB
3. ANY FAULT CONDITION RESETS THE LATCH, SO LT3761 STARTS UP
WITH OPENLED DE-ASSERTED
www.tdk.com
www.kemet.com
www.murata.com
www.t-yuden.com
3761 F06
Kemet
Figure 6. OPENLED Logic Block Diagram
Murata
Taiyo Yuden
Input Capacitor Selection
Theinputcapacitorsuppliesthetransientinputcurrentfor
the power inductor of the converter and must be placed
andsizedaccordingtothetransientcurrentrequirements.
Theswitchingfrequency,outputcurrentandtolerableinput
voltage ripple are key inputs to estimating the capacitor
value. An X7R type ceramic capacitor is usually the best
choicesinceithastheleastvariationwithtemperatureand
DC bias. Typically, boost and SEPIC converters require a
lower value capacitor than a buck mode converter. As-
suming that a 100mV input voltage ripple is acceptable,
the required capacitor value for a boost converter can be
estimated as follows:
Output Capacitor Selection
The selection of the output capacitor depends on the load
and converter configuration, i.e., step-up or step-down
and the operating frequency. For LED applications, the
equivalent resistance of the LED is typically low and the
output filter capacitor should be sized to attenuate the
current ripple. Use of X7R type ceramic capacitors is
recommended.
To achieve the same LED ripple current, the required filter
capacitor is larger in the boost and buck-boost mode ap-
plications than that in the buck mode applications. Lower
operating frequencies will require proportionately higher
capacitor values.
µF
VOUT
CIN(µF) = ILED(A)•
• tSW(µs)•
V
A •µs
IN
3761f
17
LT3761
applicaTions inFormaTion
Soft-Start Capacitor Selection
Forapplicationsoperatingathighinputoroutputvoltages,
the power switch is typically chosen for drain voltage V
DS
For many applications, it is important to minimize the
inrush current at start-up. The built-in soft-start circuit
significantly reduces the start-up current spike and output
voltage overshoot. Connect a capacitor from the DIM/SS
pin to GND to use this feature. The soft-start interval is
set by the softstart capacitor selection according to the
equation:
rating and low gate charge Q . Consideration of switch
G
on-resistance, R
, is usually secondary because
DS(ON)
switchinglossesdominatepowerloss.TheINTV regula-
CC
tor on the LT3761 has a fixed current limit to protect the IC
from excessive power dissipation at high V , so the FET
IN
G
should be chosen so that the product of Q at 7.85V and
switching frequency does not exceed the INTV current
CC
1.2V
12µA
100µs
nF
limit. For driving LEDs be careful to choose a switch with
TSS = CSS
•
= CSS •
a V rating that exceeds the threshold set by the FB pin
DS
in case of an open-load fault. The required power MOSFET
provided there is no additional current supplied to the
DIM/SS pin for programming the duty cycle of the PWM
dimming signal generator. A typical value for the soft-start
capacitor is 10nF which gives a 1ms start-up interval. The
soft-start pin reduces the oscillator frequency and the
maximum current in the switch.
V
DS
rating of different topologies can be estimated using
the following equations plus a diode forward voltage, and
any additional ringing across its drain-to-source during
its off-time.
Boost: V > V
DS
LED
Buck Mode: V > V
DS
IN(MAX)
The soft-start capacitor discharges if one of the follow-
ing events occurs: the EN/UVLO falls below its threshold;
output overcurrent is detected at the ISP/ISN pins; IC
SEPIC, Inverting: V > V
+ V
LED
DS
IN(MAX)
Since the LT3761 gate driver is powered from the 7.85V
overtemperature; or INTV undervoltage. During start-
CC
INTV ,the6VratedMOSFETworkswellforalltheLT3761
CC
up with EN/UVLO, charging of the soft-start capacitor is
enabled after the first PWM high period. In the start-up
sequence, after switching is enabled by PWM the switch-
applications.
It is prudent to measure the MOSFET temperature in
steady state to ensure that absolute maximum ratings
are not exceeded.
ing continues until V
> 25mV or DIM/SS > 1V. PWM
ISP-ISN
pin negative edges during this start-up interval are not
processed until one of these two conditions are met so
that the regulator can reach steady state operation shortly
after PWM dimming commences.
SeveralMOSFETvendorsarelistedinTable4.TheMOSFETs
used in the application circuits in this data sheet have
been found to work well with the LT3761. Consult factory
applications for other recommended MOSFETs.
Power MOSFET Selection
Table 4. Recommended Power MOSFET Manufacturers
The selection criteria for the power MOSFET includes
MANUFACTURER
Vishay Siliconix
Infineon
WEB
the drain-source breakdown voltage (V ), the threshold
DS
www.vishay.com
www.infineon.com
www.renesas.com
voltage (V
), the on-resistance (R
), the gate
GS(TH)
DS(ON)
to source and gate to drain charges (Q and Q ), the
GS
GD
Renesas
maximumdraincurrent(I
resistances (R , R ).
)andtheMOSFET’sthermal
D(MAX)
θJC θJA
3761f
18
LT3761
applicaTions inFormaTion
Schottky Rectifier Selection
For buck mode, select a resistor according to:
0.07V
ILED
The power Schottky diode conducts current during the
interval when the switch is turned off. Select a diode
rated for the maximum SW voltage as described in the
section on power MOSFET selection. If using the PWM
featurefordimming, itmaybeimportanttoconsiderdiode
leakage, which increases with the temperature, from the
output during the PWM low interval. Therefore, choose
the Schottky diode with sufficiently low leakage current.
Table 5hassomerecommended componentvendors. The
RSENSE,BUCK
≤
These equations provide an estimate of the sense resistor
value based on reasonable assumptions about induc-
tor current ripple during steady state switching. Lower
values of sense resistor may be required in applications
where inductor ripple current is higher. Examples include
applications with current limited operation at high duty
cycle, and those with discontinuous conduction mode
(DCM) switching. It is always prudent to verify the peak
inductor current in the application to ensure the sense
resistor selection provides margin to the SENSE current
limit threshold.
diode current and V should be considered when select-
F
ing the diode to be sure that power dissipation does not
exceed the rating of the diode. The power dissipated by
the diode in a converter is:
P = I • V • (1-D )
MAX
D
D
F
The placement of R
should be close to the source of
SENSE
It is prudent to measure the diode temperature in steady
state to ensure that its absolute maximum ratings are not
exceeded.
the NMOS FET and GND of the LT3761. The SENSE input
to LT3761 should be a Kelvin connection to the positive
terminal of R
. Verify the power on the resistor to
ensure that it does not exceed the rated maximum.
SENSE
Table 5. Schottky Rectifier Manufacturers
MANUFACTURER
Vishay
WEB
Inductor Selection
www.vishay.com
www.centralsemi.com
www.diodes.com
Central Semiconductor
Diodes, Inc.
TheinductorusedwiththeLT3761shouldhaveasaturation
current rating appropriate to the maximum switch current
selectedwiththeR
resistor.Chooseaninductorvalue
SENSE
Sense Resistor Selection
based on operating frequency, input and output voltage to
provide a current mode ramp on SENSE during the switch
on-time of approximately 20mV magnitude. The following
equations are useful to estimate the inductor value for
continuousconductionmodeoperation(usetheminimum
value for V and maximum value for V ):
The resistor, R , between the source of the exter-
SENSE
nal NMOS FET and GND should be selected to provide
adequate switch current to drive the application without
exceeding the 105mV (typical) current limit threshold on
the SENSE pin of LT3761. For a boost converter, select a
resistor value according to:
IN
LED
RSENSE • VLED V – V
(
)
IN
LED
LBUCK
=
V • 0.07V
V • 0.02V • f
IN
IN
OSC
RSENSE,BOOST
≤
V
•ILED
LED
RSENSE • VLED • V
IN
LBUCK-BOOST
=
For buck-boost mode and SEPIC, select a resistor ac-
cording to:
VLED + V • 0.02V • f
IN
OSC
(
)
RSENSE • V
V
LED – VIN
(
)
IN
V • 0.07V
IN
LBOOST
=
RSENSE,BUCK-BOOST
≤
VLED • 0.02V • fOSC
V + V
I
(
)
IN
LED LED
3761f
19
LT3761
applicaTions inFormaTion
Use the equation for Buck-Boost when choosing an in-
ductor value for SEPIC – if the SEPIC inductor is coupled,
then the equation’s result can be used as is. If the SEPIC
uses two uncoupled inductors, then each should have a
inductance double the result of the equation.
and secondary inductors. The C should be sized to limit
DC
its voltage ripple. The power loss on the C ESR reduces
DC
theLEDdriverefficiency. Therefore, thesufficientlowESR
ceramic capacitors should be selected. The X5R or X7R
ceramic capacitor is recommended for C .
DC
Table 6 provides some recommended inductor vendors.
Board Layout
Table 6. Recommended Inductor Manufacturers
The high speed operation of the LT3761 demands care-
ful attention to board layout and component placement.
Figure 7 provides a suggested layout for the boost con-
verter. The exposed pad of the package is the only GND
terminal of the IC and is also important for its thermal
management. It is crucial to achieve a good electrical and
thermal contact between the exposed pad and the ground
planeoftheboard.Toreduceelectromagneticinterference
(EMI), it is important to minimize the area of the high dV/
dt switching node between the inductor, switch drain and
anode of the anode of the Schottky rectifier. Use a ground
plane under the switching node to eliminate interplane
coupling to sensitive signals.
MANUFACTURER
Coilcraft
WEB
www.coilcraft.com
www.cooperet.com
www.we-online.com
www.vishay.com
Cooper-Coiltronics
Würth-Midcom
Vishay
Loop Compensation
The LT3761 uses an internal transconductance error
amplifier whose V output compensates the control loop.
C
The external inductor, output capacitor and the compen-
sation resistor and capacitor determine the loop stability.
The inductor and output capacitor are chosen based on
performance, size and cost. The compensation resistor
Proper layout of the power paths with high di/dt is es-
sential to robust converter operation. The following high
di/dt loops of different topologies should be kept as tight
as possible to reduce inductive ringing:
and capacitor at V are selected to optimize control loop
C
responseandstability.FortypicalLEDapplications,a4.7nF
compensation capacitor at V is adequate, and a series
C
resistor should always be used to increase the slew rate
1. In boost configuration, the high di/dt loop of each chan-
nel contains the output capacitor, the sensing resistor,
the power NMOS and the Schottky diode.
on the V pin to maintain tighter regulation of LED current
C
during fast transients on the input supply to the converter.
The DC-Coupling Capacitor Selection for SEPIC
LED Driver
2. In buck mode configuration, the high di/dt loop of each
channelcontainstheinputcapacitor,thesensingresistor,
the power NMOS and the Schottky diode.
The DC voltage rating of the DC-coupling capacitor C
DC
connectedbetweentheprimaryandsecondaryinductors of
3.Inbuck-boostmodeconfiguration,thehighdi/dtloopof
eachchannelcontainsthecapacitorconnectingbetween
a SEPIC should be larger than the maximum input voltage:
V
and GND, the sensing resistor, the power NMOS
V
CDC
> V
IN(MAX)
OUT
and the Schottky diode.
C
has nearly a rectangular current waveform. During
DC
4. In SEPIC configuration, the high di/dt loop contains the
powerNMOS,senseresistor,outputcapacitor,Schottky
diode and the DC-coupling capacitor.
the switch off-time, the current through C is I , while
DC
VIN
approximately –I
voltage ripple causes current distortions on the primary
flows during the on-time. The C
LED
DC
3761f
20
LT3761
applicaTions inFormaTion
The ground terminal of the switch current sense resistor
should be star connected to the underside of the IC. Do
not extensively route high impedance signals such as FB
should Kelvin connecttotheGND oftheLT3761. Likewise,
thegroundterminalofthebypasscapacitorfortheINTV
and V , as they may pick up switching noise. In particular,
CC
C
regulator should be placed near the GND of the switching
avoid routing FB and PWMOUT in parallel for more than
a few millimeters on the board. Minimize resistance in
series with the SENSE input to avoid changes (most likely
reduction) to the switch current limit threshold.
path. Typically this requirement will result in the external
switchbeingclosesttotheIC,alongwiththeINTV bypass
CC
capacitor. The ground for the compensation network (V )
C
andotherDCcontrolsignals(e.g.,FB,PWM,DIM/SS,CTRL)
PGND AGND
DIM
V
OPENLED
REF CTRL
R
DIM
C
PWM
VIAS TO GROUND PLANES
C
SS
R
T
9
10
11
12
13
14
15
16
8
7
6
5
4
3
2
1
R2
R1
C
C
R
C
LAYER 2
GROUND
PLANE
x
x
V
OUT
VIA
CV
CC
SPLIT
L1
R3
R4
x
x
SENSE VIA
AGND
PGND
5
6
7
8
4
3
2
1
1
–
M2
3
LED
M1
2
R
SENSE
C
C
OUT
OUT
D1
C
IN
+
LED
R
LED
V
GND
IN
3761 F07
COMPONENT DESIGNATIONS REFER TO BOOST LED DRIVER FOR AUTOMOTIVE HEADLAMP SCHEMATIC
Figure 7. Suggested Layout of the Boost LED Driver for Automotive Headlamp in the Typical Applications Section
3761f
21
LT3761
Typical applicaTions
94% Efficient Boost LED Driver for Automotive Headlamp with 25:1 PWM Dimming
L1
10µH
D1
V
IN
8V TO
60V
C
R1
IN
Boost Efficiency and Output Current vs VIN
2.2µF
×2
V
IN
R3
499k
C
OUT
R
LED
0.25Ω
1A
M1
R
GATE
1M
EN/UVLO
2.2µF
100
96
92
88
84
80
1.6
1.4
1.2
1.0
0.8
0.6
100V
×4
R2
90.9k
PWM TIED TO INTV
CC
V
REF
SENSE
1M
LT3761
SENSE
R4
16.9k
10mΩ
CTRL
EFFICIENCY
GND
INTV
CC
140k
100k
FB
ISP
ISN
60W
OPENLED
DIM/SS
PWM
LED
DIM
STRING
R
OUTPUT CURRENT
DIM
PWMOUT
124k
V
RT INTV
CC
C
C
SS
0.01µF
R
T
R
C
INTV
C
28.7k
350kHz
CC
PWM
5.1k
47nF
C
VCC
1µF
C
C
300Hz
0
10
20
30
(V)
40
50
60
4.7nF
M2
V
IN
37551 TA02b
3761 TA02a
M1: INFINEON BSC123N08NS3-G
D1: DIODES INC PDS5100
(CURRENT DERATED FOR V < 10V)
IN
L1: COILTRONICS HC9-100-R
M2: VISHAY SILICONIX Si2328DS
OUT IN
C
, C : MURATA GRM42-2X7R225K100R
SEE SUGGESTED LAYOUT FIGURE 7
Boost LED Driver with Output Short-Circuit Protection with Externally Driven PWM
L1
10µH
D1
V
0.25Ω
IN
8V TO
60V
2.2µF
×2
100V
2.2µF
×4
100V
499k
V
IN
GATE
M1
EN/UVLO
V
REF
SENSE
90.9k
1M
LT3761
10mΩ
1k
CTRL
Q1
INTV
CC
GND
140k
2.4k
100k
ISP
ISN
M2
OPENLED
150pF
D2
1A
1M
PWM
PWMOUT
FB
DIM/SS
27k
INTV
Q2
V
C
RT INTV
CC
16.9k
Q3
CC
60W
LED
STRING
1k
5.1k
10nF
28.7k
350kHz
27k
4.7nF
2.2k
1µF
1N4148
3761 TA10
M1: INFINEON BSC123NO8NS3-G
D1: DIODES INC PDS5100
L1: COILTRONICS HC9-100-R
M2: VISHAY SILICONIX Si7113DN
D2: VISHAY 10BQ100
Q1, Q3: CENTRAL CMPT3906
Q2: ZETEX FMMT493
3761f
22
LT3761
Typical applicaTions
Boost LED Driver with Output Short-Circuit Protection with Internally Generated PWM
L1
10µH
D1
V
0.25Ω
IN
8V TO
60V
2.2µF
×2
100V
2.2µF
×4
100V
499k
V
IN
GATE
M1
EN/UVLO
V
REF
SENSE
90.9k
1M
LT3761
10mΩ
1k
CTRL
Q1
INTV
CC
GND
140k
2.4k
OPTION FOR
INTERNALLY GENERATED
PWM DIMMING
100k
ISP
ISN
M2
OPENLED
I
LED
1M
150pF
D2
124k
DIM
1A
+
DIM/SS
PWM
FB
LED
PWMOUT
RT INTV
CC
22nF
640Hz
V
C
60W
LED
STRING
16.9k
20k
Q2
28.7k
350kHz
10nF
5.1k
INTV
CC
1µF
4.7nF
1k
3761 TA09a
CURRENT DERATED
FOR V < 10V
IN
28k
M1: INFINEON BSC123NO8NS3-G
D1: DIODES INC PDS5100
L1: COILTRONICS HC9-100-R
M2: VISHAY SILICONIX Si7113DN
D2: VISHAY 10BQ100
1N4148
OPTIONAL CIRCUIT
FOR ALWAYS-ON
OPERATION
Q1: CENTRAL CMPT3906
Q2: ZETEX FMMT493
High Side Disconnect Internally Generated
PWM Dimming Waveform
Output Short-Circuit Waveform Showing Hiccup
Mode Operation with Internally Generated PWM
PWMOUT
DIM = 8V
V
= 24V, V
= 60V, DIM = 0V
LED
IN
PWMOUT
+
I
LED
2A/DIV
52V
+
+
LED SHORT TO GND
I
LED
V
LED
0.5A/DIV
0V
3761 TA09b
3761 TA09c
10µs/DIV
1ms/DIV
3761f
23
LT3761
Typical applicaTions
10W Grounded Anode Inverting LED Driver
2.2µF
×2
35V
L1
4.7µH
1:1
V
IN
5V TO
18V
3
1
10Ω
2
4
4.7µF
10V
4.7µF
25V
100k
34k
V
IN
D1
M1
GATE
EN/UVLO
SENSE
LT3761
10mΩ
91mΩ
–10V
CLAMP
GND
PWM
10Ω
OPENLED
ISN
ISP
M2
2.5A
0.47µF
59k
FB
–
LED
DIM/SS
V
REF
10W
LED
INTV
CC
CTRL
2k
10nF
0.01µF
PWMOUT
V
RT
C
1µF
M1: VISHAY SILICONIX Si4162DY (30V)
D1: DIODES PDS1040 CTL
L1: WÜRTH 744870004
2k
28.7k
350kHz
0.1µF
Q1
M2: VISHAY SILICONIX Si2312BDS (20V)
LED: CREE XLAMP XM-L
20k
Q1: ZETEX FMMT593
3761 TA04a
PWM Dimming Waveform
PWM
V
= 12V, V
= –3.6V
LED
IN
I
LED
1A/DIV
–
V
LED
2V/DIV
3761 TA04b
10µs/DIV
3761f
24
LT3761
Typical applicaTions
40W SEPIC LED Driver
C2
2.2µF
×2
50V
L1
10µH
1:1
D1
V
IN
8V TO
40V
3
1
C1
2
4
•
499k
2.2µF
×2
C3
10µF
×5
V
IN
GATE
0.15Ω
1.67A
M1
1M
EN/UVLO
50V
V
REF
SENSE
90.9k
35V
1M
LT3761
8mΩ
CTRL
49.9k
GND
FB
INTV
CC
133k
100k
40W
ISP
ISN
LED
OPENLED
PWM
STRING
DIM/SS
PWMOUT
V
RT INTV
C
CC
INTV
1µF
CC
28.7k
350kHz
10nF
10k
4.7nF
M2
3761 TA05a
M1: INFINEON BSC123NO8
D1: DIODES INC PDS5100
L1: COILCRAFT MSD1278-103
M2: VISHAY SILICONIX Si2306BDS
LED: CREE XLAMP XM-L (×7)
C1, C2: KEMET C1210C225K5
C3: TAIYO YUDEN UMK325BJ106M
SEPIC Efficiency,
Output Current vs VIN
PWM Dimming Waveform
2.1
1.8
1.5
1.2
0.9
0.6
100
96
92
88
84
80
PWM
OUTPUT CURRENT
EFFICIENCY
I
LED
0.5A/DIV
3761 TA05c
100µs/DIV
0
20
(V)
30
40
10
V
IN
37551 TA05b
3761f
25
LT3761
Typical applicaTions
Boost LED Driver for 30kHz PWM Dimming
L1
0.82µH
D1
V
IN
8V TO
20V
C2
C1
10µF
25V
187k
V
10µF
×2
IN
Boost PWM Dimming Waveform
499k
M1
GATE
0.25Ω
1A
EN/UVLO
35V
SENSE
V
IN
= 16V, V
= 30V
LED
39.2k
V
REF
PWM
LT3761
6mΩ
CTRL
PWM
17.8k
GND
INTV
CC
FB
ISP
ISN
1µF
100k
I
LED
0.5A/DIV
OPENLED
DIM/SS
PWMOUT
RT
3761 TA06b
5µs/DIV
V
0.1µF
C
20.5k
500kHz
3k
4.7nF
L1: VISHAY IHLP2525CZ
D1: DIODES PDS1040CTL
M1: INFINEON BSC059N04
M2: VISHAY Si2318CDS
M2
3761 TA06a
Buck Mode 5A LED Driver for 40kHz PWM Dimming
V
IN
44V TO 80V
340k
V
IN
ISP
EN/UVLO
50mΩ
2W
5A
10k
LT3761
ISN
UP TO
8 LEDS
V
REF
0.22µF
4V TO 40V
CTRL
PWM
PWMOUT
M2
Buck Mode PWM Dimming Waveform
C1
4.7µF
×4
6.2V
1M
D2
PWM
50V
V
= 48V, V
= 38V
LED
INTV
CC
IN
1µF
100k
2.2nF
200k
200k
I
LED
2A/DIV
L1
1µH
GATE
OPENLED
158k
FB
Q1
10k
3761 TA07b
DIM/SS
5µs/DIV
V
C
RT
GND SENSE
D1
M1
16.9k
600kHz
0.1µF
22k
4.7nF
C2
2.2µF
×2
VISHAY
5mΩ
0.5W
100V
3761 TA07a
L1: WÜRTH 744331010
M1: INFINEON BSC123NO8NS3
M2: INFINEON BSC093NO4LS
D1: DIODES PDS5100
D2: CENTRAL SEMI CMSSH-3S
C1: TDK C4532X7R1H475
C2: TDK C3225X7R2A225
LED: CREE XLAMP XM-L (×7)
Q1: ZETEX FMMT593
3761f
26
LT3761
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MSE Package
16-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1667 Rev E)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
(.112 ±.004)
2.845 ±0.102
(.112 ±.004)
0.889 ±0.127
(.035 ±.005)
1
8
0.35
REF
5.23
(.206)
MIN
1.651 ±0.102
(.065 ±.004)
1.651 ±0.102
(.065 ±.004)
3.20 – 3.45
(.126 – .136)
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
DETAIL “B”
16
9
0.305 ±0.038
0.50
(.0197)
BSC
NO MEASUREMENT PURPOSE
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
(.0120 ±.0015)
TYP
0.280 ±0.076
(.011 ±.003)
RECOMMENDED SOLDER PAD LAYOUT
16151413121110
9
REF
DETAIL “A”
0.254
(.010)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0° – 6° TYP
4.90 ±0.152
(.193 ±.006)
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
1 2 3 4 5 6 7 8
DETAIL “A”
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 ±0.0508
(.004 ±.002)
MSOP (MSE16) 0911 REV E
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
3761f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LT3761
Typical applicaTion
HV Boost Efficiency and
LED Current vs VIN
100
96
92
88
84
80
1.0
0.8
0.6
0.4
0.2
0.6
PWM TIED TO INTV
CC
80W High Voltage Boost LED Driver with 25:1 Internally Generated PWM Dimming
L1
22µH
D1
EFFICIENCY
V
IN
12V TO
60V
2.2µF
×2
100V
C
OUT
187k
21k
V
IN
0.22µF
×8
M1
GATE
LED CURRENT
EN/UVLO
1M
0805
250V
V
REF
SENSE
590k
20k
LT3761
12mΩ
CTRL
80W
GND
FB
INTV
CC
LED
8.66k
STRING
135V MAX
100k
10
20
30
40
50
60
PWMOUT
OPENLED
DIM/SS
PWM
DIM
0V TO
8V
V
(V)
IN
ISP
ISN
37551 TA03b
124k
V
RT INTV
CC
0.1µF
C
M2
Dimming Waveform
10nF
1.4kHz
39.2k
250kHz
2k
4.7nF
INTV
CC
PWM
(1V/DIV)
1µF
0.39Ω
650mA
DIM = 4V
V
V
= 36V
IN
LED
= 134V
M1, M2: INFINEON BSC520N15
D1: DIODES PDS4150
CURRENT DERATED
I
LED
(0.2A/DIV)
FOR V < 35V
L1: COILTRONICS HC9-220-R
IN
C
: TDK C3225X7R2E224K
3761 TA03a
OUT
3761 TA03c
200µs/DIV
relaTeD parTs
PART NUMBER
LT3755/LT3755-1/ High Side 40V, 1MHz LED Controller with True Color 3000:1
LT3755-2 PWM Dimming
LT3756/LT3756-1/ High Side 100V, 1MHz LED Controller with True Color 3000:1 V : 6V to 100V, V
DESCRIPTION
COMMENTS
V : 4.5V to 40V, V
= 75V, 3000:1 True Color PWM Dimming
IN
SD
OUT(MAX)
I
< 1μA, 3mm × 3mm QFN-16 and MSOP-16E Packages
= 100V, 3000:1 True Color PWM Dimming
IN
OUT(MAX)
LT3756-2
PWM Dimming
I
< 1μA, 3mm × 3mm QFN-16 and MSOP-16E Packages
SD
LT3796
High Side 100V, 1MHz LED Controller with True Color 3000:1 V : 6V to 100V, V
= 100V, 3000:1 True Color PWM Dimming
IN
OUT(MAX)
PWM Dimming, PMOS Disconnect FET Driver, Input Current
Limit and Input/Output Current Reporting
I
< 1μA, TSSOP-28E Packages
SD
LT3956
LT3754
LT3518
High Side 80V, 3.5A, 1MHz LED Driver with True Color 3,000:1 V : 6V to 80V, V
= 80V, True Color PWM Dimming = 3000:1,
IN
OUT(MAX)
PWM Dimming
I
< 1μA, 5mm × 6mm QFN-36 Package
SD
60V, 1MHz Boost 16-Channel 40mA LED Driver with True
Color 3000:1 PWM Dimming and 2% Current Matching
V : 4.5V to 40V, V
SD
= 60V, True Color PWM Dimming = 3000:1,
IN
OUT(MAX)
I
< 1μA, 5mm × 5mm QFN-32 Package
2.3A, 2.5MHz High Current LED Driver with 3000:1 Dimming V : 3V to 30V, V
= 45V, 3000:1 True Color PWM Dimming,
IN
OUT(MAX)
with PMOS Disconnect FET Driver
I
< 1μA, 4mm × 4mm QFN-16 and TSSOP-16E Packages
SD
LT3478/LT3478-1 4.5A, 2MHz High Current LED Driver with 3000:1 Dimming
V : 2.8V to 36V, V
SD
= 40V, 3000:1 True Color PWM Dimming,
IN
OUT(MAX)
I
< 1μA, TSSOP-16E Package
LT3791/LT3791-1 60V, Synchronous Buck-Boost 700kHz LED Controller
V : 4.7V to 60V, V
Range: 0V to 60V, True Color PWM,
IN
OUT
Analog = 100:1, I < 1µA, TSSOP-38E Package
SD
3761f
LT 0812 • PRINTED IN USA
28 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2012
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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