LT3782 [Linear]
2-Phase Step-Up DC/DC Controller; 两相升压型DC / DC控制器
| 型号： | LT3782 |
| 厂家： | 
Linear |
| 描述： | 2-Phase Step-Up DC/DC Controller |
| 文件： | 总16页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3782
2-Phase Step-Up
DC/DC Controller
U
DESCRIPTIO
FEATURES
■
2-Phase Operation Reduces Required Input and
The LT®3782 is a current mode two phase step-up DC/DC
converter controller. Its high switching frequency (up to
500kHz) and 2-phase operation reduce system filtering
capacitance and inductance requirements.
Output Capacitance
■
Programmable Switching Frequency:
150kHz to 500kHz
6V to 40V Input Range
10V Gate Drive with VCC ≥13V
High Current Gate Drive (4A)
■
With 10V gate drive (VCC ≥13V) and 4A peak drive current,
the LT3782 can drive most industrial grade high power
MOSFETs with high efficiency. For synchronous applica-
tions, the LT3782 provides synchronous gate signals with
programmable falling edge delay to avoid cross conduc-
tion when using external MOSFET drivers. Other features
include programmable undervoltage lockout, soft-start,
current limit, duty cycle clamp (50% or higher) and slope
compensation.
■
■
■
Programmable Soft-Start and Current Limit
■
Programmable Slope Compensation for
High Noise Immunity
■
MOSFET Gate Signals with Programmable
Falling Edge Delay for External Synchronous
Drivers
■
Programmable Undervoltage Lockout
■
■
The LT3782 is available in a thermally enhanced 28-lead
SSOP package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 6144194.
Programmable Duty Cycle Clamp (50% or Higher)
Thermally EnhanUced 28-Lead SSOP Package
APPLICATIO S
■
Industrial Equipment
■
Telecom Infrastructure
■
Interleaved Isolated Power Supply
U
TYPICAL APPLICATIO
50V 4A Boost Converter
V
V
IN
10V TO 36V
OUT
50V, 4A
L1
L2
C
D1
OUT1
Efficiency and Power Loss
vs Load Current
V
GBIAS1
CC
10µF
50V
2x
30BQ060
1µF
R6
+
GBIAS2
GBIAS
C3
2µF
825k
D2
97
95
93
91
89
87
85
18
15
12
9
+
C
OUT2
220µF
C
30BQ060
IN
V
IN
= 24V
RUN
M1
EFFICIENCY
10µF
50V
2x
BGATE1
Si7852dp
2x
R8
274k
V
IN
= 12V
R
LT3782
S1
0.004Ω
V
R
V
IN
= 12V
EE1
SLOPE
59k
M2
Si7852dp
2x
SLOPE
DELAY
DCL
BGATE2
V
IN
= 24V
6
L1, L2: PB2020.223
, C : X7R, TDK
C
R
IN OUT1
FREQ
80k
R
POWER LOSS
S2
0.004Ω
3
R
SET
V
EE2
+
10Ω
10Ω
10nF
0
SS
0
1
2
3
4
5
SENSE1
SENSE1
0.1µF
I
(A)
OUT
10nF
–
3782 TA01b
R
F1
475k
V
C
+
–
13k
6.8nF
SENSE2
SENSE2
100pF
R
F2
24.9k
FB
GND
3782 TA01
3782fa
1
LT3782
W W
U W
U
W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
ORDER PART
NUMBER
1
2
28 GBIAS
27
SGATE2
SGATE1
NC
VCC Supply Voltage.................................................. 40V
GBIAS, GBIAS1, GBIAS2 Pin (Externally Forced)
V
CC
3
26 NC
............................................................................ 14V
SYNC, RUN Pin........................................................ 30V
Operating Junction Temperature Range (Notes 2, 3)
.......................................................... –40°C to 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
SS................................................................–0.3V to 6V
SENSE1+, SENSE2+, SENSE1–, SENSE2–
LT3782EFE
4
25 NC
GND
5
24 VEE1
23 BGATE1
22 GBIAS1
21 GBIAS2
20 BGATE2
19 VEE2
18 NC
SYNC
DELAY
DCL
6
7
29
+
8
SENSE1
–
9
SENSE1
10
11
12
13
14
SLOPE
R
SET
–
FE PART
MARKING
17 RUN
16 FB
SENSE2
SENSE2
+
15
V
C
SS
................................................................–0.3V to 2V
LT3782EFE
FE PACKAGE
28-LEAD PLASTIC SSOP
EXPOSED PAD (PIN 29) IS GND
MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 38°C/ W
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
outputs, unless otherwise noted.
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = 13V, R = 80k, operating maximum V = 24V, no load on any
A
CC
SET
CC
PARAMETER
Overall
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage (V
)
●
●
6
40
16
V
CC
Supply Current (I
Shutdown
)
V ≤ 0.5V (Switching Off), V ≤ 40V
11
mA
VCC
C
CC
RUN Threshold
2.3
2.45
80
2.6
V
RUN Threshold Hysteresis
Supply Current in Shutdown
mV
1V ≤ RUN ≤ V , V ≤ 30V
0.4
40
0.65
90
mA
µA
REF CC
RUN ≤ 0.3V, V ≤ 30V
CC
RUN Pin Input Current
V
= 2.3V
●
–0.5
–2
µA
RUN
Voltage Amplifier gm
Reference Voltage (V
)
2.42
2.4
2.44
2.464
2.488
V
V
REF
●
●
●
Transconductance
V
V
= 1V, ∆I = ±2µA
200
260
0.2
1.5
0.35
11
370
0.6
µmho
µA
V
VC
FB
VC
Input Current I
= V
= 0
= 0
FB
REF
V High
C
I
I
VC
VC
V Low
C
0.4
14
28
V
Source Current I
V
V
= 0.7V – 1V, V = V – 100mV
8
13
0.3
6
µA
µA
V
VC
VC
VC
FB
REF
Sink Current I
= 0.7V – 1V, V = V + 100mV
20
VC
FB
REF
V Threshold for Switching Off (BGATE1, BGATE2 Low)
C
●
Soft-Start Current I
V
= 0.1V – 2.8V
10
15
µA
3782fa
SS
SS
2
LT3782
ELECTRICAL CHARACTERISTICS
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = 13V, R = 80k, operating maximum V = 24V, no load on any
A
CC
SET
CC
outputs, unless otherwise noted.
SYMBOL PARAMETER
Current Amplifier CA1, CA2
CONDITIONS
MIN
TYP
MAX
UNITS
Voltage Gain ∆V /∆V
4
C
SENSE
+
–
+
–
Current Limit (V
Input Current (I
Oscillator
– V
) (V
– V
)
50
62
60
80
mV
SENSE1
SENSE1
–
SENSE2
+
SENSE2
+
–
, I
, I
, I
)
∆V
= 0V
SENSE
µA
SENSE1 SENSE1 SENSE2 SENSE2
Switching Frequency
R
R
R
= 130k
= 80k
= 40k
●
●
●
130
212
386
154
250
465
177
288
533
kHz
kHz
kHz
SET
SET
SET
Synchronization Pulse Threshold on SYNC Pin
Rising Edge V
0.8
1.2
2
V
SYNC
Synchronization Frequency Range
(Note: Operation Switching Frequency Equals
Half of the Synchronization Frequency)
R
R
R
= 130k
= 80k
= 40k
180
290
550
240
392
715
kHz
kHz
kHz
SET
SET
SET
V
R
= 80k
2.3
V
RSET
SET
Maximum Duty Cycle
V
= V – 25mV, R > 80K
●
●
90
83
94
90
%
%
FB
REF
SET
SET
R
= 40K
Duty Cycle Limit
R
= 80k , V
≤ 0.3V
50
75
%
%
SET
DCL
DCL
DCL
V
V
= 1.2V
= V
Max Duty Cycle
RSET
DCL Pin Input Current
V
= 0.3V
●
●
–0.1
–0.3
µA
DCL
Gate Driver
V
I
< 70mA
10.2
11
11.7
10.5
V
GBIAS
GBIAS
BGATE1, BGATE2 High Voltage
13V ≤ V ≤ 24V, I
V
= –100mA
= –100mA
●
●
7.8
3.8
9.2
5
V
V
CC
BGATE
= 8V, I
CC
BGATE
BGATE1, BGATE2 Source Current (Peak)
Capacitive Load >22µF
Capacitive Load >50µF
3
4
A
A
BGATE1, BGATE2 Low Voltage
8V ≤ V ≤ 24V, I
= 100mA
●
●
0.5
0.7
V
CC
BGATE
BGATE1, BGATE2 Sink Current (Peak)
Capacitive Load >22µF
Capacitive Load >50µF
3
4
A
A
SGATE1, SGATE2 High Voltage
SGATE1, SGATE2 Low Voltage
SGATE1, SGATE2 Peak Current
Delay of BGATE High
8V ≤ V ≤ 24V, I
= –20mA
= 20mA
4.5
5.5
0.5
100
6.7
0.7
V
V
CC
SGATE
SGATE
8V ≤ V ≤ 24V, I
CC
500pF Load
mA
DELAY Pin and R Pin Shorted
100
150
250
500
ns
ns
ns
ns
SET
V
V
V
= 1V
= 0.5V
= 0.25V
DELAY
DELAY
DELAY
Delay Pin Input Current
V
= 0.25V
●
–0.1
–0.3
µA
DELAY
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LT3782 is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 125°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
3782fa
3
LT3782
U W
TYPICAL PERFOR A CE CHARACTERISTICS T = 25°C unless otherwise noted.
A
∆V
vs V , ∆Frequency vs V
CC
REF
CC
V
GBIAS
vs I
I
vs V
(R = 80k)
SET
GBIAS
CC
CC
11.0
10.9
10.8
10.7
10.6
10.5
10.4
10.3
10.2
10.1
10.0
20
18
16
14
12
10
8
3
2
12
10
8
1
∆V
REF
0
6
–1
–2
–3
–4
–5
4
2
∆Frequency
6
0
4
–2
–4
2
0
50
(mA)
6
8
10 12 14 16 18 20 22 24 26 28 30
(V)
6
9
12
15 18
(V)
21 24 27 30
0
100
V
CC
V
I
CC
GBIAS
3782 G02
3782 G03
3782 G01
V
vs I
at Start-Up
GBIAS
Reference Voltage vs
Temperature
GBIAS
Switching Frequency vs R
(Charging 2µF)
FREQ
600
500
400
300
200
100
2.446
2.444
2.442
2.440
2.438
2.436
2.434
14
12
10
8
800
700
600
500
400
300
200
100
0
V
GBIAS
6
4
I
GBIAS
2
0
–2
0
20 40 60 80 100 120 140 160 180 200
(kΩ)
0
25
75
100
125
150
0
250µ
500µ
750µ
1m
50
JUNCTION TEMPERATURE (°C)
R
TIME (s)
FREQ
3782 G04
3782 G06
3782 G05
SGATE (Low) to BGATE (High)
Delay vs V (R = 80k)
Switching Frequency vs Duty
Cycle
Maximum Duty Cycle Limit vs
DCL SET
V
(R = 80k)
DELAY SET
1000
900
800
700
600
500
400
300
200
100
0
105
100
95
120
110
100
90
80
90
70
60
85
50
40
80
0
0.5
1.0
V
1.5
(V)
2.0
2.5
100
200
300
400
500
600
0.9 1.2
0
0.3 0.6
1.5 1.8 2.1 2.4
SWITCHING FREQUENCY (kHz)
V
(V)
DELAY
DCL
3782 G07
3782 G08
3782 G09
3782fa
4
LT3782
U
U
U
PI FU CTIO S
SGATE2 (Pin 1): Second Phase Synchronous Drive Sig-
nal. An external driver buffer is needed to drive the top
synchronous power FET.
VC (Pin 15): The output of the gm error amplifier and the
control signal of the current loop of the current-mode
PWM. Switching starts at 0.7V, and higher VC voltages
corresponds to higher inductor current.
SGATE1 (Pin 2): First Phase Synchronous Drive Signal.
An external driver buffer is needed to drive the top syn-
chronous power FET.
FB (Pin 16): Error Amplifier Inverting Input. A resistor
divider to this pin sets the output voltage.
NC (Pin 3): Not Connected. Can be connected to GND.
GND (Pin 4): Chip Ground.
RUN (Pin 17): LT3782 goes into shutdown mode when
V
RUN isbelow2.2Vandgoestolowbiascurrentshutdown
mode when VRUN is below 0.3V.
SYNC (Pin 5): Synchronization Input. The pulse width can
rangefrom10%to70%.Notethattheoperatingfrequency
is half of the sync frequency.
NC (Pin 18): Not Connected. Can be connected to GND.
VEE2 (Pin 19): Gate Driver BGATE2 Ground. This pin
should be connected to the ground side of the second
current sense resistor.
DELAY (Pin 6): When synchronous drivers are used, the
programmable delay that delays BGATE turns on after
SGATE turns off.
BGATE2 (Pin 20): Second Phase MOSFET Driver.
DCL (Pin 7): This pin programs the limit of the maximum
dutycycle.WhenconnectedtoVRSET,itoperatesatnatural
maximum duty cycle, approximately 90%.
SENSE1+ (Pin 8): First Phase Current Sense Amplifier
Positive Input. An RC filter is required across the current
sense resistor. Current limit threshold is set at 60mV.
SENSE1– (Pin 9): First Phase Current Sense Amplifier
Negative Input. An RC filter is required across the current
sense resistor.
GBIAS2 (Pin 21): Bias for Gate Driver BGATE2. Should be
connected to GBIAS or an external power supply between
12V to 14V. A bypass low ESR capacitor of 2µF or larger
is needed and should be connected directly to the pin to
minimize parasitic impedance.
GBIAS1 (Pin 22): Bias for Gate Driver BGATE1. Should be
connected to GBIAS2.
BGATE1 (Pin 23): First Phase MOSFET Driver.
VEE1 (Pin 24): Gate Driver BGATE1 Ground. This pin
should be connected to the ground side of the second
current sense resistor.
SLOPE (Pin 10): A resistor from SLOPE to GND increases
the internal current mode PWM slope compensation.
RSET (Pin 11): A resistor from RSET to GND sets the
NC (Pin 25): Not Connected. Can be connected to GND.
NC (Pin 26): Not Connected. Can be connected to GND.
oscillator charging current and the operating frequency.
SENSE2– (Pin12):SecondPhaseCurrentSenseAmplifier
Negative Input. An RC filter is required across the current
sense resistor.
SENSE2+ (Pin13):SecondPhaseCurrentSenseAmplifier
Positive Input. An RC filter is required across the current
sense resistor. Current limit threshold is set at 60mV.
VCC (Pin 27): Chip Power Supply. Good supply bypassing
is required.
GBIAS (Pin 28): Internal 11V regulator output for biasing
internal circuitry. Should be connected to GBIAS1 AND
GBIAS2.
EXPOSED PAD (Pin 29): The exposed package pad is
fused to internal ground and is for heat sinking. Solder the
bottom metal plate onto expanded ground plane for opti-
mum thermal performance.
SS (Pin 14): Soft-Start. A capacitor on this pin sets the
output ramp up rate. The typical time for SS to reach the
programmed level is (C • 2.44V)/10µA.
3782fa
5
LT3782
W
BLOCK DIAGRA
V
V
OUT
IN
L1
15µ
D1
V
CC
V
GBIAS
= V – 1V AND CLAMPED AT 11V
CC
C
IN
20µF
27
REGULATOR
L2
15µ
D2
GBIAS1
+
C
LOW POWER
SHUTDOWN
OUT
22
21
28
+
–
+
–
+
100µF
R6
R8
GBIAS2
GBIAS
C3
2µF
A5
A11
A8
RUN
17
–
+
+
+
0.5V
7V
A6
V
– 2.5V
R
F1
CC
+
–
R
F2
A7
+
A20
2.44V
SGATE1
DELAY
2
6
A4
A1
ONE SHOT
GBIAS1
A9
R
SET
+
–
+
A12
2.5V
BGATE1
BGATE1
A13
22
8
M1
R
A14
R1
50k
SLOPE COMP
CH1
R7
+
–
SENSE1
SENSE1
S1
10Ω
C2
2nF
+
BLANKING
PWM1
R3
9
V
–
+
EE1
24
A3
BGATE1
CL1
–
+
SGATE1
SET
DELAY
60mV
SGATE2
1
A15
A17
+
–
+
A16
2.5V
DELAY
BGATE2
ONE SHOT
GBIAS2
BGATE2
A18
A2
20
13
M2
A19
R2
50k
SLOPE COMP
CH2
R9
+
–
R
SENSE2
SENSE2
S2
10Ω
SET
SLOPE
SYNC
C4
2nF
+
BLANKING
CH1
CH2
SLOPE
COMP
PWM2
10
5
R4
S
R
S
R
12
19
V
–
EE2
A10
R
SET
D6
D7
FB
11
OSC
CK
D
Q
Q
+
–
16
–
3782 BD
LOGIC
R
FREQ
+
GM
C5
20pF
NOTE:
CL2
PACKAGE BOTTOM METAL PLATE (PIN 29)
IS FUSED TO CHIP DIE AGND
V
+
REF
GND
I1
10µA
60mV
4
D4
4V
V
SS
14
C
7
15
R5
2k
C7
10nF
DCL
C1
2000pF
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LT3782
U
W U U
APPLICATIO S I FOR ATIO
Operation
Soft-Start and Shutdown
The LT3782 is a two phase constant frequency current
mode boost controller. Switching frequency can be pro-
grammed up to 500kHz. During normal switching cycles,
thetwochannelsarecontrolledbyinternalflip-flopandare
180 degrees out of phase.
During soft-start, the voltage on the SS pin (VSS) controls
the output voltage. The output voltage thus ramps up
following VSS. The effective range of VSS is from 0V to
2.44V. The typical time for the output to reach the pro-
grammed level is
Referring to the Block Diagram, the LT3782 basic func-
tions include a transconductance amplifer (gm) to regu-
late the output voltage and to control the current mode
PWMcurrentloop.Italsoincludesthenecessarylogicand
flip-flop to control the PWM switching cycles, two high
speedgatedriverstodrivehighpowerN-ChannelMOSFETs,
and 2-phase control signals to drive external gate drivers
for optional synchronous operation.
C •2.44V
t =
10µA
C is the capacitor connected from the SS pin to Gnd.
Undervoltage Lockout and Shutdown
Only when VRUN is higher than 2.45V VGBIAS will be active
and the switching enabled. The LT3782 goes into low
current shutdown when VRUN is below 0.3V. A resistor
divider can be used on RUN pin to set the desired VCC
undervoltage lockout voltage. A 120mV hysteresis is built
in on RUN pin thresholds.
In normal operation, each switching cycle starts with a
switch turn-on. The inductor current of each channel is
sampled through the current sense resistor and amplified
then compared to the error amplifier output VC to turn the
switch off. The phase delay of the second channel is
controlled by the divide-by-two D flip-flop and is exactly
180 degrees out of phase of the first channel. With a
resistordividerconnectedtotheFBpin, theoutputvoltage
is programmed to the desired value. The 10V gate drivers
aresufficienttodrivemosthighpowerN-ChannelMOSFET
in many industrial applications.
Oscillation Frequency Setting and Synchronization
The switching frequency of LT3782 can be set up to
500kHz by a resistor RFREQ from pin RSET to ground.
For fSET = 250kHz, RFREQ = 80k
OncetheswitchingfrequencyfSET ischosen, RFREQ canbe
found from the Switching Frequency vs RFREQ graph
found under the Typical Electrical Characteristics section.
Additional important features include shutdown, current
limit,soft-start,synchronizationandprogrammablemaxi-
mum duty cycle. Additional slope compensation can be
added also.
Note that because of the 2-phase operation, the internal
oscillator is running at twice the switching frequency. To
synchronize the LT3782 to the system frequency fSYSTEM
the synchronizing frequency fSYNC should be two times
fSYSTEM, and the LT3782 switching frequency fSET should
be set below 80% of fSYSTEM
,
Output Voltage Programming
With a 2.44V feedback reference voltage VREF, the output
VOUT is programmed by a resistor divider as shown in the
Block Diagram.
.
fSYNC = 2fSYSTEM and fSET < (fSYSTEM • 0.8)
Forexample,tosynchronizetheLT3782to200kHzsystem
frequency fSYSTEM, fSYNC needs to be set at 400kHz and
fSET needs to be set at 160kHz. From the Switching
Frequency vs RFREQ graph found under the Typical Electri-
cal Characteristics section, RFREQ = 130k.
⎛
⎞
⎟
⎠
RF1
RF2
VOUT = 2.44 1+
⎜
⎝
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LT3782
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W U U
APPLICATIO S I FOR ATIO
Witha200nsone-shottimeronchip, theLT3782provides
flexibility on the external sync pulse width. The sync pulse
threshold is about 1.2V (Figure 1).
to compensate for the propagation delay of external gate
driver, a resistor divider can be used from RSET to ground
to program VDELAY for the longer delay needed. For
example, for a switching frequency of 250kHz and delay of
150ns, then RFREQ1 + RFREQ2 should be 80k and VDELAY
should be 1V, with VRSET = 2.3V then RFREQ1 = 47.5k and
RFREQ2 = 32.5k (see Figure 3).
5V TO 20V
5k
LT3782
SYNC
VN2222
DELAY
3782 F01
PULSE WIDTH > 200ns
LT3782
Figure 1. Synchronizing with External Clock
R
SET
3782 F03
R
R
FREQ1
47.5k
Current Limit
FREQ2
32.5k
Current limit is set by the 60mV threshold across SEN1P,
SEN1N for channel one and SEN2P, SEN2N for channel
two. By connecting an external resistor RS (see Block
Diagram), the current limit is set for 60mV/RS. RS should
be placed very close to the power switch with very short
traces. A low pass RC filter is needed across RS to filter out
the switching spikes. Good Kelvin sensing is required for
accurate current limit. The input bypass capacitor ground
should be at the same ground point of the current sense
resistor to minimize the ground current path.
Figure 3. Increase Delay Time
Duty Cycle Limit
When DCL pin is shorted to RSET pin and switching
frequency is less than 250kHz (RFREQ > 80k), the maxi-
mum duty cycle of LT3782 will be at least 90%. The
maximumdutycyclecanbeclampedto50%bygrounding
the DCL pin or to 75% by forcing the VDCL voltage to 1.2V
with a resistor divider from RSET pin to ground. The typical
DCL pin input current is 0.2µA.
Synchronous Rectifier Switches
For high output voltage applications, the power loss of the
catch diodes are relatively small because of high duty
cycle.Ifdiodespowerlossorheatisaconcern,theLT3782
provides PWM signals through SGATE1 and SGATE2 pins
todriveexternalMOSFETdriversforsynchronousrectifier
operation. Note that SGATE drives the top switch and
BGATE drives the bottom switch. To avoid cross conduc-
tionbetweentopandbottomswitches, theBGATEturn-on
isdelayed100ns(whenDELAYpinistiedtoRSET pin)from
SGATE turn-off (see Figure 2). If a longer delay is needed
Slope Compensation
The LT3782 is designed for high voltage and/or high
current applications, and very often these applications
generate noise spikes that can be picked up by the current
sensing amplifier and cause switching jitter. To avoid
switching jitter, careful layout is absolutely necessary to
minimize the current sensing noise pickup. Sometimes
increasingslopecompensationtoovercomethenoisecan
help to reduce jitter. The built-in slope compensation can
be increased by adding a resistor RSLOPE from SLOPE pin
to ground. Note that smaller RSLOPE increases slope
compensation and the minimum RSLOPE allowed is
RFREQ/2.
BGATE1
SGATE1
SET
DELAY
3782 F02
Figure 2. Delay Timing
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LT3782
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APPLICATIO S I FOR ATIO
Layout Considerations
Power Inductor Selection
To prevent EMI, the power MOSFETs and input bypass
capacitor leads should be kept as short as possible. A
groundplaneshouldbeusedundertheswitchingcircuitry
to prevent interplane coupling and to act as a thermal
spreading path. Note that the bottom pad of the package
is the heat sink, as well as the IC signal ground, and must
be soldered to the ground plane.
In a boost circuit, a power inductor should be designed to
carry the maximum input DC current. The inductance
should be small enough to generate enough ripple current
to provide adequate signal to noise ratio to the LT3782. An
empiricalstartingoftheinductorripplecurrent(perphase)
is about 40% of maximum DC current, which is half of the
input DC current in a 2-phase circuit:
In a boost converter, the conversion gain (assuming
100% efficiency) is calculated as (ignoring the forward
voltage drop of the boost diode):
IOUT(MAX) •VOUT
IOUT(MAX) •VOUT
∆IL ≅ 40%•
= 20%•
2V
V
IN
IN
where VIN, VOUT and IOUT are the DC input voltage, output
voltage and output current, respectively.
VOUT
V
IN
1
1−D
=
And the inductance is estimated to be:
where D is the duty ratio of the main switch. D can then be
estimated from the input and output voltages:
V •D
fs • ∆IL
IN
L =
V
V
VOUT
IN(MIN)
IN
D = 1−
;DMAX = 1−
where fs is the switching frequency per phase.
VOUT
The saturation current level of inductor is estimated to be:
The Peak and Average Input Currents
IOUT(MAX) •VOUT
∆IL
2
I
IN
2
The control circuit in the LT3782 measures the input
current by using a sense resistor in each MOSFET source,
so the output current needs to be reflected back to the
input in order to dimension the power MOSFET properly.
Based on the fact that, ideally, the output power is equal to
the input power, the maximum average input current is:
ISAT
≥
+
≅ 70%•
V
IN(MIN)
Sense Resistor Selection
During the switch on-time, the control circuit limits the
maximum voltage drop across the sense resistor to about
60mV. The peak inductor current is therefore limited to
60mV/R. The relationship between the maximum load
current, duty cycle and the sense resistor RSENSE is:
IO(MAX)
1– DMAX
The peak current is:
I
=
IN(MAX)
1– DMAX
IO(MAX)
1– DMAX
R ≤ VSENSE(MAX)
•
I
= 1.2•
IO(MAX)
IN(PEAK)
1.2•
2
The maximum duty cycle, DMAX, should be calculated at
minimum VIN.
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9
LT3782
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APPLICATIO S I FOR ATIO
The power dissipated by the MOSFET in a 2-phase boost
converter is:
Power MOSFET Selection
Important parameters for the power MOSFET include the
drain-to-source breakdown voltage (BVDSS), the thresh-
old voltage (VGS(TH)), the on-resistance (RDS(ON)) versus
gate-to-source voltage, the gate-to-source and gate-to-
drain charges (QGS and QGD, respectively), the maximum
drain current (ID(MAX)) and the MOSFET’s thermal resis-
tances (RTH(JC) and RTH(JA)).
2
I
⎛
⎞
O(MAX)
⎜
⎝
⎟
⎠
2
PFET
=
•RDS(ON) •D •ρT
1– D
(
)
I
⎛
⎞
O(MAX)
⎜
⎟
⎠
⎝
2
2
The gate drive voltage is set by the 10V GBIAS regulator.
Consequently, 10V rated MOSFETs are required in most
high voltage LT3782 applications.
+ k •VO
•
•CRSS • f
1– D
(
)
The first term in the equation above represents the I2R
losses in the device, and the second term, the switching
losses. The constant, k = 1.7, is an empirical factor
inversely related to the gate drive current and has the
dimension of 1/current. The ρT term accounts for the
temperature coefficient of the RDS(ON) of the MOSFET,
which is typically 0.4%/°C. Figure 4 illustrates the varia-
tion of normalized RDS(ON) over temperature for a typical
power MOSFET.
Pay close attention to the BVDSS specifications for the
MOSFETsrelativetothemaximumactualswitchvoltagein
the application. The switch node can ring during the turn-
off of the MOSFET due to layout parasitics. Check the
switching waveforms of the MOSFET directly across the
drain and source terminals using the actual PC board lay-
out (not just on a lab breadboard!) for excessive ringing.
Calculating Power MOSFET Switching and Conduction
Losses and Junction Temperatures
2.0
1.5
1.0
0.5
0
In order to calculate the junction temperature of the power
MOSFET, the power dissipated by the device must be
known. This power dissipation is a function of the duty
cycle, the load current and the junction temperature itself
(duetothepositivetemperaturecoefficientofitsRDS(ON)).
As a result, some iterative calculation is normally required
to determine a reasonably accurate value. Care should be
taken to ensure that the converter is capable of delivering
the required load current over all operating conditions
(line voltage and temperature), and for the worst-case
specifications for VSENSE(MAX) and the RDS(ON) of the
MOSFET listed in the manufacturer’s data sheet.
50
100
–50
150
0
JUNCTION TEMPERATURE (°C)
3782 F06
Figure 4. Normalized R
vs Temperature
DS(ON)
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10
LT3782
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APPLICATIO S I FOR ATIO
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:
tion will further reduce the input capacitor ripple current
rating. The ripple current is plotted in Figure 5. Please note
that the ripple current is normalized against
TJ = TA + PFET • RTH(JA)
V
L • fs
IN
Inorm
=
The RTH(JA) to be used in this equation normally includes
the RTH(JC) for the device plus the thermal resistance from
the case to the ambient temperature (RTH(CA)). This value
of TJ can then be compared to the original, assumed value
used in the iterative calculation process.
Output Capacitor Selection
The voltage rating of the output capacitor must be greater
than the maximum output voltage with sufficient derating.
Because the ripple current in output capacitor is a pulsat-
ing square wave in a boost circuit, it is important that the
ripple current rating of the output capacitor be high
enough to deal with this large ripple current. Figure 6
shows the output ripple current in the 1- and 2-phase
designs. As we can see, the output ripple current of a
2-phase boost circuit reaches almost zero when the duty
cycle equals 50% or the output voltage is twice as much
as the input voltage. Thus the 2-phase technique signifi-
cantly reduces the output capacitor size.
Input Capacitor Choice
The input capacitor must have high enough voltage and
ripple current ratings to handle the maximum input volt-
ageandRMSripplecurrentrating. Theinputripplecurrent
in a boost circuit is very small because the input current is
continuous. With 2-phase operation, the ripple cancella-
Normalized Peak-to-Peak Input
Ripple Current
1.00
0.90
0.80
0.70
Normalized Output RMS
Ripple Currents
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
0.60
1-PHASE
0.50
0.40
2-PHASE
0.30
0.20
0.10
0
1-PHASE
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE
2-PHASE
3782 F04
Figure 5. Normalized Input Peak-to-Peak Ripple Current:
0.4 0.5
DUTY CYCLE OR (1-V /V
0.1 0.2 0.3
0.6 0.7 0.8 0.9
)
IN OUT
V
IN
3782 F05
Inorm
=
L • fs
Figure 6. Normalized Output Ripple Currents in Boost Converter:
1-Phase and 2-Phase. I Is the DC Output Current.
The RMS Ripple Current is About 29% of the Peak-to-Peak
Ripple Current.
OUT
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11
LT3782
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APPLICATIO S I FOR ATIO
For a given VIN and VOUT, we can calculate the duty cycle
D and then derive the output RMS ripple current from
Figure 6. After choosing output capacitors with sufficient
RMS ripple current rating, we also need to consider the
ESR requirement if Electrolytic caps, Tantulum caps,
POSCAPs or SP CAPs are selected. Given the required
output ripple voltage spec ∆VOUT (in RMS value) and the
calculated RMS ripple current ∆IOUT, one can estimate the
ESR value of the output capacitor to be
1. The supply current into VIN. The VIN current is the sum
of the DC supply current IQ (given in the Electrical
Characteristics) and the MOSFET driver and control
currents. The DC supply current into the VIN pin is
typically about 7mA and represents a small power loss
(much less than 1%) that increases with VIN. The driver
current results from switching the gate capacitance of
thepowerMOSFET;thiscurrentistypicallymuchlarger
than the DC current. Each time the MOSFET is switched
onandthenoff,apacketofgatechargeQG istransferred
from GBIAS to ground. The resulting dQ/dt is a current
that must be supplied to the GBIAS capacitor through
the VIN pin by an external supply. In normal operation:
∆VOUT
ESR ≤
∆IOUT
External Regulator to Bias Gate Drivers
IQ(TOT) ≈ IQ = f • QG
If VIN is higher than 24V and the applications require the
LT3782 to drive large MOSFETs the IC temperature may
gettoohigh.Toreduceheat,anexternalregulatorbetween
12V to 14V should be used to override the internal VGBIAS
regulator to supply the current needed for BGATE1 and
BGATE2 (see Figure 7).
PIC = VIN • (IQ + f • QG)
2. Power MOSFET switching and conduction losses:
2
IO(MAX)
⎛
⎞
⎜
⎟
2
P
FET
=
•RDS(ON) •DMAX •ρT
⎜
⎟
1– DMAX
⎜
⎝
⎟
⎠
LT3782
GBIAS
+
12V
GBIAS1
GBIAS2
IO(MAX)
2
2
+ k •VO
•
•CRSS • f
3782 F07
2µF
1– DMAX
3. The I2R losses in the sense resistor can be calculated
almost by inspection.
Figure 7
Efficiency Considerations
2
IO(MAX)
⎛
⎞
The efficiency of a switching regulator is equal to the
output power divided by the input power (¥100%). Per-
cent efficiency can be expressed as:
⎜
⎟
2
PR(SENSE)
=
•R•DMAX
⎜
⎟
1– DMAX
⎜
⎝
⎟
⎠
% Efficiency = 100% – (L1 + L2 + L3 + …),
where L1, L2, etc. are the individual loss components as
a percentage of the input power. It is often useful to
analyze individual losses to determine what is limiting the
efficiency and which change would produce the most
improvement. Although all dissipative elements in the
circuit produce losses, four main sources usually account
for the majority of the losses in LT3782 application
circuits:
4. The losses in the inductor are simply the DC input
currentsquaredtimesthewindingresistance. Express-
ing this loss as a function of the output current yields:
2
IO(MAX)
⎛
⎞
⎜
⎟
2
PR(WINDING)
=
•RW
⎜
⎟
1– DMAX
⎜
⎝
⎟
⎠
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12
LT3782
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APPLICATIO S I FOR ATIO
5. Losses in the boost diode. The power dissipation in the
In order to help dissipate the power from MOSFETs and
diodes, keep the ground plane on the layers closest to the
layers where power components are mounted. Use power
planes for MOSFETs and diodes in order to improve the
spreading of the heat from these components into the
PCB.
boost diode is:
IO(MAX)
PDIODE
=
•VD
2
The boost diode can be a major source of power loss in
a boost converter. For 13.2V input, 42V output at 3A, a
Schottky diode with a 0.4V forward voltage would
dissipate 600mW, which represents about 1% of the
input power. Diode losses can become significant at
low output voltages where the forward voltage is a
significant percentage of the output voltage.
For best electrical performance, the LT3782 circuit should
be laid out as follows:
Place all power components in a tight area. This will
minimize the size of high current loops. Orient the input
andoutputcapacitorsandcurrentsenseresistorsinaway
that minimizes the distance between the pads connected
to ground plane.
6. Other losses, including CIN and CO ESR dissipation and
inductor core losses, generally account for less than
2% of the total losses.
Place the LT3782 and associated components tightly
together and next to the section with power components.
PCB Layout Considerations
Use a local via to ground plane for all pads that connect to
ground. Use multiple vias for power components.
To achieve best performance from an LT3782 circuit, the
PC board layout must be carefully done. For lower power
applications, a two-layer PC board is sufficient. However,
at higher power levels, a multiplayer PC board is recom-
mended.Usingasolidgroundplaneunderthecircuitisthe
easiest way to ensure that switching noise does not affect
the operation.
Connect the current sense inputs of LT3782 directly to the
current sense resistor pads. Connect the current sense
traces on the opposite sides of pads from the traces
carrying the MOSFETs source currents to ground. This
technique is referred to as Kelvin sensing.
3782fa
13
LT3782
U
TYPICAL APPLICATIO S
10V to 24V Input to 24V, 8A Output Boost Converter
10V TO 24V INPUT
1
2
3
4
5
6
28
27
26
25
24
23
SGATE1
SGATE2
NC
GBIAS
2R2
L1
V
CC
D1
PB2020-103
UPS840
NC
NC
Q1
PH3330
1µF
GND
C
OUT2
330µF, 35V, 2x
CS1
SYNC
DELAY
V
EE1
0.004Ω
BGATE1
GBIAS1
GBIAS2
7
8
22
21
DCL
OUTPUT
24V
8A
10Ω
+
–
CS1
SENSE1
LT3782
C
C
OUT1
22µF, 25V, 4x
IN
2.2µF
10nF
22µF
9
20
19
25V
SENSE1
SLOPE
BGATE2
0.004Ω
59k
82k
10
V
EE2
NC
CS2
825k
274k
11
12
18
17
R
SET
Q2
PH3330
–
+
SENSE2
RUN
FB
10nF
10Ω
24.9k
221k
13
14
16
15
L2
PB2020-103
CS2
SENSE2
SS
D2
UPS840
V
C
3782 TA02
4.7nF
L1, L2: PULSE PB2020-103
ALL CERAMIC CAPACITORS ARE X7R, TDK
C
C1
6.8nF
R
C1
C
C2
100pF
13.3k
*OUTPUT CURRENT WITH BOTH INPUTS PRESENT
Efficiency
100
98
96
94
92
90
88
86
15V
IN
12V
IN
0
1
2
3
4
5
6
7
8
I
(A)
OUT
3782 TA02b
3782fa
14
LT3782
U
PACKAGE DESCRIPTIO
FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation EB
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
4.75
(.187)
28 2726 25 24 23 22 21 20 19 18 1716 15
6.60 ±0.10
2.74
(.108)
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
4.50 ±0.10
SEE NOTE 4
6.40
2.74
(.252)
(.108)
BSC
0.45 ±0.05
1.05 ±0.10
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
5
7
1
2
3
4
6
8
9 10 12 13 14
11
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE28 (EB) TSSOP 0204
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
2. DIMENSIONS ARE IN
FOR EXPOSED PAD ATTACHMENT
MILLIMETERS
(INCHES)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3. DRAWING NOT TO SCALE
3782fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LT3782
U
TYPICAL APPLICATIO S
28V Output Base Station Power Converter with Redundant Input
V
INA
0V TO 28V*
1
2
3
4
5
6
28
27
26
25
24
23
SGATE1
SGATE2
NC
GBIAS
2R2
L1
10µH
V
CC
D1
UPS840
BAS516
NC
NC
Q1
PH4840S
1µF
GND
C
INA
22µF
C
OUT2
330µF, 35V, 2x
CS1
0.004Ω
SYNC
DELAY
V
EE1
BGATE1
GBIAS1
GBIAS2
7
8
22
21
DCL
OUTPUT
28V
4A (8A**)
10Ω
+
–
CS1
SENSE1
LT3782
C
OUT1
2.2µF
10nF
10µF, 50V, 4x
9
20
19
SENSE1
SLOPE
BGATE2
0.004Ω
CS2
59k
82k
10
V
EE2
NC
C
INB
22µF
825k
274k
11
12
18
17
R
SET
Q2
PH4840S
–
+
SENSE2
RUN
FB
10nF
10Ω
24.9k
261k
13
14
16
15
L2
10µH
BAS516
CS2
SENSE2
SS
D2
UPS840
V
C
3782 TA03
NOTE:
4.7nF
V
INB
0V TO 28V*
C
C1
4.7nF
*INPUT VOLTAGE RANGE FOR VINA AND VINB IS 0V TO 28V.
AT LEAST ONE OF THE INPUTS MUST BE 12V OR HIGHER.
R
C1
C
C2
100pF
15k
L1, L2: PULSE PB2020-103
ALL CERAMIC CAPACITORS ARE X7R, TDK
**OUTPUT CURRENT WITH BOTH INPUTS 12V OR HIGHER
RELATED PARTS
PART NUMBER
DESCRIPTION
Current Mode PWM Controller
Current Mode DC/DC Controller
COMMENTS
LT®1619
300kHz Fixed Frequency, Boost, SEPIC, Flyback Topology
LTC1624
SO-8; 300kHz Operating Frequency; Buck, Boost, SEPIC Design;
V
Up to 36V
IN
LTC1696
Overvoltage Protection Controller
0.8V ≤ V ≤ 24V, ±2% Overvoltage Threshold Accuracy,
IN
ThinSOT Package
LTC1700
No R ™Synchronous Step-Up Controller
Up to 95% Efficiency, Operation as Low as 0.9V Input
SENSE
LTC1871/LTC1871-7
LT1930
Wide Input Range Controller
No R
, 7V Gate Drive, Current Mode Control
SENSE
1.2MHz, SOT-23 Boost Converter
Single Switch Synchronous Forward Controller
Up to 34V Output, 2.6V ≤ V ≤ 16V, Miniature Design
High Efficiency, 25W to 500W, Wide Input Range, Adaptive
Duty Cycle Clamp
IN
LT1952
LTC3425
5A, 8MHz 4-Phase Monolithic Step-Up DC/DC Converter
0.5V ≤ V ≤ 4.5V, 2.4V ≤ V
≤ 5.25V, Very Low Output Ripple
OUT
IN
LTC3703/LTC3703-5
100V and 60V, Step-Down and Step-Up DC/DC
Synchronous Controller
High Efficiency Synchronous Operation, High Voltage Operation,
No Transformer Required
LTC3728
LTC3729
Dual, 550kHz, 2-Phase Synchronous Step-Down
Controller
Dual 180° Phased Controllers, V : 3.5V to 35V, 99% Duty Cycle,
IN
5x5QFN, SSOP-28 Packages
20A to 200A, 550kHz PolyPhase™ Synchronous Controller Expandable from 2-Phase to 12-Phase, Uses all Surface Mount
Components, V up to 36V
IN
LTC3731
LTC3803
3- to 12-Phase Step-Down Synchronous Controller
SOT-23 Flyback Controller
60A to 240A Output Current, 0.6V ≤ V
Adjustable Slope Compensation, Internal Soft-Start, Current
Mode 200kHz Operation
≤ 6V, 4.5V ≤ V ≤ 32V
OUT IN
LTC3806
Synchronous Flyback Controller
High Efficiency, Improves Cross Regulation in Multiple Output
Designs, Current Mode, 3mm × 4mm 12 Pin DFN Package
No RSENSE and PolyPhase are trademarks of Linear Technology Corporation.
3782fa
LT/LT 0705 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2004
相关型号：
LT3782AEFE#PBF
LT3782A - 2-Phase Step-Up DC/DC Controller; Package: TSSOP; Pins: 28; Temperature Range: -40°C to 85°C
Linear
LT3782AEUFD#TR
IC 0.07 A SWITCHING CONTROLLER, 533 kHz SWITCHING FREQ-MAX, PQCC28, 4 X 5 MM, PLASTIC, MO-220WXXX-X, QFN-28, Switching Regulator or Controller
Linear
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