LT3800IFE-TRPBF_技术文档

LT3800

High-Voltage Synchronous

Current Mode Step-Down

U

Controller

FEATURES

DESCRIPTIO

The LT^®3800 is a 200kHz fixed frequency high voltage

synchronous current mode step-down switching regula-

torcontroller.TheICdrivesstandardgateN-channelpower

MOSFETs and can operate with input voltages from 4V to

60V.AnonboardregulatorprovidesICpowerdirectlyfrom

V_INandprovidesforoutput-derivedpowertominimizeV_IN

quiescent current. MOSFET drivers employ an internal

dynamic bootstrap feature, maximizing gate-source “ON”

voltages during normal operation for improved operating

efficiencies.TheLT3800incorporatesBurstMode^®opera-

tion, which reduces no load quiescent current to under

100µA. Light load efficiencies are also improved through

a reverse inductor current inhibit, allowing the controller

to support discontinuous operation. Both Burst Mode

operation and the reverse-current inhibit features can be

disabled if desired. The LT3800 incorporates a program-

mablesoft-startthatdirectlycontrolsthevoltageslewrate

of the converter output for reduced startup surge currents

and overshoot errors. The LT3800 is available in a 16-lead

thermally enhanced TSSOP package.

■

Wide 4V to 60V Input Voltage Range

■

Output Voltages up to 36V

■

Adaptive Nonoverlap Circuitry Prevents Switch

Shoot-Through

■

Reverse Inductor Current Inhibit for Discontinuous

Operation Improves Efficiency with Light Loads

■

Output Slew Rate Controlled Soft-Start with

Auto-Reset

■

100µA No Load Quiescent Current

■

Low 10µA Current Shutdown

■

1% Regulation Accuracy

■

200kHz Operating Frequency

■

Standard Gate N-Channel Power MOSFETs

■

Current Limit Unaffected by Duty Cycle

■

Reverse Overcurrent Protection

■

16-Lead Thermally Enhanced TSSOP Package

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APPLICATIO S

■

12V and 42V Automotive and Heavy Equipment

■

48V Telecom Power Supplies

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

Burst Mode is a registered trademark of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

■

Avionics and Industrial Control Systems

Distributed Power Converters

■

Protected by U.S. Patents, including 5481178, 6611131, 6304066, 6498466, 6580258.

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TYPICAL APPLICATIO

12V 75W DC/DC Converter with Reverse Current Inhibit and Input UVLO

V

IN

20V TO 55V

+

1µF

56µF

Efficiency and Power Loss

×3

×2

V

BOOST

TG

IN

100

95

90

85

80

75

70

6

5

4

3

2

1

0

1µF

V

= 24V

= 60V

IN

Si7850DP

Si7370DP

1M

V

= 36V

LT3800

IN

82.5k

SHDN

SW

V

1.5nF

IN

BAS19

200k

C

SS

15µH

V

= 48V

IN

1N4148

174k

1%

BURST_EN

V

CC

20k

1%

1µF

V

BG

B160

FB

LOSS (48V)

V

PGND

C

82.5k

680pF

100pF

–

+

SENSE

SGND

0.015Ω

10

0.1

1

V

I

(A)

OUT

12V AT 75W

LOAD

3800 TA01b

+

10µF

270µF

3800 TA01a

3800fb

1

LT3800

W W

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ABSOLUTE AXI U RATI GS_{(Note 1)}

PI CO FIGURATIO

Supply Voltages

TOP VIEW

Input Supply Pin (V_IN) .............................. –0.3V to 65V

Boosted Supply Pin (BOOST) ................... –0.3V to 80V

Boosted Supply Voltage (BOOST – SW) .. –0.3V to 24V

Boosted Supply Reference Pin (SW) ........... –2V to 65V

Local Supply Pin (V_CC) ............................. –0.3V to 24V

Input Voltages

V

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

BOOST

TG

IN

NC

SHDN

SW

C

NC

SS

17

BURST_EN

V

CC

SENSE⁺, SENSE^–...................................... –0.3V to 40V

SENSE⁺– SENSE^–......................................... –1V to 1V

BURST_EN Pin ......................................... –0.3V to 24V

Other Inputs (SHDN, C_SS, V_FB, V_C) .......... –0.3V to 5.0V

Input Currents

V

BG

FB

V

C

PGND

–

+

SENSE

FE PACKAGE

16-LEAD PLASTIC TSSOP

T_JMAX= 125°C, θ_JA= 40°C/W, θ_JC= 10°C/W

SHDN, C_SS............................................... –1mA to 1mA

Maximum Temperatures

EXPOSED PAD (PIN 17) IS SGND

MUST BE SOLDERED TO PCB

Operating Junction Temperature Range (Note 2)

LT3800E (Note 3) ............................. –40°C to 125°C

LT3800I ............................................ –40°C to 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

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W

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ORDER I FOR ATIO

LEAD FREE FINISH

LT3800EFE#PBF

LT3800IFE#PBF

TAPE AND REEL

LT3800EFE#TRPBF

LT3800IFE#TRPBF

PART MARKING

3800EFE

3800IFE

PACKAGE DESCRIPTION

16-Lead Plastic TSSOP

TEMPERATURE RANGE

–40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges.

Consult LTC Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS

SENSE = SENSE = 10V, SGND = PGND = SW = 0V, CTG = CBG = 3300pF, unless otherwise noted.

The

●

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T = 25°C. V = 20V, V = BOOST = BURST_EN = 10V, SHDN = 2V,

A

IN

CC

–

+

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Operating Voltage Range (Note 4)

Minimum Start Voltage

UVLO Threshold (Falling)

UVLO Hysteresis

●

4

7.5

3.65

60

V

IN

3.80

670

3.95

mV

I

V

Supply Current

Burst Mode Current

Shutdown Current

V

> 9V

BURST_EN

20

8

µA

VIN

IN

CC

= 0V, V = 1.35V

FB

= 0V

●

15

SHDN

V

Operating Voltage

●

75

20

V

BOOST

Operating Voltage Range (Note 5)

UVLO Threshold (Rising)

UVLO Hysteresis

V

– V

BOOST

SW

5

0.4

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2

LT3800

ELECTRICAL CHARACTERISTICS

SENSE = SENSE = 10V, SGND = PGND = SW = 0V, CTG = CBG = 3300pF, unless otherwise noted.

The

●

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T = 25°C. V = 20V, V = BOOST = BURST_EN = 10V, SHDN = 2V,

A

IN

CC

–

+

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

I

BOOST Supply Current (Note 6)

BOOST Burst Mode Current

BOOST Shutdown Current

1.4

0.1

mA

µA

BOOST

V

= 0V

BURST_EN

SHDN

V

Operating Voltage (Note 5)

Output Voltage

UVLO Threshold (Rising)

●

20

8.3

V

CC

8.0

6.25

500

UVLO Hysteresis

mV

I

V

Supply Current (Note 6)

Burst Mode Current

Shutdown Current

●

3

80

20

3.6

mA

µA

VCC

CC

V

= 0V

BURST_EN

µA

SHDN

Short-Circuit Current

●

–40

–120

mA

V

Enable Threshold (Rising)

Threshold Hysteresis

1.30

1.35

120

1.40

V

mV

SHDN

Common Mode Range

●

0

140

36

175

SENSE

+

–

Current Limit Sense Voltage

Reverse Protect Sense Voltage

Reverse Current Offset

V

– V

150

–150

10

mV

SENSE

+

, V

BURST_EN

= V

CC

SENSE

= 0V or V

= V

BURST_EN

FB

I

f

Input Current

V

= 0V

= 2.75V

> 4V

0.8

–20

–0.3

mA

µA

SENSE

O

SENSE(CM)

+

–

(I

SENSE

+ I

SENSE

)

mA

Operating Frequency

190

175

200

1.231

25

210

220

kHz

●

V

Error Amp Reference Voltage

Measured at V Pin

1.224

1.215

1.238

1.245

V

FB

I

Feedback Input Current

nA

FB

V

Soft-Start Disable Voltage

Soft-Start Disable Hysteresis

V

Rising

FB

1.185

300

V

mV

FB(SS)

I

Soft-Start Capacitor Control Current

Error Amp Transconductance

Error Amp DC Voltage Gain

Error Amp Output Range

2

µA

µmhos

dB

CSS

g

●

275

350

62

400

m

A

V

C

Zero Current to Current Limit

10% to 90% or 90% to 10%

1.2

±30

V

I

Error Amp Sink/Source Current

µA

VC

V

Gate Drive Output On Voltage (Note 7)

Gate Drive Output Off Voltage

9.8

0.1

V

TG,BG

t

Gate Drive Rise/Fall Time

Minimum Off Time

50

ns

TG,BG

TG(OFF)

TG(ON)

NOL

450

300

Minimum On Time

●

500

Gate Drive Nonoverlap Time

TG Fall to BG Rise

BG Fall to TG Rise

200

150

ns

3800fb

3

LT3800

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 4: V voltages below the start-up threshold (7.5V) are only

IN

supported when V is externally driven above 6.5V.

CC

Note 5: Operating range dictated by MOSFET absolute maximum gate-

source voltage ratings.

Note 2: This IC includes overtemperature protection that is intended to

protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

Note 3: The LT3800E is guaranteed to meet performance specifications from

0°C to 125°C junction temperature. Specifications over the –40°C to 125°C

operating junction temperature range are assured by design, characterization

and correlation with statistical process controls. The LT3800I is guaranteed

over the full –40°C to 125°C operating junction temperature range.

Note 6: Supply current specification does not include switch drive

currents. Actual supply currents will be higher.

Note 7: DC measurement of gate drive output “ON” voltage is typically

8.6V. Internal dynamic bootstrap operation yields typical gate “ON”

voltages of 9.8V during standard switching operation. Standard operation

gate “ON” voltage is not tested but guaranteed by design.

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TYPICAL PERFOR A CE CHARACTERISTICS

Shutdown Threshold (Falling)

vs Temperature

Shutdown Threshold (Rising)

vs Temperature

V

vs Temperature

CC

8.1

8.0

7.9

7.8

1.37

1.36

1.35

1.34

1.33

1.240

1.235

1.230

1.225

1.220

I

CC

= 0mA

I

CC

= 20mA

50

75 100

–50 –25

125

–50 –25

0

25

50

75

100 125

0

25

–50 –25

0

25

50

75

100 125

TEMPERATURE (°C)

3800 G03

3800 G01

3800 G02

V

vs I

V

vs V

I

Current Limit vs Temperature

CC

CC(LOAD)

CC

IN

CC

8

7

6

5

4

3

200

175

150

125

100

75

8.05

8.00

7.95

7.90

7.85

I

= 20mA

= 25°C

T

= 25°C

CC

A

T

A

50

8

4

5

6

7

9

10 11 12

–50 –25

0

25

50

75

100 125

0

5

15 20 25 30

40

10

35

V

(V)

TEMPERATURE (°C)

I

(mA)

IN

CC(LOAD)

3800 G05

3800 G06

3800 G04

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4

LT3800

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TYPICAL PERFOR A CE CHARACTERISTICS

Error Amp Transconductance

vs Temperature

V

UVLO Threshold (Rising)

CC

I

vs V (SHDN = 0V)

vs Temperature

CC

6.30

6.25

6.20

6.15

380

360

340

320

25

20

15

T

= 25°C

A

10

5

0

–50 –25

0

25

50

75

100 125

0

2

4

6

8

10 12 14 16 18 20

(V)

–50 –25

0

25

50

75

100 125

TEMPERATURE (°C)

V

TEMPERATURE (°C)

CC

3800 G07

3800 G08

3800 G12

Error Amp Reference

vs Temperature

Operating Frequency

vs Temperature

+

–

I

vs V

(SENSE + SENSE )

SENSE(CM)

= 25°C

1.232

1.231

1.230

1.229

1.228

1.227

800

600

400

200

0

220

210

200

190

180

T

A

–200

–400

–50 –25

0

25

50

75

100 125

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

(V)

–50 –25

0

25

50

75

100 125

TEMPERATURE (°C)

V

TEMPERATURE (°C)

SENSE(CM)

3800 G11

3800 G09

3800 G10

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PI FU CTIO S

V_IN(Pin 1): Converter Input Supply.

C_SS(Pin 4): Soft-Start AC Coupling Capacitor Input.

Connectcapacitor(C_SS)inserieswitha200kresistorfrom

pin to converter output (V_OUT). Controls converter start-

up output voltage slew rate (∆V_OUT/∆t). Slew rate corre-

sponds to 2µA average current through the soft-start

coupling capacitor. The capacitor value for a desired

output startup slew rate follows the relation:

NC (Pin 2): No Connection.

SHDN (Pin 3): Precision Shutdown Pin. Enable threshold

is 1.35V (rising) with 120mV of input hysteresis. When in

shutdown mode, all internal IC functions are disabled. The

precision threshold allows use of the SHDN pin to incor-

porate UVLO functions. If the SHDN pin is pulled below

0.7V, the IC enters a low current shutdown mode with

I_VIN<10µA.Inlow-currentshutdown,theICwillsink20µA

from the V_CCpin until that local supply has collapsed.

Typical pin input bias current is <10nA and the pin is

internally clamped to 6V.

C_SS= 2µA/(∆V_OUT/∆t)

Shorting this pin to SGND disables the soft-start function

BURST_EN (Pin 5): Burst Mode Operation Enable Pin.

This pin also controls reverse-inhibit mode of operation.

When the pin voltage is below 0.5V, Burst Mode operation

3800fb

5

LT3800

U

PI FU CTIO S

and reverse-current inhibit functions are enabled. When

the pin voltage is above 0.5V, Burst Mode operation is

disabled, but reverse-current inhibit operation is main-

tained. DC/DC converters operating with reverse-current

inhibitoperation(BURST_EN=V_FB)havea1mAminimum

loadrequirement.Reverse-currentinhibitisdisabledwhen

the pin voltage is above 2.5V. This pin is typically shorted

to ground to enable Burst Mode operation and reverse-

current inhibit, shorted to V_FBto disable Burst Mode

operation while enabling reverse-current inhibit, and con-

nected to V_CCpin to disable both functions. See Applica-

tions Information section.

clamp on the V_Cpin is set at 100mV below the burst

threshold, which limits the negative excursion of the pin

voltage. Therefore, this pin cannot be pulled low with a

low-impedance source. If the V_Cpin must be externally

manipulated, do so through a 1kΩ series resistance.

SENSE^–(Pin 8): Negative Input for Current Sense Ampli-

fier. Sensed inductor current limit set at ±150mV across

SENSE inputs.

SENSE⁺(Pin 9): Positive Input for Current Sense Ampli-

fier. Sensed inductor current limit set at ±150mV across

SENSE inputs.

PGND (Pin 10): High Current Ground Reference for Syn-

chronous Switch. Current path from pin to negative termi-

nal of V_CCdecoupling capacitor must not corrupt SGND.

V_FB(Pin 6): Error Amplifier Inverting Input. The

noninvertinginputoftheerroramplifierisconnectedtoan

internal 1.231V reference. Desired converter output volt-

age (V_OUT) is programmed by connecting a resistive

divider from the converter output to the V_FBpin. Values for

the resistor connected from V_OUTto V_FB(R2) and the

resistor connected from V_FBto ground (R1) can be calcu-

lated via the following relationship:

BG (Pin 11): Synchronous Switch Gate Drive Output.

V_CC(Pin 12): Internal Regulator Output. Most IC func-

tions are powered from this pin. Driving this pin from an

external source reduces V_INpin current to 20µA. This pin

is decoupled with a low ESR 1µF capacitor to PGND.

In shutdown mode, this pin sinks 20µA until the pin

voltage is discharged to 0V. See Typical Performance

Characteristics.

V

⎛

⎜

⎝

⎞

⎠

OUT

R2 = R1•

– 1

⎟

1.231

The V_FBpin input bias current is 25nA, so use of extremely

high value feedback resistors could cause a converter

output that is slightly higher than expected. Bias current

error at the output can be estimated as:

NC (Pin 13): No Connection.

SW (Pin 14): Reference for V_BOOSTSupply and High

Current Return for Bootstrapped Switch.

∆V_OUT(BIAS)= 25nA • R2

TG (Pin 15): Bootstrapped Switch Gate Drive Output.

V_C(Pin 7): Error Amplifier Output. The voltage on the V_C

pin corresponds to the maximum (peak) switch current

per oscillator cycle. The error amplifier is typically config-

ured as an integrator by connecting an RC network from

thispintoground. Thisnetworkcreatesthedominantpole

for the converter voltage regulation feedback loop. Spe-

cific integrator characteristics can be configured to opti-

mize transient response. Connecting a 100pF or greater

high frequency bypass capacitor from this pin to ground

is also recommended. When Burst Mode operation is

enabled(seePin5description),aninternallowimpedance

BOOST (Pin 16): Bootstrapped Supply – Maximum Oper-

ating Voltage (Ground Referred) to 75V. This pin is

decoupled with a low ESR 1µF capacitor to pin SW. The

voltage on the decoupling capacitor is refreshed through

a rectifier from either V_CCor an external source.

Exposed Package Backside (SGND) (Pin 17): Low Noise

Ground Reference. SGND connection is made through the

exposed lead frame on back of TSSOP package which

must be soldered to the PCB ground.

3800fb

6

LT3800

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FU CTIO AL DIAGRA

V

IN

UVLO

(<4V)

BST

V

BOOST

16

15

CC

UVLO

1

V

IN

UVLO

(<6V)

8V

REG

BOOSTED

SWITCH

DRIVER

3.8V

REG

INTERNAL

SUPPLY RAIL

DRIVE

CONTROL

TG

FEEDBACK

SW

14

12

REFERENCE

NOL

–

+

1.231V

SWITCH

DRIVE

LOGIC

CONTROL

V

CC

+

–

3

5

SHDN

SYNCHRONOUS

SWITCH DRIVER

DRIVE

CONTROL

BG

11

10

PGND

+

–

BURST_EN

OSCILLATOR

+

–

Q

R

S

6

7

V

FB

SLOPE COMP

GENERATOR

–

+

g

m

Q

ERROR

AMP

R

0.5V

CURRENT

SENSE

–

+

COMPARATOR

V

S

C

SOFT-START

DISABLE/BURST

ENABLE

–

+

REVERSE

CURRENT

INHIBIT

+

1V

–

+

Burst Mode

OPERATION

1.185V

160mV

2µA

4

C

SS

–

+

SENSE

9

8

10mV

–

SENSE

GND

17

3800 FD

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LT3800

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APPLICATIO S I FOR ATIO

Overview

threshold is not obtained for the entire oscillator cycle, the

switch driver is disabled at the end of the cycle for 450ns.

This minimum off-time mode of operation assures regen-

eration of the BOOST bootstrapped supply.

The LT3800 is a high input voltage range step-down

synchronous DC/DC converter controller IC that uses a

200kHz constant frequency, current mode architecture

with external N-channel MOSFET switches.

Power Requirements

The LT3800 has provisions for high efficiency, low load

operation for battery-powered applications. Burst Mode

operation reduces total average input quiescent currents

to100µAduringnoloadconditions.Alowcurrentshutdown

mode can also be activated, reducing quiescent current to

<10µA. Burst Mode operation can be disabled if desired.

The LT3800 is biased using a local linear regulator to

generate internal operational voltages from the V_INpin.

Virtually all of the circuitry in the LT3800 is biased via an

internallinearregulatoroutput(V_CC).Thispinisdecoupled

with a low ESR 1µF capacitor to PGND.

The V_CCregulator generates an 8V output provided there

is ample voltage on the V_INpin. The V_CCregulator has

approximately 1V of dropout, and will follow the V_INpin

with voltages below the dropout threshold.

The LT3800 also employs a reverse-current inhibit fea-

ture, allowing increased efficiencies during light loads

through nonsynchronous operation. This feature disables

the synchronous switch if inductor current approaches

zero. If full time synchronous operation is desired, this

feature can be disabled.

The LT3800 has a start-up requirement of V_IN> 7.5V. This

assures that the onboard regulator has ample headroom

to bring the V_CCpin above its UVLO threshold. The V_CC

regulator can only source current, so forcing the V_CCpin

above its 8V regulated voltage allows use of externally

derived power for the IC, minimizing power dissipation in

the IC. Using the onboard regulator for start-up, then

deriving power for V_CCfrom the converter output maxi-

mizes conversion efficiencies and is common practice. If

V_CCismaintainedabove6.5Vusinganexternalsource,the

LT3800 can continue to operate with V_INas low as 4V.

Much of the LT3800’s internal circuitry is biased from an

internal linear regulator. The output of this regulator is the

V

_CCpin, allowing bypassing of the internal regulator. The

associated internal circuitry can be powered from the

output of the converter, increasing overall converter effi-

ciency. Using externally derived power also eliminates the

IC’s power dissipation associated with the internal V_INto

V_CCregulator.

Theory of Operation (See Block Diagram)

TheLT3800operateswith3mAquiescentcurrentfromthe

V_CCsupply. This current is a fraction of the actual V_CC

quiescent currents during normal operation. Additional

current is produced from the MOSFET switching currents

for both the boosted and synchronous switches and are

typically derived from the V_CCsupply.

The LT3800 senses converter output voltage via the V_FB

pin. The difference between the voltage on this pin and an

internal 1.231V reference is amplified to generate an error

voltage on the V_Cpin which is, in turn, used as a threshold

for the current sense comparator.

Because the LT3800 uses a linear regulator to generate

V_CC, power dissipation can become a concern with high

V_INvoltages. Gate drive currents are typically in the range

of 5mA to 15mA per MOSFET, so gate drive currents can

create substantial power dissipation. It is advisable to

derive V_CCand V_BOOSTpower from an external source

whenever possible.

During normal operation, the LT3800 internal oscillator

runs at 200kHz. At the beginning of each oscillator cycle,

the switch drive is enabled. The switch drive stays enabled

until the sensed switch current exceeds the V_Cderived

threshold for the current sense comparator and, in turn,

disables the switch driver. If the current comparator

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8

LT3800

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APPLICATIO S I FOR ATIO

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Charge Pump Doubler

TheonboardV_CCregulatorwillprovidegatedrivepowerfor

start-upunderallconditionswithtotalMOSFETgatecharge

loads up to 180nC. The regulator can operate the LT3800

continuously,providedtheV_INvoltageand/orMOSFETgate

chargecurrentsdonotcreateexcessivepowerdissipation

in the IC. Safe operating conditions for continuous regu-

latoruseareshowninFigure1.Inapplicationswherethese

conditions are exceeded, V_CCmust be derived from an

external source after start-up.

V

OUT

B0520

V

CC

1µF

LT3800

Si1555DL

BG

Charge Pump Tripler

70

V

OUT

1µF

B0520

60

50

40

1µF

B0520

1µF

V

CC

Si1555DL

30

LT3800

SAFE

20

3800 AI01

OPERATING

CONDITIONS

10

BG

0

50

100

150

200

TOTAL FET GATE CHARGE (nC)

3800 F01

Inductor Auxiliary Winding

Figure 1. V Regulator Continuous Operating Conditions

CC

TG

In LT3800 converter applications with output voltages in

the 9V to 20V range, back-feeding V_CCand V_BOOSTfrom

the converter output is trivial, accomplished by connect-

ing diodes from the output to these supply pins. Deriving

these supplies from output voltages greater than 20V will

require additional regulation to reduce the feedback volt-

age.Outputslowerthan9Vwillrequirestep-uptechniques

toincreasethefeedbackvoltagetosomethinggreaterthan

the 8V V_CCregulated output. Low power boost switchers

are sometimes used to provide the step-up function, but

a simple charge-pump can perform this function in many

instances.

SW

LT3800

N

•

V

OUT

V

CC

•

BG

3800 AI04

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Burst Mode

During Burst Mode operation, V_INpin current is 20µA and

V_CCcurrent is reduced to 80µA. If no external drive is

provided for V_CC, all V_CCbias currents originate from the

V_INpin, giving a total V_INcurrent of 100µA. Burst current

can be reduced further when V_CCis driven using an output

derived source, as the V_CCcomponent of V_INcurrent is

then reduced by the converter buck ratio.

TheLT3800employslowcurrentBurstModefunctionality

to maximize efficiency during no load and low load condi-

tions. Burst Mode operation is enabled by shorting the

BURST_EN pin to SGND. Burst Mode operation can be

disabled by shorting BURST_EN to either V_FBor V_CC.

When the required switch current, sensed via the V_Cpin

voltage, is below 15% of maximum, the Burst Mode

operation is employed and that level of sense current is

latchedontotheICcontrolpath. Iftheoutputloadrequires

less than this latched current level, the converter will

overdrive the output slightly during each switch cycle.

This overdrive condition is sensed internally and forces

the voltage on the V_Cpin to continue to drop. When the

voltage on V_Cdrops 150mV below the 15% load level,

switching is disabled and the LT3800 shuts down most of

its internal circuitry, reducing total quiescent current to

100µA.Whentheconverteroutputbeginstofall,theV_Cpin

voltage begins to climb. When the voltage on the V_Cpin

climbs back to the 15% load level, the IC returns to normal

operation and switching resumes. An internal clamp on

the V_Cpin is set at 100mV below the switch disable

threshold, which limits the negative excursion of the pin

voltage, minimizing the converter output ripple during

Burst Mode operation.

Reverse-Current Inhibit

The LT3800 contains a reverse-current inhibit feature to

maximize efficiency during light load conditions. This

mode of operation allows discontinuous operation, and is

sometimes referred to as “pulse-skipping” mode. Refer to

Figure 2.

ThisfeatureisenabledwithBurstModeoperation,andcan

also be enabled while Burst Mode operation is disabled by

shorting the BURST_EN pin to V_FB.

Whenreverse-currentinhibitisenabled,theLT3800sense

amplifier detects inductor currents approaching zero and

disables the synchronous switch for the remainder of the

switch cycle. If the inductor current is allowed to go

negative before the synchronous switch is disabled, the

switch node could inductively kick positive with a high

dv/dt. The LT3800 prevents this by incorporating a 10mV

positive offset at the sense inputs.

PULSE SKIP MODE

FORCED CONTINUOUS

I

L

I

L

DECREASING

LOAD

CURRENT

3800 F02

Figure 2. Inductor Current vs Mode

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U

corresponds to 2µA average current during the soft-start

Withthereverse-currentinhibitfeatureenabled,anLT3800

converter will operate much like a nonsynchronous

converter during light loads. Reverse-current inhibit re-

duces resistive losses associated with inductor ripple

currents, which improves operating efficiencies during

light-load conditions.

interval. This capacitor value follows the relation:

2E^–6• t_SS

C_SS1

=

V_OUT

R_SSis typically set to 200k for most applications.

An LT3800 DC/DC converter that is operating in reverse-

inhibit mode has a minimum load requirement of 1mA

(BURST_EN = V_FB). Since most applications use output-

generated power for the LT3800, this requirement is met

by the bias currents of the IC, however, for applications

that do not derive power from the output, this require-

ment is easily accomplished by using a 1.2k resistor

connected from V_FBto ground as one of the converter

outputvoltageprogrammingresistors(R1). Thereareno

minimumloadrestrictionswheninBurstModeoperation

(BURST_EN < 0.5V) or continuous conduction mode

(BURST_EN > 2.5V).

C

SS1

LT3800

R

SS

A

V

C

SS

OUT

3800 AI06

Considerations for Low Voltage Output Applications

The LT3800 C_SSpin biases to 220mV during the soft-start

cycle, and this voltage is increased at network node “A” by

the 2µA signal current through R_SS, so the output has to

reach this value before the soft-start function is engaged.

The value of this output soft-start start-up voltage offset

(V_OUT(SS)) follows the relation:

Soft-Start

V_OUT(SS)= 220mV + R_SS• 2E^–6

TheLT3800incorporatesaprogrammablesoft-startfunc-

tion to control start-up surge currents, limit output over-

shoot and for use in supply sequencing. The soft-start

function directly monitors and controls output voltage

slew rate during converter start-up.

which is typically 0.64V for R_SS= 200k.

In some low voltage output applications, it may be desir-

able to reduce the value of this soft-start start-up voltage

offset. This is possible by reducing the value of R_SS. With

reduced values of R_SS, the signal component caused by

voltage ripple on the output must be minimized for proper

soft-start operation.

As the output voltage of the converter rises, the soft-start

circuit monitors δV/δt current through a coupling capaci-

tor and adjusts the voltage on the V_Cpin to maintain an

average value of 2µA. The soft-start function forces the

programmed slew rate while the converter output rises to

95% regulation, which corresponds to 1.185V on the V_FB

pin. Once 95% regulation is achieved, the soft-start circuit

isdisabled.Thesoft-startcircuitwillre-enablewhentheV_FB

pin drops below 70% regulation, which corresponds to

300mV of control hysteresis on the V_FBpin, which allows

for a controlled recovery from a ‘brown-out’ condition.

Peak-to-peak output voltage ripple (∆V_OUT) will be im-

posed on node “A” through the capacitor C_SS1. The value

of R_SScan be set using the following equation:

∆V_OUT

1.3E^–6

R_SS

=

It is important to use low ESR output capacitors for

LT3800 voltage converter designs to minimize this ripple

voltage component. A design with an excessive ripple

component can be evidenced by observing the V_Cpin

during the start cycle.

The desired soft-start rise time (t_SS) is programmed via

a programming capacitor C_SS1, using a value that

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Desirable Soft-Start Characteristic

Soft-Start Characteristic Showing Excessive Ripple Component

V

OUT

V

OUT(SS)

V(V )

C

3800 AI07

3800 AI08

250µs/DIV

The soft-start cycle should be evaluated to verify that the

reduced R_SSvalue allows operation without excessive

modulation of the V_Cpin before finalizing the design.

Inductor current typically doesn’t reach I_MAXin the few

cyclesthatoccurbeforesoft-startbecomesactive,butcan

with high input voltages or small inductors, so the above

relation is useful as a worst-case scenario.

If the V_Cpin has an excessive ripple component during the

soft-startcycle, converteroutputrippleshouldbereduced

or R_SSincreased. Reduction in converter output ripple is

typically accomplished by increasing output capacitance

and/or reducing output capacitor ESR.

This energy transfer increase in output voltage is typically

small,butforsomelowvoltageapplicationswithrelatively

small output capacitors, it can become significant. The

voltage rise can be reduced by increasing output capaci-

tance, which puts additional limitations on C_OUTfor these

low voltage supplies. Another approach is to add an

external current limit foldback circuit which reduces the

value of I_MAXduring start-up.

External Current Limit Foldback Circuit

An additional start-up voltage offset can occur during the

period before the LT3800 soft-start circuit becomes ac-

tive. Before the soft-start circuit throttles back the V_Cpin

in response to the rising output voltage, current as high as

the peak programmed current limit (I_MAX) can flow in the

inductor. Switching will stop once the soft-start circuit

takes hold and reduces the voltage on the V_Cpin, but the

output voltage will continue to increase as the stored

energy in the inductor is transferred to the output capaci-

tor. With I_MAXflowing in the inductor, the resulting lead-

ing-edge rise on V_OUTdue to energy stored in the inductor

follows the relationship:

An external current limit foldback circuit can be easily

incorporated into an LT3800 DC/DC converter application

by placing a 1N4148 diode and a 47k resistor from the

converteroutput(V_OUT)totheLT3800’sV_Cpin. Thislimits

the peak current to 0.25 • I_MAXwhen V_OUT= 0V. A current

limit foldback circuit also has the added advantage of

providingareducedoutputcurrentintheDC/DCconverter

during short-circuit fault conditions, so a foldback circuit

may be useful even if the soft-start function is disabled.

If the soft-start circuit is disabled by shorting the C_SSpin

to ground, the external current limit fold-back circuit must

be modified by adding an additional diode and resistor.

The 2-diode, 2-resistor network shown also provides

0.25 • I_MAXwhen V_OUT= 0V.

⎛ L ⎞^1/2

∆V_OUT= I_MAX

•

⎜

⎟

⎝ C_OUT

⎠

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Alternative Current Limit Foldback Circuit for Applications That

Have Soft-Start Disabled

Current Limit Foldback Circuit for

Applications That Use Soft-Start

V

C

1N4148

27k

47k

39k

V

OUT

3800 AI10

V

3800 AI09

OUT

Adaptive Nonoverlap (NOL) Output Stage

Shutdown

The FET driver output stages implement adaptive

nonoverlap control. This feature maintains a constant

dead time, preventing shoot-through switch currents,

independentofthetype,sizeoroperatingconditionsofthe

external switch elements.

The LT3800 SHDN pin uses a bandgap generated refer-

ence threshold of 1.35V. This precision threshold allows

use of the SHDN pin for both logic-level controlled appli-

cationsandanalogmonitoringapplicationssuchaspower

supply sequencing.

Each of the two switch drivers contains a NOL control

circuit, which monitors the output gate drive signal of the

other switch driver. The NOL control circuits interrupt the

“turn on” command to their associated switch driver until

the other switch gate is fully discharged.

The LT3800 operational status is primarily controlled by a

UVLO circuit on the V_CCregulator pin. When the IC is

enabled via the SHDN pin, only the V_CCregulator is en-

abled. Switching remains disabled until the UVLO thresh-

old is achieved at the V_CCpin, when the remainder of the

IC is enabled and switching commences.

Antislope Compensation

Because an LT3800 controlled converter is a power trans-

fer device, a voltage that is lower than expected on the

input supply could require currents that exceed the sourc-

ing capabilities of that supply, causing the system to lock

up in an undervoltage state. Input supply start-up protec-

tion can be achieved by enabling the SHDN pin using a

resistivedividerfromtheV_INsupplytoground. Settingthe

divider output to 1.35V when that supply is at an adequate

voltage prevents an LT3800 converter from drawing large

currents until the input supply is able to provide the

required power. 120mV of input hysteresis on the SHDN

pin allows for almost 10% of input supply droop before

disabling the converter.

Most current mode switching controllers use slope com-

pensationtopreventcurrentmodeinstability. TheLT3800

is no exception. A slope-compensation circuit imposes an

artificial ramp on the sensed current to increase the rising

slope as duty cycle increases. Unfortunately, this addi-

tional ramp corrupts the sensed current value, reducing

the achievable current limit value by the same amount as

the added ramp represents. As such, current limit is

typically reduced as duty cycles increase. The LT3800

contains circuitry to eliminate the current limit reduction

typically associated with slope compensation. As the

slope-compensation ramp is added to the sensed current,

a similar ramp is added to the current limit threshold

reference. The end result is that current limit is not

compromised, so a LT3800 converter can provide full

power regardless of required duty cycle.

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Programming LT3800 V UVLO

Inductor Selection

IN

TheprimarycriterionforinductorvalueselectioninLT3800

applications is ripple current created in that inductor.

Basic design considerations for ripple current are output

voltageripple, andtheabilityoftheinternalslopecompen-

sationwaveformtopreventcurrentmodeinstability. Once

the value is determined, an inductor must also have a

saturation current equal to or exceeding the maximum

peak current in the inductor.

V

IN

LT3800

R

B

A

3

SHDN

SGND

17

3800 AI02

Ripplecurrent(∆I_L)inaninductorforagivenvalue(L)can

be approximated using the relation:

The UVLO voltage, V_IN(UVLO), is set using the following

relation:

⎛

⎝

V_OUT⎞ V_OUT

∆I = 1–

•

⎟

⎜

V

_IN(UVLO)– 1.35V

L

V

IN

⎠ f_O•L

R_A= R_B•

1.35V

The typical range of values for ∆I is 20% to 40% of

I_OUT(MAX), where I_OUT(MAX)is the maximum converter

output load current. Ripple currents in this range typically

yieldagooddesigncompromisebetweeninductorperfor-

mance versus inductor size and cost, and values in this

range are generally a good starting point. A starting point

inductor value can thus be determined using the relation:

If additional hysteresis is desired for the enable function,

anexternalpositivefeedbackresistorcanbeusedfromthe

LT3800 regulator output.

The shutdown function can be disabled by connecting the

SHDN pin to V_INthrough a large value pull-up resistor.

This pin contains a low impedance clamp at 6V, so the

SHDN pin will sink current from the pull-up resistor (R_PU):

⎛

⎝

V_OUT

V

IN

⎞

⎠

1–

⎜

⎟

V – 6V

R_PU

IN

I_SHDN

=

L = V_OUT

•

f_O• 0.3 •I_OUT(MAX)

Because this arrangement will pull the SHDN pin to the 6V

clamp voltage, it will violate the 5V absolute maximum

voltage rating of the pin. This is permitted, however, as

longastheabsolutemaximuminputcurrentratingof1mA

is not exceeded. Input SHDN pin currents of <100µA are

recommended; a 1MΩ or greater pull-up resistor is typi-

cally used for this configuration.

Use of smaller inductors increase output ripple currents,

requiring more capacitance on the converter output. Also,

with converter operation with duty cycles greater than

50%, the slope compensation criterion, described later,

must be met. Designing for smaller ripple currents re-

quires larger inductor values, which can increase con-

verter cost and/or footprint.

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Somemagneticsvendorsspecifyavolt-secondproductin

their data sheet. If they do not, consult the vendor to make

sure the specification is not being exceeded by your

design. The required volt-second product is calculated as

follows:

duty cycle, to generate an equivalent slope of at least

1E⁵• I_LIMITA/sec, where I_LIMITis the programmed con-

verter current limit. Current limit is programmed by using

a sense resistor (R_S) such that I_LIMIT= 150mV/R_S, so the

equation for the minimum inductance to meet the current

mode instability criterion can be reduced to:

V_OUT

f_O

⎛

⎝

V_OUT

V

IN

⎞

L

_MIN= (5E^–5)(V_OUT)(R_S)

For example, with V_OUT= 5V and R_S= 20mΩ:

_MIN= (5E^–5)(5)(0.02) = 5µH

Volt -Second ≥

• 1–

⎜

⎟

⎠

Magnetics vendors specify either the saturation current,

the RMS current, or both. When selecting an inductor

based on inductor saturation current, the peak current

through the inductor, I_OUT(MAX)+ (∆I/2), is used. When

selectinganinductorbasedonRMScurrentthemaximum

load current, I_OUT(MAX), is used.

L

After calculating the minimum inductance value, the volt-

second product, the saturation current and the RMS

current for your design, an off the shelf inductor can be

selected from a magnetics vendor. A list of magnetics

vendors can be found at http://www.linear.com/ezone/

vlinksorbycontactingtheLinearTechnologyApplications

department.

The requirement for avoiding current mode instability is

keeping the rising slope of sensed inductor ripple current

(S1)greaterthanthefallingslope(S2).Duringcontinuous-

current switcher operation, the rising slope of the current

waveform in the switched inductor is less than the falling

slopewhenoperatingatdutycycles(DC)greaterthan50%.

To avoid the instability condition during this operation, a

false signal is added to the sensed current, increasing the

perceived rising slope. To prevent current mode instabil-

ity,theslopeofthisfalsesignal(Sx)mustbesufficientsuch

that the sensed rising slope exceeds the falling slope, or

S1 + Sx ≥ S2. This leads to the following relations:

Output Voltage Programming

Output voltage is programmed through a resistor feed-

back network to V_FB(Pin 6) on the LT3800. This pin is the

inverting input of the error amplifier, which is internally

referenced to 1.231V. The divider is ratioed to provide

1.231V at the V_FBpin when the output is at its desired

value. The output voltage is thus set following the relation:

V

⎛

⎜

⎝

⎞

⎠

OUT

R2 = R1•

– 1

⎟

Sx ≥ S2 (2DC – 1)/DC

where:

1.231

when an external resistor divider is connected to the

output as shown.

S2 ~ V_OUT/L

Solving for L yields a relation for the minimum inductance

that will satisfy slope compensation requirements:

Programming LT3800 Output Voltage

V

OUT

2DC – 1

DC • Sx

L_MIN= V_OUT

•

LT3800

R2

6

V

FB

The LT3800 maximizes available dynamic range using a

slopecompensationgeneratorthatcontinuouslyincreases

the additional signal slope as duty cycle increases. The

slope compensation waveform is calibrated at an 80%

R1

SGND

17

3800 AI03

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Power MOSFET Selection

I_MAIN= (I_LOAD)(DC)

I_SYNC= (I_LOAD)(1 – DC)

External N-channel MOSFET switches are used with the

LT3800. The positive gate-source drive voltage of the

LT3800 for both switches is roughly equivalent to the V_CC

supply voltage, for use of standard threshold MOSFETs.

The R_DS(ON)required for a given conduction loss can be

calculated using the relation:

P_LOSS= I_SWITCH²• R_DS(ON)

SelectioncriteriaforthepowerMOSFETsincludethe“ON”

resistance(R_DS(ON)),totalgatecharge(Q_G),reversetransfer

In high voltage applications (V_IN> 20V), the main switch

is required to slew very large voltages. MOSFET transition

losses are proportional to V_INand can become the

dominant power loss term in the main switch. This transi-

tion loss takes the form:

capacitance(C_RSS),maximumdrain-sourcevoltage(V_DSS

)

2

and maximum current.

ThepowerFETsselectedmusthaveamaximumoperating

V

_DSSexceeding the maximum V_IN. V_GSvoltage maximum

P_TR≈ (k)(V_IN)²(I_SWITCH)(C_RSS)(f_O)

must exceed the V_CCsupply voltage.

where k is a constant inversely related to the gate drive

current, approximated by k = 2 in LT3800 applications,

and I_SWITCHis the converter output current. The power

loss terms for the switches are thus:

Total gate charge (Q_G) is used to determine the FET gate

drive currents required. Q_Gincreases with applied gate

voltage, so the Q_Gfor the maximum applied gate voltage

must be used. A graph of Q_Gvs. V_GSis typically provided

in MOSFET datasheets.

P_MAIN= (DC)(I_SWITCH)²(1 + d)(R_DS(ON)) +

2(V_IN)²(I_SWITCH)(C_RSS)(f_O)

In a configuration where the LT3800 linear regulator is

providing V_CCand V_BOOSTcurrents, the V_CC8V output

voltage can be used to determine Q_G. Required drive

current for a given FET follows the simple relation:

P_SYNC= (1 – DC)(I_SWITCH)²(1 + d)(R_DS(ON)

)

The (1 + d) term in the above relations is the temperature

dependency of R_DS(ON), typically given in the form of a

normalized R_DS(ON)vs Temperature curve in a MOSFET

data sheet.

I_GATE= Q_G(8V)• f_O

Q_G(8V)is the total FET gate charge for V_GS= 8V, and f₀=

operating frequency. If these currents are externally de-

rived by backdriving V_CC, use the backfeed voltage to

determine Q_G. Be aware, however, that even in a backfeed

configuration, the drive currents for both boosted and

synchronousFETsarestilltypicallysuppliedbytheLT3800

internal V_CCregulator during start-up. The LT3800 can

start using FETs with a combined Q_G(8V)up to 180nC.

The C_RSSterm is typically smaller for higher voltage FETs,

and it is often advantageous to use a FET with a higher V_DS

rating to minimize transition losses at the expense of

additional R_DS(ON)losses.

In some applications, parasitic FET capacitances couple

the negative going switch node transient onto the bottom

gate drive pin of the LT3800, causing a negative voltage in

excess of the Absolute Maximum Rating to be imposed on

that pin. Connection of a catch Schottky diode from this

pin to ground will eliminate this effect. A 1A current rating

is typically sufficient for the diode.

Oncevoltagerequirementshavebeendetermined,R_DS(ON)

can be selected based on allowable power dissipation and

required output current.

InanLT3800buckconverter, theaverageinductorcurrent

is equal to the DC load current. The average currents

through the main (bootstrapped) and synchronous

(ground-referred) switches are:

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Input Capacitor Selection

Output Capacitor Selection

The large currents typical of LT3800 applications require

special consideration for the converter input and output

supply decoupling capacitors. Under normal steady state

buck operation, the source current of the main switch

MOSFET is a square wave of duty cycle V_OUT/V_IN. Most of

this current is provided by the input bypass capacitor. To

prevent large input voltage transients and avoid bypass

capacitor heating, a low ESR input capacitor sized for the

maximum RMS current must be used. This maximum

capacitor RMS current follows the relation:

The output capacitor in a buck converter generally has

muchlessripplecurrentthantheinputcapacitor. Peak-to-

peak ripple current is equal to that in the inductor (∆I_L),

typically a fraction of the load current. C_OUTis selected to

reduce output voltage ripple to a desirable value given an

expected output ripple current. Output ripple (∆V_OUT) is

approximated by:

∆V_OUT≈ ∆I_L(ESR + [(8)(f_O) • C_OUT]^–1)

where f_O= operating frequency.

∆V_OUTincreases with input voltage, so the maximum

operating input voltage should be used for worst-case

calculations. Multiple capacitors are often paralleled to

meet ESR requirements. Typically, once the ESR require-

ment is satisfied, the capacitance is adequate for filtering

and has the required RMS current rating. An additional

ceramic capacitor in parallel is commonly used to reduce

the effect of parasitic inductance in the output capacitor,

which reduces high frequency switching noise on the

converter output.

1

2

I_MAX

V

V – V

(

)

(

)

OUT IN OUT

I_RMS

=

V_IN

which peaks at a 50% duty cycle, when I_RMS= I_MAX/2.

The bulk capacitance is calculated based on an acceptable

maximum input ripple voltage, ∆V_IN, which follows the

relation:

V_OUT

IncreasinginductanceisanoptiontoreduceESRrequire-

ments. For extremely low ∆V_OUT,an additional LC filter

stage can be added to the output of the supply. Applica-

tion Note 44 has information on sizing an additional

output LC filter.

V

IN

C_IN(BULK)= I_OUT(MAX)

•

∆V • f_O

IN

∆V is typically on the order of 100mV to 200mV. Alumi-

num electrolytic capacitors are a good choice for high

voltage, bulkcapacitanceduetotheirhighcapacitanceper

unit area.

Layout Considerations

The LT3800 is typically used in DC/DC converter designs

that involve substantial switching transients. The switch

drivers on the IC are designed to drive large capacitances

and,assuch,generatesignificanttransientcurrentsthem-

selves. Careful consideration must be made regarding

supply bypass capacitor locations to avoid corrupting the

ground reference used by IC.

The capacitor voltage rating must be rated greater than

V_IN(MAX). The combination of aluminum electrolytic ca-

pacitors and ceramic capacitors is a common approach to

meeting supply input capacitor requirements. Multiple

capacitors are also commonly paralleled to meet size or

height requirements in a design.

Capacitor ripple current ratings are often based on only

2000 hours (three months) lifetime; it is advisable to

derate either the ESR or temperature rating of the capaci-

tor for increased MTBF of the regulator.

Typically, high current paths and transients from the input

supply and any local drive supplies must be kept isolated

from SGND, to which sensitive circuits such as the error

amp reference and the current sense circuits are referred.

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Effectivegroundingcanbeachievedbyconsideringswitch

current in the ground plane, and the return current paths

of each respective bypass capacitor. The V_INbypass

return, V_CCbypass return, and the source of the synchro-

nous FET carry PGND currents. SGND originates at the

negative terminal of the V_OUTbypass capacitor, and is the

small signal reference for the LT3800.

such that current paths in the ground plane do not cross

through signal ground areas. Signal ground refers to the

Exposed Pad on the backside of the LT3800 IC. SGND is

referenced to the (–) terminal of the V_OUTdecoupling

capacitor and is used as the converter voltage feedback

reference. Power ground currents are controlled on the

LT3800 via the PGND pin, and this ground references the

high current synchronous switch drive components, as

well as the local V_CCsupply. It is important to keep PGND

and SGND voltages consistent with each other, so sepa-

ratingthesegroundswiththintracesisnotrecommended.

When the synchronous FET is turned on, gate drive surge

currents return to the LT3800 PGND pin from the FET

source. The BOOST supply refresh surge currents also

returnthroughthissamepath.ThesynchronousFETmust

be oriented such that these PGND return currents do not

corrupt the SGND reference. Problems caused by the

PGND return path are generally recognized during heavy

load conditions, and are typically evidenced as multiple

switch pulses occurring during a single 5µs switch cycle.

This behavior indicates that SGND is being corrupted and

grounding should be improved. SGND corruption can

often be eliminated, however, by adding a small capacitor

(100pF-200pF) across the synchronous switch FET from

drain to source.

Don’t be tempted to run small traces to separate ground

paths. A good ground plane is important as always, but

PGND referred bypass elements must be oriented such

that transient currents in these return paths do not

corrupt the SGND reference.

During the dead-time between switch conduction, the

body diode of the synchronous FET conducts inductor

current. Commutating this diode requires a significant

charge contribution from the main switch. At the instant

the body diode commutates, a current discontinuity is

created and parasitic inductance causes the switch node

to fly up in response to this discontinuity. High currents

andexcessiveparasiticinductancecangenerateextremely

fast dV/dt rise times. This phenomenon can cause

avalanche breakdown in the synchronous FET body di-

ode, significant inductive overshoot on the switch node,

and shoot-through currents via parasitic turn-on of the

synchronous FET. Layout practices and component ori-

entations that minimize parasitic inductance on this node

is critical for reducing these effects.

Thehighdi/dtloopformedbytheswitchMOSFETsandthe

input capacitor (C_IN) should have short wide traces to

minimize high frequency noise and voltage stress from

inductive ringing. Surface mount components are pre-

ferred to reduce parasitic inductances from component

leads. Connect the drain of the main switch MOSFET

directly to the (+) plate of C_IN, and connect the source of

the synchronous switch MOSFET directly to the (–) termi-

nal of C_IN. This capacitor provides the AC current to the

switch MOSFETs. Switch path currents can be controlled

by orienting switch FETs, the switched inductor, and input

and output decoupling capacitors in close proximity to

each other.

Ringing waveforms in a converter circuit can lead to

devicefailure,excessiveEMI,orinstability.Inmanycases,

you can damp a ringing waveform with a series RC

network across the offending device. In LT3800 applica-

tions, any ringing will typically occur on the switch node,

which can usually be reduced by placing a snubber across

thesynchronousFET. Useofasnubbernetwork, however,

should be considered a last resort. Effective layout prac-

tices typically reduce ringing and overshoot, and will

eliminate the need for such solutions.

Effective grounding techniques are critical for successful

DC/DC converter layouts. Orient power path components

Locate the V_CCand BOOST decoupling capacitors in close

proximity to the IC. These capacitors carry the MOSFET

3800fb

18

LT3800

W U U

U

APPLICATIO S I FOR ATIO

drivers’highpeakcurrents.Locatethesmall-signalcompo-

nentsawayfromhighfrequencyswitchingnodes(BOOST,

SW, TG, V_CCand BG). Small-signal nodes are oriented on

the left side of the LT3800, while high current switching

nodes are oriented on the right side of the IC to simplify

layout. This also helps prevent corruption of the SGND

reference.

Locate the feedback resistors in close proximity to the

LT3800 to minimize the length of the high impedance V_FB

node.

The SENSE^–and SENSE⁺traces should be routed to-

gether and kept as short as possible.

The LT3800 packaging has been designed to efficiently

remove heat from the IC via the Exposed Pad on the

backside of the package. The Exposed Pad is soldered to

a copper footprint on the PCB. This footprint should be

madeaslargeaspossibletoreducethethermalresistance

of the IC case to ambient air.

Connect the V_FBpin directly to the feedback resistors in-

dependent of any other nodes, such as the SENSE^–pin.

The feedback resistors should be connected between the

(+) and (–) terminals of the output capacitor (C_OUT).

Orientation of Components Isolates Power Path and PGND Currents,

Preventing Corruption of SGND Reference

V

IN

BOOST

SW

+

TG

SW

SGND

REFERRED

COMPONENTS

LT3800

V

CC

+

BG

SGND PGND

3800 AI05

V

OUT

I

SENSE

3800fb

19

LT3800

U

TYPICAL APPLICATIO S

6.5V-55V to 5V 10A DC/DC Converter with Charge Pump Doubler V Refresh and Current Limit Foldback

CC

V

IN

6.5V TO 55V

C2

C8

+

1µF

100V

56µF

63V

×2

X7R ×3

V

BOOST

TG

IN

C1 1µF

16V X7R

D1

BAS19

M1

Si7850DP

×2

R

A

NC

1M

LT3800

C7

1.5nF

SHDN

SW

NC

R4 75k

L1

C

SS

5.6µH

R2

309k

1%

R1

100k

1%

BURST_EN

V

CC

C3 1µF

16V X7R

M2

Si7370DP

×2

DS3

B160

×2

V

FB

BG

V

PGND

C

R3

R5

47k

C10

100pF

–

+

62k

SENSE

C9

470pF

SGND

R

S

0.01Ω

D2

1N4148

V

OUT

5V AT 10A

DS1

MBRO520L

C6

+

C5

M3

10µF

6.3V

X7R

DS2

MBRO520L

220µF

1/2 Si1555DL

×2

3800 TA02a

M4

C4

1µF

1/2 Si1555DL

C5: SANYO POSCAP 6TP220M

L1: IHLP-5050FD-01

Efficiency and Power Loss

100

12

10

95

V

= 24V

IN

= 13.8V

IN

V

= 48V

IN

90

85

8

6

V

= 55V

IN

POWER LOSS

= 48V

80

75

4

2

0

V

IN

POWER LOSS

IN

V

= 13.8V

70

0

2

4

6

8

10

I

(A)

OUT

3800 TA02b

3800fb

20

LT3800

U

TYPICAL APPLICATIO S

9V-38V to 3.3V 10A DC/DC Converter with Input UVLO and Burst Mode Operation

No Load I(V ) = 100µA

IN

V

IN

9V TO 38V

C8

C9

+

100µF

50V

×2

4.7µF

50V

V

BOOST

TG

IN

X7R ×3

C5 1µF

16V X7R

M1

Si7884DP

R

A

NC

R

B

1M

LT3800

187k

SHDN

SW

NC

C1 1nF

R4 39k

D1

L1

C

SS

MBR520

3.3µH

R1

100k

1%

R2

BURST_EN

V

C10

CC

169k

1%

C4 1µF

16V X7R

100pF

DS1

SS14

×2

M2

Si7884DP

V

BG

FB

V

PGND

C

R3

82k

C2

C3

100pF

–

+

SENSE

SGND

R

S

330pF

0.01Ω

V

OUT

3.3V AT 10A

C7

+

C6

10µF

6.3V

X7R

C6: SANYO POSCAP 4TPD470M

L1: IHLP-5050FD-01

470µF

×2

3800 TA03a

Efficiency and Power Loss

92

90

88

86

84

82

80

78

7

6

5

4

3

2

1

0

V

= 13.8V

IN

0.1

10

1

I

(A)

LOAD

3800 TA03b

3800fb

21

LT3800

U

TYPICAL APPLICATIO S

9V-38V to 5V 6A DC/DC Converter with All Ceramic Capacitors, Input UVLO,

Burst Mode Operation and Current Limit Foldback

V

IN

9V TO 38V

C8

22µF

×3

V

BOOST

TG

IN

C5 1µF

10V X7R

R

A

M1

C9 1nF

187k

1M

NC

Si7884DP

LT3800

R

B

SHDN

SW

NC

C1 3.9nF

R4 51k

D1

L1

C

SS

BAS19

10µH

R2

154k

1%

R1

49.9k

1%

C6

47pF

BURST_EN

V

CC

C4 1µF

10V X7R

DS1

SS14

M2

Si7884DP

V

BG

FB

C

PGND

R3

27k

C2

1nF

C3

100pF

R5

47k

D2

1N4148

–

+

SENSE

SGND

R

S

0.02Ω

V

OUT

5V AT 6A

C7

100µF

×2

3800 TA05a

C7: TDK C4532X5R0J107MT

C8: TDK C5750X7R1E226MT

L1: IHLP-5050FD-01

Efficiency and Power Loss

100

95

90

85

80

75

70

65

60

3.20

V

= 13.8V

IN

2.80

2.40

2.00

1.60

1.20

0.80

0.40

0

0.001

0.01

0.1

1

10

I

(A)

LOAD

3800 TA05b

3800fb

22

LT3800

U

PACKAGE DESCRIPTIO

FE Package

16-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663)

Exposed Pad Variation BC

4.90 – 5.10*

(.193 – .201)

3.58

(.141)

3.58

(.141)

16 1514 13 12 1110

9

6.60 ±0.10

4.50 ±0.10

2.94

(.116)

6.40

(.252)

BSC

SEE NOTE 4

2.94

(.116)

0.45 ±0.05

1.05 ±0.10

0.65 BSC

5

7

8

1

2

3

4

6

RECOMMENDED SOLDER PAD LAYOUT

1.10

(.0433)

MAX

4.30 – 4.50*

(.169 – .177)

0.25

REF

0° – 8°

0.65

(.0256)

BSC

0.09 – 0.20

(.0035 – .0079)

0.50 – 0.75

(.020 – .030)

0.05 – 0.15

(.002 – .006)

0.195 – 0.30

FE16 (BC) TSSOP 0204

(.0077 – .0118)

TYP

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

FOR EXPOSED PAD ATTACHMENT

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

MILLIMETERS

(INCHES)

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

3800fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

23

LT3800

U

TYPICAL APPLICATIO

24V-48V to –12V 75W Inverting DC/DC Converter with V UVLO

IN

V

IN

24V TO 48V

C10

C9

+

1µF

56µF

63V

×2

100V

X7R

×4

R7

1M

D2

1N4148

D1

BAS19

R8

1M

V

BOOST

TG

IN

M1

2N3906

NC

FDD3570

C2 1µF

16V X7R

LT3800

R3

1M

L1

15µH

R

S

SHDN

SW

NC

0.01Ω

C1 1nF

R1 200k

R2

174k

1%

R6

130k

C

SS

C6

1µF

16V

X7R

BURST_EN

V

CC

C7

150pF

100V

DS1

B180

M2

FDD3570

V

BG

FB

R5

20k

1%

PGND

C

R4

39k

–

+

SENSE

SGND

C3

470pF

C5

270µF

16V

C8

+

4.7µF

16V

C4

100pF

SPRAGUE SP

V

–12V

75W

X7R

OUT

3800 TA04a

L1: COEV MGPWL-00099

Efficiency and Power Loss

100

12

90

80

70

60

50

40

10

8

V

IN

= 24V

V

= 48V

IN

V

= 36V

IN

6

4

V

= 36V LOSS

IN

2

0

0.1

1

10

I

(A)

LOAD

3800 TA04b

RELATED PARTS

PART NUMBER

DESCRIPTION

Synchronous Step-Down Controller

No R

^TMSynchronous Step-Down Controller

COMMENTS

4V ≤ V ≤ 36V, 0.8V ≤ V

LTC1735

≤ 6V, I ≤ 20A

OUT

IN

OUT

LTC1778

LT^®1934

Current Mode Without Using Sense Resistor, 4V ≤ V ≤ 36V

SENSE

IN

Micropower Step-Down Switching Regulator

Synchronous Single Switch Forward Converter

60V Switching Regulator

3.2V ≤ V ≤ 34V, 300mA Switch, ThinSOT^TMPackage

IN

LT1952

25W to 500W Isolated Power Supplies, Small Size, High Efficiency

LT1976

3.2V ≤ V ≤ 60V, 1.5A Switch, 16-Lead TSSOP

IN

LT3010

3V to 80V LDO

50mA Output Current, 1.275V ≤ V

≤ 60V

OUT

LT3430/LT3431

LTC3703

3A, 60V Switching Regulators

5.5V ≤ V ≤ 60V, 200kHz, 16-Lead TSSOP

IN

100V Synchronous Step-Down Controller

60V Synchronous Step-Down Controller

Large 1Ω Gate Drivers, No R

SENSE

LTC3703-5

LTC3727-1

LTC3728L

High V

2-Phase Dual Step-Down Controller

0.8V ≤ V

≤ 14V, PLL: 250kHz to 550kHz

OUT

2-Phase, Dual Synchronous Step-Down Controller

550kHz, PLL: 250kHz to 550kHz, 4V ≤ V ≤ 36V

IN

No R

and ThinSOT are trademarks of Linear Technology Corporation.

SENSE

3800fb

LT 1007 REV B • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

24

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT3800IFE-TRPBF
厂家：	Linear
描述：	High-Voltage Synchronous Current Mode Step-Down Controller 高电压同步电流模式降压型控制器控制器
文件：	总24页 (文件大小：306K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT3800IFE-TRPBF [Linear]

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