LT3803 [Linear]
Quad IEEE 802.3at Power over Ethernet Controller; 以太网控制器四路符合IEEE 802.3at功率
| 型号： | LT3803 |
| 厂家： | 
Linear |
| 描述： | Quad IEEE 802.3at Power over Ethernet Controller |
| 文件： | 总30页 (文件大小：368K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4266
Quad IEEE 802.3at Power
over Ethernet Controller
FEATURES
DESCRIPTION
n
Four Independent PSE Channels
The LTC®4266 is a quad PSE controller designed for use
in IEEE 802.3 Type 1 and Type 2 (high power) compliant
Power over Ethernet systems. External power MOSFETs
enhance system reliability and minimize channel resis-
tance, cutting power dissipation and eliminating the need
for heatsinks even at Type 2 power levels. External power
componentsalsoallowuseatveryhighpowerlevelswhile
remaining otherwise compatible with the IEEE standard.
80V-rated port pins provide robust protection against
external faults.
n
Compliant with IEEE 802.3at Type 1 and 2
n
0.34Ω Total Channel Resistance
130mW/Port at 600mA
Advanced Power Management
n
8-Bit Programmable Current Limit (I
)
LIM
7-Bit Programmable Overload Currents (I
Fast Shutdown of Preselected Ports
14.5-Bit Port Current/Voltage Monitoring
2-Event Classification
)
CUT
n
Very High Reliability 4-Point PD Detection:
2-Point Forced Voltage
The LTC4266 includes advanced power management
features, including current and voltage readback and pro-
2-Point Forced Current
grammable I
and I thresholds. Available C libraries
CUT
LIM
n
n
n
n
n
n
High Capacitance Legacy Device Detection
simplify power-management software development; an
optional AUTO pin mode provides fully IEEE-compliant
standaloneoperationwithnosoftwarerequired.Proprietary
4-point PD detection circuitry minimizes false PD detec-
tion while supporting legacy phone operation. Midspan
operation is supported with built-in 2-event classification
and backoff timing. Host communication is via a 1MHz
LTC4259A-1 and LTC4258 Pin and SW Compatible
2
1MHz I C Compatible Serial Control Interface
Midspan Backoff Timer
Supports Proprietary Power Levels Above 25W
Available in 38-Pin 5mm × 7mm QFN and 36-Pin
SSOP Packages
2
I C serial interface.
APPLICATIONS
The LTC4266 is available in a 5mm × 7mm QFN package
that significantly reduces board space compared with
competing solutions. A legacy-compatible 36-pin SSOP
package is also available.
n
High Power PSE Switches/Routers
High Power PSE Midspans
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
TYPICAL APPLICATION
Complete 4-Port Ethernet High Power Source
3.3V
0.1µF
SCL
INT SHDN1 SHDN2 SHDN3 SHDN4
V
AUTO MSD RESET MID
DD
SDAIN
SDAOUT
AD0
0.22µF 100V
S1B
×4
S1B
×4
LTC4266
×4
AD1
–50V
AD2
AD3
DGND AGND V SENSE1 GATE1 OUT1 SENSE2 GATE2 OUT2 SENSE3 GATE3 OUT3 SENSE4 GATE4 OUT4
EE
PORT1
PORT2
PORT3
–50V
SMAJ58A
1µF
PORT4
4266 TA01
4266fb
1
LTC4266
ABSOLUTE MAXIMUM RATINGS
Supply Voltages (Note 1)
Operating Temperature Range
AGND – V ........................................... –0.3V to 80V
LTC4266C ................................................ 0°C to 70°C
LTC4266I .............................................–40°C to 85°C
Junction Temperature (Note 2) ............................. 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)...................300°C
EE
DGND – V ........................................... –0.3V to 80V
EE
V
– DGND ......................................... –0.3V to 5.5V
DD
Digital Pins
SCL, SDAIN, SDAOUT, INT, SHDNn, MSD, ADn,
RESET, AUTO, MID........... DGND –0.3V to V + 0.3V
DD
Analog Pins
GATEn, SENSEn, OUTn .......... V –0.3V to V + 80V
EE
EE
PIN CONFIGURATION
TOP VIEW
TOP VIEW
1
2
MSD
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
RESET
MID
AUTO
3
OUT1
INT
38 37 36 35 34 33 32
4
GATE1
SENSE1
OUT2
SCL
SDAOUT
NC
1
2
3
4
5
6
7
8
9
31 GATE1
5
30
29
28
SENSE1
OUT2
SDAOUT
SDAIN
AD3
SDAIN
AD3
6
GATE2
7
GATE2
SENSE2
AD2
27 SENSE2
8
AD2
AD1
V
V
26
25
EE
EE
9
V
EE
AD1
39
AD0
10
11
12
13
14
15
16
17
18
OUT3
AD0
DNC
NC
24 OUT3
23 GATE3
22 SENSE3
21 OUT4
GATE3
SENSE3
OUT4
NC
NC
DGND 10
NC 11
NC
GATE4
SENSE4
AGND
NC
20
NC 12
GATE4
DGND
13 14 15 16 17 18 19
V
DD
SHDN4
SHDN3
SHDN1
SHDN2
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
EXPOSED PAD IS V (PIN 39) MUST BE SOLDERED TO PCB
GW36 PACKAGE
EE
36-LEAD PLASTIC WIDE SSOP
JMAX
T
= 125°C, θ = 34°C/W
JMAX
JA
T
= 125°C, θ = 80°C/W
JA
ORDER INFORMATION
LEAD FREE FINISH
LTC4266CGW#PBF
LTC4266IGW#PBF
LTC4266CUHF#PBF
LTC4266IUHF#PBF
TAPE AND REEL
PART MARKING*
LTC4266
LTC4266
4266
PACKAGE DESCRIPTION
36-Lead Plastic Wide SSOP
36-Lead Plastic Wide SSOP
38-Lead (5mm × 7mm) Plastic QFN
38-Lead (5mm × 7mm) Plastic QFN
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
0°C to 70°C
LTC4266CGW#TRPBF
LTC4266IGW#TRPBF
LTC4266CUHF#TRPBF
LTC4266IUHF#TRPBF
4266
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
4266fb
2
LTC4266
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless
otherwise noted. (Notes 3, 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
–48V Supply Voltage
AGND – V
EE
l
l
For IEEE Type 1 Complaint Output
For IEEE Type 2 Complaint Output
45
51
57
57
V
V
l
l
l
l
l
l
Undervoltage Lock-out Level
20
25
3.3
2.2
30
V
V
V
V
Supply Voltage
V – DGND
DD
3.0
4.3
DD
DD
Undervoltage Lock-out
V
Allowable Digital Ground Offset
DGND – V
25
57
–5
3
V
EE
I
I
V
V
Supply Current
Supply Current
(AGND – V ) = 55V
–2.4
1.1
mA
mA
EE
EE
EE
(V – DGND) = 3.3V
DD
DD
DD
Detection
l
l
Detection Current – Force Current
Detection Voltage – Force Voltage
First Point, AGND – V
= 9V
OUTn
220
140
240
160
260
180
µA
µA
OUTn
Second Point, AGND – V
= 3.5V
AGND – V
, 5µA ≤ I
OUTn
≤ 500µA
OUTn
l
l
First Point
Second Point
7
3
8
4
9
5
V
V
l
l
l
l
l
Detection Current Compliance
Detection Voltage Compliance
Detection Voltage Slew Rate
Min. Valid Signature Resistance
Max. Valid Signature Resistance
AGND – V
= 0V
0.8
0.9
12
mA
V
OUTn
OUTn
V
OC
AGND – V
AGND – V
, Open Port
, C = 0.15µF
10.4
0.01
18.5
32
V/µs
kΩ
kΩ
OUTn PORT
15.5
27.5
17
29.7
Classification
l
l
V
Classification Voltage
AGND – V
, 0mA ≤ I ≤ 50mA
CLASS
16.0
53
20.5
67
V
CLASS
OUTn
Classification Current Compliance
Classification Threshold Current
V
OUTn
= AGND
61
mA
l
l
l
l
l
Class 0 – 1
Class 1 – 2
Class 2 – 3
Class 3 – 4
Class 4 – Overcurrent
AGND – V , 0.1mA ≤ I ≤ 10mA
CLASS
5.5
6.5
14.5
23
33
48
7.5
mA
mA
mA
mA
mA
13.5
21.5
31.5
45.2
15.5
24.5
34.9
50.8
l
l
V
Classification Mark State Voltage
Mark State Current Compliance
7.5
53
9
10
67
V
MARK
OUTn
V
OUTn
= AGND
61
mA
Gate Driver
l
l
GATE Pin Pull-Down Current
Port Off, V
Port Off, V
= V + 5V
0.4
mA
mA
GATEn
GATEn
EE
= V + 1V
0.08
0.12
30
EE
GATE Pin Fast Pull-Down Current
GATE Pin On Voltage
V
GATEn
GATEn
= V + 5V
mA
V
EE
l
V
– V , I
= 1µA
8
14
EE GATEn
Output Voltage Sense
l
l
V
PG
Power Good Threshold Voltage
V
– V
EE
2
2.4
2.8
V
OUTn
OUT Pin Pull-Up Resistance to AGND
0V ≤ (AGND – V
) ≤ 5V
OUTn
300
500
700
kΩ
4266fb
3
LTC4266
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless
otherwise noted. (Notes 3, 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Current Sense
l
V
CUT
Overcurrent Sense Voltage
V
– V , icut12 = icut34 = hpen = 00h
180
188
196
mV
SENSEn
EE
hpen = 0Fh, cutn[5:0] ≥ 4 (Note 12)
cutrng = 0
l
l
9
4.5
9.38
4.69
9.75
4.88
mV/LSB
mV/LSB
cutrng = 1
l
l
l
l
Overcurrent Sense in AUTO pin mode
Class 0, Class 3
Class 1
90
26
94
28
98
30
mV
mV
mV
mV
Class 2
49
52
55
Class 4
152
159
166
V
LIM
V
LIM
V
LIM
Active Current Limit in 802.3af Compliant
Mode
V
EE
– V , dblpwr = hpen = 00h
SENSEn EE
V
= 55V (Note 12)
l
l
V
< V
< AGND – 29V
OUT
OUT
204
40
212
220
100
mV
mV
EE
AGND – V
= 0V
Active Current Limit in High Power Mode
Active Current Limit in AUTO pin mode
hpen = 0Fh, limn = C0h, V = 55V
EE
l
l
l
V
V
– V = 0V to 10V
204
100
20
212
106
221
113
50
mV
mV
mV
OUT
EE
EE
+ 23V < V
< AGND – 29V
OUT
AGND – V
= 0V
OUT
V
OUT
– V = 0V to 10V, V = 55V
EE EE
Class 0 to Class 3
Class 4
l
l
102
204
106
212
110
221
mV
mV
l
l
V
V
DC Disconnect Sense Voltage
Short-Circuit Sense
V
V
– V , rdis = 0
2.6
1.3
3.8
1.9
4.8
mV
mV
MIN
SENSEn
SENSEn
EE
– V , rdis = 1
2.41
EE
l
l
V
V
– V – V , rdis = 0
160
75
200
100
255
135
mV
mV
SC
SENSEn
SENSEn
EE
LIM
– V – V , rdis = 1
EE
LIM
Port Current ReadBack
Resolution
No missing codes, fast_iv = 0
V – V
SENSEn
14
30.5
30
bits
µV/LSB
dB
LSB Weight
EE
50-60Hz Noise Rejection
(Note 7)
Port Voltage ReadBack
Resolution
No missing codes, fast_iv = 0
14
5.835
30
bits
mV/LSB
dB
LSB Weight
AGND – V
(Note 7)
OUTn
50-60Hz noise rejection
Digital Interface
l
l
V
Digital Input Low Voltage
Digital Input High Voltage
Digital Output Low Voltage
(Note 6)
(Note 6)
0.8
V
V
ILD
IHD
V
2.2
l
l
I
I
= 3mA, I = 3mA
0.4
0.7
V
V
SDAOUT
SDAOUT
INT
= 5mA, I = 5mA
INT
Internal Pull-Up to V
ADn, SHDNn, RESET, MSD
50
50
kΩ
kΩ
DD
Internal Pull-Down to DGND
AUTO, MID
4266fb
4
LTC4266
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless
otherwise noted. (Notes 3, 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Timing Characteristics
l
l
t
t
Detection Time
Detection Delay
Beginning to End of Detection (Note 7)
270
300
290
310
470
ms
ms
DET
From PD Connected to Port to Detection
Complete (Note 7)
DETDLY
l
l
l
l
l
l
t
t
t
t
t
t
First Class Event Duration
(Note 7)
11
6.8
11
19
12
8.6
12
22
13
10.3
13
ms
ms
ms
ms
ms
ms
CLE1
ME1
CLE2
ME2
CLE3
PON
First Mark Event Duration
(Notes 7, 11)
(Note 7)
Second Class Event Duration
Second Mark Event Duration
Third Class Event Duration
Power On Delay in AUTO pin mode
(Note 7)
C
PORT
= 0.6µF (Note 7)
0.1
60
From End of Valid Detect to Application of
Power to Port (Note 7)
l
Turn On Rise Time
(AGND – V ): 10% to 90% of
15
24
µs
OUT
(AGND – V ), C
= 0.15µF (Note 7)
EE
PORT
l
l
l
l
Turn On Ramp Rate
C
= 0.15µF (Note 7)
10
V/µs
PORT
Fault Delay
From I
Fault to Next Detect
1.0
2.3
1.0
1.1
2.5
1.3
s
s
s
CUT
Midspan Mode Detection Backoff
Power Removal Detection Delay
Rport = 15.5kΩ (Note 7)
2.7
2.5
From Power Removal After t to Next
Detect (Note 7)
DIS
l
l
t
t
Maximum Current Limit Duration During Port
Start-Up
t
= 0, t = 0 (Notes 7, 12)
START0
52
52
62.5
62.5
6.3
66
66
ms
ms
START
START1
, t
Maximum Current Limit Duration After Port
Start-Up
t
= 0, t
= 0 (Notes 7, 12)
ICUT0
LIM ICUT
ICUT1
l
l
Maximum Current Limit Duty Cycle
(Note 7)
5.8
1.6
6.7
3.6
%
t
t
Maintain Power Signature (MPS) Pulse Width Current Pulse Width to Reset Disconnect
Sensitivity
ms
MPS
Timer (Notes 7, 8)
l
Maintain Power Signature (MPS) Dropout
Time
t
[1:0] = 00b (Notes 5, 12)
320
350
2
380
ms
DIS
conf
l
l
l
l
t
t
Masked Shut Down Delay
Port Shut Down Delay
(Note 7)
(Note 7)
6.5
6.5
3
µs
µs
s
MSD
SHDN
2
I C Watchdog Timer Duration
1.5
3
Minimum Pulse Width for Masked Shut
Down
(Note 7)
µs
l
l
Minimum Pulse Width for SHDN
Minimum Pulse Width for RESET
(Note 7)
(Note 7)
3
µs
µs
4.5
4266fb
5
LTC4266
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless
otherwise noted. (Notes 3, 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
2
I C Timing
l
l
l
l
l
Clock Frequency
Bus Free Time
Start Hold Time
SCL Low Time
SCL High Time
Data Hold Time
(Note 7)
1
MHz
ns
t
1
t
2
t
3
t
4
t
5
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
480
240
480
240
60
ns
ns
ns
l
l
Figure 5 (Notes 7, 9) Data into chip
Data out of chip
ns
ns
120
l
l
l
l
l
l
l
l
l
t
t
t
t
t
Data Set-Up Time
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
(Notes 7, 9, 10)
80
ns
ns
ns
ns
ns
ns
µs
µs
ns
6
7
8
r
Start Set-Up Time
240
240
Stop Set-Up Time
SCL, SDAIN Rise Time
SCL, SDAIN Fall Time
Fault Present to INT Pin Low
Stop Condition to INT Pin Low
ARA to INT Pin High Time
SCL Fall to ACK Low
120
60
f
150
1.5
1.5
120
(Notes 7, 9, 10)
(Notes 7, 9)
(Notes 7, 9)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 140°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative.
Note 4: The LTC4266 operates with a negative supply voltage (with respect
to ground). To avoid confusion, voltages in this data sheet are referred to
in terms of absolute magnitude.
Note 6: The LTC4266 digital interface operates with respect to DGND. All
logic levels are measured with respect to DGND.
Note 7: Guaranteed by design, not subject to test.
Note 8: The IEEE 802.3af specification allows a PD to present its
Maintain Power Signature (MPS) on an intermittent basis without being
disconnected. In order to stay powered, the PD must present the MPS for
t
within any t
time window.
MPS
MPDO
Note 9: Values measured at V
Note 10: If fault condition occurs during an I C transaction, the INT pin
will not be pulled down until a stop condition is present on the I C bus.
and V
.
ILD(MAX)
IHD(MIN)
2
2
Note 11: Load Characteristic of the LTC4266 during Mark:
7V < (AGND – V
) < 10V or I
< 50µA
OUTn
OUT
Note 12: See the LTC4266 Software Programming documentation for
information on serial bus usage and device configuration and status
registers.
Note 5: t is the same as t
defined by IEEE 802.3at.
DIS
MPDO
4266fb
6
LTC4266
TYPICAL PERFORMANCE CHARACTERISTICS
Power On Sequence
802.3af Classification
in AUTO Pin Mode
in AUTO Pin Mode
Powering Up into a 180µF Load
10
0
GND
GND
FORCED CURRENT DETECTION
GND
V
DD
V
EE
= 3.3V
= –54V
PORT
VOLTAGE
20V/DIV
LOAD
FULLY
–10
–20
–30
CHARGED
–18.4
FORCED VOLTAGE
DETECTION
V
EE
PORT
CURRENT
802.3af
PORT 1
FOLDBACK
PORT 1
PORT
VOLTAGE
10V/DIV
425mA
CURRENT LIMIT
CLASSIFICATION
V
DD
V
EE
= 3.3V
= –54V
200 mA/DIV
–40
–50
–60
–70
V
DD
V
EE
= 3.3V
= –55V
POWER ON
0mA
PD IS CLASS 1
FET ON
GATE
VOLTAGE
10V/DIV
V
EE
V
V
EE
EE
5ms/DIV
5ms/DIV
100ms/DIV
4266 G02
4266 G01
4266 G03
2-Event Classification
in Auto Pin Mode
Classification Transient Response
to 40mA Load Step
Classification Current Compliance
0
–2
GND
V
DD
V
EE
= 3.3V
= –54V
V
DD
V
EE
= 3.3V
= –54V
40mA
0mA
PORT
CURRENT
20mA/DIV
T
A
= 25°C
–4
–17.6
–6
1ST CLASS EVENT
–8
2ND CLASS EVENT
–10
–12
–14
–16
–18
–20
PORT
VOLTAGE
10V/DIV
PORT 1
V
DD
V
EE
= 3.3V
= –55V
PORT
VOLTAGE
1V/DIV
PD IS CLASS 4
–20V
V
EE
0
10
20
30
40
50
60
70
10ms/DIV
50µs/DIV
CLASSIFICATION CURRENT
4266 G05
4266 G04
4266 G06
802.3at ILIM Threshold vs
Temperature
V
DD Supply Current vs Voltage
VEE Supply Current vs Voltage
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
2.4
2.3
2.2
2.1
215
214
213
212
211
210
860
–40°C
25°C
85°C
V
V
= 3.3V
= –54V
SENSE
DD
EE
R
= 0.25Ω
856
852
848
844
840
REG 48h = C0h
–40°C
25°C
85°C
2.0
–60 –55 –50 –45 –40 –35 –30 –25 –20
SUPPLY VOLTAGE (V)
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3
SUPPLY VOLTAGE (V)
–40
0
40
–80
120
V
V
TEMPERATURE (°C)
EE
DD
4266 G08
4266 G07
4266 G09
4266fb
7
LTC4266
TYPICAL PERFORMANCE CHARACTERISTICS
802.3af ILIM Threshold vs
Temperature
802.3at ICUT Threshold vs
Temperature
108.00
107.25
106.50
432
429
163
162
652
648
644
640
V
V
= 3.3V
= –54V
SENSE
V
V
= 3.3V
= –54V
SENSE
DD
EE
DD
EE
R
= 0.25Ω
R
= 0.25Ω
REG 48h = 80h
PORT 1
REG 47h = E2h
PORT 1
161
160
159
158
426
423
420
105.75
105.00
636
630
–40
0
40
80
120
–40
0
40
80
120
TEMPERATURE (°C)
TEMPERATURE (°C)
4266 G10
4266 G11
802.3af ICUT Threshold vs
Temperature
DC Disconnect Threshold vs
Temperature
96.00
95.25
94.50
93.75
93.00
384
381
8.00
2.0000
1.9375
V
V
= 3.3V
= –54V
SENSE
V
V
= 3.3V
= –54V
SENSE
DD
EE
DD
EE
R
= 0.25Ω
R
= 0.25Ω
REG 47h = D4h
PORT 1
REG 47h = E2h
PORT 1
7.75
7.50
7.25
7.00
378
375
372
1.8750
1.8125
1.7500
–40
0
40
80
120
–40
0
40
80
120
TEMPERATURE (°C)
TEMPERATURE (°C)
4266 G12
4266 G13
ADC Noise Histogram
Current Readback in Fast Mode
ADC Integral Nonlinearity
Current Limit Foldback
Current Readback in Fast Mode
1.0
0.5
900
800
700
600
500
400
300
200
100
0
225
400
V
– V = 110.4mV
EE
V
V
= 3.3V
SENSEn
DD
EE
= –54V
200
175
150
125
100
75
350
300
250
200
150
100
50
R
SENSE
= 0.25Ω
REG 48h = C0h
0
–0.5
–1.0
50
25
0
0
–54
–45
–36
–9
0
191
192
193
ADC OUTPUT
196
–27
–18
194
195
0
50 100 150 200 250 300 350 400 450 500
CURRENT SENSE RESISTOR INPUT VOLTAGE (mV)
4266 G16
V
(V)
OUTn
4266 G14
4266 G15
4266fb
8
LTC4266
TYPICAL PERFORMANCE CHARACTERISTICS
ADC Noise Histogram
Current Readback in Slow Mode
ADC Integral Nonlinearity
Current Readback in Slow Mode
ADC Noise Histogram Port
Voltage Readback in Fast Mode
300
250
200
150
100
50
600
500
400
300
200
100
0
1.0
0.5
V
– V = 110.4mV
AGND – V
= 48.3V
SENSEn
EE
OUTn
0
–0.5
–1.0
0
6139
260
261
262
ADC OUTPUT
6141
6143
6145
6147
0
50 100 150 200 250 300 350 400 450 500
CURRENT SENSE RESISTOR INPUT VOLTAGE (mV)
4266 G18
263
264
265
ADC OUTPUT
4266 G17
4266 G19
ADC Integral Nonlinearity
Voltage Readback in Slow Mode
ADC Integral Nonlinearity
Voltage Readback in Fast Mode
ADC Noise Histogram Port
Voltage Readback in Slow Mode
1.0
0.5
600
500
400
300
200
100
0
1.0
0.5
AGND – V
= 48.3V
OUTn
0
0
–0.5
–1.0
–0.5
–1.0
0
10
20
30
40
50
60
0
10
20
30
40
50
60
8532
8533
8534
ADC OUTPUT
8535
8536
PORT VOLTAGE (V)
PORT VOLTAGE (V)
4266 G20
4266 G22
4266 G21
INTandSDAOUTPullDownVoltage
vs Load Current
MOSFET Gate Drive With Fast
Pull Down
3
2.5
2
GND
V
V
= 3.3V
= –54V
DD
EE
PORT
VOLTAGE
20V/DIV
V
V
EE
EE
FAST PULL DOWN
GATE
VOLTAGE
10V/DIV
1.5
1
CURRENT LIMIT
50Ω
FAULT
APPLIED
PORT
CURRENT
500mA/DIV
50Ω FAULT REMOVED
0.5
0
0mA
0
5
10
LOAD CURRENT (mA)
15 20 25 30 35 40
100µs/DIV
4266 G23
4266 G24
4266fb
9
LTC4266
TEST TIMING DIAGRAMS
t
CLASSIFICATION
DET
FORCED-CURRENT
0V
FORCED-
VOLTAGE
t
ME1
V
t
PORTn
ME2
V
OC
V
MARK
15.5V
20.5V
V
CLASS
t
CLE1
t
CLE2
PD
CONNECTED
t
CLE3
t
t
PON
DETDLY
V
EE
INT
4266 F01
Figure 1. Detect, Class and Turn-On Timing in AUTO Pin or Semi-Auto Modes
V
LIM
0V
V
V
CUT
SENSEn
V
MIN
V
TO V
EE
TO V
SENSEn
EE
t
, t
START ICUT
INT
INT
t
t
DIS
MPS
4266 F03
4266 F02
Figure 2. Current Limit Timing
Figure 3. DC Disconnect Timing
t
t
r
3
t
t
f
4
V
GATEn
SCL
t
MSD
V
EE
t
SHDN
t
5
t
t
7
t
8
t
2
6
MSD or
SHDNn
SDA
4266 F04
4266 F05
t
1
Figure 4. Shut Down Delay Timing
Figure 5. I2C Interface Timing
4266fb
10
LTC4266
I2C TIMING DIAGRAMS
SCL
SDA
AD3 AD2 AD1 AD0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
0
1
0
START BY
MASTER
ACK BY
SLAVE
ACK BY
SLAVE
ACK BY
SLAVE
STOP BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
REGISTER ADDRESS BYTE
FRAME 3
DATA BYTE
4266 F06
Figure 6. Writing to a Register
SCL
SDA
AD3 AD2 AD1 AD0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK
AD3 AD2 AD1 AD0 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
0
1
0
0
1
0
START BY
MASTER
ACK BY
SLAVE
ACK BY
SLAVE
REPEATED
START BY
MASTER
ACK BY
SLAVE
NO ACK BY
MASTER
STOP BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
REGISTER ADDRESS BYTE
FRAME 1
FRAME 2
DATA BYTE
SERIAL BUS ADDRESS BYTE
4266 F07
Figure 7. Reading from a Register
SCL
SDA
0
1
0
AD3 AD2 AD1 AD0 R/W
FRAME 1
ACK
D7 D6 D5 D4 D3 D2 D1 D0
ACK
STOP BY
MASTER
START BY
MASTER
ACK BY
SLAVE
NO ACK BY
MASTER
FRAME 2
DATA BYTE
SERIAL BUS ADDRESS BYTE
4266 F08
Figure 8. Reading the Interrupt Register (Short Form)
SCL
SDA
0
0
0
1
1
0
0
R/W
ACK
0
1
0
AD3 AD2 AD1 AD0
1
ACK
STOP BY
MASTER
START BY
MASTER
ACK BY
SLAVE
NO ACK BY
MASTER
FRAME 1
ALERT RESPONSE ADDRESS BYTE
FRAME 2
SERIAL BUS ADDRESS BYTE
4266 F09
Figure 9. Reading from Alert Response Address
4266fb
11
LTC4266
PIN FUNCTIONS
RESET: Chip Reset, Active Low. When the RESET pin is
low, the LTC4266 is held inactive with all ports off and all
internal registers reset to their power-up states. When
RESET is pulled high, the LTC4266 begins normal opera-
tion. RESET can be connected to an external capacitor
or RC network to provide a power turn-on delay. Internal
filtering of the RESET pin prevents glitches less than 1µs
wide from resetting the LTC4266. Internally pulled up to
AD3: Address Bit 3. Tie the address pins high or low to set
2
theI CserialaddresstowhichtheLTC4266responds.This
addresswillbe010A A A A b.InternallypulleduptoV .
3 2 1 0
DD
AD2: Address Bit 2. See AD3.
AD1: Address Bit 1. See AD3.
AD0: Address Bit 0. See AD3.
NC, DNC: All pins identified with “NC” or “DNC” must be
left unconnected.
V .
DD
MID: Midspan Mode Input. When high, the LTC4266 acts
as a midspan device. Internally pulled down to DGND.
DGND: Digital Ground. DGND is the return for the V
DD
supply.
INT: Interrupt Output, Open Drain. INT will pull low when
any one of several events occur in the LTC4266. It will
return to a high impedance state when bits 6 or 7 are set
in the Reset PB register (1Ah). The INT signal can be used
to generate an interrupt to the host processor, eliminating
the need for continuous software polling. Individual INT
events can be disabled using the Int Mask register (01h).
See LTC4266 Software Programming documentation for
more information. The INT pin is only updated between
V : Logic Power Supply. Connect to a 3.3V power supply
DD
relative to DGND. V must be bypassed to DGND near
DD
the LTC4266 with at least a 0.1µF capacitor.
SHDN1: Shutdown Port 1, Active Low. When pulled low,
SHDN1 shuts down port 1, regardless of the state of the
internal registers. Pulling SHDN1 low is equivalent to set-
ting the Reset Port 1 bit in the Reset Pushbutton register
(1Ah).InternalfilteringoftheSHDN1pinpreventsglitches
less than 1µs wide from reseting the port. Internally pulled
2
I C transactions.
up to V .
DD
SCL: Serial Clock Input. High impedance clock input for
2
the I C serial interface bus. SCL must be tied high if not
SHDN2: Shutdown Port 2, Active Low. See SHDN1.
SHDN3: Shutdown Port 3, Active Low. See SHDN1.
SHDN4: Shutdown Port 4, Active Low. See SHDN1.
used.
SDAOUT: Serial Data Output, Open Drain Data Output for
2
the I C Serial Interface Bus. The LTC4266 uses two pins
to implement the bidirectional SDA function to simplify
AGND: Analog Ground. AGND is the return for the V
supply.
EE
2
optoisolation of the I C bus. To implement a standard
bidirectional SDA pin, tie SDAOUT and SDAIN together.
SDAOUT should be grounded or left floating if not used.
See Applications Information for more information.
SENSE4: Port 4 Current Sense Input. SENSE4 monitors
the external MOSFET current via a 0.5Ω or 0.25Ω sense
resistor between SENSE4 and V . Whenever the voltage
EE
SDAIN: Serial Data Input. High impedance data input for
acrossthesenseresistorexceedstheovercurrentdetection
2
the I C serial interface bus. The LTC4266 uses two pins
threshold V , the current limit fault timer counts up. If
CUT
to implement the bidirectional SDA function to simplify
the voltage across the sense resistor reaches the current
2
optoisolation of the I C bus. To implement a standard
limit threshold V , the GATE4 pin voltage is lowered to
LIM
bidirectional SDA pin, tie SDAOUT and SDAIN together.
SDAIN must be tied high if not used. See Applications
Information for more information.
maintain constant current in the external MOSFET. See
Applications Information for further details. If the port is
unused, the SENSE4 pin must be tied to V .
EE
4266fb
12
LTC4266
PIN FUNCTIONS
GATE4: Port 4 Gate Drive. GATE4 should be connected
to the gate of the external MOSFET for port 4. When the
MOSFET is turned on, the gate voltage is driven to 13V
SENSE2: Port 2 Current Sense Input. See SENSE4.
GATE2: Port 2 Gate Drive. See GATE4.
OUT2: Port 2 Output Voltage Monitor. See OUT4.
SENSE1: Port 1 Current Sense Input. See SENSE4.
GATE1: Port 1 Gate Drive. See GATE 4.
(typ) above V . During a current limit condition, the
EE
voltage at GATE4 will be reduced to maintain constant
current through the external MOSFET. If the fault timer
expires, GATE4 is pulled down, turning the MOSFET off
and recording a t
or t
event. If the port is unused,
OUT1: Port 1 Output Voltage Monitor. See OUT4.
CUT
START
float the GATE4 pin.
AUTO: AUTO Pin Mode Input. AUTO pin mode allows the
OUT4: Port 4 Output Voltage Monitor. OUT4 should be
connected to the output port. A current limit foldback
circuitlimitsthepowerdissipationintheexternalMOSFET
by reducing the current limit threshold when the drain-to-
source voltage exceeds 10V. The port 4 Power Good bit is
LTC4266 to detect and power up a PD even if there is no
2
host controller present on the I C bus. The voltage of the
AUTO pin determines the state of the internal registers
when the LTC4266 is reset or comes out of V UVLO
DD
(see the Register map). The states of these register bits
2
set when the voltage from OUT4 to V drops below 2.4V
can subsequently be changed via the I C interface. The
EE
(typ). A 500k resistor is connected internally from OUT4
to AGND when the port is idle. If the port is unused, OUT4
pin must be floated.
real-time state of the AUTO pin is read at bit 0 in the Pin
Status register (11h). Internally pulled down to DGND.
Must be tied locally to either V or DGND.
DD
SENSE3: Port 3 Current Sense Input. See SENSE4.
GATE3: Port 3 Gate Drive. See GATE4.
MSD: Maskable Shutdown Input. Active low. When pulled
low, all ports that have their corresponding mask bit set
in the Misc Config register (17h) will be reset, equivalent
to pulling the SHDN pin low. Internal filtering of the MSD
pin prevents glitches less than 1µs wide from resetting
OUT3: Port 3 Output Voltage Monitor. See OUT4.
V : Main Supply Input. Connect to a –45V to –57V
EE
ports. Internally pulled up to V .
supply, relative to AGND.
DD
4266fb
13
LTC4266
OPERATION
Overview
channel; these minimize power loss compared to alterna-
tive designs with on-board MOSFETs and increase system
reliability in the event a single channel is damaged.
Power over Ethernet, or PoE, is a standard protocol for
sending DC power over copper Ethernet data wiring.
The IEEE group that administers the 802.3 Ethernet data
standards added PoE powering capability in 2003. This
original PoE spec, known as 802.3af, allowed for 48V DC
power at up to 13W. This initial spec was widely popular,
but 13W was not adequate for some requirements. In
2009, the IEEE released a new standard, known as 802.3at
PoE Basics
Common Ethernet data connections consist of two or four
twisted pairs of copper wire (commonly known as CAT-5
cable), transformer-coupled at each end to avoid ground
loops. PoE systems take advantage of this coupling ar-
rangement by applying voltage between the center-taps
of the data transformers to transmit power from the PSE
to the PD without affecting data transmission. Figure 10
shows a high-level PoE system schematic.
+
or PoE , increasing the voltage and current requirements
to provide 25W of power.
The IEEE standard also defines PoE terminology. A device
that provides power to the network is known as a PSE, or
powersourcingequipment,whileadevicethatdrawspower
from the network is known as a PD, or powered device.
PSEs come in two types: Endpoints (typically network
switches or routers), which provide data and power; and
Midspans, which provide power but pass through data.
MidspansaretypicallyusedtoaddPoEcapabilitytoexisting
non-PoE networks. PDs are typically IP phones, wireless
access points, security cameras, and similar devices, but
could be nearly anything that runs from 25W or less and
includes an RJ45-style network connector.
To avoid damaging legacy data equipment that does not
expect to see DC voltage, the PoE spec defines a protocol
that determines when the PSE may apply and remove
power. Valid PDs are required to have a specific 25k com-
mon mode resistance at their input. When such a PD is
connected to the cable, the PSE detects this signature
resistance and turns on the power. When the PD is later
disconnected, the PSE senses the open circuit and turns
power off. The PSE also turns off power in the event of a
current fault or short circuit.
When a PD is detected, the PSE optionally looks for a
classification signature that tells the PSE the maximum
power the PD will draw. The PSE can use this information
to allocate power among several ports, police the current
consumption of the PD, or to reject a PD that will draw
The LTC4266 is a third-generation quad PSE controller
that implements four PSE ports in either an endpoint or
midspandesign.Virtuallyallnecessarycircuitryisincluded
toimplementaIEEE802.3atcompliantPSEdesign,requir-
ingonlyanexternalpowerMOSFETandsenseresistorper
CAT 5
20Ω MAX
ROUNDTRIP
0.05µF MAX
PSE
PD
RJ45
4
RJ45
4
5
5
GND
1N4002
SPARE PAIR
×4
0.22µF
100V
X7R
1
1
DGND
AGND
5µF ≤ C
IN
≤ 300µF
SMAJ58A
58V
Tx
Rx
Tx
3.3V
V
DD
INT
SCL
SDAIN
SDAOUT
2
3
2
3
INTERRUPT
DATA PAIR
DATA PAIR
SMAJ58A
1/4
2
LTC4266
I C
0.1µF
1N4002
×4
Rx
V
SENSE GATE OUT
EE
1µF
GND
6
6
100V
X7R
DC/DC
CONVERTER
R
PWRGD
+
OUT
CLASS
S1B
V
0.25Ω
LTC4265
–48V
7
8
7
IRFM120A
–48V
–48V
OUT
–
IN
8
S1B
SPARE PAIR
4266 F10
Figure 10. Power Over Ethernet System Diagram
4266fb
14
LTC4266
OPERATION
more power that the PSE has available. The classification
step is optional; if a PSE chooses not to classify a PD, it
must assume that the PD is a 13W (full 802.3af power)
device.
compatible) devices can be substituted with the LTC4266
without software or PCB layout changes; only minor BOM
changes are required to implement a fully compliant
802.3at design.
Because of the backwards compatibility features, some of
the internal registers are redundant or unused when the
LTC4266 is operated as recommended. For more details
on usage in compatibility mode, refer to the LTC4258/
LTC4259A device datasheets.
New in 802.3at
Thenewer802.3atstandardsupersedes802.3afandbrings
several new features:
•ꢀ AꢀPDꢀmayꢀdrawꢀasꢀmuchꢀasꢀ25.5W.ꢀSuchꢀPDsꢀ(andꢀtheꢀ
PSEs that support them) are known as Type 2. Older
13W 802.3af equipment is classified as Type 1. Type 1
PDs will work with all PSEs; Type 2 PDs may require
Type 2 PSEs to work properly. The LTC4266 is designed
to work in both Type 1 and Type 2 PSE designs, and
also supports non-standard configurations at higher
power levels.
Special Compatibility Mode Notes
•ꢀ Theꢀ LTC4266ꢀ canꢀ useꢀ eitherꢀ 0.5Ωꢀ orꢀ 0.25Ωꢀ senseꢀ
resistors, while the LTC425x chips always used 0.5Ω.
To maintain compatibility, if the AUTO pin is low when
the LTC4266 powers up it assumes the sense resistor
is 0.5Ω; if it is high at power up, the LTC4266 assumes
0.25Ω. The resistor value setting can be reconfigured
at any time after power up. In particular, systems that
use 0.25Ω sense resistors and have AUTO tied low
must reconfigure the resistor settings after power up.
•ꢀ TheꢀClassificationꢀprotocolꢀisꢀexpandedꢀtoꢀallowꢀTypeꢀ2ꢀ
PSEs to detect Type 2 PDs, and to allow Type 2 PDs to
determine if they are connected to a Type 2 PSE. Two
versions of the new Classification protocol are avail-
able: an expanded version of the 802.3af Class Pulse
protocol, and an alternate method integrated with the
existing LLDP protocol (using the Ethernet data path).
TheLTC4266fullysupportsthenewClassPulseprotocol
and is also compatible with the LLDP protocol (which
is implemented in the data communications layer, not
in the PoE circuitry).
•ꢀ TheꢀLTC4259AꢀincludedꢀbothꢀACꢀandꢀDCꢀdisconnectꢀ
sensing circuitry, but the LTC4266 has only DC discon-
nect sensing. For the sake of compatibility, register
bits used to enable AC disconnect in the LTC4259A are
implemented in the LTC4266, but they simply mirror
the bits used for DC disconnect.
•ꢀ Theꢀ LTC4258ꢀ andꢀ LTC4259Aꢀ requiredꢀ 10kꢀ resistorsꢀ
between the OUTn pins and the drains of the external
MOSFETs. These resistors must be shorted or replaced
with zero ohm jumpers when using the LTC4266.
•ꢀ Faultꢀprotectionꢀcurrentꢀlevelsꢀandꢀtimingꢀareꢀadjustedꢀ
to reduce peak power in the MOSFET during a fault;
this allows the new 25.5W power levels to be reached
using the same MOSFETs as older 13W designs.
•ꢀ TheꢀLTC4258ꢀandꢀLTC4259AꢀincludedꢀaꢀBYPꢀpin,ꢀde-
coupledtoAGNDwith0.1µF.ThispinchangestotheMID
pin on the LTC4266. The capacitor should be removed
for Endspan applications, or replaced with a zero ohm
jumper for Midspan applications.
BACKWARDS COMPATIBILITY
The LTC4266 is designed to be backward compatible with
earlierPSEchipsinbothsoftwareandpinfunctions. Exist-
ing systems using either the LTC4258 or LTC4259A (or
4266fb
15
LTC4266
APPLICATIONS INFORMATION
Operating Modes
Reset and the AUTO/MID Pins
The LTC4266 includes four independent ports, each of
which can operate in one of four modes: manual, semi-
auto, AUTO pin or shutdown.
The initial LTC4266 configuration depends on the state
of the AUTO and MID pins during reset. Reset occurs at
power-up, or whenever the RESET pin is pulled low or the
global Reset All bit is set. Note that the AUTO pin is only
sampled when a reset occurs. Changing the state of AUTO
or MID after power-up will not change the port behavior
of the LTC4266 until a reset occurs.
Table 1. Operating Modes
AUTOMATIC
AUTO
PIN OPMD
DETECT/
CLASS
I
/I
CUT LIM
MODE
POWER-UP ASSIGNMENT
AUTO Pin
1
11b
Enabled at Automatically
Reset
Yes
Althoughtypicallyusedwithahostcontroller,theLTC4266
can also be used in a standalone mode with no connection
to the serial interface. If there is no host present, the AUTO
pin should be tied high so that, at reset, all ports will be
configured to operate automatically. Each port will detect
Reserved
Semi-auto
0
0
11b
10b
N/A
N/A
N/A
No
Host
Enabled
Upon
Request
Manual
0
0
01b Once Upon
Request
Upon
No
No
Request
and classify repeatedly until a PD is discovered, set I
CUT
Shutdown
00b
Disabled
Disabled
andI accordingtotheclassificationresults,applypower
LIM
after successful detection, and remove power when a PD
is disconnected. Similarly, if the standalone application
is a midspan, the MID pin should be tied high to enable
correct midspan detection timing.
•ꢀ Inꢀmanualꢀmode,ꢀtheꢀportꢀwaitsꢀforꢀinstructionsꢀfromꢀtheꢀ
host system before taking any action. It runs a single
detection or classification cycle when commanded to
by the host, and reports the result in its Port Status
register. The host system can command the port to turn
on or off the power at any time. This mode should only
be used for diagnostic and test purposes.
Table2showstheI andI valuesthatwillbeautomati-
CUT
LIM
callysetinAUTOpinmode, basedonthediscoveredclass.
Table 2. ICUT and ILIM Values in AUTO pin mode
•ꢀ Inꢀsemi-autoꢀmode,ꢀtheꢀportꢀrepeatedlyꢀattemptsꢀtoꢀ
detect and classify any PD attached to it. It reports the
status of these attempts back to the host, and waits for
a command from the host before turning on power to
theport.Thehostmustenabledetection(andoptionally
classification) for the port before detection will start.
CLASS
I
I
LIM
CUT
Class 1
112mA
206mA
375mA
638mA
425mA
425mA
425mA
850mA
Class 2
Class 3 or Class 0
Class 4
The automatic setting of the I
and I values only oc-
LIM
•ꢀ AUTOꢀpinꢀmodeꢀoperatesꢀtheꢀsameꢀasꢀsemi-autoꢀmodeꢀ
CUT
curs if the LTC4266 is reset with the AUTO pin high.
except that it will automatically turn on the power to the
port if detection is successful. In AUTO pin mode, I
CUT
andI valuesaresetautomaticallybytheLTC4266. The
DETECTION
LIM
AUTO pin must be high at reset to ensure proper AUTO
Detection Overview
pin mode operation.
Toavoiddamagingnetworkdevicesthatwerenotdesigned
to tolerate DC voltage, a PSE must determine whether the
connected device is a real PD before applying power. The
IEEE specification requires that a valid PD have a common
moderesistanceof25k 5%atanyportvoltagebelow10V.
ThePSEmustacceptresistancesthatfallbetween19kand
26.5k, and it must reject resistances above 33kΩ or below
15k(shadedregionsinFigure11). ThePSEmaychooseto
4266fb
•ꢀ Inꢀshutdownꢀmode,ꢀtheꢀportꢀisꢀdisabledꢀandꢀwillꢀnotꢀ
detect or power a PD.
Regardlessofwhichmodeitisin,theLTC4266willremove
powerautomaticallyfromanyportthatgeneratesacurrent
limit fault. It will also automatically remove power from
any port that generates a disconnect event if disconnect
detection is enabled. The host controller may also com-
mand the port to remove power at any time.
16
LTC4266
APPLICATIONS INFORMATION
RESISTANCE 0Ω
10k
20k
30k
150Ω (NIC)
23.75k
26.25k
26.5k
PD
PSE
15k 19k
33k
275
165
FIRST
DETECTION
POINT
4266 F11
25kΩ SLOPE
Figure 11. IEEE 802.3af Signature Resistance Ranges
SECOND
DETECTION
POINT
acceptorrejectresistancesintheundefinedareasbetween
the must-accept and must-reject ranges. In particular, the
PSE must reject standard computer network ports, many
of which have 150Ω common mode termination resistors
that will be damaged if power is applied to them (the black
region at the left of Figure 11).
VALID PD
0V-2V
OFFSET
VOLTAGE
4266 F12
Figure 12. PD Detection
4-Point Detection
Operating Modes
The LTC4266 uses a 4-point detection method to discover
PDs. False-positive detections are minimized by check-
ing for signature resistance with both forced-current and
forced-voltage measurements. Initially, two test currents
areforcedontotheport(viatheOUTnpin)andtheresulting
voltages are measured. The detection circuitry subtracts
the two V-I points to determine the resistive slope while
removing offset caused by series diodes or leakage at
the port (see Figure 12). If the forced-current detection
yields a valid signature resistance, two test voltages are
then forced onto the port and the resulting currents are
measured and subtracted. Both methods must report
valid resistances for the port to report a valid detection.
PD signature resistances between 17k and 29k (typically)
are detected as valid and reported as Detect Good in the
corresponding Port Status register. Values outside this
range,includingopenandshortcircuits,arealsoreported.
Iftheportmeasureslessthan1Vatthefirstforced-current
test, the detection cycle will abort and Short Circuit will
be reported. Table 3 shows the possible detection results.
The port’s operating mode determines when the LTC4266
runs a detection cycle. In manual mode, the port will
idle until the host orders a detect cycle. It will then run
detection, report the results, and return to idle to wait for
another command.
Insemi-automode,theLTC4266autonomouslypollsaport
for PDs, but it will not apply power until commanded to do
so by the host. The Port Status register is updated at the
end of each detection cycle. If a valid signature resistance
is detected and classification is enabled, the port will clas-
sify the PD and report that result as well. The port will then
wait for at least 100ms (or 2 seconds if midspan mode is
enabled), and will repeat the detection cycle to ensure that
the data in the port status register is up-to-date.
If the port is in semi-auto mode and high power opera-
tion is enabled, the port will not turn on in response to
a power-on command unless the current detect result is
Detect Good. Any other detect result will generate a t
START
fault if a power-on command is received. If the port is not
in high power mode, it will ignore the detection result and
apply power when commanded, maintaining backwards
compatibility with the LTC4259A.
Table 3. Detection Status
MEASURED PD SIGNATURE
Incomplete or Not Yet Tested
<2.4k
DETECTION RESULT
Detect Status Unknown
Short Circuit
BehaviorinAUTOpinmodeissimilartosemi-auto;however,
after Detect Good is reported and the port is classified (if
classification is enabled), it is automatically powered on
Capacitance > 2.7µF
C
too High
too Low
PD
2.4k < R < 17k
R
SIG
PD
17k < R < 29k
Detect Good
R too High
SIG
PD
without further intervention. In AUTO pin mode, the I
CUT
>29k
and I
thresholds are automatically set; see the Reset
LIM
>50k
Open Circuit
and the AUTO/MID Pins section for more information.
Voltage > 10V
Port Voltage Outside Detect Range
4266fb
17
LTC4266
APPLICATIONS INFORMATION
60
50
40
30
20
10
0
The signature detection circuitry is disabled when the port
is initially powered up with the AUTO pin low, in shutdown
mode, or when the corresponding detect enable bit is
cleared.
PSE LOAD LINE
48mA
OVER
CURRENT
CLASS 4
CLASS 3
33mA
23mA
Detection of Legacy PDs
CLASS 2
Proprietary PDs that predate the original IEEE 802.3af
standard are commonly referred to today as legacy de-
vices. One type of legacy PD uses a large common mode
capacitance (>10μF) as the detection signature. Note that
PDs in this range of capacitance are defined as invalid, so
a PSE that detects legacy PDs is technically noncompliant
with the IEEE spec.
TYPICAL
CLASS 3
PD LOAD
LINE
14.5mA
6.5mA
CLASS 1
CLASS 0
0
5
10
15
20
25
VOLTAGE (V
)
CLASS
4266 F13
Figure 13. PD Classification
TheLTC4266canbeconfiguredtodetectthistypeoflegacy
PD. Legacy detection is disabled by default, but can be
manually enabled on a per-port basis. When enabled, the
port will report detect good when it sees either a valid IEEE
PD or a high-capacitance legacy PD. With legacy mode
disabled, only valid IEEE PDs will be recognized.
If classification is enabled, the port will classify the PD
immediatelyafterasuccessfuldetectioncycleinsemi-auto
or AUTO pin modes, or when commanded to in manual
mode. It measures the PD classification signature by ap-
plying 18V for 12ms (both values typical) to the port via
the OUTn pin and measuring the resulting current; it then
reports the discovered class in the port status register. If
the LTC4266 is in AUTO pin mode, it will additionally use
CLASSIFICATION
the classification result to set the I and I thresholds.
CUT
LIM
See the Reset and the AUTO/MID Pins section for more
information.
802.3af Classification
A PD can optionally present a classification signature to
the PSE to indicate the maximum power it will draw while
operating. The IEEE specification defines this signature
as a constant current draw when the PSE port voltage
The classification circuitry is disabled when the port is
initially powered up with the AUTO pin low, in shutdown
mode, or when the corresponding class enable bit is
cleared.
is in the V
range (between 15.5V and 20.5V), with
CLASS
the current level indicating one of 5 possible PD classes.
Figure 14 shows a typical PD load line, starting with the
slope of the 25kΩ signature resistor below 10V, then
transitioning to the classification signature current (in
802.3at 2-Event Classification
The 802.3at spec defines two methods of classifying a
Type 2 PD.
this case, Class 3) in the V
range. Table 4 shows the
CLASS
One method adds extra fields to the Ethernet LLDP data
protocol; although the LTC4266 is compatible with this
classification method, it cannot perform classification
directly since it doesn’t have access to the data path.
LLDP classification requires the PSE to power the PD as
a standard 802.3af (Type 1) device. It then waits for the
host to perform LLDP communication with the PD and
update the PSE port data. The LTC4266 supports chang-
possible classification values.
Table 4. Classification Values
CLASS
Class 0
Class 1
Class 2
Class 3
Class 4
RESULT
No Class Signature Present; Treat Like Class 3
3W
7W
13W
ing the I
and I
levels on the fly, allowing the host
25.5W (Type 2)
LIM
CUT
to complete LLDP classification.
4266fb
18
LTC4266
APPLICATIONS INFORMATION
The second 802.3at classification method, known as
2-event classification or ping-pong, is fully supported by
the LTC4266. A Type 2 PD that is requesting more than
13W will indicate Class 4 during normal 802.3af classifi-
cation. If the LTC4266 sees Class 4, it forces the port to a
specified lower voltage (called the mark voltage, typically
9V), pauses briefly, and then re-runs classification to
verify the Class 4 reading (Figure 1). It also sets a bit in
the High Power Status register to indicate that it ran the
second classification cycle. The second cycle alerts the
PD that it is connected to a Type 2 PSE which can supply
Type 2 power levels.
a controlled manner that satisfies the PD’s power needs
while minimizing power dissipation in the MOSFET and
disturbances on the V backplane.
EE
The LTC4266 is designed to use 0.25Ω sense resistors to
minimize power dissipation. It also supports 0.5Ω sense
resistors, which are the default when LTC4258/LTC4259A
compatibility is desired.
Inrush Control
Once the command has been given to turn on a port, the
LTC4266 ramps up the GATE pin of that port’s external
MOSFET in a controlled manner. Under normal power-up
circumstances, the MOSFET gate will rise until the port
current reaches the inrush current limit level (typically
450mA), at which point the GATE pin will be servoed to
2-event ping-pong classification is enabled by setting a bit
in the port’s High Power Mode register. Note that a ping-
pongenabledportonlyrunsthesecondclassificationcycle
when it detects a Class 4 device; if the first cycle returns
Class 0 to 3, the port assumes it is connected to a Type
1 PD and does not run the second classification cycle.
maintain the specified I
current. During this inrush
INRUSH
period, a timer (t
) runs. When output charging is
START
complete, the port current will fall and the GATE pin will
be allowed to continue rising to fully enhance the MOSFET
Invalid Type 2 Class Combinations
and minimize its on-resistance. The final V is nominally
GS
The 802.3at spec defines a Type 2 PD class signature as
two consecutive Class 4 results; a Class 4 followed by a
Class 0-3 is not a valid signature. In AUTO pin mode, the
LTC4266 will power a detected PD regardless of the clas-
sification results, with one exception: if the PD presents
an invalid Type 2 signature (Class 4 followed by Class 0
to 3), the LTC4266 will not provide power and will restart
the detection process. To aid in diagnosis, the Port Status
registerwillalwaysreporttheresultsofthelastclasspulse,
so an invalid Class 4–Class 2 combination would report
a second class pulse was run in the High Power Status
register (which implies that the first cycle found Class 4),
and Class 2 in the Port Status register.
13V. If the t
timer expires before the inrush period
START
completes, the port will be turned back off and a t
fault reported.
START
Current Limit
EachLTC4266portincludestwocurrentlimitingthresholds
(I and I ), each with a corresponding timer (t
CUT
LIM
CUT
and t ). Setting the I
and I
thresholds depends
LIM
CUT
LIM
on several factors: the class of the PD, the voltage of the
main supply (V ), the type of PSE (1 or 2), the sense
EE
resistor (0.5Ω or 0.25Ω), the SOA of the MOSFET, and
whether or not the system is required to implement class
enforcement.
Per the IEEE spec, the LTC4266 will allow the port cur-
POWER CONTROL
rent to exceed I
for a limited period of time before
CUT
removing power from the port, whereas it will actively
External MOSFET, Sense R Summary
control the MOSFET gate drive to keep the port current
The primary function of the LTC4266 is to control the
delivery of power to the PSE port. It does this by control-
ling the gate drive voltage of an external power MOSFET
while monitoring the current via an external sense resis-
tor and the output voltage at the OUT pin. This circuitry
below I . The port does not take any action to limit the
LIM
current when only the I
does start the t
threshold is exceeded and current limit is active. If
the current drops below the I
its timer expires, the t
threshold is exceeded, but
LIM
CUT
timer. The t
timer starts when the
CUT
I
LIM
current threshold before
CUT
input supply to the port in
serves to couple the raw V
timer counts back down, but
EE
CUT
4266fb
19
LTC4266
APPLICATIONS INFORMATION
at 1/16 the rate that it counts up. This allows the current
limit circuitry to tolerate intermittent overload signals with
duty cycles below about 6%; longer duty cycle overloads
will turn the port off.
I
Foldback
LIM
The LTC4266 features a two-stage foldback circuit that
reduces the port current if the port voltage falls below the
normal operating voltage. This keeps MOSFET power dis-
sipationatsafelevelsfortypical802.3afMOSFETs, evenat
extended 802.3at power levels. Current limit and foldback
behavior are programmable on a per-port basis. Figure
14 shows MOSFET power dissipation with 802.3af-style
foldback compared with a typical MOSFET SOA curve;
Figure 15 demonstrates how two-stage foldback keeps
the FET within its SOA under the same conditions. Table 5
I
is typically set to a lower value than I to allow the
LIM
CUT
port to tolerate minor faults without current limiting.
Per the IEEE specification, the LTC4266 will automatically
set I
to 425mA (shown in bold in Table 5) during in-
LIM
rush at port turn-on, and then switch to the programmed
setting once inrush has completed. To maintain IEEE
I
LIM
compliance, I should kept at 425mA for all Type 1 PDs,
LIM
gives examples of recommended I register settings.
LIM
and 850mA if a Type 2 PD is detected. I is automatically
LIM
reset to 425mA when a port turns off.
1.0
0.9
0.8
0.7
0.6
0.5
0.4
Table 5. Example Current Limit Settings
INTERNAL REGISTER SETTING (hex)
I
(mA)
R
SENSE
= 0.5Ω
R
SENSE
= 0.25Ω
LIM
53
88
106
159
213
266
319
372
08
89
80
8A
09
8B
88
0.3
0.2
0.1
0.0
802.3af FOLDBACK
08
89
SOA DC AT 90°C
30
0
10
PD VOLTAGE (V) AT V
40
50
= 58V
60
20
PSE
4266 F14
425
478
00
8E
92
CB
10
D2
40
4A
50
5A
60
52
80
Figure 14. Turn On Currents vs FET Safe Operating
Area at 90°C Ambient
531
8A
584
1.0
0.9
0.8
0.7
0.6
0.5
0.4
638
90
9A
C0
CA
D0
DA
E0
49
40
4A
50
5A
60
52
744
850
956
1063
1169
1275
1488
1700
1913
2125
2338
2550
2975
0.3
0.2
0.1
0.0
802.3af FOLDBACK
SOA DC AT 90°C
30
PD VOLTAGE (V) AT V
0
10
40
50
= 58V
60
20
PSE
4266 F15
Figure 15. LTC4266 Foldback vs FET Safe Operating
Area at 90°C Ambient
4266fb
20
LTC4266
APPLICATIONS INFORMATION
Disconnect
The LTC4266 will support current levels well beyond the
maximum values in the 802.3at specification. The shaded
areas in Table 5 indicate settings that may require a larger
external MOSFET, additional heat sinking, or a reduced
The LTC4266 monitors the port to make sure that the PD
continues to draw the minimum specified current. A dis-
connect timer counts up whenever port current is below
7.5mA(typ),indicatingthatthePDhasbeendisconnected.
t
setting.
LIM
If the t timer expires, the port will be turned off and
DIS
MOSFET Fault Detection
the disconnect bit in the fault event register will be set.
LTC4266 PSE ports are designed to tolerate significant
levels of abuse, but in extreme cases it is possible for
the external MOSFET to be damaged. A failed MOSFET
may short source to drain, which will make the port ap-
pear to be on when it should be off; this condition may
also cause the sense resistor to fuse open, turning off
the port but causing the LTC4266 SENSE pin to rise to
an abnormally high voltage. A failed MOSFET may also
short from gate to drain, causing the LTC4266 GATE pin
to rise to an abnormally high voltage. The LTC4266 SENSE
and GATE pins are designed to tolerate up to 80V faults
without damage.
If the current returns before the t timer runs out, the
DIS
timer resets and will start counting from the beginning
if the undercurrent condition returns. As long as the PD
exceeds the minimum current level more often than t
it will stay powered.
,
DIS
Althoughnotrecommended,theDCdisconnectfeaturecan
be disabled by clearing the corresponding DC Disconnect
Enable bits. Note that this defeats the protection mecha-
nisms built into the IEEE spec, since a powered port will
stay powered after the PD is removed. If the still-powered
port is subsequently connected to a non-PoE data device,
the device may be damaged.
If the LTC4266 sees any of these conditions for more than
180μs, it disables all port functionality, reduces the gate
drive pull-down current for the port and reports a FET Bad
fault. This is typically a permanent fault, but the host can
attempt to recover by resetting the port, or by resetting
the entire chip if a port reset fails to clear the fault. If the
MOSFET is in fact bad, the fault will quickly return, and
the port will disable itself again. The remaining ports of
the LTC4266 are unaffected.
TheLTC4266doesnotincludeACdisconnectcircuitry, but
includes AC disconnect enable bits to maintain compat-
ibility with the LTC4259A. If the AC Disconnect Enable bits
are set, DC disconnect will be used.
Shutdown Pins
The LTC4266 includes a hardware SHDN pin for each port.
When a SHDN pin is pulled to DGND, the corresponding
port will be shut off immediately. The port remains shut
An open or missing MOSFET will not trigger a FET Bad
2
down until re-enabled via I C or a device reset in AUTO
fault, but will cause a t
to turn on the port.
fault if the LTC4266 attempts
START
pin mode.
Masked Shutdown
Voltage and Current Readback
The LTC4266 provides a low latency port shedding fea-
ture to quickly reduce the system load when required. By
allowing a pre-determined set of ports to be turned off,
the current on an overloaded main power supply can be
reduced rapidly while keeping high priority devices pow-
ered. Each port can be configured to high or low priority;
all low-priority ports will shut down within 6.5μs after
the MSD pin is pulled low. If multiple ports in a LTC4266
device are shut down via MSD, they are staggered by at
least 0.55μs to help reduce voltage transients on the main
The LTC4266 measures the output voltage and current
at each port with an internal A/D converter. Port data is
only valid when the port power is on. The converter has
two modes:
•ꢀ Slowꢀmode:ꢀ14ꢀsamplesꢀperꢀsecond,ꢀ14.5ꢀbitsꢀresolution
•ꢀ Fastꢀmode:ꢀ440ꢀsamplesꢀperꢀsecond,ꢀ9.5ꢀbitsꢀresolution
Infastmode,theleastsignificant5bitsofthelowerbyteare
zeroes so that bit scaling is the same in both modes.
4266fb
21
LTC4266
APPLICATIONS INFORMATION
supply. If a port is turned off via MSD, the corresponding
detection and classification enable bits are cleared, so
the port will remain off until the host explicitly re-enables
detection.
EXTERNAL COMPONENT SELECTION
Power Supplies and Bypassing
The LTC4266 requires two supply voltages to operate. V
requires 3.3V (nominally) relative to DGND. V requires a
DD
EE
SERIAL DIGITAL INTERFACE
negativevoltageofbetween–44Vand–57VforType 1PSEs,
or –50V to –57V for Type 2 PSEs, relative to AGND. The
relationship between the two grounds is not fixed; AGND
Overview
can be referenced to any level from V to DGND, although
DD
TheLTC4266communicateswiththehostusingastandard
2
it should typically be tied to either V or DGND.
DD
SMBus/I C 2-wire interface. The LTC4266 is a slave-only
device, and communicates with the host master using
the standard SMBus protocols. Interrupts are signaled to
the host via the INT pin. The timing diagrams (Figures 5
through 9) show typical communication waveforms and
their timing relationships. More information about the
SMBus data protocols can be found at www.smbus.org.
V
provides power for most of the internal LTC4266 cir-
DD
cuitry,anddrawsamaximumof3mA.Aceramicdecoupling
cap of at least 0.1μF should be placed from V to DGND,
as close as practical to each LTC4266 chip.
DD
Figure16showsathreecomponentlowdropoutregulator
foranegativesupplytoDGNDgeneratedfromthenegative
The LTC4266 requires both the V and V supply rails
V
EE
supply. V is tied to AGND and DGND is negative
DD
EE
DD
to be present for the serial interface to function.
referencedtoAGND.ThisregulatordrivesasingleLTC4266
device. In Figure 17, DGND is tied to AGND in this boost
Bus Addressing
converter circuit for a positive V supply of 3.3V above
DD
AGND. This circuit can drive multiple LTC4266 devices
TheLTC4266’sprimaryserialbusaddressis010xxxxb,with
the lower four bits set by the AD3-AD0 pins; this allows up
to16LTC4266sonasinglebus.AllLTC4266salsorespond
to the address 0110000b, allowing the host to write the
same command (typically configuration commands) to
multiple LTC4266s in a single transaction. If the LTC4266
is asserting the INT pin, it will also respond to the alert
response address (0001100b) per the SMBus spec.
and opto couplers.
V
is the main supply that provides power to the PDs.
EE
Because it supplies a relatively large amount of power and
issubjecttosignificantcurrenttransients,itrequiresmore
design care than a simple logic supply. For minimum IR
loss and best system efficiency, set V near maximum
EE
amplitude (57V), leaving enough margin to account for
transientover-orundershoot,temperaturedrift,andtheline
regulation specs of the particular power supply used.
Interrupts and SMBALERT
Most LTC4266 port events can be configured to trigger
an interrupt, asserting the INT pin and alerting the host to
the event. This removes the need for the host to poll the
LTC4266,minimizingserialbustrafficandconservinghost
CPU cycles. Multiple LTC4266s can share a common INT
line, with the host using the SMBALERT protocol (ARA)
to determine which LTC4266 caused an interrupt.
AGND
AGND
V
DD
D1
C1
CMHZ4687-4.3V
LTC4266
DGND
0.1µF
Q2
CMPTA92
V
R5
750k
EE
4266 F16
Register Description
V
EE
For information on serial bus usage and device configura-
tion and status, refer to the LTC4266 Software Program-
ming documentation.
Figure 16. Negative LDO to DGND
4266fb
22
LTC4266
APPLICATIONS INFORMATION
L3
L4
10µH
D28
B1100
100µH
SUMIDA CDRH5D28-101NC
SUMIDA CDRH4D28-100NC
3.3V AT 400mA
C74
100µF
6.3V
C73
10µF
6.3V
C75
R51
4.7k
1%
R53
R52
3.32k
1%
10µF
4.7k
16V
1%
C76
10µF
63V
C78
0.22µF
100V
+
5
Q13
Q14
FMMT723
C77
0.22µF
100V
V
FMMT723
CC
1
3
6
Q15
ITH/RUN
NGATE
SENSE
FDC2512
R58
10Ω
LTC3803
R54
56k
4
R55
806Ω
1%
R56
47.5k
1%
V
FB
R57
1k
R59
0.100Ω
1%, 1W
C79
2200pF
GND
2
R60
10Ω
V
EE
4266 F17
Figure 17. Positive VDD Boost Converter
Bypass capacitance between AGND and V is very im-
If the device is part of a larger system, contains additional
external non-Ethernet ports, or must be referenced to
protective ground for some other reason, the Power over
Ethernet subsystem (including all LTC4266s) must be
electrically isolated from the rest of the system. Figure 18
shows a typical isolated serial interface. The SDAOUT pin
of the LTC4266 is designed to drive the inputs of an opto-
EE
portant for reliable operation. If a short circuit occurs at
one of the output ports it can take as long as 1μs for the
LTC4266 to begin regulating the current. During this time
the current is limited only by the small impedances in the
circuit and a high current spike typically occurs, causing a
voltage transient on the V supply and possibly causing
EE
2
the LTC4266 to reset due to a UVLO fault. A 1μF, 100V
coupler directly. Standard I C/SMBus devices typically
X7R capacitor placed near the V pin is recommended
cannot drive opto-couplers, so U1 is used to buffer the
signals from the host controller side.
EE
to minimize spurious resets.
Isolating the Serial Bus
External MOSFET
TheLTC4266includesasplitSDApin(SDAINandSDAOUT)
to ease opto-isolation of the bidirectional SDA line.
CarefulselectionofthepowerMOSFETiscriticaltosystem
reliability. LTC recommends either Fairchild IRFM120A,
FDT3612, FDMC3612 or Philips PHT6NQ10T for their
proven reliability in Type 1 and Type 2 PSE applications.
Non-standard applications that provide more current than
the 850mA IEEE maximum may require heat sinking and
other MOSFET design considerations. Contact LTC Ap-
plications before using a MOSFET other than one of these
recommended parts.
IEEE 802.3 Ethernet specifications require that network
segments (including PoE circuitry) be electrically isolated
from the chassis ground of each network interface device.
However,networksegmentsarenotrequiredtobeisolated
fromeachother,providedthatthesegmentsareconnected
to devices residing within a single building on a single
power distribution system.
For simple devices such as small PoE switches, the isola-
tion requirement can be met by using an isolated main
power supply for the entire device. This strategy can be
used if the device has no electrically conducting ports
other than twisted-pair Ethernet. In this case, the SDAIN
and SDAOUT pins can be tied together and will act as a
Sense Resistor
The LTC4266 is designed to use either 0.5Ω or 0.25Ω
current sense resistors. For new designs 0.25Ω is recom-
mended to reduce power dissipation; the 0.5Ω option is
intended for existing systems where the LTC4266 is used
as a drop-in replacement for the LTC4258 or LTC4259A.
The lower sense resistor values reduce heat dissipation.
4266fb
2
standard I C/SMBus SDA pin.
23
LTC4266
APPLICATIONS INFORMATION
0.1µF
2
I C ADDRESS
LTC4266
V
DD
INT
SCL
SDAIN
SDAOUT
AD0
AD1
AD2
AD3
DGND
AGND
0100000
0100001
0100010
0.1µF
0.1µF
LTC4266
V
DD
INT
SCL
SDAIN
SDAOUT
AD0
AD1
AD2
AD3
DGND
AGND
2k
2k
U2
200Ω
V
CPU
SCL
DD
U1
200Ω
SDA
0.1µF
LTC4266
HCPL-063L
V
DD
TO
INT
SCL
SDAIN
SDAOUT
AD0
CONTROLLER
U3
200Ω
200Ω
AD1
AD2
AD3
DGND
AGND
SMBALERT
0.1µF
•
•
•
0.1µF
GND CPU
HCPL-063L
U1: FAIRCHILD NC7WZ17
U2, U3: AGILENT HCPL-063L
LTC4266
V
DD
INT
SCL
SDAIN
SDAOUT
AD0
0101110
AD1
AD2
AD3
DGND
AGND
0.1µF
LTC4266
ISOLATED
3.3V
V
INT
DD
SCL
SDAIN
SDAOUT
AD0
+
10µF
0101111
AD1
AD2
AD3
DGND
AGND
ISOLATED
GND
4266 F18
Figure 18. Opto-Isolating the I2C Bus
4266fb
24
LTC4266
APPLICATIONS INFORMATION
Four commonly available 1Ω resistors (0402 or larger
package size) can be used in parallel in place of a single
S1B diodes work well as port clamp diodes, and an
SMAJ58AorequivalentisrecommendedfortheV surge
EE
0.25Ω resistor. In order to meet the I and I accuracy
suppressor.
CUT
LIM
required by the IEEE specification, the sense resistors
should have 1% tolerance or better, and no more than
200ppm/°C temperature coefficient.
LAYOUT GUIDELINES
Standard power layout guidelines apply to the LTC4266:
place the decoupling caps for the V and V supplies
near their respective supply pins, use ground planes, and
use wide traces wherever there are significant currents.
Output Cap
DD
EE
Each port requires a 0.22μF cap across its outputs to keep
the LTC4266 stable while in current limit during startup
or overload. Common ceramic capacitors often have sig-
nificant voltage coefficients; this means the capacitance
is reduced as the applied voltage increases. To minimize
this problem, X7R ceramic capacitors rated for at least
100V are recommended.
The main layout challenge involves the arrangement of
the current sense resistors, and their connections to
the LTC4266. Because the sense resistor values are very
low, layout parasitics can cause significant errors. Care is
required to achieve specified accuracy, particularly with
disconnect currents.
ESD/Cable Discharge Protection
Figure 19 illustrates the problem. In the example on the
Ethernet ports can be subject to significant ESD events
when long data cables, each potentially charged to thou-
sands of volts, are plugged into the low impedance of the
RJ45jack. Toprotectagainstdamage, eachportrequiresa
left, two ports have load currents I and I that return to
1 2
the V power supply through a mutual resistance R .
EE
M
R represents the combined resistances of any traces,
M
planes, and vias in the PCB that I and I share as they
1
2
pair of clamp diodes; one to AGND and one to V (Figure
return to the V supply. The LTC4266 measures the volt-
EE
EE
10). An additional surge suppressor is required for each
age difference between its SENSE and V pins to sense
EE
LTC4266 chip from V to AGND. The diodes at the ports
the voltage drop across R , but as the example shows,
EE
S1
steer harmful surges into the supply rails, where they are
R introduces errors.
M
absorbed by the surge suppressor and the V bypass
EE
The example on the right shows how errors can be
minimized with a good layout. The circuit is rearranged
capacitance. The surge suppressor has the additional
benefit of protecting the LTC4266 from transients on the
so that R no longer affects V , and the V connection
M
S
EE
V
supply.
EE
to the LTC4266 is used as a Kelvin sense trace. V is not
EE
I
1
I
I
I
2
2
1
LTC4266
LTC4266
GATE
GATE
SENSE
SENSE
+
+
V
V
V
V
EE
–
S
EE
–
S
R
R
R
R
I
S1
S2
S1
S2
I
I
EE
EE
R
R
M
R
M
K
I
+ I + I
2
+ I + I
1
EE
1
2
EE
MUTUAL RESISTANCE
= I R + I R + I R
KELVIN SENSE LINE
V
S
1
S1
1
M
2 M
V
= I R – I
R
K
S
1
S1 EE
SIGNAL
SCALE ERROR
CROSSTALK ERROR
SIGNAL
SMALL OFFSET ERROR
4266 F19
Figure 19. Layout Affects Current Readback Accuracy
4266fb
25
LTC4266
APPLICATIONS INFORMATION
a perfect Kelvin connection because all four ports con-
trolled by the LTC4266 share the same sense trace, and
parallel. The four groups of resistors are arranged to
minimize the overlap in their current flows, which mini-
mizes mutual resistance. The horizontal slits cut in the
copper help to keep the currents separate. Wide copper
paths connect each group of resistors to the vias at the
center, so the resistance is very low.
because the current through the trace (I ) is not zero.
EE
However, as the equation shows, the remaining error is a
small offset term.
Figure20showstwoLTC4266chipscontrollingeightports
(A though H). The ports are separated into two groups
of four; each has its own trace on the top PCB layer that
Proper connection of the sense line is also important. In
Figure 21, U1 is not connected directly to the V plane
EE
connects to the V plane with a via. Currents from the U1
but is connected instead to a Kelvin sense trace that
leads to the sense resistor array. Similarly, the via at the
center of the sense resistor array has a matching hole
EE
sub-circuitareeffectivelyisolatedfromtheU2sub-circuit,
reducing the layout problem down to 4-port chunks; this
arrangement can be expanded for any number of ports.
in the V plane. This arrangement prevents the mutual
EE
resistance of the four large vias from influencing the
Figure 21 shows an example of good 4-port layout. Each
0.25Ω sense resistor consists of four 1Ω resistors in
current measurements.
PORTS A THROUGH D
PORTS E THROUGH H
U1
LTC4266
U2
LTC4266
SENSE1
SENSE2
SENSE3
SENSE4
SENSE1
SENSE2
SENSE3
SENSE4
V
EE
V
EE
R
SENSE
THIS TRACE PROVIDES V TO U1
EE
BUT ALSO ACTS AS A KELVIN
SENSE LINE FOR PORTS A-D
VIA
VIA
RETURN TO
V
POWER SUPPLY
EE
V
COPPER FILL ON SURFACE LAYER
PLANE ON INNER LAYER
BY KEEPING THESE COPPER FILLS SEPARATE ON
THE SURFACE, MUTUAL RESISTANCE BETWEEN
PORTS A-D AND E-H IS ELIMINATED
EE
4266 F20
V
EE
Figure 20. Layout Strategy to Reduce Mutual Resistance
4266fb
26
LTC4266
APPLICATIONS INFORMATION
EDGE OF V PLANE (ON SOME INNER LAYER)
EE
KELVIN SENSE TRACE CONNECTS U1
TO V THROUGH THE VIAS ON THE RIGHT
EE
PORT A R
PORT B R
SENSE
SENSE
PIN 1
FOUR LARGE VIAS
TO V PLANE
EE
HOLE IN V PLANE
EE
VIAS TO SOURCE PIN OF
THE PORT D MOSFET
LOCATED ON THE OPPOSITE
SIDE OF THE BOARD
PORT C R
PORT D R
SENSE
SENSE
U1
THE PADDLE IS
CONNECTED TO
EE
4266 F21
V
PINS
Figure 21. Good PCB Layout Example
PACKAGE DESCRIPTION
GW Package
36-Lead Plastic SSOP (Wide .300 Inch)
(Reference LTC DWG # 05-08-1642)
36
19
1.40 0.127
15.291 – 15.545*
(.602 – .612)
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
10.804 MIN
7.75 – 8.258
10.11 – 10.55
(.398 – .415)
1
18
0.520 0.0635
0.800 BSC
RECOMMENDED SOLDER PAD LAYOUT
7.417 – 7.595**
(.292 – .299)
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
2.286 – 2.388
(.090 – .094)
2.44 – 2.64
(.096 – .104)
0.254 – 0.406
(.010 – .016)
× 45°
0.355
REF
0° – 8° TYP
0.1 – 0.3
0.40 – 1.27
0.800
(.0315)
BSC
0.231 – 0.3175
(.0091 – .0125)
0.28 – 0.51
(.011 – .02)
TYP
(.004 – .0118)
(.015 – .050)
GW36 SSOP 0204
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
4266fb
27
LTC4266
PACKAGE DESCRIPTION
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)
0.70 ± 0.05
5.50 ± 0.05
4.10 ± 0.05
3.00 REF
5.15 0.05
3.15 0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
5.5 REF
6.10 ± 0.05
7.50 ± 0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
0.75 ± 0.05
3.00 REF
5.00 ± 0.10
37
38
0.00 – 0.05
0.40 ±0.10
PIN 1
TOP MARK
1
2
(SEE NOTE 6)
5.15 0.10
5.50 REF
7.00 ± 0.10
3.15 0.10
(UH) QFN REF C 1107
0.200 REF 0.25 ± 0.05
R = 0.125
TYP
R = 0.10
TYP
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4266fb
28
LTC4266
REVISION HISTORY (Revision history begins at Rev B)
REV
DATE
DESCRIPTION
PAGE NUMBER
1 to 6, 9, 13
1 to 26
B
3/11
Revised AGND and DGND pin references throughout data sheet.
Revised auto mode to AUTO pin mode throughout data sheet.
Added text to Operating Modes and made minor text edits throughout Applications Information section.
19 to 26
4266fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
29
LTC4266
TYPICAL APPLICATION
ISOLATED
3.3V
ISOLATED
GND
0.1µF
DGND AGND
0.22µF
2k
2k
100V
X7R
V
DD
U2
FB1
FB2
200Ω
SCL
V
CPU
1/4
DD
SDAIN
SDAOUT
INT
LTC4266
U1
SCL
V
SENSE GATE OUT
EE
200Ω
1µF
100V
X7R
S1B
R
S
0.25Ω
SDA
Q1
HCPL-063L
SMAJ58A
S1B
–48V
ISOLATED
U3
RJ45
200Ω
200Ω
CONNECTOR
T1
1
2
•
•
•
•
0.01µF
200V
0.01µF
200V
3
4
5
6
7
8
75Ω
75Ω
INTERRUPT
PHY
0.1µF
GND CPU
(NETWORK
PHYSICAL
LAYER
HCPL-063L
CHIP)
•
•
•
•
D
: DIODES INC SMAJ58A
TSS
0.01µF
200V
0.01µF
200V
Q1: FAIRCHILD IRFM120A OR PHILIPS PHT6NQ10T
U1: FAIRCHILD NC7WZ17
75Ω
75Ω
U2, U3: AGILENT HCPL-063L
FB1, FB2:TDK MPZ2012S601A
T1: PULSE H6096NL OR COILCRAFT ETH1-230LD
4266 F22
1000pF
2000V
Figure 22. One Complete Isolated Powered Ethernet Port
COMMENTS
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4266fb
LT 0311 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
30
●
●
LINEAR TECHNOLOGY CORPORATION 2009
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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