LT3971EMSE#TRPBF_技术文档

LT3992

Monolithic Dual Tracking

3A Step-Down Switching Regulator

FeaTures

DescripTion

The LT^®3992 is a dual current mode PWM step-down

DC/DC converter with two internal 4.6A switches. Inde-

n

Wide Input Range:

– Operation from 3V to 60V

Independent Supply, Shutdown, Soft-Start, UVLO,

n

pendent input voltage, shutdown, feedback, soft-start,

UVLO current limit and comparator pins for each channel

simplify complex power supply tracking and sequencing

requirements.

Programmable Current Limit and Programmable

Power Good for Each 3A Regulator

n

Die Temperature Monitor

n

Adjustable/Synchronizable Fixed Frequency

To optimize efficiency and component size, both convert-

ers have a programmable maximum current limit and are

synchronized to either a common external clock input, or

aresistorsettablefixed250kHzto2MHzinternaloscillator.

A frequency divider is provided for channel 1 to further

optimize component size. At all frequencies, a 180° phase

relationshipbetweenchannelsismaintained,reducingvolt-

age ripple and component size. A clock output is available

for synchronizing multiple regulators.

Operation from 250kHz to 2MHz with Synchronized

Clock Output

n

Independent Synchronized Switching Frequencies

Optimize Component Size

n

Antiphase Switching

n

Outputs Can Be Paralleled

n

Flexible Output Voltage Tracking

n

Low Dropout: 95% Maximum Duty Cycle

n

5mm × 5mm QFN Package

Minimum input to output voltage ratios are improved by

allowingtheswitchtostayonthroughmultipleclockcycles

onlyswitchingoffwhentheboostcapacitorneedsrecharg-

ing. Independent channel operation can be programmed

using the SHDN pin. Disabling both converters reduces

the total quiescent current to <10µA.

n

FMEA Compliant 38-Pin Exposed Pad TSSOP Package

applicaTions

n

Automotive Supplies

Distributed Supply Regulation

n

L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks of

Linear Technology Corporation. All other trademarks are the property of their respective owners.

Typical applicaTion

12V and 5V 2-Stage Multi-Frequency Step-Down Converter

Independent Synchronized

Switching Frequencies Extend

Full Frequency Input Range

V

IN1

15V TO 60V

4.7µF

V

OUT2

V

IN2

IN1

SHDN1

SHDN2

CH1

400kHz

20V/DIV

BST1

SW1

BST2

SW2

22µH

2.2µH

FB1

0.1µF

22µF

0.1µF

8.06k

IND1

IND2

V

OUT2

OUT1

12V

LT3992

5V

V

OUT1

V

OUT2

FB2

2A

1600kHz

1A

CH2

1.6MHz

5V/DIV

113k

42.2k

FB1

400kHz

47µF

8.06k

100k

CMPI1

CMPI2

CMPO1

CMPO2

PG

SS1

ILIM1

SS2

ILIM2

3992 TA01b

500ns/DIV

V

= 60V

IN

V

C2

C1

RT/SYNC CLKOUT

DIV

CLKOUT

1600kHz

0.1µF

100k

33pF

680pF

0.1µF

680pF

T

J

GND

10nF

60.4k

15k

48.7k

102k

10k

3992 TA01a

3992f

1

LT3992

absoluTe MaxiMuM raTings ^{(Note 1)}

V

, SHDN1/2, CMPO1/2.......................................60V

V

, T .............................................................. 100µA

IN1/2

C1/2 J

SW1/2....................................................................V

Operating Junction Temperature Range (Note 2)

IN1/2

BST1/2 ......................................................................75V

BST1/2 Pin Above SW1/2..........................................25V

LT3992EUH........................................ –40°C to 125°C

LT3992IUH......................................... –40°C to 125°C

LT3992EFE......................................... –40°C to 125°C

LT3992IFE.......................................... –40°C to 125°C

LT3992HFE ........................................ –40°C to 150°C

Storage Temperature Range .................. –65°C to 150°C

IND1/2, V

.........................................................60V

OUT1/2

FB1/2, CMPI1/2, SS1/2................................................5V

RT/SYNC .....................................................................5V

DIV, ILIM1/2.............................................................2.5V

pin conFiguraTion

TOP VIEW

1

2

SW1

NC

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

NC

IND1

NC

TOP VIEW

3

V

IN1

4

SHDN1

SS1

V

OUT1

NC

5

32 31 30 29 28 27 26 25

6

I

BST1

CMPO1

CMPI1

FB1

LIM1

BST1

CMPO1

CMPI1

FB1

1

2

3

4

5

6

7

8

24 ILIM1

7

V

C1

23

22

21

20

19

18

V

C1

8

NC

RT/SYNC

CLKOUT

9

RT/SYNC

CLKOUT

33

GND

10

11

12

13

14

15

16

17

18

19

39

NC

FB2

T

J

GND

T

J

FB2

CMPI2

CMPO2

BST2

DIV

CMPI2

CMPO2

BST2

NC

V

C2

VC2

17 ILIM2

I

LIM2

9

10 11 12 13 14 15 16

UH PACKAGE

SS2

SHDN2

V

OUT2

NC

V

IN2

32-LEAD (5mm × 5mm) PLASTIC QFN

NC

IND2

NC

θ

= 44°C/W, θ = 7.3°C/W

JA

JC(PAD)

SW2

EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB

*DO NOT CONNECT

FE PACKAGE

38-LEAD PLASTIC TSSOP

θ

= 17.5°C/W, θ

= 10°C/W

JA

JC(PAD)

EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB

orDer inForMaTion

LEAD FREE FINISH

LT3992EUH#PBF

LT3992IUH#PBF

LT3992EFE#PBF

LT3992IFE#PBF

LT3992HFE#PBF

TAPE AND REEL

PART MARKING*

3992

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LT3992EUH#TRPBF

LT3992IUH#TRPBF

LT3992EFE#TRPBF

LT3992IFE#TRPBF

LT3992HFE#TRPBF

–40°C to 125°C

–40°C to 150°C

32-Lead (5mm × 5mm) Plastic QFN

38-Lead Plastic TSSOP

3992

LT3992FE

38-Lead Plastic TSSOP

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

3992f

2

LT3992

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_VIN1/2= 15V unless otherwise specified. (Note 2)

PARAMETER

CONDITIONS

MIN

1.24

–1

TYP

1.32

0

MAX

1.4

1

UNITS

V

l

SHDN Voltage Threshold CH1/2

SHDN Input Current CH1/2

V

SHDN

= 1.35V

µA

V

Undervoltage Lockout (Note 3)

Shutdown Current

2.6

2.9

6

3.2

13

V

IN1

IN2

IN1

IN2

l

V

SHDN

V

SHDN

V

FB1/2

V

FB1/2

V

VC1/2

V

VIN1/2

V

VC1/2

V

VC1/2

= 0V

µA

Shutdown Current

= 0V

0.1

4.2

530

806

0

2

µA

Quiescent Current

= 2V

3

6

mA

µA

Quiescent Current

= 2V

300

786

780

–13

0

900

824

830

13

l

Feedback Voltage CH1/2

= 1V

mV

nA

Feedback Voltage Regulation

Feedback Voltage Offset CH1 to CH2

Feedback Bias Current CH1/2

= 4V to 60V

= 1V

85

300

T Output Voltage (Note 4)

J

T = 25°C, I = 25µA, Temperature = 25°C

250

1.23

–380

mV

V

mV

J

TJ

I

= 25µA, Temperature = 125°C

TJ

= 25µA, Temperature = –40°C

l

T Error

Temperature = 25°C to 125°C

–100

250

15

0

350

25

100

450

40

mV

µMho

µA

J

Error Amp g CH1/2

V

VC1/2

V

FB1/2

V

FB1/2

V

FB1/2

V

FB1/2

V

FB1/2

V

FB1/2

V

FB1/2

V

FB1/2

V

VC1/2

= 1V, I

VC1/2

=

10µA

= 1V

m

Error Amp Source Current CH1/2

Error Amp Sink Current CH1/2

Error Amp High Clamp CH1/2

= 0.7V, V

VC1/2

=0.9V, V

= 0.7V

= 0V

= 1V

15

25

40

µA

1.7

0.8

9

1.9

1.0

13.5

2.15

0.9

170

0

2.1

1.2

17

V

Error Amp Switching Threshold CH1/2

Soft-Start Source Current CH1/2

V

l

= 2V, V

= 2.0V

= 0.07V

µA

SS1/2

Soft-Start V CH1/2

1.9

0.4

130

16

2.4

2

V

OH

Soft-Start Sink Current CH1/2

= 0.7V, V

= 0V

= 2V

mA

mV

µA

SS1/2

Soft-Start V CH1/2

210

16

OL

l

Soft-Start to Feedback Offset CH1/2

SS POR Threshold CH1/2

Soft-Start Sink Current CH1/2 POR

Soft-Start SW Disable CH1/2

CMPI Bias Current CH1/2

= 1V, V

= 0.4V

SS1/2

70

110

450

115

0

140

600

150

100

500

760

94

V

= 2V, V

= 0.14V (Note 5)

150

80

FB1/2

SS1/2

= 0V (Note 5)

mV

nA

FB1/2

= 0.8V

= 0.8V, V

Rising

–100

CMPI1/2

CMP1/2

CMPI1/2

RT/SYNC

CMPO Leakage CH1/2

= 60V

70

nA

CMPO1/2

l

CMPI Threshold CH1/2

690

86

725

90

mV

%

CMPI Threshold CH1/2 of V

CMPI Hysteresis CH1/2

Rising (Note 6)

FB1/2

50

80

105

mV

µA

CMPO Sink Current CH1/2

= 0.6V, V

= 0.2V

150

11.3

11.2

50

250

12

CMPO1/2

l

RT/SYNC Reference Current

Minimum Switching Frequency

Switching Frequency

= 0.36V E- & I-Grade

= 0.36V H-Grade

=0Ω

12.7

13

µA

12

µA

R

110

1

150

1100

3.0

kHz

MHz

Deg

µA

RT/SYNC

= 28k

900

2.2

Maximum Switching Frequency

Switching Phase Angle CH1 ≥ CH2

DIV Reference Current

=100k

2.5

185

12

l

V

= 1V

10.7

0.44

13.3

0.56

DIV

CH1 DIV 2 Threshold

R

= 0V

0.5

V

RT/SYNC

3992f

3

LT3992

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_VIN1/2= 15V unless otherwise specified. (Note 2)

PARAMETER

CONDITIONS

MIN

0.89

1.39

TYP

1.0

1.5

0.25

2

MAX

1.06

1.56

UNITS

V

CH1 DIV 4 Threshold

CH1 DIV 8 Threshold

R

= 0V

RT/SYNC

V

CLKOUT V

V

OL

OH

V

CLKOUT to SW1ON Delay ( t

CLKOUT to SW2ON Delay ( t

)

CLKOUT Rising

CLKOUT Falling

60

ns

kHz

Deg

ns

V

DCLKOSW1

30

DCLKOSW2

RT/SYNC to CLKOUT Delay ( t

SYNC Frequency Range

)

V

= 0V to 2V Rising Edge

= 2V to 0V Falling Edge

300

150

DRTSYNCH

RT/SYNC

)

DRTSYNCL

250

2000

2.6

SYNC Phase Angle CH1 to CH2

Minimum Switch On-Time CH1/2

Minimum Switch Off-Time CH1/2

SYNC Frequency = 250kHz

180

160

200

2.2

Minimum Boost for 100% DC CH1/2 (Note 7)

IND + V Current CH1/2

1.6

10

V

= 0V

= 5V

1.5

0.5

5

µA

OUT

VOUT1/2

l

ILIM1/2 Reference Current

IND to V Maximum Current CH1/2

V

ILIM

= 0V

12

16

µA

V

= 0.5V, V

= 1.5V, V

= 1V (Note 8)

= 5V (Note 8)

= 1V (Note 8)

= 5V (Note 8)

0.5

0.7

3.5

1.5

1.8

4.6

3

6.4

A

OUT

ILIM1/2

VOUT

l

Switch Leakage Current CH1/2

Switch Saturation Voltage CH1/2

V

= 0V

1

10

µA

SW1/2

I

= 500mA, V

= 3A, V

= 18V

200

325

mV

SW1/2

BST1/2

= 18V

Boost Current CH1/2

I

= 500mA, V

= 8V

5

35

8

55

25

85

mA

SW1/2

BST1/2

= 3A, V

= 8V

BST1/2

Minimum Boost Voltage CH1/2 (Note 9)

I

= 3A, V

= 8V

1.0

2.2

3.0

V

SW1/2

BST1/2

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LT3992EUH/LT3992EFE is guaranteed to meet performance

specifications from 0°C to 125°C junction temperature. Specifications over

the –40°C to 125°C operating junction temperature range are assured by

design, characterization and correlation with statistical process controls.

The LT3992IUH/LT3992IFE is guaranteed over the full –40°C to 125°C

operating junction temperature range. The LT3992HFE is guaranteed

over the full –40°C to 150°C operating junction temperature range. High

junction temperatures degrade operating lifetimes. Operating lifetime is

derated at junction temperatures greater than 125°C.

Note 4: The T output voltage represents the temperature at the center

of the die while dissipating quiescent power. Due to switch power

J

dissipation and temperature gradients across the die, the T output

J

voltage measurement does not guarantee that absolute maximum junction

temperature will not be exceeded.

Note 5: An internal power on reset (POR) latch is set on the positive

transition of the SHDN1/2 pin through its threshold, thermal shutdown or

overvoltage lockout. The output of the latch activates current sources on

each SS pin which typically sink 450µA and discharge the SS capacitor.

The latch is reset when both SS pins are driven below the soft-start POR

threshold or the SHDN pin is taken below its threshold.

Note 6: The threshold is expressed as a percentage of the feedback

reference voltage for the channel.

Note 3: V undervoltage lockout is defined as the voltage which the V

IN

Note 7: To enhance dropout operation, the output switch will be turned off

for the minimum off-time only when the voltage across the boost capacitor

drops below the minimum boost for 100% duty cycle threshold.

pin must exceed for operation. The threshold guarantees that internal bias

lines are regulated and switching frequency is constant. Actual minimum

input voltage to maintain a regulated output will depend upon output

voltage and load current. See the Applications Information section.

Note 8: The IND to V

maximum current is defined as the value of

OUT

current flowing from the IND pin to the V

pin which resets the switch

OUT

latch when the V pin is at its high clamp.

C

Note 9: This is the minimum voltage across the boost capacitor needed to

guarantee full saturation of the internal power switch.

3992f

4

LT3992

Typical perForMance characTerisTics

FB Voltage and CH1-CH2 FB

Offset vs Temperature

Shutdown Quiescent Current

vs Temperature

Shutdown Threshold and Minimum

Input Voltage vs Temperature

820

815

810

805

800

8

3.5

3.0

10

9

8

7

6

5

4

3

2

1

0

6

MINIMUM

INPUT VOLTAGE

4

2.5

I

Q1

2

OFFSET

2.0

1.5

1.0

0.5

0

SHUTDOWN

THRESHOLD VOLTAGE

–2

–4

–6

–8

CH2

CH1

I

Q2

0

–50

50

100 125

150

–25

0

25

75

–25

0

150

75 100

125 150

–50

25 50 75 100 125

TEMPERATURE (°C)

–50 –25

0

25 50

TEMPERATURE (°C)

3992 G03

3992 G01

3992 G02

Soft-Start-to-Feedback Offset

vs Temperature

Error Amplifier Transconductance

vs Temperature

T_JOutput Voltage vs Temperature

415

4

3

2

1

0

1.50

1.25

1.00

0.75

0.50

0.25

0

V

= 0.4V

SS

400

385

370

355

340

325

310

295

280

265

250

R

= 30k

–1

–2

–3

–4

TJ

TO GND

–0.25

–0.50

R

TJ

= 30k TO –1V

50 75

TEMPERATURE (°C)

–50 –25

0

25

100 125 150

50 75

–50

10 30 50 70 90

TEMPERATURE (°C)

150

110 130

–50 –25

0

25

100 125 150

–30 –10

TEMPERATURE (°C)

3992 G06

3992 G04

3992 G05

Comparator Thresholds

vs Temperature

Comparator Sink Current

vs Temperature

Switching Frequency

vs Temperature

730

720

710

700

690

680

670

660

650

640

630

1800

1600

1400

1200

1000

800

600

400

200

0

400

350

300

250

200

150

100

50

SINK CURRENT AT V

= 0.4V

CMPO

R

= 44.2k

RT/SYNC

RISING THRESHOLD

R

= 28.0k

RT/SYNC

= 13.0k

= 0k

RT/SYNC

R

FALLING THRESHOLD

RT/SYNC

0

50 75

25

TEMPERATURE (°C)

–50 –25

0

100 125 150

50 75

TEMPERATURE (°C)

–50

50

100 125

150

–50 –25

0

25

100 125 150

–25

0

25

75

TEMPERATURE (°C)

3992 G09

3992 G07

3992 G08

3992f

5

LT3992

Typical perForMance characTerisTics

CLKOUT-to-SW1 Delay

vs Temperature

RT/SYNC-to-CLKOUT and SW1

Delay vs Temperature

Switching Phase vs Temperature

160

150

140

130

120

110

100

90

195

193

191

450

400

350

300

250

200

150

100

50

SW1

189

187

185

183

181

179

177

175

CLKOUT

80

70

60

0

50 75

TEMPERATURE (°C)

125

150

50 75

TEMPERATURE (°C)

–50 –25

0

25

100 125 150

–50

50

100

–50 –25

0

25

100 125 150

–25

0

25

75

TEMPERATURE (°C)

3992 G10

3992 G11

3992 G12

Synchronization Duty Cycles

vs Temperature

DIV Voltage Threshold

vs Temperature

Switch Saturation Voltage

vs Temperature

100

90

80

70

60

50

40

30

20

10

0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

400

350

300

250

200

150

100

RT/SYNC FREQUENCY = 1MHz

÷8

÷4

÷2

I

= 3A

SW

MAXIMUM RT/SYNC DUTY CYCLE

I

= 1A

SW

MINIMUM RT/SYNC DUTY CYCLE

I

= 500mA

SW

–50

50

100 125

150

–25

0

25

75

50 75

25

TEMPERATURE (°C)

75 100

125 150

–50 –25

0

100 125 150

–50 –25

0

25 50

TEMPERATURE (°C)

3992 G13

3992 G14

3992 G15

Switch Peak Current

vs Temperature

Minimum Boost Voltage

vs Temperature

Boost Current vs Temperature

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

100

90

80

70

60

50

40

30

20

10

0

3.00

2.75

2.50

2.25

2.00

1.75

1.50

1.25

1.00

I

= 3A

SW

V

= 1.5V

ILIM

3A

V

= 0.5V

ILIM

1A

0.5A

–50

50

100 125

150

–50

50

100 125

–25

0

25

75

–50 –25

50 75

25

TEMPERATURE (°C)

–25

0

25

75

150

0

100 125

150

TEMPERATURE (°C)

3992 G17

3992 G16

3992 G18

3992f

6

LT3992

Typical perForMance characTerisTics

CLKOUT Frequency

vs RT/SYNC Resistance

5V Efficiency

3.3V Efficiency

90

85

80

75

70

65

60

55

50

90

85

80

75

70

65

60

55

50

2500

2250

2000

1750

V

= 12V

IN

V

= 12V

V

= 24V

V

IN

V

IN

= 24V

= 36V

IN

1500

1250

1000

750

500

f

= 1MHz

SW

f

= 1MHz

SW

CH1 = 5V

250

0

CH1 = 5V, 0A

CH2 = 3.3V

CH2 = 3.3V, 0A

0

2.0

3.0

0.5 1.0 1.5

2.5

3.5

0

10 20 30 40 50 60 70 80

RT/SYNC RESISTANCE (kΩ)

0

3.0

0.5 1.0 1.5

2.0

OUTPUT CURRENT (A)

2.5

3.5

OUTPUT CURRENT (A)

3992 G20

3992 G19

3992 G21

5V Efficiency

3.3V Efficiency

90

85

80

75

70

65

60

55

50

45

85

80

75

70

65

60

55

50

V

= 12V

= 24V

= 36V

= 48V

= 60V

IN

V

= 12V

IN

= 24V

= 36V

= 48V

f

= 500kHz

f

= 500kHz

SW

CH1 = 5V

CH1 = 5V, 0A

CH2 = 3.3V

45

40

CH2 = 3.3V, 0A

40

0

2.0

3.0

0.5 1.0 1.5

2.5

3.5

2.0

3.0

0.5 1.0 1.5

2.5

3.5

OUTPUT CURRENT (A)

3992 G22

3992 G23

3992f

7

LT3992

pin FuncTions

BST1/2: The BST pin provides a higher than V base

ILIM1/2: The voltage present at the ILIM pin determines

the peak inductor current for the channel. The ILIM pin is

driven by an internal current source with a typical value

of 12µA. A resistor from the ILIM pin to ground sets the

ILIM voltage; the resistor value must be between 42.2k

and 120k. The maximum current limit range is 4.8A to

1.8A when the ILIM voltages are 1V and 0.5V respectively.

IN

drive to the power NPN to ensure a low switch drop. If the

voltage between the BST pin and the V pin is less than

IN

the voltage required to fully turn on the power NPN, the

power switch is turned off to recharge the BST capacitor.

CMPI1/2: The CMPI pin is an input to a comparator with a

threshold of 725mV and 80mV of hysteresis. Connecting

the CMPI pin to the FB pin will generate a power good

signalwhentheoutputiswithin90%ofitsregulatedvalue.

IND1/2:TheINDpinistheinputtotheinternalsenseresistor

that measures current flowing in the inductor. When the

current in the resistor exceeds the current dictated by the

CMPO1/2: The CMPO pin is an open-collector output that

sinks current when the CMPI pin falls below its threshold.

For a typical input voltage above 2.9V, its output state re-

V pin, the SW latch is held in reset, disabling the output

C

switch. Bias current flows out of the IND pin.

mains true, although during shutdown, V undervoltage

RT/SYNC: The voltage present at the RT/SYNC pin deter-

mines the constant switching frequency. The RT/SYNC

pin is driven by an internal current source with a typical

value of 12µA which allows a single resistor from the RT/

SYNCpintogroundtosettheRT/SYNCvoltageandresult-

ing switching frequency. Minimum switching frequency

IN1

lockout or thermal shutdown, its current sink capability is

reduced. The COMPO pins can be left open circuit or tied

together to form a single power good signal.

DIV:ThevoltagepresentattheDIVpindeterminestheratio

of channel 1 frequency to the master clock frequency set

by the RT/SYNC pin. The DIV pin is driven by an internal

current source with a typical value of 12µA which allows

a single resistor from the DIV pin to ground to set the

DIV voltage and resulting channel 1 frequency divider.

Ratios of 1, 2, 4 and 8 are available. See the Applications

Information section for more information.

is typically 110kHz when V

is 0V and maximum

RT/SYNC

switching frequency is typically 2.5MHz when V

is above 950mV.

RT/SYNC

Driving the RT/SYNC pin with an external clock signal will

synchronize the switch to the applied frequency. Synchro-

nization occurs on the rising edge of the clock signal after

theclocksignalisdetected.Eachrisingclockedgeinitiates

an oscillator ramp reset. A gain control loop servos the

oscillator charging current to maintain constant oscillator

amplitude. Hence, the slope compensation and channel

phase relationship remain unchanged. If the clock signal

is removed, the oscillator reverts to resistor mode after

thesynchronizationdetectioncircuitrytimesout.Theclock

source impedance should be set such that the current out

oftheRT/SYNCpininresistormodegeneratesafrequency

roughly equivalent to the synchronization frequency. See

theApplicationsInformationsectionformoreinformation.

DNC: Do Not Connect.

GND: The exposed pad pin is the only ground connec-

tion for the device. The exposed pad should be soldered

to a large copper area to reduce thermal resistance. The

GND pin is common to both channels and also serves as

small-signal ground. For ideal operation all small-signal

ground paths should connect to the GND pin at a single

point avoiding any high current ground returns.

FB1/2:TheFBpinisthenegativeinputtotheerroramplifier.

The output switches to regulate this pin to 806mV with

respect to the exposed ground pad. Bias current flows

out of the FB pin.

3992f

8

LT3992

pin FuncTions

SHDN1/2: The shutdown pin is used to control each

channel’s operation. In addition to controlling channel 1,

the SHDN1 pin also activates control circuitry for both

channels and must be present for channel 2 to operate.

When SHDN1 is below its threshold, quiescent current is

reduced to a typical value of 6µA. Independent channel

UVLO can be programmed by connecting the SHDN pin to

an input voltage divider. See the Applications Information

section for more information. If the shutdown features are

T : The T pin outputs a voltage proportional to junction

J J

temperature. The pin is 250mV for 25°C and has a slope

of 10mV/°C. See the Applications Information section for

more information.

V

:TheV pinistheoutputoftheerroramplifierandthe

C

C1/2

input to the peak switch current comparator. It is normally

used for frequency compensation, but can also be used

as a current clamp or control loop override. If the error

amplifier drives V above the maximum switch current

C

not used, the SHDN pin should be tied to V .

IN

level, a voltage clamp activates. This indicates that the

output is overloaded and current is pulled from the SS

pin reducing the regulation point.

SS1/2: Current flowing out the SS pin into an external

capacitor defines the rise time of the output voltage. When

theSSpinislowerthanthe0.806Vreference,thefeedback

is regulated to the SS voltage. When the SS pin exceeds

the reference voltage, the output will regulate the FB pin

voltage to 0.806V and the SS pin will continue to rise until

V

: The V pin powers the internal control circuitry

IN1

for both channels and is monitored by an undervoltage

lockout comparator. The V pin is also connected to the

IN1

collector of channel 1’s on-chip power NPN switch. The

its clamp voltage. During an output overload, the V pin is

C

V

IN1

pin has high dI/dt edges and must be decoupled to

driven above the maximum switch current level activating

ground close to the pin of the device.

its voltage clamp. When the V clamp is activated, the SS

C

V

: The V pin powers the output stage for channel 2

pinisdischargeduntiltheoutputreachesaregulationpoint

that the maximum output current can maintain. When the

overload condition is removed, the output soft starts from

that voltage. In the case of a SHDN or thermal shutdown

event, a power on reset latch ensures the capacitors on

bothchannelsarefullydischargedbeforeeitherisreleased.

Connecting both SS pins together ensures the outputs

track together.

IN2

and is monitored by an undervoltage lockout comparator.

V

voltage must be greater than typically 2.9V for V

IN1

IN2

operation. The V pin is also the collector of channel

IN2

2’s on-chip power NPN switch. The V pin has high dI/

dt edges and must be decoupled to ground close to the

IN2

pin of the device.

V

: The V

pin is the output to the internal sense

OUT1/2

OUT

resistor that measures current flowing in the inductor.

CLKOUT: The CLKOUT pin generates a square wave of 0V

to 2.5V which is synchronized to the internal oscillator. If

the switching frequency is set by an external resistor the

resultant clock duty cycle will be 50%. If the RT/SYNC pin

isdrivenbyanexternalclocksource,theresultantCLKOUT

duty cycle will mirror the external source.

When the current in the resistor exceeds the current dic-

tated by the V pin, the SW latch is held in reset disabling

C

the output switch. Bias current flows out of the V

pin.

OUT

SW1/2: The SW pin is the emitter of the internal power

NPN. At switch off, the inductor will drive this pin below

ground with a high dV/dt. An external Schottky catch

diode to ground, close to the SW pin and respective V

IN

decoupling capacitor’s ground, must be used to prevent

this pin from excessive negative voltages.

3992f

9

LT3992

block DiagraM

V

IN1

V

IN1

1.32V

+

–

SHDN1

CHANNEL 1

BST1

SW1

IND1

DROPOUT

THERMAL

SHUTDOWN

ENHANCEMENT

PRE

S

R

DRIVER

CIRCUITRY

–

+

Q

2.5V

PRE

12µA

S

R

Q

–

+

–

SS1

V

OUT1

110mV

V

C1

R1

R2

FB1

2.5V

CMPI1

12µA

CMPO1

+

–

ILIM1

0.806V

+

0.72V

+

–

R

LIM

SLOPE

2.5V

COMPENSATION

12µA

RT/SYNC

DIV

T

J

INTERNAL

2.5V

CLK1

V

+

–

R3

IN1

REGULATOR

AND

CLKOUT

GND

MASTER CLOCK

2.9V

OSCILLATOR

AND AGC

REFERENCES

CLK2 TO CHANNEL 2

R

DIV

3992 F01

Figure 1. LT3992 Block Diagram

The LT3992 is a dual channel, constant frequency, current

mode buck converter with internal 4.6A switches. Each

channelcanbeindependentlycontrolledwiththeexception

is then divided by 1, 2, 4 or 8 depending on the voltage

presentattheDIVpin. Channel2’sclockrunsatthemaster

clock frequency with a 180° phase shift from channel 1.

that V must be above the typically 2.9V undervoltage

IN1

Alternatively, if a synchronization signal is detected by

the LT3992 the RT/SYNC pin, the master clock will be

generated at the incoming frequency on the rising edge

of the synchronization pulse with channel 1 in phase with

the synchronization signal. Frequency division and phase

remainsthesameastheinternallygeneratedmasterclock.

lockoutthresholdtopowerthecommoninternalregulator,

oscillator and thermometer circuitry.

If the SHDN1 pin is taken below its 1.32V threshold the

LT3992willbeplacedinalowquiescentcurrentmode.Inthis

mode the LT3992 typically draws 6µA from V and <1µA

IN1

from V . When the SHDN pin is driven above 1.32V, the

IN2

In addition, the internal slope compensation will be au-

tomatically adjusted to prevent subharmonic oscillation

during synchronization. In either mode of oscillator op-

eration, a square wave with the master clock frequency,

synchronized to channel 1 is present at the CLKOUT pin.

internalbiascircuitsturnongeneratinganinternalregulated

voltage, 0.806V , 12µA RT/SYNC, DIV and ILIM current

FB

references, and a POR signal which sets the soft-start latch.

Once the internal reference reaches its regulation point,

the internal oscillator will start generating a master clock

signal for the two regulators at a frequency determined by

thevoltagepresentattheRT/SYNCpin.Thechannel 1clock

The two regulators are constant frequency, current mode

step-down converters. Current mode regulators are con-

trolled by an internal clock and two feedback loops that

3992f

10

LT3992

block DiagraM

control the duty cycle of the power switch. In addition to

thenormalerroramplifier,thereisacurrentsenseamplifier

that monitors switch current on a cycle-by-cycle basis.

This technique means that the error amplifier commands

current to be delivered to the output rather than voltage.

A voltage fed system will have low phase shift up to the

resonant frequency of the inductor and output capacitor,

then an abrupt 180° shift will occur. The current fed sys-

tem will have 90° phase shift at a much lower frequency,

but will not have the additional 90° shift until well beyond

the LC resonant frequency. This makes it much easier to

frequency compensate the feedback loop and also gives

much quicker transient response.

by the V voltage, output regulation is achieved by the

C

error amplifier continually adjusting the V pin voltage.

C

The error amplifier is a transconductance amplifier that

compares the FB voltage to the lowest voltage present at

eithertheSSpinoraninternal806mVreference. Compen-

sationoftheloopiseasilyachievedwithasimplecapacitor

or series resistor/capacitor from the V pin to ground.

C

The regulators’ maximum output current occurs when

the V pin is driven to its maximum clamp value by the

C

error amplifier. The value of the typical maximum switch

current can be programmed from 4.6A to 1.8A by placing

a resistor from the ILIM pin to ground.

Since the SS pin is driven by a constant current source, a

singlecapacitoronthesoft-startpinwillgeneratecontrolled

linear ramp on the output voltage.

The Block Diagram in Figure 1 shows only one of the

switching regulators whose operation will be discussed

below. The additional regulator will operate in a similar

manner with the exception that its clock will be 180° out

of phase with the other regulator.

If the current demanded by the output exceeds the maxi-

mum current dictated by the V pin clamp, the SS pin

C

will be discharged, lowering the regulation point until the

outputvoltagecanbesupportedbythemaximumcurrent.

Once the overload condition is removed, the regulator will

soft-start from the overload regulation point.

When, during power-up, an internal POR signal sets

the soft-start latch, both SS pins will be discharged to

ground to ensure proper start-up operation. When the SS

pin voltage drops below 110mV, the V pin is driven low

C

disabling switching and the soft-start latch is reset. Once

the latch is reset the soft-start capacitor starts to charge

with a typical value of 12µA.

Shutdown control or thermal shutdown will set the soft-

start latch, resulting in a complete soft-start sequence.

The switch driver operates from either the V or BST volt-

IN

As the voltage rises above 110mV on the SS pin, the V

C

age. An external diode and capacitor are used to generate

pin will be driven high by the error amplifier. When the

a drive voltage higher than V to saturate the output NPN

IN

voltage on the V pin exceeds 1V, the clock set-pulse sets

C

and maintain high efficiency. If the BST capacitor voltage

is sufficient, the switch is allowed to operate to 100% duty

cycle. If the boost capacitor discharges towards a level

insufficient to drive the output NPN, a BST pin compara-

tor forces a minimum cycle off time, allowing the boost

capacitor to recharge.

the driver flip-flop, which turns on the internal power NPN

switch. This causes current from V , through the NPN

IN

switch, inductor and internal sense resistor to increase.

When the voltage drop across the internal sense resistor

exceeds a predetermined level set by the voltage on the

V pin, the flip-flop is reset and the internal NPN switch

C

A comparator with a threshold of 720mV and 80mV of

hysteresis is provided for detecting error conditions. The

CMPO output is an open-collector NPN that is off when

the CMPI pin is above the threshold allowing a resistor

to pull the CMPO pin to a desired voltage.

is turned off. Once the switch is turned off the inductor

will drive the voltage at the SW pin low until the external

Schottky diode starts to conduct, decreasing the current

in the inductor. The cycle is repeated with the start of each

clock cycle. However, if the internal sense resistor voltage

exceedsthepredeterminedlevelatthestartofaclockcycle,

the flip-flop will not be set resulting in a further decrease

in inductor current. Since the output current is controlled

ThevoltagepresentattheT pinisproportionaltothejunction

J

temperature of the LT3992. The T pin will be 250mV for a

J

die temperature of 25°C and will have a slope of 10mV/°C.

3992f

11

LT3992

applicaTions inForMaTion

Choosing the Output Voltage

Toalleviatedutycyclerestrictionsduetominimumswitch-

on times, channel 1’s switching frequency can be divided

fromthemasterclockby1,2,4or8determinedbyresistor

The output voltage is programmed with a resistor divider

between the output and the FB pin. Choose the 1% resis-

tors according to:

R

in Figure 1. Channel 2’s switching frequency is not

DIV

affected by the DIV pin. The DIV pin is driven by a 12µA

V_OUT

0.806





currentsource. SettingresistorR setsthevoltagepres-

DIV

R1= R2 •

– 1







ent at the DIV pin which determines the divisor as shown

in Table 1. The DIV pin doesn’t have any input hysteresis

near the ratio thresholds.



R2 should be 10k or less to avoid bias current errors. Ref-

erence designators refer to the Block Diagram in Figure 1.

Table 1. Channel 1 Divisor vs V_DIV

TYPICAL DIV VOLTAGE

< 0.5V

FREQUENCY RATIO

R

(Ω)

DIV

Choosing the Switching Frequency

V

DIV

1

2

4

8

0

The LT3992 switching frequency is set by resistor R3 in

Figure 1. The RT/SYNC pin is driven by a 12µA current

source. Setting resistor R3 sets the voltage present at

the RT/SYNC pin which determines the master oscillator

frequency as illustrated in Figure 2. The R3 resistance

(in kΩ) may be calculated from the desired switching

frequency (in kHz) by the equation:

0.5V < V < 1.0V

61.9k

102k

150k

DIV

1.0V < V < 1.5V

DIV

1.5V < V

DIV

The switching frequency is typically set as high as pos-

sible to reduce overall solution size. The LT3992 employs

techniques to enhance dropout at high frequencies but

efficiency and maximum input voltage decrease due to

switching losses and minimum switch on times.

2

R3 = 1.86E-6 • f

+ 2.81E-2 • f –1.76

SW

for frequencies between 150kHz and 2000kHz. A 0V to

2.5V square wave with the same frequency as the master

oscillator and in phase with channel 1 is output via the

CLKOUT pin. The CLKOUT signal can be used to synchro-

nize multiple switching regulators.

The maximum recommended frequency can be approxi-

mated by the equation:

V_OUT+ V_D

1

Frequency (Hz) =

•

V – V + V_Dt_ON(MIN)

IN

SW

2500

2250

2000

1750

whereV istheforwardvoltagedropofthecatchdiode(D1

D

Figure 2), V is the voltage drop of the internal switch,

SW

and t

in the minimum on-time of the switch.

ON(MIN)

1500

1250

1000

750

500

250

0

10 20 30 40 50 60 70 80

RT/SYNC RESISTANCE (kΩ)

3992 F02

Figure 2. Switching Frequency vs RT/SYNC Resistance

3992f

12

LT3992

applicaTions inForMaTion

Table 2. Efficiency and Size Comparisons for Different R_RT/SYNCValues, 3.3V Output

EFFICIENCY

VIN1/2

†

FREQUENCY (kHz)

RT/SYNC (kΩ)

5.90

V

= 12V (%)

V

(V)

L (µH)*

15

C (µF)*

120

60

C + L (Area, mm2)

IN(MAX)

250

500

88

87

84

82

78

60

59.8

54.6

51.9

46.9

19.1

13.0

43

21

14

9

8.2

1000

1500

2250

28.0

3.3

30

44.2

2.2

22

69.8

1

15

†

V

is defined as the highest typical input voltage that maintains constant output voltage ripple.

IN(MAX)

* Inductor and capacitor values chosen for stability and constant ripple current.

The following example along with the data in Table 2

illustrates the trade-offs of switch frequency selection for

a single input voltage system.

Forcing switch off for a minimum time will only occur at the

end of a clock cycle when the boost capacitor needs to be

recharged.Thisoperationhasthesameeffectasloweringthe

clock frequency for a fixed off time, resulting in a higher duty

cycle and lower minimum input voltage. The resultant duty

cycle depends on the charging times of the boost capacitor

and can be approximated by the following equation:

Example:

V = 25V, V

D

= 3.3V, I

= 2A, t

= 180ns,

IN

OUT

SW

OUT

ON(MIN)

V = 0.6V, V = 0.4V.

3.3+ 0.6

25 – 0.4+ 0.6 180ns

1

Max Frequency =

•

~ 850kHz

DC_MAX

=

1

1+

B

RT/SYNC ~ 23.2kΩ (Figure 2 )

Input Voltage Range

where B is 3A divided by the typical boost current from

the Electrical Characteristics table.

Once the switching frequency has been determined, the

input voltage range of the regulator can be determined. The

minimum input voltage is determined by either the LT3992’s

minimumoperatingvoltageof~2.9V,orbyitsmaximumduty

cycle. The duty cycle is the fraction of time that the internal

switchisonduringaclockcycle. Unlikemostfixedfrequency

regulators, the LT3992 will not switch off at the end of each

clock cycle if there is sufficient voltage across the boost

capacitor (C3 in Figure 1) to fully saturate the output switch.

This leads to a minimum input voltage of:

V_OUT+ V_D

DC_MAX

V

=

– V_D+ V_SW

IN(MIN)

where V is the voltage drop of the internal switch.

SW

Figure 4 shows a typical graph of minimum input voltage

vs load current for the 3.3V output shown in Figure 15.

6

V

= 3.3V

OUT

t

P

5

4

3

2

1

0

START-UP

SW1

SW2

RUNNING

t /2

P

t

P

t /2

P

t

P

CLKOUT

3992 F03

0

1000 1500 2000 2500 3000 3500

500

t

DCLKOSW1

t

DCLKOSW2

CURRENT (mA)

3992 F04

Figure 4. Minimum Input Voltage vs Load Current

Figure 3. Timing Diagram RT/SYNC = 28.0k, t_P= 1µs, V_DIV= 0V

3992f

13

LT3992

applicaTions inForMaTion

In cases where multiple input voltages are present, or the

V /V ratio for channel 1 is significantly different than

The maximum input voltage is determined by the absolute

maximum ratings of the V and BST pins and by the

IN OUT

IN

channel2, channel1’sfrequencycanbedividedbyafactor

of 2, 4 or 8 from the programmed value by setting the DIV

pin resistor to the appropriate value. Dividing channel 1’s

frequency will increase the maximum input voltage by the

same ratio. Channel 1’s external components will have to

be chosen according to the resulting frequency.

frequency and minimum duty cycle. The minimum duty

cycle is defined as:

DC

= t

• Frequency

ON(MIN)

MIN

Maximum input voltage as:

V_OUT+ V_D

DC_MIN

V

=

– V_D+ V_SW

IN(MAX)

Example:

V

= 3.3V, I

= 1A, frequency = 1MHz, temperature

OUT

Note that the LT3992 will regulate if the input voltage is

taken above the calculated maximum voltage as long as

= 25°C, V = 0.1V, B = 50 (from boost characteristics

SW

specification), V = 0.4V, t

= 180ns. R = 1.2kΩ.

D

ON(MIN)

DIV

maximum ratings of the V and BST pins are not violated.

IN

However operation in this region of input voltage will

exhibit pulse skipping behavior.

DC_MIN1= t_ON(MIN1)• Frequency/4 = 0.045

3.3+ 0.4

Example:

V

=

– 0.4+ 0.1= >60V

IN1(MAX)

0.045

V

= 3.3V, I

= 1A, frequency = 1MHz, temperature

OUT

= 25°C, V = 0.1V, B = 50 (from boost characteristics

SW

Inductor Selection and Maximum Output Current

specification), V = 0.4V, t

= 180ns:

D

ON(MIN)

A good first choice for the LT3992 inductor value is:

1

DC_MAX

=

= 98%

V_OUT

f

1

L =

1+

50

where f is frequency in MHz and L is in µH.

3.3+ 0.4

0.98

V

=

– 0.4+ 0.1= 3.48V

IN(MIN)

With this value 3A of load current will be available over

the entire input voltage range. The inductor’s RMS cur-

rent rating must be greater than your maximum load

current and its saturation current should be higher than

the maximum peak switch current, and will reduce the

output voltage ripple.

DC_MIN= t_ON(MIN)•Frequency = 0.18

3.3+ 0.4

V

=

– 0.4+ 0.1= 20.2V

IN(MAX)

0.18

2 • t

If the maximum load for a single channel is lower than

2.5A, then you can decrease the value of the inductor and

operate with higher ripple current, or you can adjust the

maximum switch current for the channel via the ILIM pin.

Thisallowsyoutouseaphysicallysmallerinductor, orone

with a lower DCR resulting in higher efficiency.

P

SW1

SW2

1/(2 • t )

t

P

t /2

P

t

P

The peak inductor and switch current is:

CLKOUT

∆I_L

2

I_SW(PK)= I_L(PK)= I_OUT

+

3992 F05

t

DCLKOSW1

t

DCLKOSW2

Figure 5. Timing Diagram RT/SYNC = 28.0k,

t_P= 1µs, V_DIV= 0.75V

3992f

14

LT3992

applicaTions inForMaTion

To maintain output regulation, this peak current must be

less than the LT3992’s switch current limit, ILIM. ILIM

can be set between 1.8A and 4.6A for each channel via

a resistor from the ILIM pin to ground. The ILIM pin is

WhentheLT3992’sinputsuppliesareoperatedatdifferent

input voltages, an input capacitor sized for that channel

should be placed as close as possible to the respective

V pins.

IN

drivenbya12µAcurrentsource. SettingresistorR sets

LIM

A caution regarding the use of ceramic capacitors at the

input. A ceramic input capacitor can combine with stray

inductance to form a resonant tank circuit. If power is

applied quickly (for example by plugging the circuit into

a live power source) this tank can ring, doubling the in-

put voltage and damaging the LT3992. The solution is to

either clamp the input voltage or dampen the tank circuit

by adding a lossy capacitor in parallel with the ceramic

capacitor. For details, see Application Note 88.

the voltage present at the ILIM pin which determines the

maximumswitchcurrentasillustratedinFigure6.Thevalue

for R must be greater than 42.2k. A capacitor from the

LIM

ILIM pin to ground, or a resistor divider from the output,

can be used to limit the peak current during start-up. If a

capacitor is used it must be discharged before power-up

to ensure proper operation.

Referring to Figure 6, as the peak current limit is reduced,

slope compensation further reduces the peak current with

increasing duty cycle.

Output Capacitor Selection

Typicallystep-downregulatorsareeasilycompensatedwith

an output crossover frequency that is 1/10 of the switch-

ing frequency. This means that the time that the output

capacitor must supply the output load during a transient

step is ~2 or 3 switching periods. With an allowable 1%

drop in output voltage during the step, a good starting

value for the output capacitor can be expressed by:

When the ILIM pin is used to reduce the peak switch cur-

rent, the equation for inductor choice becomes:

50 • V_OUT

L =

f •R_ILIM

where f is frequency in MHz, L in µH and R in kΩ.

4.5

4.0

Max Load Step

C_VOUT

=

Frequency • 0.01• V_OUT

3.5

Example:

3.0

2.5

2.0

1.5

V

= 3.3V, Frequency = 1MHz, Max Load Step = 2A.

2

OUT

C_VOUT

=

= 60µF

1E6• 0.01• 3.3V

The calculated value is only a suggested starting value.

Increasethevalueiftransientresponseneedsimprovement

or reduce the capacitance if size is a priority. The output

capacitor filters the inductor current to generate an output

with low voltage ripple. It also stores energy in order to

satisfytransientloadsandtostabilizetheLT3992’scontrol

loop. The switching frequency of the LT3992 determines

the value of output capacitance required. Also, the current

mode control loop doesn’t require the presence of output

capacitor series resistance (ESR). For these reasons, you

are free to use ceramic capacitors to achieve very low

output ripple and small circuit size.

1.0

40

50

60

70

80

90

100

ILIM PIN RESISTOR (kΩ)

3992 F06

Figure 6. Peak Switch Current vs ILIM Resistor

Input Capacitor Selection

Bypass the inputs of the LT3992 circuit with a 4.7µF or

higher ceramic capacitor of X7R or X5R type. A lower

value or a less expensive Y5V type can be used if there

is additional bypassing provided by bulk electrolytic or

tantalum capacitors.

3992f

15

LT3992

applicaTions inForMaTion

Youcanalsouseelectrolyticcapacitors. TheESRsofmost

aluminum electrolytics are too large to deliver low output

ripple. Tantalum and newer, lower ESR organic electrolytic

capacitors intended for power supply use, are suitable

and the manufacturers will specify the ESR. The choice of

capacitor value will be based on the ESR required for low

ripple. Because the volume of the capacitor determines

its ESR, both the size and the value will be larger than a

ceramic capacitor that would give you similar ripple per-

formance. One benefit is that the larger capacitance may

give better transient response for large changes in load

current. Table 3 lists several capacitor vendors.

BST Pin Considerations

The capacitor and diode tied to the BST pin generate a

voltage that is higher than the input voltage. In most cases

a0.47µFcapacitorandasmallSchottkydiode(suchasthe

BAT41) will work well. To ensure optimal performance at

duty cycles greater than 80%, use a 0.5A Schottky diode

(such as a MBR0560). Almost any type of film or ceramic

capacitor is suitable, but the ESR should be <1Ω to ensure

it can be fully recharged during the off time of the switch.

The capacitor value can be approximated by:

I

_OUT(MAX)• V_OUT

C_BST

=

5 • V – 2 • f

V

(

)

IN

OUT

Table 3

VENDOR

Taiyo Yuden

AVX

TYPE

SERIES

where I

is the maximum load current.

OUT(MAX)

Ceramic X5R, X7R

Figure 7 shows four ways to arrange the boost circuit. The

BST pin must be more than 3V above the SW pin for full

efficiency. Generally, for outputs of 3.3V and higher the

standard circuit (Figure 7a) is the best. For lower output

voltages the boost diode can be tied to the input (Fig-

ure 7b). The circuit in Figure 7a is more efficient because

the BST pin current comes from a lower voltage source.

Figure 7c shows the boost voltage source from available

DC sources that are greater than 3V. The highest efficiency

is attained by choosing the lowest boost voltage above 3V.

For example, if you are generating 3.3V and 1.8V and the

3.3V is on whenever the 1.8V is on, the 1.8V boost diode

can be connected to the 3.3V output. In any case, you

must also be sure that the maximum voltage at the BST

pin is less than the maximum specified in the Absolute

Maximum Ratings section.

Ceramic X5R, X7R

Tantalum

Kemet

Tantalum

TA Organic

AL Organic

T491, T494, T495

T520

A700

Sanyo

Panasonic

TDK

TA/AL Organic

AL Organic

POSCAP

SP CAP

Ceramic X5R, X7R

Catch Diode

The diode D1 conducts current only during switch-off

time. Use a Schottky diode to limit forward voltage drop to

increase efficiency. The Schottky diode must have a peak

reverse voltage that is equal to regulator input voltage and

sized for average forward current in normal operation.

Average forward current can be calculated from:

I_OUT

V

IN

The boost circuit can also run directly from a DC voltage

that is higher than the input voltage by more than 3V, as

in Figure 7d. The diode is used to prevent damage to the

I_D(AVG)

=

• V – V

(

IN

OUT

)

Withashortedcondition, diodecurrentwillincreasetothe

typical value determined by the peak switch current limit

of the LT3992 set by the ILIM pin. This is safe for short

periods of time, but it would be prudent to check with the

diode manufacturer if continuous operation under these

conditions can be tolerated.

LT3992 in case V is held low while V is present. The

X

IN

circuit saves several components (both BST pins can be

tied to D2). However, efficiency may be lower and dissipa-

tion in the LT3992 may be higher. Also, if V is absent, the

X

LT3992 will still attempt to regulate the output, but will do

so with very low efficiency and high dissipation because

the switch will not be able to saturate, dropping 1.5V to

2V in conduction.

3992f

16

LT3992

applicaTions inForMaTion

D2

C3

D2

V

BST

V

SW

V

IN

SW

IN

LT3992

IND

OUT

IND

OUT

V

< 3V

OUT

V

OUT

GND

V

– V = V

V

– V = V

BST SW IN

BST(MAX)

BST

SW

OUT

= V + V

= 2 • V

IN

BST(MAX)

IN

OUT

(7a)

(7b)

D2

V

= LOWEST V

IN

X

V

> V + 3V

IN

X

OR V

> 3V

OUT

C3

BST

V

SW

V

IN

SW

IN

LT3992

IND

OUT

IND

OUT

V

< 3V

V

< 3V

OUT

V

OUT

GND

V

– V = V

V

– V = V

BST SW X

BST

SW

X

3992 F07

= V + V

= V

X

BST(MAX)

IN

X

BST(MAX)

= 3V

= V + 3V

IN

X(MIN)

(7c)

(7d)

Figure 7. BST Pin Considerations

The minimum input voltage of an LT3992 application is

limited by the minimum operating voltage (typically 2.9V)

and by the maximum duty cycle as outlined above. For

proper start-up, the minimum input voltage is also limited

by the boost circuit. If the input voltage is ramped slowly,

or the LT3992 is turned on with its SS pin when the output

is already in regulation, then the boost capacitor may not

be fully charged. Because the boost capacitor is charged

with the energy stored in the inductor, the circuit will rely

on some minimum load current to get the boost circuit

running properly. This minimum load will depend on input

and output voltages, and on the arrangement of the boost

circuit. The Typical Performance Characteristics section

shows plots of the minimum load current to start and to

runasafunctionofinputvoltagefor3.3Voutputs.Inmany

cases the discharged output capacitor will present a load

to the switcher which will allow it to start. The plots show

Outputs Greater Than 6V

For outputs greater than 6V, add a resistor of 1k to 2.5k

across the inductor to damp the discontinuous ringing of

the SW node, preventing unintended SW current. The 24V

output circuit in the Typical Applications section shows

the location of this resistor.

Frequency Compensation

The LT3992 uses current mode control to regulate the

output.Thissimplifiesloopcompensation.Inparticular,the

LT3992 does not require the ESR of the output capacitor

for stability so you are free to use ceramic capacitors to

achieve low output ripple and small circuit size. Frequency

compensation is provided by the components tied to the

V pin. Generally a capacitor and a resistor in series to

C

ground determine loop gain. In addition, there is a lower

value capacitor in parallel. This capacitor is not part of

the loop compensation but is used to filter noise at the

switching frequency.

theworst-casesituationwhereV isrampingveryslowly.

IN

Use a Schottky diode for the lowest start-up voltage.

3992f

17

LT3992

applicaTions inForMaTion

Loop compensation determines the stability and transient

performance.Designingthecompensationnetworkisabit

complicatedandthebestvaluesdependontheapplication

and in particular the type of output capacitor. A practical

approach is to start with one of the circuits in this data

sheet that is similar to your application and tune the com-

pensation network to optimize the performance. Stability

should then be checked across all operating conditions,

including load current, input voltage and temperature.

Synchronization

The RT/SYNC pin can also be used to synchronize the

regulatorstoanexternalclocksource.DrivingtheRT/SYNC

resistor with a clock source triggers the synchronization

detection circuitry. Once synchronization is detected, the

rising edge of SW1 will be synchronized to the rising edge

of the RT/SYNC signal and the rising edge of SW2 syn-

chronized to the falling edge of the RT/SYNC signal (see

Figures 10 and 11). During synchronization, a 0V to 2.4V

square wave with the same frequency and duty cycle as

the synchronization signal is output via the CLKOUT pin

with a typical propagation delay of 250ns. In addition, an

internal AGC loop will adjust slope compensation to avoid

subharmonic oscillation. If the synchronization signal is

halted, thesynchronizationdetectioncircuitrywilltimeout

in typically 10µs at which time the LT3992 reverts to the

free-runningfrequencybasedontheRT/SYNCpinvoltage.

The LT1375 data sheet contains a more thorough discus-

sion of loop compensation and describes how to test the

stability using a transient load.

Figure8showsanequivalentcircuitfortheLT3992control

loop. The error amp is a transconductance amplifier with

finite output impedance. The power section, consisting of

the modulator, power switch and inductor, is modeled as

a transconductance amplifier generating an output cur-

rent proportional to the voltage at the V pin. Note that

The synchronizing clock signal input to the LT3992 must

have a frequency between 200kHz and 2MHz, a duty cycle

between 20% and 80%, a low state below 0.5V and a high

state above 1.6V. Synchronization signals outside of these

parameters will cause erratic switching behavior. If the

RT/SYNC pin is held above 1.6V at any time, switching

will be disabled.

C

the output capacitor integrates this current, and that the

capacitor on the V pin (C ) integrates the error amplifier

C

output current, resulting in two poles in the loop. In most

cases a zero is required and comes from either the output

capacitor ESR or from a resistor in series with C .

C

This simple model works well as long as the value of the

inductor is not too high and the loop crossover frequency

is much lower than the switching frequency. A phase lead

If the synchronization signal is not present during regu-

lator start-up (for example, the synchronization circuitry

is powered from the regulator output) the RT/SYNC pin

must remain below 1V until the synchronization circuitry

is active for proper start-up operation.

capacitor (C ) across the feedback divider may improve

PL

the transient response.

LT3992

CURRENT MODE

POWER STAGE

m

OUTPUT

g

= 4.8mho

C

R1

R2

ESR

PL

g

= 400µmho

m

FB

–

+

V

C

C1

3.6M

R

CERAMIC

C

ERROR

AMP

TANTALUM

OR

POLYMER

0.806V

C

F

C

3992 F08

Figure 8. Model for Loop Response

3992f

18

LT3992

applicaTions inForMaTion

t

P

Ifthesynchronizationsignalpowersupinanundetermined

state (V , V , Hi-Z), connect the synchronization clock

OL OH

SW1

SW2

to the LT3992 as shown in Figure 9. The circuit as shown

will isolate the synchronization signal when the output

voltage is below 90% of the regulated output. The LT3992

will start up with a switching frequency determined by the

resistor from the RT/SYNC pin to ground.

t /2

P

t

P

t /2

P

t

P

CLKOUT

Ifthesynchronizationsignalpowersupinalowimpedance

state (V ), connect a resistor between the RT/SYNC pin

OL

t

DCLKOSW1

t

DCLKOSW2

and the synchronizing clock. The equivalent resistance

seen from the RT/SYNC pin to ground will set the start-

up frequency.

t /2

P

t

P

RT/SYNC

3992 F10

If the synchronization signal powers up in a high imped-

ance state (Hi-Z), connect a resistor from the RT/SYNC

pin to ground. The equivalent resistance seen from the

RT/SYNC pin to ground will set the start-up frequency.

t

DRTSYNC

Figure 10. Timing Diagram RT/SYNC = 1MHz, Duty Cycle = 50%

t

P

V

OUT1

V

CC

SW1

SW2

LT3992

RT/SYNC

SYNCHRONIZATION

CIRCUITRY

PG1

CLK

t

P

3992 F09

t

P

PON

Figure 9. Synchronous Signal Powered from Regulator’s Output

CLKOUT

t

DCLKOSW1

DCLKOSW2

PON

t

P

RT/SYNC

DRTSYNCH

3992 F11

t

DRTSYNCH

Figure 11. Timing Diagram RT/SYNC = 1MHz, Duty Cycle > 50%

3992f

19

LT3992

applicaTions inForMaTion

Reducing Input Ripple Voltage

Shutdown and Undervoltage/Overvoltage Lockout

Synchronizing the switches to the rising and falling edges

ofthesynchronizationsignalprovidestheuniqueabilityto

Typically, undervoltage lockout (UVLO) is used in situa-

tions where the input supply is current limited, or has a

relatively high source resistance. A switching regulator

draws constant power from the source, so source cur-

rent increases as source voltage drops. This looks like a

negative resistance load to the source and can cause the

sourcetocurrentlimitorlatchlowunderlowsourcevoltage

conditions. UVLO prevents the regulator from operating

at source voltages where these problems might occur.

reduceinputripplecurrentsinsystemswhereV andV

IN1

IN2

are connected to the same supply. Decreasing the input

current ripple reduces the required input capacitance. For

example, the input ripple voltage shown in Figure 12 for

a typical antiphase dual 14.4V to 8.5V and 14.4V to 3.3V

regulator is decreased from a peak of 472mV to 160mV

as shown in Figure 13 by driving the LT3992 with a 71%

duty cycle synchronization signal.

An internal comparator will force both channels into shut-

down below the minimum V of 2.9V. This feature can be

IN1

used to prevent excessive discharge of battery-operated

SW1

SW2

systems.InadditiontotheV undervoltagelockout,both

IN1

channels will be disabled when SHDN1 is less than 1.32V.

Programmable UVLO may be implemented using an input

voltage divider and one of the internal comparators (see

the Typical Applications section).

INPUT

RIPPLE V

RT/SYNC

When the SHDN pin is taken above 1.32V, its respective

channel is allowed to operate. When the SHDN pin is

drivenbelow1.32V, itschannelisplacedinalowquiescent

current state. There is no hysteresis on the SHDN pins.

3992 F12

Figure 12. Dual 14.4V/8.5V, 14.4V/3.3V with 180° Phase

KeeptheconnectionsfromanyseriesresistorstotheSHDN

pins short and make sure that the interplane or surface

capacitance to switching nodes is minimized.

SW1

SW2

Soft-Start

INPUT

RIPPLE V

The output of the LT3992 regulates to the lowest voltage

presentateithertheSSpinoraninternal0.806Vreference.

A capacitor from the SS pin to ground is charged by an

internal 12µA current source resulting in a linear output

ramp from 0V to the regulated output whose duration is

given by:

RT/SYNC

3992 F13

Figure 13. Dual 14.4V/8.5V, 14.4V/3.3V with 256° Phase

C_SS• 0.806V

t_RAMP

=

12µA

At power-up, a reset signal sets the soft-start latch and

discharges both SS pins to approximately 0V to ensure

proper start-up. When both SS pins are fully discharged

the latch is reset and the internal 12µA current source

starts to charge the SS pin.

3992f

20

LT3992

applicaTions inForMaTion

When the SS pin voltage is below 110mV, the V pin is

when the threshold is exceeded. The CMPO pin is active

(sink capability is reduced in shutdown and undervoltage

C

pulled low which disables switching. This allows the SS

pin to be used as an individual shutdown for each channel.

lockout mode) as long as the V pin voltage exceeds

IN1

typically 2.9V.

As the SS pin voltage rises above 110mV, the V pin is

C

released and the output is regulated to the SS voltage.

When the SS pin voltage exceeds the internal 0.806V

reference, the output is regulated to the reference. The

SS pin voltage will continue to rise until it is clamped at

typically 2.15V.

The comparators can be used to monitor input and output

voltages as well as die temperature. See the Typical Ap-

plications circuit collection for examples.

Output Tracking/Sequencing

Complexoutputtrackingandsequencingbetweenchannels

can be implemented using the LT3992’s SS and CMPO

pins. Figure 14 shows several configurations for output

tracking/sequencing for a 3.3V and 1.8V application.

In the event of a V undervoltage lockout, the soft-start

IN1

latch is set for both channels, triggering a full start-up

sequence. If a channel’s SHDN pin is driven below 1.32V,

its overvoltage lockout is enabled, or the internal die

temperature for its power switch exceeds its maximum

rating during normal operation, the soft-start latch is set

for that channel.

Independent soft-start for each channel is shown in Fig-

ure 14a. The output ramp time for each channel is set by

thesoft-startcapacitorasdescribedinthesoft-startsection.

Inaddition,iftheloadexceedsthemaximumoutputswitch

Ratiometric tracking is achieved in Figure 14b by con-

necting both SS pins together. In this configuration, the

SS pin source current is doubled (24µA) which must be

taken into account when calculating the output rise time.

current, the output will start to drop causing the V pin

C

clamp to be activated. As long as the V pin is clamped,

C

the SS pin will be discharged. As a result, the output will

be regulated to the highest voltage that the maximum

output current can support. For example, if a 6V output is

loaded by 1Ω the SS pin will drop to 0.46V, regulating the

output at 4.6V ( 4.6A • 1Ω ). Once the overload condition

is removed, the output will soft start from the temporary

voltage level to the normal regulation point.

By connecting a feedback network from V

to the SS2

OUT1

voltage, absolute

pin with the same ratio that sets V

OUT2

tracking shown in Figure 14c is implemented. The mini-

mum value of the top feedback resistor (R1) should be set

such that the SS pin can be driven all the way to ground

with 0.9mA of sink current when V

is at its regulated

OUT1

Since the SS pin is clamped at typically 2.15V and has to

discharge to 0.806V before taking control of regulation,

momentary overload conditions will be tolerated without

a soft-start recovery. The typical time before the SS pin

takes control is:

voltage. In addition, a small V

voltage offset will be

OUT2

present due to the SS2 12µA source current. This offset

can be corrected for by slightly reducing the value of R2.

Figure 14d illustrates output sequencing. When V

is

OUT1

within 10% of its regulated voltage, CMPO1 releases the

SS2 soft-start pin allowing V to soft-start. In this case

C_SS•1.2V

0.9mA

OUT2

t_SS(CONTROL)

=

CMPO1 will be pulled up to 2V by the SS pin. If a greater

voltage is needed for CMPO1 logic, a pull-up resistor to

Open-Collector Comparators

V

can be used. This will decrease the soft-start ramp

OUT1

time and increase tolerance to momentary shorts.

The CMPO pin is the open-collector output of an internal

comparator. The comparator compares the CMPI pin volt-

age to 90% of the reference voltage (0.72V) with 80mV

of hysteresis.

If precise output ramp up and down is required, drive the

SS pins as shown in Figure 14e. The minimum value of

resistor (R3) should be set such that the SS pin can be

driven all the way to ground with 0.9mA of sink current

during power-up and fault conditions.

The CMPO pin has a typical sink capability of 250µA when

theCMPIpinisbelowthethresholdandcanwithstand60V

3992f

21

LT3992

applicaTions inForMaTion

Independent Start-Up

Ratiometric Start-Up

Absolute Start-Up

V

OUT1

0.5V/DIV

V

OUT1

0.5V/DIV

PG1

PG2

PG1

PG2

PG1

V

OUT2

0.5V/DIV

PG2

5ms/DIV

10ms/DIV

LT3992

V

OUT1

V

OUT1

V

OUT1

R1 R3

R2

R1 R3

FB1

CMPI1

FB1

CMPI1

FB1

CMPI1

R2

2.5V

CMPO1

12µA

SS1

12µA

SS1

12µA

SS1

PG1

0.72V

+

–

0.72V

+

–

0.72V

+

–

0.1µF

R4 R6

0.1µF

V

OUT2

R4 R6

R5

R4 R6

R5

FB2

CMPI2

R5

2.5V

CMPO2

PG2

12µA

SS2

12µA

SS2

12µA

SS2

0.72V

+

–

0.72V

+

–

0.72V

+

–

R8

0.22µF

R7

(14a)

(14b)

(14c)

Output Sequencing

Controlled Power Up and Down

V

OUT1

V

OUT1

0.5V/DIV

PG1/PG2

V

OUT2

V

OUT2

0.5V/DIV

PG1

PG2

SS1/2

10ms/DIV

LT3992

V

OUT1

V

OUT1

R1

R2

R1 R3

FB1

CMPI1

FB1

CMPI1

R2

2.5V

CMPO1

12µA

SS1

12µA

SS1

PG1

0.72V

+

–

0.72V

+

–

R5

+

0.1µF

–

V

OUT2

V

OUT2

R4 R6

R5

R4 R6

R5

FB2

CMPI2

FB2

CMPI2

2.5V

CMPO2

PG2

12µA

SS2

12µA

SS2

0.72V

+

–

0.72V

+

–

3992 F14

0.22µF

(14d)

(14e)

Figure 14. SS Pin Configurations

3992f

22

LT3992

applicaTions inForMaTion

Application Optimization

For example, assume a maximum input of 60V:

V = 60V, V

= 3.3V at 1.5A and V

= 12V at 1.5A.

In multiple channel applications requiring large V to

OUT

IN

OUT1

OUT2

IN

V

ratios, the maximum frequency and resulting in-

V_OUT+ V_D

1

Frequency (Hz) =

•

ductor size is determined by the channel with the largest

ratio. The LT3992’s multi-frequency operation allows the

user to minimize component size for each channel while

maintaining constant frequency operation. The circuit in

Figure 15 illustrates this approach. A 2-stage step-down

approach coupled with multi-frequency operation will

further reduce external component size by allowing an

V – V + V_Dt_ON(MIN)

IN

SW

V – V

IN

• V

OUT

(

)

OUT

L =

V • f

IN

Single Step-Down:

3.3+ 0.6

60V – 0.4+ 0.6 180ns

1

increase in frequency for the channel with the lower V

IN

Frequency (Hz) =

•

≅ 350kHz

to V

ratio. The drawback to this approach is that the

OUT

outputpowercapabilityforthefirststageisdeterminedby

the output power drawn from the second stage. The dual

step-down application in Figure 16 steps down the input

60V – 3.3 • 3.3

60V • 350kHz

(

)

L1=

L2 =

≥ 9µH

60V – 12 •12

60V • 350kHz

(

)

voltage (V ) to the highest output voltage then uses that

IN1

≥ 27µH

voltage to power the second output (V ). V

must be

IN2

OUT1

able to provide enough current for its output plus V

OUT2

2-Stage Step-Down:

maximumload. NotethattheV

voltagemustbeabove

OUT1

12+ 0.6

60V – 0.4+ 0.6 180ns

1

V

IN2

’s minimum input voltage as specified in the Electrical

Frequency (Hz) =

•

≅ 1MHz

Characteristics (typically 2.9V) when the second channel

starts to switch. Delaying channel 2 can be accomplished

by either independent soft-start capacitors or sequencing

with the CMP01 output.

60V – 12 •12

60V •1MHz

(

)

L1=

L2 =

≥ 10µH

12 – 3.3 • 3.3

12 •1MHz

(

)

≥ 2.4µH

2-Stage Step-Down Multi-Frequency:

= 61.9k, FREQ1 = 900kHz, FREQ2 = 1800kHz.

R

DIV

60V – 12 •12

60V • 900kHz

(

)

L1=

≥ 11µH

12 – 3.3 • 3.3

12 •1800kHz

(

)

L2 =

≥ 1.3µH

In addition, R

= 52.3k reduces the peak current limit

ILIM2

on Channel 2 to 2.5A, which reduces inductor size and

catch diode requirements.

3992f

23

LT3992

applicaTions inForMaTion

V

IN1

15V TO 60V

4.7µF

V

IN2

IN1

SHDN1

SHDN2

BST1

SW1

BST2

SW2

V

OUT1

22µH

0.47µF

0.22µF

IND1

IND2

V

OUT2

12V

OUT1

3.3V

LT3992

V

OUT1

V

OUT2

FB2

1.5A

400kHz

1.5A

100µF

×2

24.9k

113k

FB1

200kHz

PG1

47µF

8.06k

100k

CMPI1

CMPI2

CMPO1

CMPO2

PG2

SS1

SS2

ILIM1

ILIM2

I

LIM1

V

C2

C1

CLKOUT

400kHz

0.1µF

RT/SYNC CLKOUT

DIV

33pF

0.1µF

680pF

15k

1000pF

13k

T

J

GND

33pF

10nF

60.4k

10k

61.9k

3992 F15

Figure 15. 12V and 3.3V Dual Step-Down Multi-Frequency Converter

V

IN1

15V TO 60V

4.7µF

V

OUT2

V

IN2

IN1

SHDN1

SHDN2

BST1

SW1

BST2

SW2

22µH

2.2µH

0.1µF

10µF

0.1µF

8.06k

IND1

IND2

V

OUT2

OUT1

12V

LT3992

3.3V

V

OUT1

V

OUT2

FB2

2A

1600kHz

1A

113k

24.9k

FB1

400kHz

47µF

8.06k

100k

CMPI1

CMPI2

FB1

CMPO1

CMPO2

PG

SS1

SS2

ILIM1

ILIM2

ILIM1

V

C2

C1

CLKOUT

1600kHz

RT/SYNC CLKOUT

DIV

33pF

0.1µF

60.4k

680pF

470pF

0.1µF

T

J

GND

10nF

15k

48.7k

102k

16k

3992 F16

Figure 16. 12V and 3.3V 2-Stage Multi-Frequency Step-Down Converter

3992f

24

LT3992

applicaTions inForMaTion

Shorted and Reverse Input Protection

PCB Layout

If the inductor is chosen so that it won’t saturate exces-

sively,anLT3992step-downregulatorwilltolerateashorted

output. There is another situation to consider in systems

where the output will be held high when the input to the

LT3992 is absent. This may occur in battery charging

applicationsorinbatteryback-upsystemswhereabattery

or some other supply is diode OR-ed with the LT3992’s

For proper operation and minimum EMI, care must be

taken during printed circuit board (PCB) layout. Figure 18

shows the high di/dt paths in the buck regulator circuit.

Notethatlargeswitchedcurrentsflowinthepowerswitch,

the catch diode and the input capacitor. The loop formed

by these components should be as small as possible.

These components, along with the inductor and output

capacitor, should be placed on the same side of the cir-

cuit board and their connections should be made on that

layer. Place a local, unbroken ground plane below these

components, and tie this ground plane to system ground

at one location, ideally at the ground terminal of the out-

put capacitor C2. Route all small signal analog returns

to the ground connection at the bottom of the package.

Additionally, the SW and BST traces should be kept as

short as possible.

output. If the V

pin is allowed to float and the SHDN

IN1/2

pin is held high (either by a logic signal or because it is

tied to V ), then the LT3992’s internal circuitry will pull its

IN

quiescent current through its SW pin. This is fine if your

system can tolerate a few mA in this state. If you ground

the SHDN pin, the SW pin current will drop to essentially

zero. However, if the V pin is grounded while the output

IN

is held high, then parasitic diodes inside the LT3992 can

pull large currents from the output through the SW pin

and the V

pin. Figure 17 shows a circuit that will run

IN1/2

only when the input voltage is present and that protects

LT3992

GND

V

IN

SW

against a shorted or reversed input.

PARASITIC DIODE

D4

V

SW

IN

V

IN1/2

OUT1/2

(18a)

LT3992

GND

V

SW

IN

3992 F17

Figure 17. Diode D4 Prevents a Shorted Input from Discharging a

Backup Battery Tied to the Output

(18b)

LT3992

V

SW

IN

GND

3992 F18

(18c)

Figure 18. Subtracting the Current When the Switch Is On (18a)

from the Current When the Switch Is Off (18b) Reveals the Path of

the High Frequency Switching Current (18c). Keep this Loop Small.

The Voltage on the SW and BST Traces Will Also Be Switched; Keep

These Traces As Short As Possible. Finally, Make Sure the Circuit

Is Shielded with a Local Ground Plane

3992f

25

LT3992

applicaTions inForMaTion

Thermal Considerations

The LT3992’s powerful 4.6A switches allow the converter

to source large output currents. Depending on the con-

verter’s operating conditions, the resulting internal power

dissipation can raise the junction temperature beyond

its maximum rating. Operating conditions include input

voltages, output voltages, switching frequencies, output

currents, and the ambient environmental temperature,

etc. An estimation of the junction temperature rise above

ambient temperature helps determine whether a given

design may exceed the maximum junction ratings for

specific operating conditions. However, temperature rise

depends on PCB design and the proximity to other heat

sources. The final converter design must be evaluated

on the bench.

ThePCBmustalsoprovideheatsinkingtokeeptheLT3992

cool. The exposed metal on the bottom of the package

must be soldered to a ground plane. This ground should

be tied to other copper layers below with thermal vias;

these layers will spread the heat dissipated by the LT3992.

Place additional vias near the catch diodes. Adding more

copper to the top and bottom layers and tying this copper

to the internal planes with vias can further reduce thermal

resistance. The topside metal and component outlines

in Figure 19 illustrate proper component placement and

trace routing.

3992 F19

Figure 19. PCB Top Layer and Component Placement for TSSOP and QFN Packages

3992f

26

LT3992

applicaTions inForMaTion

An estimation of the junction temperature rise begins by

determining which circuit components dissipate power.

In order to simplify the power loss estimation, only the

inductors,catchdiodes,andtheLT3992willbeconsidered

as heat sources. After the operating conditions have been

determined, the individual power losses are calculated by:

Forexample,thetypicalapplicationcircuitslistedinTable4

are used to calculate the individual power loss contribu-

tions in Table 5. Table 6 shows the estimated power loss

andjunctiontemperatureriseaboveambienttemperature.

Note that the larger TSSOP package demonstrates better

thermal performance than the compact QFN package on

the LT3992 demo circuit boards. For LT3992 applications

that favor thermal performance, the TSSOP package is

the preferred package option.







V_OUT

V_{IN }

Power_D1,2= 1−

•I

• V_FD



OUT



2

Power_IND1,2= R_IND•I_OUT

Table 4

V_OUT

Power_CH1,2= 0.1•

V_IN

2

•I_OUT+ 2• 10^–3

V

f

V

I

V I

OUT2 OUT2

IN1

IN2

SW

OUT1 OUT1

APPLICATION (V) (V)

CH1 CH2

(V)

12

5

(A)

1.5

2

(V)

(A)

Front Page

Back Page

48

12

48

400 1600

5

2

I_OUT• V_OUT• V_BOOST

40• V_IN

300

3

2

•V_IN+

+

Table 5

V





I_OUT

IN

V_IN•I_OUT• f_SW• 10⁻⁶•

+

PD1

PD2

PL1

(W)

PL2

PCH1

(W)

PCH2

(W)





2.5 0.25





APPLICATION

Front Page

Back Page

(W)

0.54

0.88

(W)

0.56

0.92

(W)

0.28

0.2

0.23

0.28

0.99

0.95

0.79

0.91

where:

f

= Switching Frequency in kHz

SW

Table 6

R

= Inductor Resis tance

P

(W)

T

TSSOP (°C)

T

QFN (°C)

MEAS

53.3

IND

LOSS

RISE

APPLICATION

Front Page

Back Page

CALC

MEAS

3.2

CALC

48.3

56.4

MEAS

46.1

CALC

56.8

64.3

V

FD

= Catch Diode Forward Voltage Drop

3.38

4.14

V

= Switch Boost Voltage

BOOST

4.2

53.0

62.9

For the LT3992 demo board using the TSSOP package,

the estimated junction temperature rise above ambient

temperature is found by:

The power loss and temperature rise equations provided

in the Thermal Considerations section serve as a good

starting point for estimating the junction temperature

rise. However, the LT3992 is a very versatile converter.

The combination of independent input voltages, output

voltages, output currents, switching frequencies, and

package selections for the LT3992 dictate that no power

loss estimation scheme can accommodate every possible

operating condition. As such, it is absolutely necessary to

evaluate a converter’s performance at the bench.

T

≈ 10 • (Power + Power ) +

D1

D2

RISETSSOP

12.3 • (Power

+ Power

) + 17.5 •

IND2

IND1

Power

+ Power

CH2

(

)

CH1

The estimated junction temperature rise above ambient

for the LT3992 QFN layout is:

T_RISEQFN≈ 8.5• (Power_D1+ Power_D2)+

13• (Power_IND1+ Power_IND2)+ 23•

Power_CH1+ Power_CH2

Thepowerdissipationintheotherpowercomponentssuch

as boost diodes, input and output capacitors, inductor

core loss, and trace resistances cause additional copper

heating and can further increase what the IC sees as am-

bient temperature. See the LT1767 data sheet’s Thermal

Considerations section.

(

)

3992f

27

LT3992

applicaTions inForMaTion

Die Temperature and Thermal Shutdown

Generating a Negative Regulated Voltage

The LT3992 T pin outputs a voltage proportional to the

The simple charge pump circuit in Figure 21 uses the

CLKOUT pin output to generate a negative voltage, elimi-

nating the need for an external regulated supply. Surface

mount capacitors and dual-package Schottky diodes

minimize the board area needed to implement the nega-

tive voltage supply.

J

internal junction temperature. The T pin typically outputs

J

250mV for 25°C and has a slope of 10mV/°C. Without the

aidofexternalcircuitry,theT pinoutputisvalidfrom20°C

J

to150°C(200mVto1.5V)withamaximumloadof100µA.

Full Temperature Range Measurement

30k

To extend the operating temperature range of the T out-

J

T

J

put below 20°C, connect a resistor from the T pin to a

J

LT3992

CLKOUT

GND

330pF

D4

negative supply as shown in Figure 20. The negative rail

voltage and T pin resistor may be calculated using the

J

0.1µF

D3

following equations:

3992 F21

D3, D4: ZETEX BAT54S

2 • TEMP(MIN)°C

V_NEG

≤

Figure 21. Circuit to Generate the Negative Voltage Rail to

Extend the T_JPin Operating Range

100

| V_NEG

33µA

|

R1 ≤

As a safeguard, the LT3992 has an additional thermal

shutdownthresholdsetatatypicalvalueof163°Cforeach

channel. Each time the threshold is exceeded, a power on

sequence for that channel will be initiated. The sequence

will then repeat until the thermal overload is removed.

where:

TEMP(MIN)°C is the minimum temperature where a

valid T pin output is required.

J

V

NEG

= Regulated negative voltage supply.

It should be noted that the T pin voltage represents

J

For example:

a steady-state temperature and should not be used to

guarantee that maximum junction temperatures are

not exceeded. Instantaneous power along with thermal

gradients and time constants may cause portions of the

die to exceed maximum ratings and thermal shutdown

thresholds. Be sure to calculate die temperature rise for

steady state (>1Min) as well as impulse conditions.

TEMP(MIN)°C = –40°C

V

NEG

V

NEG

≤ –0.8V

= –1, R1 ≤ |V |/33µA = 30.2kΩ

NEG

LT3992

R1

T

J

V

NEG

GND

+

3992 F20

Figure 20. Circuit to Extend the T_JPin Operating Range

3992f

28

LT3992

applicaTions inForMaTion

CLKOUT Capacitive Loading

A minor drawback to generating a negative rail from the

CLKOUT pin is that the charge pump adds capacitance to

the CLKOUT pin, resulting in an output synchronization

clock signal phase delay. Figures 22 and 23 show the im-

pact of capacitive loading on the CLKOUT signal rise and

fall times. Note that a typical 10:1 150MHz oscilloscope

probe contributes significant capacitance to the CLKOUT

node, necessitating a low capacitance probe for accurate

measurements.ApplicationsrequiringCLKOUTtogenerate

the negative supply voltage and provide the synchroniza-

tion clock to other regulators may benefit from buffering

CLKOUT prior to the charge pump circuitry.

CHARGE PUMP

SCOPE PROBE: 15pF

SYNCHRONIZED LT3992

RT/SYNC PIN

FET PROBE: 2pF

500mV/DIV

3992 F22

40ns/DIV

FREQUENCY: 1.000MHz

Figure 22. CLKOUT Rise Time

Other Linear Technology Publications

SCOPE PROBE: 15pF

Application Notes 19, 35 and 44 contain more detailed

descriptions and design information for buck regulators

and other switching regulators. The LT1376 data sheet

has a more extensive discussion of output ripple, loop

compensation and stability testing. Design Note DN100

shows how to generate a dual (+ and –) output supply

using a buck regulator.

CHARGE PUMP

SYNCHRONIZED

LT3992 RT/SYNC PIN

500mV/DIV

FET PROBE: 2pF

3992 F23

20ns/DIV

FREQUENCY: 1.000MHz

Figure 23. CLKOUT Fall Time

3992f

29

LT3992

Typical applicaTions

3992f

30

LT3992

Typical applicaTions

24V and 5V 2-Stage Dual Step-Down Converter

V

IN1

25V TO 60V

4.7µF

V

OUT2

V

IN2

IN1

SHDN1

BST1

SHDN2

BST2

SW1

SW2

22µH

2k

4.7µH

FB1

0.1µF

8.06k

IND1

IND2

V

OUT2

OUT1

24V

LT3992

5V

V

OUT1

V

OUT2

FB2

2A

1MHz

0.5A

10µF

232k

42.2k

FB1

1MHz

47µF

8.06k

100k

CMPI1

CMPI2

CMPO1

CMPO2

PG

SS1

SS2

ILIM1

ILIM2

V

C2

C1

CLKOUT

1MHz

0.1µF

33pF

0.1µF

RT/SYNC CLKOUT

DIV

470pF

28k

680pF

10k

T

J

GND

10nF

42.2k

28k

100k

3992 TA03

3.3V/5A Single Output with UVLO and Power Good

V

IN

5V TO 18V

60V TRANSIENT

4.7µF

×2

374k

V

IN2

IN1

130k

SHDN1

SHDN2

0.22µF

CMPI2

BST1

SW1

CMPO2

4.7µH

ILIM1

ILIM2

SS1

IND1

V

3.3V

5A

OUT

LT3992

V

OUT1

OUT2

47µF

×2

V

2MHz EFFECTIVE RIPPLE

SS2

BST2

SW2

IND2

0.22µF

V

C1

820pF

V

C2

24.9k

CLKOUT

1MHz

CLKOUT

RT/SYNC

FB1

33pF

CMPI1

8.06k

100k

T

J

FB2

0.1µF

PG

DIV

CMPO1

10nF

60.4k

20k

28k

GND

3992 TA04

3992f

31

LT3992

Typical applicaTions

Power Supply Dual Input Single 3.3V/4A Output Step-Down Converter

V

IN1

IN2

12V

5V

4.7µF

13k

1µF

47.5k

V

IN2

IN1

SHDN1

SHDN2

SHDN1

CMPI2

BST1

SW1

0.22µF

CMPO2

2.2µH

SS1

IND1

V

3.3V

4A

LT3992

OUT

V

SS2

OUT1

OUT2

V

LIM1

LIM2

47µF

BST2

SW2

IND2

0.22µF

24.9k

V

C1

2.2µH

680pF

V

C2

CLKOUT

2MHz

CLKOUT

RT/SYNC

FB1

0.1µF

33pF

CMPI1

8.06k

64.9k

61.9k

DIV

FB2

T

J

CMPO1

61.9k

42.2k

GND

21k

10nF

3992 TA05

5V and 1.8V Dual 2-Stage Converter

1µF

V

IN1

7V TO 60V

4.7µF

V

IN2

IN1

SHDN1

BST1

SHDN2

BST2

SW1

SW2

15µH

2.2µH

0.22µF

IND1

IND2

V

OUT2

OUT1

LT3992

1.8V

5V

1A

V

OUT1

OUT2

FB2

1A

1600kHz

22µF

42.2k

47µF

10k

100pF

8.06k

FB1

400kHz

FB1

CMPI1

CMPI2

100k

8.06k

PG

CMPO1

SS1

CMPO2

SS2

ILIM1

ILIM2

ILIM1

V

C2

C1

CLOCKOUT

1600kHz

RT/SYNC CLKOUT

DIV

820pF

33pF

T

J

0.1µF

33pF

GND

470pF

21k

0.1µF

21k

13k

48.7k 102k

10nF

3992 TA06

3992f

32

LT3992

Typical applicaTions

3992f

33

LT3992

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

FE Package

38-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1772 Rev C)

Exposed Pad Variation AA

4.75 REF

9.60 – 9.80*

(.378 – .386)

4.75

(.187)

REF

38

20

6.60 0.10

4.50 REF

2.74 REF

SEE NOTE 4

6.40

REF (.252)

BSC

2.74

(.108)

0.315 0.05

1.05 0.10

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

1

19

1.20

(.047)

MAX

4.30 – 4.50*

(.169 – .177)

0.25

REF

0° – 8°

0.50

(.0196)

BSC

0.09 – 0.20

(.0035 – .0079)

0.50 – 0.75

(.020 – .030)

0.05 – 0.15

(.002 – .006)

0.17 – 0.27

FE38 (AA) TSSOP REV C 0910

(.0067 – .0106)

TYP

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

2. DIMENSIONS ARE IN

FOR EXPOSED PAD ATTACHMENT

MILLIMETERS

(INCHES)

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

3. DRAWING NOT TO SCALE

3992f

34

LT3992

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UH Package

32-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1693 Rev D)

0.70 0.05

5.50 0.05

4.10 0.05

3.45 0.05

3.50 REF

(4 SIDES)

3.45 0.05

PACKAGE OUTLINE

0.25 0.05

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

BOTTOM VIEW—EXPOSED PAD

PIN 1 NOTCH R = 0.30 TYP

OR 0.35 × 45° CHAMFER

R = 0.05

TYP

0.00 – 0.05

R = 0.115

TYP

0.75 0.05

5.00 0.10

(4 SIDES)

31 32

0.40 0.10

PIN 1

TOP MARK

(NOTE 6)

1

2

3.45 0.10

3.50 REF

(4-SIDES)

3.45 0.10

(UH32) QFN 0406 REV D

0.200 REF

0.25 0.05

0.50 BSC

NOTE:

1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE

M0-220 VARIATION WHHD-(X) (TO BE APPROVED)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3992f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

35

LT3992

Typical applicaTion

FMEA Fault Tolerant 5V/2A and 3.3V/2A Dual Converter

V

IN1

6V TO 60V

4.7µF

100k

10µH

V

IN2

IN1

SHDN2

SHDN1

SHDN2

BST1

SW1

BST2

SW2

15µH

0.47µF

100µF

0.47µF

806Ω

IND1

IND2

LT3992

V

3.3V

2A

OUT1

5V

OUT2

V

OUT1

FB1

OUT2

2A

FB2

4.22k

2.49k

100µF

300kHz

806Ω

100k

249k

PG2

CMPI1

CMPI2

CMPO1

SS1

CMPO2

SS2

PG

SS2

ILIM2

ILIM1

ILIM2

V

C2

C1

CLKOUT

300kHz

RT/SYNC CLKOUT

DIV

33pF

100nF

1000pF

11.8k

1000pF

T

J

10nF

GND

10nF

7.15k

12.1k

60.4k

3992 TA08

relaTeD parTs

PART NUMBER DESCRIPTION

COMMENTS

= 3V to 36V, V

LT3692/

LT3692A

36V, Dual 3.5A, 2.25MHz High Efficiency Step-Down

DC/DC Converter

V

= 0.8V, I = 4mA, I < 10µA,

OUT(MIN) Q SD

IN

5mm × 5mm QFN-32, TSSOP-38E

LT3507/

LT3507A

36V, Triple 2.4A, 1.4A and 1.4A (I ), 2.5MHz, High

V

= 4V to 36V, V

= 0.8V, I = 7mA, I = 1µA,

OUT(MIN) Q SD

OUT

IN

Efficiency Step-Down DC/DC Converter with LDO Controller

5mm × 7mm QFN-38

LT3508

LT3680

LT3693

LT3480

LT3980

LT3971

LT3991

36V with Transient Protection to 40V, Dual 1.4A (I ), 3MHz,

V

= 3.7V to 37V, V

= 0.8V, I = 4.6mA, I = 1µA,

OUT(MIN) Q SD

OUT

IN

High Efficiency Step-Down DC/DC Converter

4mm × 4mm QFN-24, TSSOP-16E

36V, 3A, 2.4MHz High Efficiency Micropower Step-Down

DC/DC Converter

V

IN

= 3.6V to 36V, V = 0.8V, I = 75µA, I < 1µA,

OUT(MIN)

Q

SD

3mm × 3mm DFN-10, MSOP-10E

36V, 3A, 2.4MHz High Efficiency Step-Down DC/DC Converter

V

= 3.6V to 36V, V

= 0.8V, I = 1.3mA, I < 1µA,

IN

OUT(MIN)

Q

SD

3mm × 3mm DFN-10, MSOP-10E

36V with Transient Protection to 60V, 2A (I ), 2.4MHz, High

V

= 3.6V to 38V, Transients to 60V, V

= 0.78V,

OUT

IN

OUT(MIN)

Efficiency Step-Down DC/DC Converter with Burst Mode^®Operation I = 70µA, I < 1µA, 3mm × 3mm DFN-10, MSOP-10E

Q

SD

58V with Transient Protection to 80V, 2A (I ), 2.4MHz, High

V

IN

= 3.6V to 58V, Transients to 80V, V

= 0.79V,

OUT

OUT(MIN)

Efficiency Step-Down DC/DC Converter with Burst Mode Operation

I = 75µA, I < 1µA, 3mm × 4mm DFN-16, MSOP-16E

Q

SD

38V, 1.2A (I ), 2MHz, High Efficiency Step-Down

V

= 4.2V to 38V, V

= 1.2V, I = 2.8µA, I < 1µA,

OUT(MIN) Q SD

OUT

IN

DC/DC Converter with Only 2.8µA of Quiescent Current

3mm × 3mm DFN-10, MSOP-10E

55V, 1.2A (I ), 2MHz, High Efficiency Step-Down

V

= 4.2V to 55V, V

= 1.2V, I = 2.8µA, I < 1µA,

OUT(MIN) Q SD

OUT

IN

DC/DC Converter with Only 2.8µA of Quiescent Current

3mm × 3mm DFN-10, MSOP-10E

3992f

LT 0312 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

36

●

 LINEAR TECHNOLOGY CORPORATION 2012

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT3971EMSE#TRPBF
厂家：	Linear
描述：	LT3971 - 38V, 1.2A, 2MHz Step-Down Regulator with 2.8µA Quiescent Current; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C
文件：	总36页 (文件大小：517K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT3971EMSE#TRPBF [Linear]

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