LT3990IDDB#TRPBF [Linear]
IC 0.865 A SWITCHING REGULATOR, 2640 kHz SWITCHING FREQ-MAX, PDSO10, 3 X 2 MM, LEAD FREE, PLASTIC, MO-229WECD-1, DFN-10, Switching Regulator or Controller;
| 型号： | LT3990IDDB#TRPBF |
| 厂家： | 
Linear |
| 描述： | IC 0.865 A SWITCHING REGULATOR, 2640 kHz SWITCHING FREQ-MAX, PDSO10, 3 X 2 MM, LEAD FREE, PLASTIC, MO-229WECD-1, DFN-10, Switching Regulator or Controller 稳压器 开关 |
| 文件： | 总28页 (文件大小：417K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3976
40V, 5A, 2MHz Step-Down
Switching Regulator with
3.3µA Quiescent Current
FeaTures
DescripTion
n
Ultralow Quiescent Current:
3.3µA I at 12V to 3.3V
OUT
The LT®3976 is an adjustable frequency monolithic buck
switchingregulatorthatacceptsawideinputvoltagerange
up to 40V. Low quiescent current design consumes only
3.3µAofsupplycurrentwhileregulatingwithnoload. Low
ripple Burst Mode operation maintains high efficiency at
low output currents while keeping the output ripple below
15mV in a typical application. The LT3976 can supply up
to 5A of load current and has current limit foldback to
limitpowerdissipationduringshort-circuit. Alowdropout
voltage of 500mV is maintained when the input voltage
drops below the programmed output voltage, such as
during automotive cold crank.
Q
IN
Low Ripple Burst Mode® Operation
n
Output Ripple < 15mV
P-P
n
n
n
n
n
n
n
n
n
n
n
n
n
Wide Input Range: Operation from 4.3V to 40V
5A Maximum Output Current
Excellent Start-Up and Dropout Performance
Adjustable Switching Frequency: 200kHz to 2MHz
Synchronizable Between 250kHz to 2MHz
Accurate Programmable Undervoltage Lockout
Low Shutdown Current: I = 700nA
Q
Power Good Flag
Soft-Start Capability
Thermal Shutdown Protection
An internally compensated current mode topology is used
for fast transient response and good loop stability. A high
efficiency 75mΩ switch is included on the die along with a
boost Schottky diode. An accurate 1.02V threshold enable
pin can be driven directly from a microcontroller or used
as a programmable undervoltage lockout. A capacitor on
theSSpinprovidesacontrolledinrushcurrent(soft-start).
Current Limit Foldback with Soft-Start Override
Saturating Switch Design: 75mΩ On-Resistance
Small, Thermally Enhanced 16-Lead MSOP and
24-Lead 3mm × 5mm QFN Packages
applicaTions
A power good flag signals when V
reaches 91.6% of
OUT
n
Automotive Battery Regulation
the programmed output voltage. The LT3976 is available
in small 16-lead MSOP and 24-lead 3mm × 5mm QFN
packages with exposed pad for low thermal resistance.
n
Portable Products
n
Industrial Supplies
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
No-Load Supply Current
3.3V Step-Down Converter
8
IN REGULATION
V
IN
4.3V TO 40V
V
OUT
= 3.3V
7
6
5
4
3
2
1
0
V
IN
OFF ON
EN
PG
BOOST
SW
3.3µH
0.47µF
10µF
2Ω
470pF
PDS540
LT3976
SS
RT
OUT
FB
V
3.3V
5A
1M
OUT
10pF
SYNC
GND
10nF
47µF
1210
×2
20 25
130k
576k
0
5
10 15
30 35 40
INPUT VOLTAGE (V)
3976 TA01a
f = 400kHz
3976 G05
3976f
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For more information www.linear.com/3976
LT3976
absoluTe MaxiMuM raTings
(Note 1)
V , EN Voltage (Note 3) ...........................................40V
Operating Junction Temperature Range (Note 2)
IN
BOOST Pin Voltage ...................................................55V
BOOST Pin Above SW Pin.........................................30V
FB, RT, SYNC, SS Voltage ...........................................6V
PG Voltage ................................................................30V
OUT Voltage..............................................................16V
LT3976E............................................. –40°C to 125°C
LT3976I ............................................. –40°C to 125°C
LT3976H............................................ –40°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)...................300°C
pin conFiguraTion
TOP VIEW
24 23 22 21
1
2
3
4
5
6
7
8
SS
OUT
NC
20 SYNC
TOP VIEW
PG
RT
19
18
1
2
3
4
5
6
7
8
SYNC
PG
FB
SS
16
15
14
13
12
11
10
9
OUT
BOOST
SW
RT
BST
NC
17 NC
EN
17
GND
EN
25
GND
V
IN
IN
IN
16
SW
V
V
SW
SW
SW
SW
15 VIN
14 VIN
NC
NC
MSE PACKAGE
16-LEAD PLASTIC MSOP
VIN
13
θ
= 40°C/W
9
10 11 12
JA
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
UDD PACKAGE
24-LEAD (3mm × 5mm) PLASTIC QFN
= 46°C/W
θ
JA
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
LT3976EMSE#PBF
LT3976IMSE#PBF
LT3976HMSE#PBF
LT3976EUDD#PBF
LT3976IUDD#PBF
TAPE AND REEL
PART MARKING*
3976
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3976EMSE#TRPBF
LT3976IMSE#TRPBF
LT3976HMSE#TRPBF
LT3976EUDD#TRPBF
LT3976IUDD#TRPBF
16-Lead Plastic MSOP
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–40°C to 125°C
–40°C to 125°C
3976
16-Lead Plastic MSOP
3976
16-Lead Plastic MSOP
LGHV
24-Lead (3mm × 5mm) Plastic QFN
24-Lead (3mm × 5mm) Plastic QFN
LGHV
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping
container.Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3976f
2
For more information www.linear.com/3976
LT3976
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
4
MAX
4.3
UNITS
V
l
Minimum Input Voltage
(Note 3)
Dropout Comparator Threshold
Dropout Comparator Threshold Hysteresis
(V – OUT) Falling
IN
430
500
25
570
mV
mV
Quiescent Current from V
V
V
V
Low
0.7
1.6
1.3
2.7
30
µA
µA
µA
IN
EN
EN
EN
High, V
High, V
Low
Low
SYNC
SYNC
l
l
FB Pin Current
V
= 1.5V
0.1
12
nA
FB
Feedback Voltage
1.183
1.173
1.197
1.197
1.212
1.222
V
V
l
FB Voltage Line Regulation
Switching Frequency
4.3V < V < 40V (Note 3)
0.0003
0.01
%/V
IN
R = 11.8k
1.8
0.8
160
2.25
1
200
2.7
1.2
240
MHz
MHz
kHz
T
R = 41.2k
T
R = 294k
T
Minimum Switch On-Time
Minimum Switch Off-Time (Note 4)
Switch Current Limit
120
150
10
ns
ns
A
200
V
V
= 1V
= 0V
= 1A
7.5
12.5
FB
FB
Foldback Switch Current Limit
4.8
A
Switch V
I
80
mV
μA
mV
μA
V
CESAT
SW
Switch Leakage Current
Boost Schottky Forward Voltage
Boost Schottky Reverse Leakage
Minimum Boost Voltage (Note 5)
BOOST Pin Current
0.02
730
0.02
1.3
1
I
= 100mA
SH
V
= 12V
2
REVERSE
l
l
1.8
32
I
= 1A, V
– V = 3V
20
mA
V
SW
BOOST
SW
EN Voltage Threshold
EN Falling, V ≥ 4.3V
0.92
5
1.02
60
1.12
IN
EN Voltage Hysteresis
mV
nA
%
EN Pin Current
0.2
20
13
PG Threshold Offset from V
V
Falling
8.4
FB
FB
PG Hysteresis as % of Output Voltage
PG Leakage
1.7
%
V
V
= 3V
0.02
480
1.0
1
µA
μA
V
PG
PG
l
PG Sink Current
= 0.4V
125
0.6
SYNC Low Threshold
SYNC High Threshold
SYNC Pin Current
1.18
0.1
1.5
2.6
V
V
V
= 6V
nA
μA
SYNC
SS Source Current
= 0.5V
0.9
1.8
SS
temperature range. The LT3976H is guaranteed over the full –40°C to
150°C operating junction temperature range. High junction temperatures
degrade operating lifetimes. Operating lifetime is derated at junction
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
temperatures greater than 125°C. The junction temperature (T , in °C) is
J
calculated from the ambient temperature (T , in °C) and power dissipation
A
Note 2: The LT3976E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization, and correlation with statistical process controls. The
LT3976I is guaranteed over the full –40°C to 125°C operating junction
(P , in Watts) according to the formula:
D
T = T + (P • θ )
JA
J
A
D
where θ (in °C/W) is the package thermal impedance.
JA
3976f
3
For more information www.linear.com/3976
LT3976
elecTrical characTerisTics
Note 3: Minimum input voltage depends on application circuit.
Note 6: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed the maximum operating junction temperature
when overtemperature protection is active. Continuous operation above
the specified maximum operating junction temperature may impair device
reliability or permanently damage the device.
Note 4: The LT3976 contains circuitry that extends the maximum duty
cycle if there is sufficient voltage across the boost capacitor. See the
Application Information section for more details.
Note 5: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the switch.
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted.
Efficiency at 5VOUT
Efficiency at 3.3VOUT
Efficiency at 5VOUT
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
100
90
80
70
60
50
40
30
20
10
0
f
= 800kHz
= 5V
FRONT PAGE APPLICATION
f
= 800kHz
= 5V
SW
OUT
SW
OUT
V
V
= 3.3V
V
OUT
12V
24V
36V
12V
24V
36V
12V
24V
36V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0.01
0.1
10
100 1000 10000
1
LOAD CURRENT (A)
LOAD CURRENT (mA)
LOAD CURRENT (A)
3976 G01
3976 G02
3976 G03
Efficiency at 3.3VOUT
No-Load Supply Current
No-Load Supply Current
10000
1000
100
10
8
7
6
5
4
3
2
1
0
100
90
80
70
60
50
40
30
20
10
0
FRONT PAGE APPLICATION
IN REGULATION
FRONT PAGE APPLICATION
V
V
= 12V
V
= 3.3V
V
= 3.3V
IN
OUT
OUT
OUT
= 3.3V
DUE TO
CATCH DIODE
LEAKAGE
12V
24V
36V
1
20 25
0
5
10 15
30 35 40
–55 –25
5
35
65
95 125 155
0.01
0.1
10
100 1000 10000
1
TEMPERATURE (°C)
LOAD CURRENT (mA)
INPUT VOLTAGE (V)
3876 G06
3976 G05
3976 G04
3976f
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For more information www.linear.com/3976
LT3976
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted.
Reference Voltage
Load Regulation
Line Regulation
0.5
0.4
1.230
1.225
1.220
1.215
1.210
1.205
1.200
1.195
1.190
1.185
1.180
1.175
1.170
0.05
0.04
0.03
0.02
0.01
0
V
V
= 12V
IN
OUT
V
= 5V
OUT
= 3.3V
LOAD = 1A
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.01
–0.02
–0.03
–0.04
–0.05
0
1
2
3
4
5
–55
5
35
65
95 125 155
–25
25
INPUT VOLTAGE (V)
5
15
20
30
35
40
10
LOAD CURRENT (A)
TEMPERATURE (°C)
3976 G08
3976 G07
3976 G09
Thermal Derating
Thermal Derating
Switch Current Limit
10.0
9.5
6
5
4
3
2
1
0
6
5
4
3
2
1
0
12V
24V
36V
H-GRADE
12V
24V
36V
H-GRADE
9.0
8.5
I-GRADE
I-GRADE
8.0
7.5
7.0
V
f
= 3.3V
V
f
= 5V
OUT
SW
OUT
SW
= 400kHz
= 400kHz
2.5in × 2.5in 4-LAYER BOARD
25 50 75 100
TEMPERATURE (°C)
2.5in × 2.5in 4-LAYER BOARD
25 50 75 100
TEMPERATURE (°C)
0
0.2
0.4
0.6
0.8
1.0
0
125
150
0
125
150
DUTY CYCLE
3976 G12
LIMITED BY MAXIMUM
3976 G10
3976 G11
LIMITED BY MAXIMUM
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
Θ
JA
= 40°C/W
Θ
= 40°C/W
JA
Soft-Start
Switch Current Limit
Current Limit Foldback
10
9
8
7
6
5
4
3
2
1
0
12
11
10
9
10
9
8
7
6
5
4
3
2
1
0
3V
0
S
%
S
=
D
3
V
T
Y
C
Y
C
L
E
10
9
8
7
6
5
4
3
2
1
0
0
0.2
0.4
0.6
0.8
1.0
1.2
F
B
P
I
N
V
O
L
T
A
G
E
(
V
)
3
9
7
6
G
1
4
V
V
= 1V
= 0V
30% DUTY CYCLE
30% DUTY CYCLE
FB
FB
30% DUTY CYCLE
V
= 3V
SS
8
7
6
0
0.5
1.0
1.5
2.0
2.5
65
TEMPERATURE (°C)
125 155
–55 –25
5
35
95
0
0.2
0.6
0.8
1.0
1.2
0.4
SS PIN VOLTAGE (V)
FB PIN VOLTAGE (V)
3976 G15
3976 G13
3976 G14
3976f
5
For more information www.linear.com/3976
LT3976
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted.
Switch VCESAT
BOOST Pin Current
Minimum On-Time
350
300
90
80
70
60
50
40
30
20
10
200
180
V
f
= 0V
SYNC
SW
= 2MHz
250
200
150
100
50
160
140
120
100
80
LOAD = 1A
LOAD = 2.5A
LOAD = 5A
0
0
60
1
2
3
5
0
4
0
4
5
–55
35
65
95
125 155
1
2
3
–25
5
SWITCH CURRENT (A)
SWITCH CURRENT (A)
TEMPERATURE (°C)
3976 G16
3976 G17
3976 G18
RT Programmed Switching
Frequency
Minimum Off-Time
Switching Frequency
780
720
660
600
250
225
200
175
150
125
100
350
300
V
SW
= 0V
SYNC
f
= 2MHz
250
200
150
100
50
LOAD = 5A
540
480
420
LOAD = 2.5A
LOAD = 1A
0
65
TEMPERATURE (°C)
125 155
–55 –25
5
35
95
65
TEMPERATURE (°C)
125 155
2.2
2
–55 –25
5
35
95
0.2
0.8
0.4 0.6
1
1.2 1.4 1.6 1.8
SWITCHING FREQUENCY (MHz)
3976 G20
3976 G19
3976 G21
Internal Undervoltage Lockout
(UVLO)
Frequency Foldback
EN Thresholds
700
600
500
400
300
200
100
0
6
5
4
3
1.09
EN RISING
1.08
1.07
1.06
1.05
1.04
1.03
1.02
2
1
0
EN FALLING
1.01
65
TEMPERATURE (°C)
125 155
–55 –25
5
35
65
95 125 155
0.8
FB PIN VOLTAGE (V)
1.2
–55 –25
35
95
0
0.2
0.4
0.6
1
5
TEMPERATURE (°C)
3976 G22
3976 G23
3976 G24
3976f
6
For more information www.linear.com/3976
LT3976
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted.
Minimum Input Voltage,
VOUT = 5V
Minimum Input Voltage,
VOUT = 3.3V
PG Thresholds
1.12
6.5
6.0
5.5
5.0
4.5
4.0
5.0
4.5
4.0
3.5
3.0
2.5
V
f
= 5V
V
= 3.3V
OUT
SW
OUT
= 800kHz
FRONT PAGE APPLICATION
1.11
1.10
TO RUN/TO START
TO RUN/TO START
FB RISING
1.09
1.08
1.07
1.06
1.05
FB FALLING
1.04
–25
5
65
95 125 155
0
1
2
3
4
5
–55
35
0
1
2
3
4
5
TEMPERATURE (°C)
LOAD CURRENT (A)
LOAD CURRENT (A)
3976 G25
3976 G26
3976 G27
SS Pin Current
Boost Capacitor Charger
Burst Frequency
2.6
900
800
700
600
500
400
300
200
100
0
160
140
120
100
80
V
= 0.5V
V
= V
IN
SS
BST
2.4
2.2
V
SW
= 5V
OUT
f
= 800kHz
2.0
1.8
1.6
1.4
1.2
V
SW
= 3.3V
OUT
f
= 600kHz
60
40
20
1.0
0
–25
5
65
95 125 155
–55
35
80 100
8
10
0
20 40 60
120 140 160
0
2
4
6
12 14 16
TEMPERATURE (°C)
LOAD CURRENT (mA)
OUT PIN VOLTAGE (V)
3976 G29
3976 G28
3976 G30
Boost Diode Forward Voltage
Dropout Comparator Thresholds
600
580
560
540
520
500
480
460
440
420
400
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
RISING
OUT
V
FALLING
OUT
1
65
TEMPERATURE (°C)
0
0.5
1.5
2
–55
5
35
95 125
–25
155
BOOST DIODE CURRENT (A)
3976 G31
3976 G32
3976f
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For more information www.linear.com/3976
LT3976
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted.
Start-Up/Dropout Performance
Start-Up/Dropout Performance
Burst Mode Switching Waveforms
V
V
V
IN
IN
IN
V
IN
V
1V/DIV
1V/DIV
SW
5V/DIV
V
V
OUT
OUT
I
L
V
V
OUT
OUT
0.5A/DIV
1V/DIV
1V/DIV
V
OUT
10mV/DIV
3976 G34
3976 G35
3976 G33
1kΩ LOAD
100ms/DIV
V
V
= 12V
5µs/DIV
2.5Ω LOAD
100ms/DIV
IN
(5mA IN REGULATION)
= 3.3V
= 20mA
= 47µF
(2A IN REGULATION)
OUT
I
LOAD
C
OUT
Full Frequency Switching
Waveforms
Dropout Switching Waveforms
V
V
SW
2V/DIV
SW
5V/DIV
I
I
L
1A/DIV
L
1A/DIV
V
V
OUT
50mV/DIV
OUT
20mV/DIV
3976 G36
3976 G37
V
V
= 12V
1µs/DIV
V
= 5V
IN
5µs/DIV
IN
= 3.3V
= 1A
V
SET FOR 5V
= 0.5A
OUT
OUT
I
LOAD
I
LOAD
C
= 47µF
C
= 47µF
OUT
OUT
Load Transient: 0.5A to 4.5A
Load Transient: 10mA to 4A
I
I
L
L
2A/DIV
2A/DIV
V
V
OUT
OUT
200mV/DIV
500mV/DIV
3976 G39
3976 G38
50µs/DIV
12V
50µs/DIV
12V
IN
IN
OUT
= 2 × 47µF
3.3V
3.3V
OUT
C
C
= 2 × 47µF
OUT
OUT
3976f
8
For more information www.linear.com/3976
LT3976
pin FuncTions (MSE/UDD)
FB (Pin 1/Pins 23, 24): The LT3976 regulates the FB pin
to1.197V.Connectthefeedbackresistordividertaptothis
pin. Also, connect a phase lead capacitor between FB and
the output. Typically, this capacitor is 10pF.
V (Pins 10, 11, 12/Pins 13, 14, 15): The V pin sup-
IN IN
plies current to the LT3976’s internal circuitry and to the
internalpowerswitch.Thesepinsmustbelocallybypassed.
EN (Pin 13/Pin 16): The part is in shutdown when this
pin is low and active when this pin is high. The hysteretic
thresholdvoltageis1.08Vgoingupand1.02Vgoingdown.
SS(Pin2/Pin1):AcapacitoristiedbetweenSSandground
to slowly ramp up the peak current limit of the LT3976 on
start-up. There is an internal 1.8μA pull-up on this pin.
The soft-start capacitor is actively discharged when the
EN pin goes low, during undervoltage lockout or thermal
shutdown. Float this pin to disable soft-start.
The EN threshold is only accurate when V is above 4.3V.
IN
If V is lower than 3.9V, internal UVLO will place the part
IN
in shutdown. Tie to V if shutdown feature is not used.
IN
RT (Pin 14/Pin 18): A resistor is tied between RT and
ground to set the switching frequency.
OUT (Pin 3/Pin 2): This pin is an input to the dropout
comparator which maintains a minimum dropout of
PG (Pin 15/Pin 19): The PG pin is the open-drain output of
an internal comparator. PGOOD remains low until the FB
pin is within 8.4% of the final regulation voltage. PGOOD
500mV between V and OUT. The OUT pin connects to
IN
the anode of the internal boost diode. This pin also sup-
plies the current to the LT3976’s internal regulator when
OUT is above 3.2V. Connect this pin to the output when
the programmed output voltage is less than 16V.
is valid when V is above 2V.
IN
SYNC (Pin 16/Pin 20): This is the external clock synchro-
nization input. Ground this pin for low ripple Burst Mode
operation at low output loads. Tie to a clock source for
synchronization, which will include pulse skipping at low
output loads. When in pulse-skipping mode, quiescent
current increases to 11µA in a typical application at no
load. Do not float this pin.
BOOST (Pin 4/Pin 4): This pin is used to provide a drive
voltage,higherthantheinputvoltage,totheinternalbipolar
NPN power switch.
SW (Pins 5, 6, 7/Pins 6, 7, 8): The SW pin is the output of
an internal power switch. Connect these pins to the induc-
tor, catch diode, and boost capacitor. An R-C snubber to
GND is needed to ensure robustness under all conditions.
Typical values are 2Ω and 470pF.
GND (Exposed Pad Pin 17/Pin 21, Exposed Pad Pin 25):
Ground. The exposed pad must be soldered to the PCB.
NC (Pins 8, 9/Pins 3, 5, 9-12, 17, 22): No Connects.
These pins are not connected to internal circuitry.
3976f
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LT3976
block DiagraM
OUT
V
IN
V
IN
C1
+
0.5V
–
–
+
–
+
INTERNAL 1.197V REF
SHDN
1.02V
+
–
SWITCH
BOOST
SW
EN
RT
+
SLOPE COMP
LATCH
R
C3
L1
OSCILLATOR
200kHz TO 2MHz
Q
S
R
T
V
OUT
SYNC
PG
Burst Mode
DETECT
R3
C6
D1 C2
ERROR AMP
V
CLAMP
C
V
+
–
+
1.097V
C
1.8µA
–
SS
C4
OPT
SHDN
GND
FB
R2
R1
3976 BD
C5
3976f
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LT3976
operaTion
The LT3976 is a constant frequency, current mode step-
down regulator. An oscillator, with frequency set by RT,
sets an RS flip-flop, turning on the internal power switch.
An amplifier and comparator monitor the current flowing
Between bursts, all circuitry associated with controlling
the output switch is shut down reducing the input supply
current to 1.7μA. In a typical application, 3.3μA will be
consumed from the supply when regulating with no load.
between the V and SW pins, turning the switch off when
IN
The oscillator reduces the LT3976’s operating frequency
when the voltage at the FB pin is low. This frequency
foldback helps to control the output current during start-
up and overload.
this current reaches a level determined by the voltage at
V (see Block Diagram). An error amplifier measures the
C
output voltage through an external resistor divider tied
to the FB pin and servos the V node. If the error ampli-
C
The LT3976 can provide up to 5A of output current. A
current limit foldback feature throttles back the current
limit during overload conditions to limit the power dis-
sipation. When SS is below 2V, the LT3976 overrides
the current limit foldback circuit to avoid interfering with
start-up. Thermal shutdown further protects the part from
excessivepowerdissipation,especiallyinelevatedambient
temperature environments.
fier’s output increases, more current is delivered to the
output; if it decreases, less current is delivered. An active
clamp on the V pin provides current limit. The V pin is
C
C
also clamped by the voltage on the SS pin; soft-start is
implemented by generating a voltage ramp at the SS pin
using an external capacitor.
Aninternalregulatorprovidespowertothecontrolcircuitry.
The bias regulator normally draws power from the V
IN
If the input voltage decreases towards the programmed
output voltage, the LT3976 will start to skip switch-off
times and decrease the switching frequency to maintain
output regulation. As the input voltage decreases below
the programmed output voltage, the output voltage will be
regulated 500mV below the input voltage. This enforced
minimum dropout voltage limits the duty cycle and keeps
the boost capacitor charged during dropout conditions.
Since sufficient boost voltage is maintained, the internal
switchcanfullysaturateyieldinglowdropoutperformance.
pin, but if the OUT pin is connected to an external volt-
age higher than 3.2V, bias power will be drawn from the
external source (typically the regulated output voltage).
This improves efficiency.
If the EN pin is low, the LT3976 is shut down and draws
700nA from the input. When the EN pin falls below 1.02V,
the switching regulator will shut down, and when the EN
pinrisesabove1.08V, theswitchingregulatorwillbecome
active. This accurate threshold allows programmable
undervoltage lockout.
The LT3976 contains a power good comparator which
trips when the FB pin is at 91.6% of its regulated value.
The PG output is an open-drain transistor that is off when
the output is in regulation, allowing an external resistor
The switch driver operates from either V or from the
IN
BOOST pin. An external capacitor is used to generate a
voltage at the BOOST pin that is higher than the input
supply. This allows the driver to fully saturate the internal
bipolar NPN power switch for efficient operation.
to pull the PG pin high. Power good is valid when V is
IN
above 2V. When the LT3976 is shut down the PG pin is
actively pulled low.
To further optimize efficiency, the LT3976 automatically
switches to Burst Mode operation in light load situations.
3976f
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LT3976
applicaTions inForMaTion
Achieving Ultralow Quiescent Current
diode should have less than a few µA of typical reverse
leakage at room temperature. These two considerations
are reiterated in the FB Resistor Network and Catch Diode
Selection sections.
To enhance efficiency at light loads, the LT3976 operates
in low ripple Burst Mode operation, which keeps the out-
put capacitor charged to the desired output voltage while
minimizing the input quiescent current. In Burst Mode
operation the LT3976 delivers single pulses of current to
the output capacitor followed by sleep periods where the
output power is supplied by the output capacitor. When in
sleepmodetheLT3976consumes1.7μA,butwhenitturns
on all the circuitry to deliver a current pulse, the LT3976
consumes several mA of input current in addition to the
switch current. Therefore, the total quiescent current will
be greater than 1.7μA when regulating.
It is important to note that another way to decrease the
pulse frequency is to increase the magnitude of each
single current pulse. However, this increases the output
voltage ripple because each cycle delivers more power to
the output capacitor. The magnitude of the current pulses
was selected to ensure less than 15mV of output ripple in
a typical application. See Figure 2.
V
SW
5V/DIV
As the output load decreases, the frequency of single cur-
rent pulses decreases (see Figure 1) and the percentage
of time the LT3976 is in sleep mode increases, resulting
in much higher light load efficiency. By maximizing the
time between pulses, the converter quiescent current
gets closer to the 1.7μA ideal. Therefore, to optimize the
quiescent current performance at light loads, the current
in the feedback resistor divider and the reverse current
in the catch diode must be minimized, as these appear
to the output as load currents. Use the largest possible
feedback resistors and a low leakage Schottky catch diode
in applications utilizing the ultralow quiescent current
performanceoftheLT3976.Thefeedbackresistorsshould
preferably be on the order of MΩ and the Schottky catch
I
L
0.5A/DIV
V
OUT
10mV/DIV
3976 F02
V
V
= 12V
5µs/DIV
IN
= 3.3V
= 20mA
= 47µF
OUT
I
LOAD
C
OUT
Figure 2. Burst Mode Operation
While in Burst Mode operation, the burst frequency and
the charge delivered with each pulse will not change with
outputcapacitance.Therefore,theoutputvoltageripplewill
be inversely proportional to the output capacitance. In a
typicalapplicationwitha22µFoutputcapacitor,theoutput
ripple is about 10mV, and with a 47µF output capacitor
the output ripple is about 5mV. The output voltage ripple
can continue to be decreased by increasing the output
capacitance, though care must be taken to minimize the
effects of output capacitor ESR and ESL.
900
800
V
SW
= 5V
OUT
= 800kHz
700
600
500
400
300
200
100
0
f
At higher output loads (above 150mA for the front page
application) the LT3976 will be running at the frequency
programmed by the R resistor, and will be operating in
standard PWM mode. The transition between PWM and
low ripple Burst Mode operation is seamless, and will not
disturb the output voltage.
V
SW
= 3.3V
OUT
f
= 600kHz
T
80 100
120 140 160
0
20 40 60
To ensure proper Burst Mode operation, the SYNC pin
must be grounded. When synchronized with an external
clock, the LT3976 will pulse skip at light loads. At very
LOAD CURRENT (mA)
3976 F01
Figure 1. Switching Frequency in Burst Mode Operation
3976f
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LT3976
applicaTions inForMaTion
light loads, the part will go to sleep between groups of
pulses, so the quiescent current of the part will still be low,
but not as low as in Burst Mode operation. The quiescent
current in a typical application when synchronized with an
external clock is 11µA at no load. Holding the SYNC pin
DC high yields no advantages in terms of output ripple or
minimum load to full frequency, so is not recommended.
Table 1. Switching Frequency vs RT Value
SWITCHING FREQUENCY (MHz)
R VALUE (kΩ)
T
0.2
0.3
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
294
182
130
78.7
54.9
41.2
32.4
26.1
21.5
17.8
14.7
12.4
FB Resistor Network
The output voltage is programmed with a resistor divider
between the output and the FB pin. Choose the resistor
values according to:
⎛
⎜
⎝
⎞
VOUT
1.197V
R1=R2
– 1
⎟
⎠
Operating Frequency Trade-Offs
Reference designators refer to the Block Diagram. 1%
resistors are recommended to maintain output voltage
accuracy.
Selectionoftheoperatingfrequencyisatrade-offbetween
efficiency,componentsize,minimumdropoutvoltage,and
maximum input voltage. The advantage of high frequency
operation is that smaller inductor and capacitor values
may be used. The disadvantages are lower efficiency, and
lower maximum input voltage. The highest acceptable
The total resistance of the FB resistor divider should be
selected to be as large as possible to enhance low current
performance. The resistor divider generates a small load
on the output, which should be minimized to optimize the
low supply current at light loads.
switching frequency (f
) for a given application
SW(MAX)
can be calculated as follows:
VOUT + VD
tON(MIN) V – V + VD
WhenusinglargeFBresistors,a10pFphaseleadcapacitor
should be connected from V
to FB.
fSW(MAX) =
OUT
(
)
IN
SW
Setting the Switching Frequency
where V is the typical input voltage, V
is the output
IN
OUT
The LT3976 uses a constant frequency PWM architecture
that can be programmed to switch from 200kHz to 2MHz
by using a resistor tied from the RT pin to ground. A table
voltage, V is the catch diode drop (~0.5V), and V is
D
SW
the internal switch drop (~0.3V at max load). This equa-
tion shows that slower switching frequency is necessary
showing the necessary R value for a desired switching
T
to safely accommodate high V /V
ratio. This is due
IN OUT
frequency is in Table 1.
to the limitation on the LT3976’s minimum on-time. The
minimum on-time is a strong function of temperature.
Use the typical minimum on-time curve to design for an
application’s maximum temperature, while adding about
30%forpart-to-partvariation.Theminimumdutycyclethat
can be achieved taking minimum on time into account is:
To estimate the necessary R value for a desired switching
T
frequency, use the equation:
51.1
RT =
– 9.27
1.09
f
SW
DC
= f • t
SW ON(MIN)
MIN
where R is in kΩ and f is in MHz.
T
SW
where f is the switching frequency, the t
is the
SW
ON(MIN)
minimum switch on-time.
3976f
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LT3976
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A good choice of switching frequency should allow ad-
equate input voltage range (see next two sections) and
keep the inductor and capacitor values small.
The duty cycle is the fraction of time that the internal
switch is on during a clock cycle. Unlike many fixed fre-
quency regulators, the LT3976 can extend its duty cycle
by remaining on for multiple clock cycles. The LT3976
will not switch off at the end of each clock cycle if there
is sufficient voltage across the boost capacitor (C3 in
the Block Diagram). Eventually, the voltage on the boost
capacitor falls and requires refreshing. When this occurs,
the switch will turn off, allowing the inductor current to
recharge the boost capacitor. This places a limitation on
the maximum duty cycle as follows:
Maximum Input Voltage Range
The LT3976 can operate from input voltages of up to 40V.
Often the highest allowed V during normal operation
IN
(V
) is limited by the minimum duty cycle rather
IN(OP-MAX)
than the absolute maximum ratings of the V pin. It can
IN
be calculated using the following equation:
VOUT + VD
fSW • tON(MIN)
V
=
– VD + VSW
βSW
IN(OP-MAX)
DCMAX =
βSW +1
where t
is the minimum switch on-time. A lower
ON(MIN)
whereβ isequaltothebetaoftheinternalpowerswitch.
switching frequency can be used to extend normal opera-
tion to higher input voltages.
SW
The beta of the power switch is typically about 50, which
leads to a DC
of about 98%. This leads to a minimum
MAX
The circuit will tolerate inputs above the maximum op-
erating input voltage and up to the absolute maximum
input voltage of approximately:
VOUT + VD
DCMAX
ratings of the V and BOOST pins, regardless of chosen
IN
V
=
– VD + VSW
IN(MIN1)
switching frequency. However, during such transients
whereV ishigherthanV
, theLT3976willenter
IN(OP-MAX)
IN
where V
is the output voltage, V is the catch diode
pulse-skippingoperationwheresomeswitchingpulsesare
skipped to maintain output regulation. The output voltage
ripple and inductor current ripple will be higher than in
OUT
D
drop, V is the internal switch drop and DC
is the
SW
MAX
maximum duty cycle.
typical operation. Do not overload when V is greater
IN
The final factor affecting the minimum input voltage is
the minimum dropout voltage. When the OUT pin is tied
to the output, the LT3976 regulates the output such that
than V
.
IN(OP-MAX)
During start-up or overload, the switch node slews very
fast due to the 10A peak current limit. At high voltages
duringtheseconditions,anR-Csnubberontheswitchnode
is required to ensure robustness of the LT3976. Typical
values for the snubber are 2Ω and 470pF. See the Typical
Applications section to see how the snubber is connected.
it stays 500mV below V . This enforced minimum drop-
IN
out voltage is due to reasons that are covered in the next
section. This places a limitation on the minimum input
voltage as follows:
V
= V
+ V
IN(MIN2)
OUT DROPOUT(MIN)
where V
DROPOUT(MIN)
is the programmed output voltage and
Minimum Input Voltage Range
OUT
V
istheminimumdropoutvoltageof500mV.
The minimum input voltage is determined by either the
LT3976’sminimumoperatingvoltageof4.3V,itsmaximum
duty cycle, or the enforced minimum dropout voltage.
See the Typical Performance Characteristics section for
the minimum input voltage across load for outputs of
3.3V and 5V.
Combining these factors leads to the overall minimum
input voltage:
V
= Max (V
, V
, 4.3V)
IN(MIN)
IN(MIN1) IN(MIN2)
3976f
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LT3976
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Minimum Dropout Voltage
It is important to note that the 500mV dropout voltage
specified is the minimum difference between V and
IN
To achievealowdropoutvoltage,theinternalpowerswitch
must always be able to fully saturate. This means that the
boost capacitor, which provides a base drive higher than
V
OUT
. When measuring V to V
with a multimeter,
IN
OUT
the measured value will be higher than 500mV because
you have to add half the ripple voltage on the input and
half the ripple voltage on the output. With the normal
ceramic capacitors specified in the data sheet, this mea-
sured dropout voltage can be as high as 650mV at high
load. If some bulk electrolytic capacitance is added to the
input and output the voltage ripple, and subsequently the
measured dropout voltage, can be significantly reduced.
Additionally, when operating in dropout at high currents,
high ripple voltage on the input and output can generate
audible noise. This noise can also be significantly reduced
by adding bulk capacitance to the input and output to
reduce the voltage ripple.
V , must always be able to charge up when the part starts
IN
up and then must also stay charged during all operating
conditions.
Duringstart-upifthereisinsufficientinductorcurrent,such
as during light load situations, the boost capacitor will be
unable to charge. When the LT3976 detects that the boost
capacitor is not charged, it activates a 100mA (typical)
pull-down on the OUT pin. If the OUT pin is connected to
theoutput, theextraloadwillincreasetheinductorcurrent
enough to sufficiently charge the boost capacitor. When
the boost capacitor is charged, the current source turns
off, and the part may re-enter Burst Mode operation.
Inductor Selection and Maximum Output Current
To keep the boost capacitor charged regardless of load
during dropout conditions, a minimum dropout voltage
is enforced. When the OUT pin is tied to the output, the
LT3976 regulates the output such that:
For a given input and output voltage, the inductor value
and switching frequency will determine the ripple current.
The ripple current increases with higher V or V
and
IN
OUT
decreases with higher inductance and faster switching
V – V
> V
DROPOUT(MIN)
IN
OUT
frequency. A good first choice for the inductor value is:
where V
is 500mV. The 500mV dropout volt-
DROPOUT(MIN)
VOUT + VD
L =
age limits the duty cycle and forces the switch to turn off
regularly to charge the boost capacitor. Since sufficient
voltageacrosstheboostcapacitorismaintained,theswitch
is allowed to fully saturate and the internal switch drop
stays low for good dropout performance. Figure 3 shows
2fSW
where f is the switching frequency in MHz, V
is the
OUT
SW
output voltage, V is the catch diode drop (~0.5V) and L
D
is the inductor value is μH.
the overall V to V
performances during start-up and
IN
OUT
dropout conditions.
The inductor’s RMS current rating must be greater than
the maximum load current and its saturation current
should be about 30% higher. For robust operation in fault
conditions (start-up or overload) and high input voltage
(>30V), the saturation current should be above 13A. To
keep the efficiency high, the series resistance (DCR)
should be less than 0.1Ω, and the core material should
be intended for high frequency applications. Table 2 lists
several inductor vendors.
V
V
IN
IN
1V/DIV
V
OUT
V
OUT
1V/DIV
3976 F03
1kΩ LOAD
100ms/DIV
(5mA IN REGULATION)
Figure 3. VIN to VOUT Performance
3976f
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Table 2. Inductor Vendors
maximum load current will depend on the input voltage. In
addition,lowinductancemayresultindiscontinuousmode
operation, which further reduces maximum load current.
For details of maximum output current and discontinuous
operation, see Linear Technology’s Application Note 44.
VENDOR
Coilcraft
Sumida
URL
www.coilcraft.com
www.sumida.com
www.tokoam.com
www.we-online.com
www.cooperet.com
www.murata.com
Toko
Finally, for duty cycles greater than 50% (V /V > 0.5),
OUT IN
Würth Elektronik
Coiltronics
Murata
a minimum inductance is required to avoid sub-harmonic
oscillations, see Application Note 19.
One approach to choosing the inductor is to start with
the simple rule given above, look at the available induc-
tors, and choose one to meet cost or space goals. Then
use the equations above to check that the LT3976 will be
able to deliver the required output current. Note again
that these equations assume that the inductor current is
Theinductorvaluemustbesufficienttosupplythedesired
maximum output current (I
), which is a function
OUT(MAX)
of the switch current limit (I ) and the ripple current.
LIM
ΔIL
2
IOUT(MAX) = ILIM
–
continuous. Discontinuous operation occurs when I
OUT
TheLT3976limitsitspeakswitchcurrentinordertoprotect
itselfandthesystemfromoverloadandshort-circuitfaults.
is less than ΔI /2.
L
Current Limit Foldback and Thermal Protection
The LT3976’s switch current limit (I ) is typically 10A at
LIM
low duty cycles and decreases linearly to 8A at DC = 0.8.
The LT3976 has a large peak current limit to ensure a 5A
max output current across duty cycle and current limit
distribution, as well as allowing a reasonable inductor
ripple current. During a short-circuit fault, having a large
current limit can lead to excessive power dissipation and
temperatureriseintheLT3976, aswellastheinductorand
catch diode. To limit this power dissipation, the LT3976
starts to fold back the current limit when the FB pin falls
below 0.8V. The LT3976 typically lowers the peak current
limit about 50% from 10A to 5A.
When the switch is off, the potential across the inductor
is the output voltage plus the catch diode drop. This gives
the peak-to-peak ripple current in the inductor:
1–DC • V + VD
(
)
(
)
OUT
ΔIL =
L • fSW
where f is the switching frequency of the LT3976, DC is
SW
the duty cycle and L is the value of the inductor. Therefore,
the maximum output current that the LT3976 will deliver
depends on the switch current limit, the inductor value,
and the input and output voltages. The inductor value may
have to be increased if the inductor ripple current does
Duringstart-up,whentheoutputvoltageandFBpinarelow,
current limit foldback could hinder the LT3976’s ability to
start up into a large load. To avoid this potential problem,
the LT3976’s current limit foldback will be disabled until
the SS pin has charged above 2V. Therefore, the use of
a soft-start capacitor will keep the current limit foldback
feature out of the way while the LT3976 is starting up.
not allow sufficient maximum output current (I
)
OUT(MAX)
giventheswitchingfrequency,andmaximuminputvoltage
used in the desired application.
The optimum inductor for a given application may differ
fromtheoneindicatedbythissimpledesignguide.Alarger
valueinductorprovidesahighermaximumloadcurrentand
reducestheoutputvoltageripple.Ifyourloadislowerthan
the maximum load current, than you can relax the value of
the inductor and operate with higher ripple current. This
allowsyoutouseaphysicallysmallerinductor,oronewith
a lower DCR resulting in higher efficiency. Be aware that if
the inductance differs from the simple rule above, then the
The LT3976 has thermal shutdown to further protect the
part during periods of high power dissipation, particularly
in high ambient temperature environments. The thermal
shutdown feature detects when the LT3976 is too hot
and shuts the part down, preventing switching. When the
thermal event passes and the LT3976 cools, the part will
restart and resume switching. A thermal shutdown event
actively discharges the soft-start capacitor.
3976f
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LT3976
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Input Capacitor
wheref isinMHz, andC
istherecommendedoutput
SW
OUT
capacitance in μF. Use X5R or X7R types. This choice will
provide low output ripple and good transient response.
Transientperformancecanbeimprovedwithahighervalue
capacitorifcombinedwithaphaseleadcapacitor(typically
10pF) between the output and the feedback pin. A lower
value of output capacitor can be used to save space and
cost but transient performance will suffer.
BypasstheinputoftheLT3976circuitwithaceramiccapaci-
tor of X7R or X5R type. Y5V types have poor performance
over temperature and applied voltage, and should not be
used. A 4.7μF to 10μF ceramic capacitor is adequate to
bypass the LT3976 and will easily handle the ripple cur-
rent. Note that larger input capacitance is required when
a lower switching frequency is used (due to longer on
times). If the input power source has high impedance, or
there is significant inductance due to long wires or cables,
additional bulk capacitance may be necessary. This can
be provided with a low performance electrolytic capacitor.
When choosing a capacitor, look carefully through the
data sheet to find out what the actual capacitance is under
operating conditions (applied voltage and temperature).
A physically larger capacitor or one with a higher voltage
rating may be required. Table 3 lists several capacitor
vendors.
Step-down regulators draw current from the input sup-
ply in pulses with very fast rise and fall times. The input
capacitor is required to reduce the resulting voltage
ripple at the LT3976 and to force this very high frequency
switching current into a tight local loop, minimizing EMI.
A 10μF capacitor is capable of this task, but only if it is
placed close to the LT3976 (see the PCB Layout section).
Asecondprecautionregardingtheceramicinputcapacitor
concernsthemaximuminputvoltageratingoftheLT3976.
A ceramic input capacitor combined with trace or cable
inductance forms a high quality (under damped) tank
circuit. If the LT3976 circuit is plugged into a live supply,
the input voltage can ring to twice its nominal value, pos-
sibly exceeding the LT3976’s voltage rating. If the input
supply is poorly controlled or the user will be plugging
the LT3976 into an energized supply, the input network
should be designed to prevent this overshoot. See Linear
TechnologyApplicationNote88foracompletediscussion.
Table 3. Recommended Ceramic Capacitor Vendors
MANUFACTURER
AVX
URL
www.avxcorp.com
www.murata.com
www.t-yuden.com
www.vishay.com
www.tdk.com
Murata
Taiyo Yuden
Vishay Siliconix
TDK
Ceramic Capacitors
When in dropout, the LT3976 can excite ceramic ca-
pacitors at audio frequencies. At high load, this could be
unacceptable. Simply adding bulk input capacitance to
the input and output will significantly reduce the voltage
ripple and the audible noise generated at these nodes to
acceptable levels.
A final precaution regarding ceramic capacitors concerns
the maximum input voltage rating of the LT3976. As pre-
viously mentioned, a ceramic input capacitor combined
with trace or cable inductance forms a high quality (under
damped)tankcircuit.IftheLT3976circuitispluggedintoa
live supply, the input voltage can ring to twice its nominal
value, possibly exceeding the LT3976’s rating. If the input
supply is poorly controlled or the user will be plugging
the LT3976 into an energized supply, the input network
should be designed to prevent this overshoot. See Linear
TechnologyApplicationNote88foracompletediscussion.
Output Capacitor and Output Ripple
The output capacitor has two essential functions. Along
with the inductor, it filters the square wave generated by
the LT3976 to produce the DC output. In this role it deter-
minestheoutputripple,solowimpedance(attheswitching
frequency) is important. The second function is to store
energy in order to satisfy transient loads and stabilize the
LT3976’s control loop. Ceramic capacitors have very low
equivalent series resistance (ESR) and provide the best
ripple performance. A good starting value is:
300
VOUT • fSW
COUT
=
3976f
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Catch Diode Selection
Table 4. Schottky Diodes. The Reverse Current Values Listed
Are Estimates Based Off of Typical Curves for Reverse Current
vs Reverse Voltage at 25°C
The catch diode (D1 from the Block Diagram) conducts
current only during the switch off time. Average forward
current in normal operation can be calculated from:
V at
I at
R
R
25°C
(µA)
F
V at 5A 5A MAX V = 20V
F
TYP 25°C
25°C
(mV)
PART NUMBER V (V)
I
(A)
AVE
(mV)
R
⎛
⎜
⎝
⎞
⎟
⎠
V – V
IN
OUT
On Semiconductor
ID(AVG) = IOUT
V
IN
MBRS540T3
Diodes Inc.
B540C
40
5
450
500
120
where I
is the output load current. The current rating of
OUT
40
40
60
45
60
5
5
5
8
8
510
480
610
450
400
550
520
670
—
2
4
the diode should be selected to be greater than or equal to
the application’s output load current, so that the diode is
robust for a wide input voltage range. A diode with even
higher current rating can be selected for the worst-case
scenarioofoverload,wherethemaxdiodecurrentcanthen
increase to the typical peak switch current. Short circuit is
not the worst-case condition due to current limit foldback.
Peakreversevoltageisequaltotheregulatorinputvoltage.
For inputs up to 40V, a 40V diode is adequate.
PDS540
PDS560
0.9
18
60
SBR8A45SP5
SBR8AU60P5
—
charge the boost capacitor. Above 16V, the OUT pin abs
max is violated. For outputs between 2.5V and 3.2V, an
external Schottky diode to the output is sufficient because
anexternalSchottkywillhavemuchlowerforwardvoltage
drop than the internal boost diode.
An additional consideration is reverse leakage current.
When the catch diode is reversed biased, any leakage
current will appear as load current. When operating under
light load conditions, the low supply current consumed
by the LT3976 will be optimized by using a catch diode
with minimum reverse leakage current. Low leakage
Schottky diodes often have larger forward voltage drops
at a given current, so a trade-off can exist between low
load and high load efficiency. Often Schottky diodes with
larger reverse bias ratings will have less leakage at a given
output voltage than a diode with a smaller reverse bias
rating. Therefore, superior leakage performance can be
achieved at the expense of diode size. Table 4 lists several
Schottky diodes and their manufacturers.
For output voltages less than 2.5V, there are two options.
An external Schottky diode can charge the boost capaci-
tor from the input (Figure 4c) or from an external voltage
source (Figure 4d). Using an external voltage source is
the better option because it is more efficient than charg-
ing the boost capacitor from the input. However, such
a voltage rail is not always available in all systems. For
output voltages greater than 16V, an external Schottky
diode from an external voltage source should be used to
charge the boost capacitor (Figure 4e). In applications
using an external voltage source, the supply should be
between 3.1V and 16V. When using the input, the input
voltage may not exceed 27V. In all cases, the maximum
voltage rating of the BOOST pin must not be exceeded.
BOOST and OUT Pin Considerations
When the output is above 16V, the OUT pin can not be
tied to the output or the OUT pin abs max will be violated.
It should instead be tied to GND (Figure 4e). This is to
prevent the dropout circuitry from interfering with switch-
ing behavior and to prevent the 100mA active pull-down
from drawing power. It is important to note that when
the output is above 16V and the OUT pin is grounded,
the dropout circuitry is not connected, so the minimum
dropout will be about 1.5V, rather than 500mV. If the
CapacitorC3andtheinternalboostSchottkydiode(seethe
Block Diagram) are used to generate a boost voltage that
is higher than the input voltage. In most cases a 0.47μF
capacitor will work well. The BOOST pin must be more
than 1.8V above the SW pin for best efficiency and more
than 2.6V above the SW pin to allow the LT3976 to skip
off times to achieve very high duty cycles. For outputs
between 3.2V and 16V, the standard circuit with the OUT
pinconnectedtotheoutput(Figure4a)isbest. Below3.2V
the internal Schottky diode may not be able to sufficiently
output is less than 3.2V and an external Schottky is used
3976f
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LT3976
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to charge the boost capacitor, the OUT pin should still be
tied to the output even though the minimum input voltage
of the LT3976 will be limited by the 4.3V minimum rather
than the minimum dropout voltage.
Enable and Undervoltage Lockout
The LT3976 is in shutdown when the EN pin is low and
active when the pin is high. The falling threshold of the
EN comparator is 1.02V, with 60mV of hysteresis. The EN
With the OUT pin connected to the output, a 100mA ac-
tive load will charge the boost capacitor during light load
start-upandanenforced500mVminimumdropoutvoltage
will keep the boost capacitor charged across operating
conditions (see Minimum Dropout Voltage section). This
yieldsexcellentstart-upanddropoutperformance.Figure5
showstheminimuminputvoltagefor3.3Vand5Voutputs.
pin can be tied to V if the shutdown feature is not used.
IN
Undervoltage lockout (UVLO) can be added to the LT3976
as shown in Figure 6. Typically, UVLO is used in situa-
tions where the input supply is current limited, or has a
relatively high source resistance. A switching regulator
draws constant power from the source, so source cur-
rent increases as source voltage drops. This looks like a
BOOST
LT3976
BOOST
LT3976
BOOST
V
V
SW
V
V
SW
V
V
IN
SW
IN
IN
IN
IN
IN
LT3976
GND
OUT
OUT
OUT
V
V
V
OUT
OUT
OUT
GND
GND
(4a) For 3.2V ≤ V
OUT
≤ 16V
(4b) For 2.5V ≤ V
OUT
≤ 3.2V
(4c) For V
OUT
< 2.5V, V < 27V
IN
V
S
V
S
BOOST
BOOST
LT3976
V
V
SW
V
V
IN
SW
IN
IN
IN
LT3976
GND
OUT
OUT
V
V
OUT
OUT
GND
3976 F04
(4d) For V
< 2.5V, 3.1V ≤ V ≤ 16V
(4e) For V
> 16V, 3.1V ≤ V ≤ 16V
OUT S
OUT
S
Figure 4. Five Circuits for Generating the Boost Voltage
6.5
5.0
V
f
= 5V
OUT
SW
V
= 3.3V
OUT
= 800kHz
FRONT PAGE APPLICATION
6.0
5.5
5.0
4.5
4.0
4.5
4.0
3.5
3.0
2.5
TO RUN/TO START
TO RUN/TO START
0
1
2
3
4
5
0
1
2
3
4
5
LOAD CURRENT (A)
LOAD CURRENT (A)
3976 F05a
3976 F05b
Figure 5. The Minimum Input Voltage Depends on Output Voltage and Load Current
3976f
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LT3976
V
IN
I
L
1A/DIV
R3
R4
1.02V
+
–
SHDN
EN
V
OUT
1V/DIV
LT3976 F06
V
SS
Figure 6. Undervoltage Lockout
0.5V/DIV
3976 F07
1ms/DIV
negative resistance load to the source and can cause the
sourcetocurrentlimitorlatchlowunderlowsourcevoltage
conditions. UVLO prevents the regulator from operating
at source voltages where the problems might occur. The
UVLO threshold can be adjusted by setting the values R3
and R4 such that they satisfy the following equation:
Figure 7. Soft-Start Waveforms for the Front-Page Application
with a 10nF Capacitor on SS. EN Is Pulsed High for About 7ms
with a 1.65Ω Load Resistor
Synchronization
To select low ripple Burst Mode operation, tie the SYNC
pin below 0.5V (this can be ground or a logic output).
⎛
⎜
⎝
⎞
⎟
⎠
R3+R4
VUVLO = V
EN(THRESH)
R4
Synchronizing the LT3976 oscillator to an external fre-
quency can be done by connecting a square wave (with
20% to 80% duty cycle) to the SYNC pin. The square
wave amplitude should have valleys that are below 0.5V
and peaks above 1.5V (up to 6V).
where V
is the falling threshold of the EN pin,
EN(THRESH)
whichisapproximately1.02V,andwhereswitchingshould
stop when V falls below V . Note that due to the
IN
UVLO
comparator’s hysteresis, switching will not start until the
The LT3976 will pulse skip at low output loads while syn-
chronized to an external clock to maintain regulation. At
verylightloads, thepartwillgotosleepbetweengroupsof
pulses, so the quiescent current of the part will still be low,
but not as low as in Burst Mode operation. The quiescent
current in a typical application when synchronized with an
external clock is 11µA at no load. Holding the SYNC pin
DC high yields no advantages in terms of output ripple or
minimum load to full frequency, so is not recommended.
Never float the SYNC pin.
input is about 6% above V
.
UVLO
When operating in Burst Mode operation for light load
currents, the current through the UVLO resistor network
can easily be greater than the supply current consumed
by the LT3976. Therefore, the UVLO resistors should be
large to minimize their effect on efficiency at low loads.
Soft-Start
The SS pin can be used to soft start the LT3976 by throt-
tlingthemaximuminputcurrentduringstart-upandreset.
An internal 1.8μA current source charges an external
capacitor generating a voltage ramp on the SS pin. The
The LT3976 may be synchronized over a 250kHz to 2MHz
range. The R resistor should be chosen to set the LT3976
T
switchingfrequency20%belowthelowestsynchronization
SS pin clamps the internal V node, which slowly ramps
C
input. For example, if the synchronization signal will be
up the current limit. Maximum current limit is reached
when the SS pin is about 1.5V or higher. By selecting a
large enough capacitor, the output can reach regulation
without overshoot. Figure 7 shows start-up waveforms
for a typical application with a 10nF capacitor on SS for
a 1.65Ω load when the EN pin is pulsed high for 7ms.
250kHz and higher, the R should be selected for 200kHz.
T
To assure reliable and safe operation the LT3976 will only
synchronize when the output voltage is near regulation
as indicated by the PG flag. It is therefore necessary to
choosealargeenoughinductorvaluetosupplytherequired
output current at the frequency set by the R resistor (see
T
InductorSelectionsection).Theslopecompensationisset
The external SS capacitor is actively discharged when the
EN pin is low, or during thermal shutdown. The active
pull-down on the SS pin has a resistance of about 150Ω.
by the R value, while the minimum slope compensation
T
required to avoid subharmonic oscillations is established
3976f
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by the inductor size, input voltage and output voltage.
Since the synchronization frequency will not change the
slopes of the inductor current waveform, if the inductor
is large enough to avoid subharmonic oscillations at the
Protection section). There is another situation to consider
in systems where the output will be held high when the
input to the LT3976 is absent. This may occur in battery
charging applications or in battery backup systems where
a battery or some other supply is diode ORed with the
frequency set by R , than the slope compensation will be
T
sufficient for all synchronization frequencies.
LT3976’s output. If the V pin is allowed to float and the
IN
EN/UVLO pin is held high (either by a logic signal or be-
Power Good Flag
cause it is tied to V ), then the LT3976’s internal circuitry
IN
will pull its quiescent current through its SW pin. This is
fine if your system can tolerate a few μA in this state. If
you ground the EN pin, the SW pin current will drop to
ThePGpinisanopen-drainoutputwhichisusedtoindicate
to the user when the output voltage is within regulation.
When the output is lower than the regulation voltage by
more than 8.4%, as determined from the FB pin voltage,
the PG pin will pull low to indicate the power is not good.
Otherwise, the PG pin will go high impedance and can
be pulled logic high with a resistor pull-up. The PG pin is
only comparing the output voltage to an accurate refer-
essentially zero. However, if the V pin is grounded while
IN
the output is held high, regardless of EN, parasitic diodes
insidetheLT3976canpullcurrentfromtheoutputthrough
the SW pin and the V pin. Figure 9 shows a circuit that
IN
will run only when the input voltage is present and that
protects against a shorted or reversed input.
ence when the LT3976 is enabled and V is above 4.3V.
IN
D4
PDS540
When the part is shutdown, the PG is actively pulled low to
indicate that the LT3976 is not regulating the output. The
input voltage must be greater than 1.4V to fully turn-on
the active pull-down device. Figure 8 shows the status of
the PG pin as the input voltage is increased.
V
IN
V
BOOST
SW
IN
V
OUT
EN
LT3976
OUT
FB
4
3
2
1
0
+
GND
BACKUP
3976 F09
Figure 9. Diode D4 Prevents a Shorted Input from Discharging
a Backup Battery Tied to the Output. It Also Protects the Circuit
from a Reversed Input. The LT3976 Runs Only When the Input
Is Present
PCB Layout
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
For proper operation and minimum EMI, care must be
taken during printed circuit board layout. Figure 10 shows
a sample component placement with trace, ground plane
and via locations, which serves as a good PCB layout
example. Note that large, switched currents flow in the
INPUT VOLTAGE (V)
3976 F08
Figure 8. PG Pin Voltage Versus Input Voltage when PG
Is Connected to 3V Through a 150k Resistor. The FB Pin
Voltage Is 1.15V
LT3976’s V and SW pins, the catch diode (D1), and the
IN
Shorted and Reversed Input Protection
input capacitor (C1). The loop formed by these compo-
nents should be as small as possible. These components,
along with the inductor and output capacitor, should be
placed on the same side of the circuit board, and their
connections should be made on that layer. Place a local,
If the inductor is chosen so that it won’t saturate exces-
sively, a LT3976 buck regulator will tolerate a shorted
output and the power dissipation will be limited by current
limit foldback (see Current Limit Foldback and Thermal
3976f
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LT3976 power dissipation by the thermal resistance from
junctiontoambient.ThetemperatureriseoftheLT3976for
a 3.3V and 5V application was measured using a thermal
camera and is shown in Figure 11.
SS
SYNC
V
OUT
17
V
OUT
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
FB
BST
PG
Also keep in mind that the leakage current of the power
Schottky diode goes up exponentially with junction tem-
perature.Whenthepowerswitchisoff,thepowerSchottky
diode is in parallel with the power converter’s output
filter stage. As a result, an increase in a diode’s leakage
current results in an effective increase in the load, and a
corresponding increase in the input quiescent current.
Therefore, the catch Schottky diode must be selected
with care to avoid excessive increase in light load supply
current at high temperatures.
RT
OUT
EN
V
IN
SW
3976 F10
Figure 10. Layout Showing a Good PCB Design
70
V
f
= 3.3V
OUT
SW
65
60
55
50
45
40
35
30
25
20
15
10
5
= 400kHz
unbrokengroundplanebelowthesecomponents. TheSW
and BOOST nodes should be as small as possible. Finally,
keep the FB and RT nodes small so that the ground traces
will shield it from the SW and BOOST nodes. The exposed
pad on the bottom of the package must be soldered to
ground so that the pad acts as a heat sink. To keep thermal
resistance low, extend the ground plane as much as pos-
sible, and add thermal vias under and near the LT3976 to
additional ground planes within the circuit board and on
the bottom side.
2.5in × 2.5in 4-LAYER BOARD
12V
24V
36V
0
1
2
3
4
5
OUTPUT CURRENT (A)
3976 F11a
High Temperature Considerations
Figure 11a. Temperature Rise of the LT3976 in
the Front Page Application
For higher ambient temperatures, care should be taken in
the layout of the PCB to ensure good heat sinking of the
LT3976. The exposed pad on the bottom of the package
must be soldered to a ground plane. This ground should
be tied to large copper layers below with thermal vias;
these layers will spread the heat dissipated by the LT3976.
Placing additional vias can reduce the thermal resistance
further.Whenoperatingathighambienttemperatures,the
maximum load current should be derated as the ambient
temperature approaches the maximum junction rating.
(See Thermal Derating curve in the Typical Performance
Characteristics section.)
90
V
f
= 5V
OUT
SW
= 800kHz
80
70
60
50
40
30
20
10
0
2.5in × 2.5in 4-LAYER BOARD
12V
24V
36V
1
2
3
4
5
Power dissipation within the LT3976 can be estimated by
calculatingthetotalpowerlossfromanefficiencymeasure-
ment and subtracting the catch diode loss and inductor
loss. The die temperature is calculated by multiplying the
OUTPUT CURRENT (A)
3976 F11b
Figure 11b. Temperature Rise of the LT3976 in a
5VOUT Application
3976f
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Fault Tolerance of QFN Package
If the output voltage is less than 6V, then the application
circuit can be setup normally (see Figure 12a) because a
SS to OUT short will not violate the SS pin 6V absolute
maximum and a PG short to either RT or SYNC will not
violate the 6V absolute maximum on each of those pins.
TheQFNpackageisdesignedtotoleratesinglefaultcondi-
tions. Shorting two adjacent pins together or leaving one
singlepinfloatingdoesnotraisetheoutputvoltageorcause
damagetotheLT3976regulator. However, theapplication
circuit must meet a few requirements discussed in this
section in order to achieve this fault tolerance.
If the output voltage is greater than 6V, the best way to
solve the problem of violating the SS absolute maximum
when shorted to OUT is to tie the OUT pin to GND. Note
that grounding the OUT pin will compromise the dropout
performance of the LT3976. When OUT is grounded, an
Tables 5 and 6 show the effects that result from shorting
adjacent pins or from a floating pin, respectively.
Therearethreeitemswhichrequireconsiderationinterms
of the application circuit to achieve fault tolerance: SS-
OUT pin short, RT-PG pin short, and PG-SYNC pin short.
external Schottky diode to either the output, V , or an-
IN
other voltage source must be used to charge the boost
capacitor. The PG pull-up resistor must be increased
Table 5. Effects of Pin Shorts
PINS
EFFECT
SS-OUT
V
may fall below regulation voltage for V
less than or equal to 6V. For outputs above 6V, the absolute maximum of the SS pin
OUT
OUT
would be violated, so the OUT pin must be tied to GND (see discussion in the Fault Tolerance section)
V -EN
IN
No effect. In most applications, EN is tied to V . If EN is driven with a logic signal, the customer must ensure that the circuit generating
IN
that signal can withstand the maximum V
IN
RT-PG
No effect if PG is floated. V
will fall below regulation if PG is connected to the output with a resistor pull-up as long as the resister
OUT
divider formed by the PG pin pull-up and the RT resistor prevents the RT pin absolute maximum from being violated (see discussion in
the Fault Tolerance section). In both cases, the switching frequency will be significantly increased if the output goes below regulation,
which may cause the LT3976 to go into pulse-skipping mode if the minimum on-time is violated.
PG-SYNC
No effect if PG is floated. No effect if PG is connected to the output with a resistor pull-up as long as there is a resistor to GND on the
SYNC pin or the SYNC pin is tied to GND. This is to ensure that the resistor divider formed by the PG pin pull-up and the SYNC pin
resistor to GND prevents the SYNC pin Absolute Maximum from being violated (see discussion in the Fault Tolerance section).
Table 6. Effects of Floating Pins
PIN
SS
EFFECT
No effect; soft-start feature will not function.
700
600
500
400
300
200
100
0
0
0.2
0.4
0.6
0.8
1
1.2
F
B
P
I
N
V
O
L
T
A
G
E
(
V
)
3
9
7
6
G
2
2
OUT
V
may fall below regulation voltage. With the OUT pin disconnected, the boost capacitor cannot be charged and thus the power
OUT
switch cannot fully saturate, which increases power dissipation.
V may fall below regulation voltage. With the BOOST pin disconnected, the boost capacitor cannot be charged and thus the power
OUT
BOOST
switch cannot fully saturate, which increases power dissipation.
SW
No effect; there are several SW pins.
V
No effect; there are several V pins.
IN
IN
EN
V
may fall below regulation voltage. Part may work normally or be shutdown depending on how the application circuit couples to the
OUT
floating EN pin.
V may fall below regulation voltage.
OUT
RT
PG
No effect.
SYNC
No effect. The LT3976 may be in Burst Mode operation or pulse-skipping mode depending on how the application circuit couples to the
floating SYNC pin.
FB
No effect; there are two FB pins.
GND
No effect; there are several GND connections. If Exposed Pad is floated, thermal performance will be degraded.
3976f
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LT3976
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and a SYNC pin resistor to GND added, so that a PG pin
short to either SYNC or RT will form resistor dividers to
keep the voltage on the SYNC and RT pins below their
rated absolute maximum. This application is shown in
Figure 12b. The external Schottky must be connected
such that the absolute maximum of the BOOST pin is not
violated. The SYNC pin resistor can be removed if the
SYNC pin is grounded or PG is left floating both of which
also result in fault tolerant circuits.
Other Linear Technology Publications
Application Notes 19, 35 and 44 contain more detailed
descriptions and design information for buck regulators
and other switching regulators. The LT1376 data sheet
has a more extensive discussion of output ripple, loop
compensation and stability testing. Design Note 318
shows how to generate a bipolar output supply using a
buck regulator.
V
IN
0.47µF
V
IN
BOOST
3.3µH
EN
SW
EXTERNAL
INPUT
2Ω
SYNC
150k
470pF
1M
LT3976
10µF
PGOOD
PG
OUT
SS
RT
FB
V
OUT
10nF
GND
47µF
1210
×2
34.9k
316k
10pF
3976 F12a
f = 800kHz
Figure 12a. Fault Tolerant for VOUT < 6V
(Note: For VOUT < 3.3V External Boost Schottky Diode Is Needed)
V
IN
0.47µF
3.3µH
V
BOOST
SW
IN
EN
EXTERNAL
INPUT
2Ω
470pF
SYNC
249k
LT3976
10µF
40.2k
PGOOD
PG
SS
RT
OUT
1M
FB
V
OUT
10nF
GND
47µF
1210
×2
54.9k
316k
10pF
3976 F12b
f = 800kHz
Figure 12b. Fault Tolerant for VOUT < 27V
(Note: For VOUT < 3V External Boost Schottky Diode
Should Be Connected to the Input)
Figure 12. Two Example Circuits to Achieve Fault Tolerance (FMEA) with the LT3976 QFN Package
3976f
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LT3976
Typical applicaTions
5V Step-Down Converter
12V Step-Down Converter
V
V
IN
13.2V* TO 40V
IN
6V* TO 40V
V
IN
V
IN
OFF ON
EN
PG
BOOST
SW
OFF ON
EN
PG
BOOST
SW
3.3µH
6.8µH
0.47µF
2Ω
0.47µF
10µF
10µF
2Ω
470pF
LT3976
LT3976
470pF
SS
RT
OUT
FB
SS
RT
OUT
FB
V
5V
5A
1M
V
12V
5A
1M
OUT
OUT
10pF
10pF
SYNC
GND
SYNC
GND
10nF
10nF
47µF
1210
×2
47µF
1210
54.9k
316k
54.9k
110k
3976 TA02
3976 TA03
f = 800kHz
D = PDS540
L = IHLP-2525CZ-01
f = 800kHz
D = PDS540
L = IHLP-4040DZ-01
* MINIMUM V CAN BE LOWERED WITH ADDITIONAL
IN
INPUT AND OUTPUT CAPACITANCE.
* MINIMUM V CAN BE LOWERED WITH ADDITIONAL
IN
INPUT AND OUTPUT CAPACITANCE.
5V, 2MHz Step-Down Converter with Power Good
4V Step-Down Converter with a High Impedance Input Source
V
IN
5.9V TO 18V
(40V TRANSIENTS)
+
0.47µF
1.5µH
BOOST
SW
V
IN
V
V
24V
IN
5.49M
499k
OFF ON
EN
PG
EN
BOOST
SW
–
3.3µH
0.47µF
150k
+
2Ω
470pF
C
BULK
2Ω
470pF
4.7µF
100µF
LT3976
LT3976
PGOOD
PG
OUT
SS
RT
OUT
FB
SS
RT
V
4V
5A
1M
OUT
V
1M
OUT
5V
5A
FB
10pF
10pF
SYNC
GND
10µF
47nF
SYNC
GND
10nF
47µF
1210
×2
54.9k
432k
47µF
1210
14.7k
316k
3976 TA05
3976 TA04
f = 800kHz
f = 2MHz
D = PDS540
L = IHLP-2525CZ-01
D = PDS540
L = IHLP-2525CZ-01
2.5V Step-Down Converter
1.8V Step-Down Converter
DFLS160
DFLS160
V
IN
4.3V TO 27V
V
IN
4.3V TO 40V
V
BOOST
SW
V
IN
IN
0.47µF
OFF ON
EN
OFF ON
EN
PG
BOOST
SW
3.3µH
2.2µH
0.47µF
PG
10µF
×2
10µF
2Ω
470pF
2Ω
470pF
LT3976
LT3976
SS
RT
OUT
FB
SS
RT
OUT
FB
V
2.5V
5A
V
1.8V
5A
1M
4.7pF
499k
10pF
OUT
OUT
SYNC
GND
SYNC
GND
10nF
10nF
47µF
1210
×4
47µF
1210
×4
130k
909k
97.6k
1M
3976 TA06
3976 TA07
f = 400kHz
f = 500kHz
D = PDS540
L = IHLP-2525CZ-01
D = PDS540
L = IHLP-2525CZ-01
3976f
25
For more information www.linear.com/3976
LT3976
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MSE Package
16-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1667 Rev E)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
(.112 ±.004)
2.845 ±0.102
(.112 ±.004)
0.889 ±0.127
(.035 ±.005)
1
8
0.35
REF
5.23
(.206)
MIN
1.651 ±0.102
(.065 ±.004)
1.651 ±0.102
(.065 ±.004)
3.20 – 3.45
(.126 – .136)
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
DETAIL “B”
16
9
0.305 ±0.038
0.50
(.0197)
BSC
NO MEASUREMENT PURPOSE
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
(.0120 ±.0015)
TYP
0.280 ±0.076
(.011 ±.003)
RECOMMENDED SOLDER PAD LAYOUT
16151413121110
9
REF
DETAIL “A”
0.254
(.010)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0° – 6° TYP
4.90 ±0.152
(.193 ±.006)
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
1 2 3 4 5 6 7 8
DETAIL “A”
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 ±0.0508
(.004 ±.002)
MSOP (MSE16) 0911 REV E
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
3976f
26
For more information www.linear.com/3976
LT3976
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UDD Package
24-Lead Plastic QFN (3mm × 5mm)
(Reference LTC DWG # 05-08-ꢀ833 Rev Ø)
0.70 0.05
3.50 0.05
2.ꢀ0 0.05
ꢀ.50 REF
3.65 0.05
ꢀ.65 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
3.50 REF
4.ꢀ0 0.05
5.50 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN ꢀ NOTCH
R = 0.20 OR 0.25
0.75 0.05
× 45° CHAMFER
ꢀ.50 REF
23
R = 0.05 TYP
3.00 0.ꢀ0
24
0.40 0.ꢀ0
PIN ꢀ
TOP MARK
(NOTE 6)
ꢀ
2
3.65 0.ꢀ0
ꢀ.65 0.ꢀ0
5.00 0.ꢀ0
3.50 REF
(UDD24) QFN 0808 REV Ø
0.200 REF
0.00 – 0.05
0.25 0.05
0.50 BSC
R = 0.ꢀꢀ5
TYP
BOTTOM VIEW—EXPOSED PAD
NOTE:
ꢀ. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3976f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
27
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT3976
Typical applicaTion
1.2V Step-Down Converter
DFLS160
V
IN
4.3V TO 27V
(40V TRANSIENT)
3.3V
V
IN
OFF ON
EN
PG
BOOST
SW
2.2µH
0.47µF
10µF
2Ω
470pF
LT3976
SS
RT
OUT
FB
V
1.2V
5A
OUT
SYNC
GND
10nF
47µF
1210
×4
130k
3976 TA08
f = 400kHz
D = PDS540
L = IHLP-2525CZ-01
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
= 3.6V to 38V, Transients to 60V, V
LT3480
LT3980
LT3971
LT3991
LT3970
LT3990
36V with Transient Protection to 60V, 2A (I ), 2.4MHz, High
V
= 0.78V,
OUT(MIN)
OUT
IN
Efficiency Step-Down DC/DC Converter with Burst Mode® Operation I = 70µA, I < 1µA, 3mm × 3mm DFN-10, MSOP-10E
Q
SD
58V with Transient Protection to 80V, 2A (I ), 2.4MHz, High
Efficiency Step-Down DC/DC Converter with Burst Mode Operation
V
Q
= 3.6V to 58V, Transients to 80V, V
= 0.79V,
OUT
IN
OUT(MIN)
I = 75µA, I < 1µA, 3mm × 4mm DFN-16, MSOP-16E
SD
38V, 1.2A (I ), 2MHz, High Efficiency Step-Down
V
= 4.2V to 38V, V
= 1.2V, I = 2.8µA, I < 1µA,
OUT
IN
OUT(MIN) Q SD
DC/DC Converter with Only 2.8µA of Quiescent Current
3mm × 3mm DFN-10, MSOP-10E
55V, 1.2A (I ), 2MHz, High Efficiency Step-Down
V
= 4.2V to 55V, V
= 1.2V, I = 2.8µA, I < 1µA,
OUT
IN
OUT(MIN) Q SD
DC/DC Converter with Only 2.8µA of Quiescent Current
3mm × 3mm DFN-10, MSOP-10E
V = 4.2V to 40V, V = 1.2V, I = 2.5µA, I < 0.7µA,
IN
40V, 350mA (I ), 2MHz, High Efficiency Step-Down
OUT
OUT(MIN)
Q
SD
DC/DC Converter with Only 2.5µA of Quiescent Current
2mm × 3mm DFN-10, MSOP-10E
V = 4.2V to 62V, V = 1.2V, I = 2.5µA, I < 0.7µA,
IN
62V, 350mA (I ), 2.2MHz, High Efficiency Step-Down
OUT
OUT(MIN)
Q
SD
DC/DC Converter with Only 2.5µA of Quiescent Current
3mm × 3mm DFN-10, MSOP-16E
3976f
LT 0113 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
LINEAR TECHNOLOGY CORPORATION 2013
(408)432-1900 FAX: (408) 434-0507 www.linear.com/3976
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