LT4180IGN#TRPBF [Linear]
LT4180 - Virtual Remote Sense Controller; Package: SSOP; Pins: 24; Temperature Range: -40°C to 85°C;
| 型号： | LT4180IGN#TRPBF |
| 厂家： | 
Linear |
| 描述： | LT4180 - Virtual Remote Sense Controller; Package: SSOP; Pins: 24; Temperature Range: -40°C to 85°C 光电二极管 |
| 文件： | 总18页 (文件大小：346K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT4180
Virtual Remote Sense
Controller
FeaTures
DescripTion
The LT®4180 solves the problem of providing tight load
regulation over long, highly resistive cables without
requiring an additional pair of remote sense wires. This
Virtual Remote Sense™ device continuously interrogates
the line impedance and corrects the power supply output
voltage via its feedback loop to maintain a steady voltage
at the load regardless of current changes.
n
Tight Load Regulation with Highly Resistive Cables
without Requiring Remote Sense Wiring
n
Compatible with Isolated and Nonisolated Power
Supplies
n
1ꢀ Internal Voltage Reference
n
5mA Sink Current Capability
n
Soft-Correct Reduces Turn-On Transients
n
Undervoltage and Overvoltage Protection
The LT4180 is a full-featured controller with 5mA opto-
isolator sink capability, under/overvoltage lockout,
soft-start and a 1ꢀ internal voltage reference. The
Virtual Remote Sense feature set includes user-program-
mable dither frequency and optional spread spectrum
dither.
n
Pin-Programmable Dither Frequency
n
Optional Spread Spectrum Dither
n
Wide V Range: 3.1V to 50V
IN
n
24-Lead SSOP Package
applicaTions
The LT4180 works with any topology and type of isolated
or nonisolated power supply, including DC/DC converters
and adjustable linear regulators.
n
12V High Intensity Lamps
n
28V Industrial Systems
n
High Power (>40 Watts) CAT5 Cable Systems
Wiring Drop Cancellation for Notebook Computer
Battery Charging
AC and DC Adaptors
Well-Logging and Other Remote Instrumentation
Surveillance Equipment
n
The LT4180 is available in a 24-lead, SSOP package.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
Virtual Remote Sense is a trademark of Linear Technology Corporation. All other trademarks
are the property of their respective owners.
n
n
n
Typical applicaTion
Isolated Power Supply with Virtual Remote Sense
VLOAD vs VWIRE
5.00
4.99
4.98
4.97
4.96
4.95
CAT5E CABLE
R
SENSE
LINE
LINE
+
C
L
R
L
SWITCHING
REGULATOR
V
C
V
SENSE DIV0 DIV1 DIV2 SPREAD CHOLD1 CHOLD2 CHOLD3 CHOLD4
LT4180
4.94
4.93
4.92
4.91
IN
–
DRAIN
COMP
R
OSC
C
OSC
VIRTUAL REMOTE SENSE
OV
RUN FB
4180 TA01a
0
0.5
1
1.5
2
2.5
3
V
(V)
WIRING
4180 TAO1b
4180fb
1
For more information www.linear.com/4180
LT4180
absoluTe MaxiMuM raTings
pin conFiguraTion
(Note 1)
TOP VIEW
V ............................................................. –0.3V to 52V
IN
SENSE.......................................................V – 0.3V to V
1
2
V
V
24
23
22
21
20
19
18
17
16
15
14
13
INTV
CC
IN
IN
IN
DRAIN
COMP
INTVCC, RUN, FB, OV, ROSC, OSC,
DIV0, DIV1, DIV2, SPREAD, CHOLD1,
PP
3
SENSE
RUN
4
CHOLD1
GUARD2
CHOLD2
GUARD3
CHOLD3
GUARD4
CHOLD4
FB
CHOLD2, CHOLD3, CHOLD4, DRAIN, COMP,
5
OV
GUARD2, GUARD3, GUARD4, V ............ –0.3V to 5.5V
PP
6
SPREAD
DIV0
DIV1
DIV2
OSC
V Pin Current.......................................................10mA
IN
7
INTVCC Pin Current .............................................–10mA
COSC Pin Current..................................................3.3mA
Maximum Junction Temperature .......................... 125°C
Operating Junction Temperature Range (Note 2)
E-, I-Grades ....................................... –40°C to 125°C
MP-Grade .......................................... –55°C to 125°C
Storage Temperature Range .................. –65°C to 125°C
8
9
10
11
12
ROSC
COSC
GND
GN PACKAGE
24-LEAD NARROW PLASTIC SSOP
T
= 150°C, θ = 85°C/W
JA
JMAX
orDer inForMaTion
LEAD FREE FINISH
LT4180EGN#PBF
LT4180IGN#PBF
LT4180MPGN#PBF
TAPE AND REEL
PART MARKING*
LT4180GN
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
LT4180EGN#TRPBF
LT4180IGN#TRPBF
LT4180MPGN#TRPBF
24-Lead Narrow Plastic SSOP
24-Lead Narrow Plastic SSOP
24-Lead Narrow Plastic SSOP
LT4180GN
–40°C to 125°C
LT4180GN
–55°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = SENSE = 5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
50
UNITS
V
l
l
V
IN
Operating Supply Voltage
Input Quiescent Current
Reference Voltage
3.10
IV
ROSC Open, COSC Open, SENSE = V
1
2
mA
IN
IN
V
REF
V
= V
CHOLD3
= 1.2V, Measured at CHOLD4
Clock Phase
1.209
1.197
1.221
1.221
1.233
1.245
V
V
CHOLD2
l
During Track ∆V
OUT
I
Open-Drain Current Limit
With FB = V + 200mV, OSC Stopped with
5
12
17
mA
LIM
REF
Voltage Feedback Loop Closed
V
V
DRAIN Low Voltage
V
V
= 3V
= 5V
0.3
V
V
OL
IN
IN
LDO Regulator Output Voltage
3.15
INTVCC
4180fb
2
For more information www.linear.com/4180
LT4180
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = SENSE = 5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
= 2.5V
MIN
TYP
MAX
UNITS
V
LDO Regulator Output Voltage in
Dropout
V
2.2
V
INTVCC
IN
V
V
V
V
Overvoltage Threshold
Overvoltage Input Hysteresis
Run Threshold
Rising
1.21
1.21
V
mV
V
OV
V
– V
– V
15
80
OHYST
RUN
RISING
FALLING
FALLING
Falling
Run Input Hysteresis
V
15
–0.2
0.891
–1
80
0.2
mV
µA
RHYST
RISING
I
Input Bias Current
FB
A
Current Amplifier Gain Ratio
Current Amplifier Input Bias Current
A
/A , A Measured in V/V
VL VH
0.9
0.909
1
V(RATIO)
SENSE
V
I
Measured at SENSE with SENSE = V
µA
V/V
µA
IN
A
∆V Amplifier Gain
FB
9.7
10
60
25
25
10
10.3
V
I
I
I
I
Track/Hold Charging Current
Track/Hold Charging Current
Track/Hold Charging Current
Track/Hold Charging Current
Measured at CHOLD1 with V
Measured at CHOLD2 with V
Measured at CHOLD3 with V
Measured at CHOLD4 with V
= 1.2V
= 1.2V
= 1.2V
= 1.5V,
CHOLD1
CHOLD2
CHOLD3
CHOLD4
CHOLD1
CHOLD2
CHOLD3
CHOLD4
µA
µA
µA
V
= 1V, V
= 1.2V
CHOLD3
CHOLD2
Measured at CHOLD4 with V
CHOLD2
= 1.5V,
–200
µA
CHOLD4
V
= 1.4V, V
= 1.2V
CHOLD3
I
I
I
I
I
f
Soft-Correct Current
Measured at CHOLD4
1.5
1
µA
µA
SC
Track/Hold Leakage Current
Track/Hold Leakage Current
Track/Hold Leakage Current
Track/Hold Leakage Current
Oscillator Frequency
Measured at CHOLD1 with V
Measured at CHOLD2 with V
Measured at CHOLD3 with V
Measured at CHOLD4 with V
= 1.2V
= 1.2V
= 1.2V
= 1.2V
LKG1
LKG2
LKG3
LKG4
OSC
CHOLD1
CHOLD2
CHOLD3
CHOLD4
1
µA
1
µA
1
µA
R
= 20k, C
= 1nF
170
200
120
230
kHz
µmho
OSC
OSC
g
Voltage Error Amplifier
Transconductance
Measured from FB to COMP, V
OSC Stopped with Voltage Feedback Loop Closed
= 2V,
COMP
mFB
g
Current Amplifier Transconductance
Measured from SENSE to COMP, V
= 2V,
COMP
700
µmho
mIAMP
OSC Stopped with Current Feedback Loop Closed
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
to 125°C operating junction temperature range are assured by design
characterization and correlation with statistical process controls. The
LT4180I is guaranteed over the full –40°C to 125°C operating junction
temperature range. The LT4180MP is guaranteed over the full –55°C to
125°C operating junction temperature range.
Note 2. The LT4180E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
Note 3. Positive current is defined as flowing into a pin.
4180fb
3
For more information www.linear.com/4180
LT4180
Typical perForMance characTerisTics
Oscillator Frequency
vs Temperature
V
REF vs Temperature
INTVCC vs Temperature
204.0
203.5
203.0
202.5
202.0
201.5
1.2215
1.2210
1.2205
3.165
3.160
3.155
3.150
3.145
3.140
3.135
R
= 20k
= 1nF
OSC
OSC
C
1.2200
1.2195
1.2190
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4108 G03
4108 G01
4108 G02
IDRAIN vs VDRAIN
Normal Timing
Spread Spectrum Timing
14
12
500mV/DIV
500mV/DIV
C
C
HOLD1
HOLD1
WITH 15k
WITH 15k
10
PULL-DOWN
PULL-DOWN
8
6
4
2
2V/DIV
OSC
2V/DIV
OSC
4180 G05
4180 G06
5µs/DIV
1µs/DIV
TRIGGERED ON CHOLD1
TRIGGERED ON OSC
0
0.2 0.3 0.4 0.5 0.6
0.7 0.8 0.9
1
0
0.1
V
(V)
DRAIN
4180 G04
Load Step in
12V Linear Application
VLOAD vs VWIRE
Load Step in Buck Application
5.00
4.99
4.98
4.97
4.96
4.95
4.94
4.93
4.92
4.91
V
V
SENSE
SENSE
2V/DIV
2V/DIV
V
LOAD
V
LOAD
2V/DIV
2V/DIV
500mA
1.5A
I
LOAD
200mA
I
200mA/DIV
LOAD
500mA/DIV
500mA
R
= 8Ω
WIRE
R
= 2.5Ω
4180 G09
WIRE
4180 G08
5ms/DIV
10ms/DIV
200mA TO 500mA LOAD TRANSIENT
100µF LOAD CAP
500mA TO 1.5A LOAD TRANSIENT
470µF LOAD CAP
0
0.5
1
1.5
2
2.5
3
V
(V)
WIRING
4180 G07
4180fb
4
For more information www.linear.com/4180
LT4180
pin FuncTions
INTV (Pin 1): The LDO Output. A low ESR ceramic
VirtualRemoteSense.Thisisahighcurrentoutputcapable
of driving opto-isolators. Other isolation methods may
also be used with this output.
CC
capacitor provides decoupling and output compensation.
1µF or more should be used.
DRAIN (Pin 2): Open-Drain of the Output Transistor. This
pin drives either the LED in an opto-isolator, or pulls down
on the regulator control pin.
DIV2 (Pin 16): Dither Division Ratio Programming Pin.
DIV1 (Pin 17): Dither Division Ratio Programming Pin.
DIV0 (Pin 18): Dither Division Ratio Programming Pin.
Use the following table to program the dither division
COMP(Pin3):GateoftheOutputTransistor.Thispinallows
additional compensation. It must be left open if unused.
ratio (f /f
)
OSC DITHER
CHOLD1 (Pin 4): Connects to track/hold amplifier hold
capacitor. The other end of this capacitor should be Kelvin
connected to GND.
Table 1. Programming the Dither Division Ratio (fOSC/fDITHER
)
DIV2
DIV1
DIV0
DIVISION RATIO
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
16
GUARD2 (Pin 5): Guard Ring Drive for CHOLD2.
CHOLD2 (Pin 6): Connects to track/hold amplifier hold
capacitor. The other end of this capacitor should be Kelvin
connected to GND.
32
64
128
256
512
1024
GUARD3 (Pin 7): Guard Ring Drive for CHOLD3.
CHOLD3 (Pin 8): Connects to track/hold amplifier hold
capacitor. The other end of this capacitor should be Kelvin
connected to GND.
For example, f
= DIV0 = 0.
= f
/128 with DIV2 = 1 and DIV1
OSC
DITHER
GUARD4 (Pin 9): Guard Ring Drive for CHOLD4.
CHOLD4 (Pin 10): Connects to track/hold amplifier hold
capacitor. The other end of this capacitor should be Kelvin
connected to GND.
SPREAD (Pin 19): Spread Spectrum Enable Input. Dither
phasing is pseudo-randomly adjusted when SPREAD is
tied high.
FB (Pin 11): Receives the feedback voltage from an exter-
nal resistor divider across the main output. An (optional)
capacitor to ground may be added to eliminate high
frequency noise. The time constant for this RC network
should be no greater than 0.1 times the dither frequency.
OV(Pin20):OvervoltageComparatorInput.Thisprevents
line drop correction when wiring drops would cause ex-
cessive switching power supply output voltage. Set OV
so V
≤ 1.50V
.
REG(MAX)
LOAD
For example, with f
= 1kHz, t = 0.1ms.
DITHER
RUN (Pin 21): The RUN pin provides the user with an ac-
curate means for sensing the input voltage and program-
ming the start-up threshold for the line drop corrector.
GND (Pin 12): Ground.
COSC (Pin 13): Oscillator Timing Capacitor. Oscillator
frequency is set by this capacitor and ROSC. For best ac-
curacy,theminimumrecommendedcapacitanceis100pF.
SENSE (Pin 22): Current Sense Input. This input connects
to the current sense resistor. Kelvin connect to R
.
SENSE
V
(Pin 23): Connect this pin to INTV .
CC
ROSC (Pin 14): Oscillator Timing Resistor. Oscillator
frequency is set by this resistor and COSC.
PP
V (Pin24):MainSupplyPin.V mustbelocallybypassed
IN
IN
to ground. Kelvin connect the current sense resistor to
this pin and minimize interconnect resistance.
OSC (Pin 15): Oscillator Output. This output may be
used to synchronize the switching regulator to the
4180fb
5
For more information www.linear.com/4180
LT4180
block DiagraM
1
22
SENSE
23
V
PP
V
INTV
IN
CC
24
12
4
–
AMP
+
HI_GAIN
I
TRIM
CIRCUIT
LDO
REF_OK
GND
BANDGAP
REF
TRACK/
HOLD
TRACK_HI_I
CHOLD1
–
+
SPREAD
DIV0
19
18
17
16
GM1
FB
+
11
5
SPREAD
SPECTRUM
CLOCK
DIV1
GM2
–
INST
AMP
GUARD2
FB_SELECT
DIV2
TRACK/
HOLD
GENERATOR
+
–
CORRECTED _REF
TRACK_DELTA_FB
TRACK/
HOLD
CHOLD2
CHOLD3
GUARD3
TRACK/
HOLD
6
8
7
REF
TRACK_LOW_FB
TRACK_HI_FB
CHOLD4
COMP
10
3
CLK
MOD
GUARD4
9
OSC
OSC
15
DRAIN
OV
2
R
LIM
20
+
OVERVOLTAGE
OV
–
RUN
21
–
UNDERVOLTAGE
UV
+
COSC
14 13
ROSC
4180 BD
4180fb
6
For more information www.linear.com/4180
LT4180
operaTion
Voltage drops in wiring can produce considerable load
loop is then switched to a current regulating control loop
and the output current is changed by 10ꢀ. Two sample-
and-holdcurrentsstorethevoltageatthehighcurrentand
low current level of the modulation. This voltage change
is the result of a 10ꢀ change in current, making the volt-
age change 10ꢀ of the total drop in the line. The voltage
change is amplified by a factor of 10.
regulation errors in electrical systems (Figure 1). As
load current, I , increases the voltage drop in the wiring
L
(I • RW) increases and the voltage delivered to the sys-
L
tem (V ) drops. The traditional approach to solving this
L
problem,remotesensing,regulatesthevoltageattheload,
increasingthepowersupplyvoltage(V )tocompensate
OUT
for voltage drops in the wiring. While remote sensing
works well, it does require an additional pair of wires to
measure at the load, which may not always be practical.
The amplified voltage change that occurs with the current
is again sampled and held and is used as the correction
voltage. The correction voltage is summed into the output
and this corrects for the line drop. Since this correction
is actually open-loop, the actual voltage at the load is not
measured. The ability of the LT4180 to correct for line
dropsisdependentupontheaccuracyofthecomputations.
The LT4180 eliminates the need for a pair of remote sense
wires by creating a Virtual Remote Sense. Virtual remote
sensing is achieved by measuring the incremental change
involtagethatoccurswithanincrementalchangeincurrent
in the wiring (Figure 2). This measurement can then be
used to infer the total DC voltage drop in the wiring, which
can then be compensated for. The Virtual Remote Sense
takes over control of the power supply via the feedback
The LT4180 can correct better than 50 to 1 for line drops.
For example, a 10V drop in the line becomes a 200mV
change at the load.
pin (V ) of the power supply maintaining tight regulation
The frequency of the correction cycle can be set from over
32kHz down to less than 250Hz, depending on the size of
the capacitors in the system. For very large capacitors in
highcurrentsystems, thedithercorrectionclockwouldbe
run more slowly. In simpler systems with smaller output
capacitors, the dither can be run at a higher frequency. If
the load contains frequencies similar to the dither, beat
notes can result between the load and the LT4180. A
spread spectrum option on the LT4180 allows the device
to change phasing during the correction cycle so that it
will not interfere with load pulses.
FB
of load voltage, V .
L
The LT4180 operates by modulating the output current of
the regulator and looking at the resulting voltage change.
A large output capacitor is placed across the load so the
AC impedance at the load is low. [Normally, a capacitor
appears across the load in remote sensing situations to
keep the impedance low at that point]. This capacitor is
large enough that the AC impedance at the load is very low
compared to the line resistance. When the output current
is modulated, any voltage change that appears across the
terminals of the LT4180 is due to the resistance in the line
since the AC resistance at the load is very low.
Finally, the LT4180 takes into account all resistances
between the LT4180 and the load capacitor. It can correct
for cable connections, line resistances and varying contact
resistances. By measuring the peak change at the output of
the LT4180 one can monitor the impedance between the
LT4180 and the load, and detect increasing impedances
There are four sample-and-hold capacitors in the LT4180.
The operation cycles through several stages to obtain the
correction voltage. First, the output voltage is regulated
and the control point is sampled and held. The control
I
L
I
L
RW
POWER SUPPLY
V
SYSTEM
RW
+
OUT
+
L
–
POWER SUPPLY
V
SYSTEM
+
OUT
+
L
–
V
POWER WIRING
V
POWER WIRING
–
V
FB
–
4180 F02
4180 F01
REMOTE SENSE WIRING
VIRTUAL REMOTE
SENSE
Figure 1. Traditional Remote Sensing
Figure 2. Virtual Remote Sensing
4180fb
7
For more information www.linear.com/4180
LT4180
operaTion
from degrading contacts. Making the capacitor larger can
minimize the voltage ripple at the load due to acombination
of load regulation and the dither frequency of the LT4180.
–10ꢀ change in output current has been measured and
is stored in the Virtual Remote Sense. This voltage is used
during the next Virtual Remote Sense cycle to compensate
for voltage drops due to wiring resistance.
Figure 3 shows the timing diagram for Virtual Remote
Sense. A new cycle begins when the power supply and
VirtualRemoteSenseclosethelooparoundV
(regulate
OUT
V
OUT
OUT
V
= H). Both V
and I
slew and settle to a new
OUT
OUT
OUT
REGULATE V
value, and these values are stored in the Virtual Remote
Sense (track V high = L and track I = L). The V
TRACK V
HIGH
OUT
OUT
OUT
OUT
TRACK I
OUT
feedback loop is opened and a new feedback loop is set
REGULATE I
TRACK V
LOW
LOW
OUT
up commanding the power supply to deliver 90ꢀ of the
OUT
previouslymeasuredcurrent(0.9I ).V dropstoanew
OUT
OUT
TRACK ∆V
value as the power supply reaches a new steady state, and
OUT
4180 F03
this information is also stored in the Virtual Remote Sense.
At this point, the change in output voltage (∆V ) for a
Figure 3. Simplified Timing Diagram, Virtual Remote Sense
OUT
applicaTions inForMaTion
INTRODUCTION
Isolated power supplies and regulators may also be used
by adding an opto-coupler (Figure 5). LT4180 output volt-
TheLT4180isdesignedtointerfacewithavarietyofpower
suppliesandregulatorshavingeitheranexternalfeedback
or control pin. In Figure 4, the regulator error amplifier
age INTV supplies power to the opto-coupler LED. In
CC
situations where the control pin V of the regulator may
C
exceed 5V, a cascode may be added to keep the DRAIN
pin of the LT4180 below 5V (Figure 6). Use a low VT
MOSFET for the cascode transistor.
(which is a g amplifier) is disabled by tying its inverting
m
input to ground. This converts the error amplifier into a
constant-current source which is then controlled by the
drain pin of the LT4180. This is the preferred method of
interfacingbecauseiteliminatestheregulatorerrorampli-
fier from the control loop which simplifies compensation
and provides best control loop response.
INTV
REGULATOR
CC
OPTO-COUPLER
+
V
C
LT4180
–
DRAIN
REGULATOR
LT4180
4180 F05
I
OR
TH
V
C
+
–
DRAIN
Figure 5. Isolated Power Supply Interface
4180 F04
TO V > 5V
C
Figure 4. Nonisolated Regulator Interface
COMP
LT4180
INTV
For proper operation, increasing control voltage should
correspond to increasing regulator output. For example,
in the case of a current mode switching power supply,
the control pin ITH should produce higher peak currents
as the ITH pin voltage is made more positive.
CC
DRAIN
4180 F06
Figure 6. Cascoded DRAIN Pin for Isolated Supplies
4180fb
8
For more information www.linear.com/4180
LT4180
applicaTions inForMaTion
DESIGN PROCEDURE
For example, if the power supply takes 1ms to settle
(worst-case) to within 1ꢀ of final value:
The first step in the design procedure is to determine
whethertheLT4180willcontrolalinearorswitchingsupply/
regulator. If using a switching power supply or regulator,
it is recommended that the supply be synchronized to the
LT4180 by connecting the OSC pin to the SYNC pin (or
equivalent) of the supply.
1
F1 =
= 500Hz
2 • 1e –3
Next, determine the propagation time of the wiring. In
order to ignore transmission line effects, the dither period
should be approximately twenty times longer than this.
This will limit dither frequency to:
If the power supply is synchronized to the LT4180, the
power supply switching frequency is determined by:
V
F
F2 =
Hz
4
fOSC
=
20 • 1.017ns/ft • L
ROSC • COSC
WhereV isthevelocityfactor(orvelocityofpropagation),
F
Recommended values for R
are between 20k and 100k
OSC
and L is the length of the wiring (in feet).
(with 30.1k the optimum for best accuracy) and greater
than 100pF for C . C may be reduced to as low as
For example, assume the load is connected to a power
supply with 1000ft of CAT5 cable. Nominal velocity of
propagation is approximately 70ꢀ.
OSC OSC
50pF, but oscillator frequency accuracy will be somewhat
degraded.
0.7
The following example synchronizes a 250kHz switching
power supply to the LT4180. In this example, start with
OSC
F2 =
= 34.4kHz
20 • 1.017e–9 • 1000
R
= 30.1k:
The maximum dither frequency should not exceed F1 or
F2 (whichever is less):
4
COSC
=
= 531pF
250kHz • 30.1k
f
< min (F1, F2).
DITHER
This example uses 470pF. For 250kHz:
4
Continuing this example, the dither frequency should be
less than 500Hz (limited by the power supply).
ROSC
=
= 34.04k
250kHz • 470pF
With the dither frequency known, the division ratio can
be determined:
The closest standard 1ꢀ value is 34k.
fOSC
fDITHER
250,000
500
DRATIO
=
=
= 500
The next step is to determine the highest practical dither
frequency. This may be limited either by the response
time of the power supply or regulator, or by the propaga-
tion time of the wiring connecting the load to the power
supply or regulator.
The nearest division ratio is 512 (set DIV0 = L, DIV1 =
DIV2 = H). Based on this division ratio, nominal dither
frequency will be:
First determine the settling time (to 1ꢀ of final value)
of the power supply. The settling time should be the
fOSC
DRATIO
250,000
512
fDITHER
=
=
= 488Hz
worst-case value (over the whole operating envelope: V ,
IN
I , etc.).
LOAD
After the dither frequency is determined, the minimum
load decoupling capacitor can be determined. This load
capacitor must be sufficiently large to filter out the dither
signal at the load.
1
F1 =
Hz
2 • tSETTLING
4180fb
9
For more information www.linear.com/4180
LT4180
applicaTions inForMaTion
NPO ceramic or other capacitors with low leakage and di-
electricabsorptionshouldbeusedforallHOLDcapacitors.
2.2
CLOAD
=
RWIRE • 2 • fDITHER
Set CHOLD4 to 1µF. This value will be adjusted later.
WhereC
WIRE
tor of the wiring pair, and f
frequency.
istheminimumloaddecouplingcapacitance,
LOAD
R
is the minimum wiring resistance of one conduc-
Compensation
is the minimum dither
DITHER
Start with a 47pF capacitor between the COMP and DRAIN
pins of the LT4180. Add an RC network in parallel with the
47pF capacitor, 10k and 10nF are good starting values.
Once the output voltage has been confirmed to regulate at
thedesiredlevelatnoload, increasetheloadcurrenttothe
100ꢀ level and monitor the wire current (dither current)
with a current probe. Verify the dither current resembles
a square wave with the desired dither frequency.
Continuing the example, our CAT5 cable has a maximum
9.38Ω/100m conductor resistance.
Maximum wiring resistance is:
R
WIRE
R
WIRE
= 2 • 1000ft • 0.305m/ft • 0.0938Ω/m
= 57.2Ω
With an oscillator tolerance of 15ꢀ, the minimum
dither frequency is 414.8Hz, so the minimum decoupling
capacitance is:
If the output voltage is too low, increase the value of the
10kresistoruntilsomeovershootisobservedattheleading
edge of the dither current waveform. If the output voltage
is still too low, decrease the value of the 10nF capacitor
and repeat the previous step. Repeat this process until the
full load output voltage increases to within 1ꢀ below the
no load level. Refer to Figures 7a, 7b and 7c, which show
compensation of the 12V 1.5A buck regulator Typical Ap-
plication on the data sheet. Check for proper voltage drop
correction over the load range. The dither current should
have good half-wave symmetry. Namely, the waveform
shouldhavesimilarriseandfalltimes,enoughsettlingtime
at top and bottom and minimum to no over/undershoot.
2.2
CLOAD
=
= 46.36µF
57.2Ω • 2 • 414.8Hz
This is the minimum value. Select a nominal value to ac-
count for all factors which could reduce the nominal, such
as initial tolerance, voltage and temperature coefficients
and aging.
CHOLD Capacitor Selection and Compensation
CHOLD1
A 47nF capacitor will suffice for most applications. A
smaller value might allow faster recovery from a sudden
load change, but care must be taken to ensure full load
p-p ripple at this node is kept within 5mV:
V
LOAD
11.2V
I
DITHER
50mA/DIV
2.5nF
CHOLD2 = CHOLD3 =
fDITHER(kHz)
4180 F07a
20µs/DIV
For a dither frequency of 488Hz:
2.5nF
Figure 7a. Dither Current and VOUT with
10nF, 10k Compensation 1.5A Load
CHOLD2 = CHOLD3 =
= 5.12nF
0.488(kHz)
4180fb
10
For more information www.linear.com/4180
LT4180
applicaTions inForMaTion
V
V
LOAD
1V/DIV
LOAD
11.9V
I
I
DITHER
DITHER
500mA/DIV
500mA/DIV
4180 F07b
4180 F08b
20µs/DIV
Figure 8b. 500mA to 1A Transient Response Test
with CHOLD4 = 47nF Nicely Damped Behavior
Figure 7b. Dither Current and VOUT with
10nF, 37k Compensation 1.5A Load
After all the CHOLD values have been finalized, check for
proper voltage drop correction and converter behavior
(start-up, regulation, etc.), over the load and input volt-
age ranges.
V
LOAD
11.9V
Setting Output Voltage, Undervoltage and Overvoltage
Thresholds
I
DITHER
50mA/DIV
The RUN pin has accurate rising and falling thresholds
whichmaybeusedtodeterminewhenVirtualRemoteSense
operation begins. Undervoltage threshold should never
be set lower than the minimum operating voltage of the
LT4180 (3.1V).
4180 F07c
20µs/DIV
Figure 7c. Dither Current and VOUT with
3.3nF, 28k Compensation 1.5A Load
The overvoltage threshold should be set slightly greater
than the highest voltage which will be produced by the
power supply or regulator:
Set Final Value of CHOLD4
Set the minimum value for CHOLD4, by performing a
transient load test of 30ꢀ to 60ꢀ of the load and set the
value of CHOLD4 to where a nicely damped waveform is
observed. Refer to Figures 8a and 8b for an illustration.
V
= V
+ V
LOAD(MAX) WIRE(MAX)
OUT(MAX)
V
should never exceed 1.5 • V
LOAD
OUT(MAX)
Since the RUN and OV pins connect to MOSFET input
comparators,inputbiascurrentsarenegligibleandacom-
mon voltage divider can be used to set both thresholds
(Figure 9).
V
LOAD
1V/DIV
I
DITHER
500mA/DIV
4180 F08a
10ms/DIV
Figure 8a. 500mA to 1A Transient Response
Test with CHOLD4 = 25nF CHOLD4 Too Small
4180fb
11
For more information www.linear.com/4180
LT4180
applicaTions inForMaTion
⎛
⎜
⎝
⎞
⎟
⎠
1.22V • 37.5k
V
IN
R
=
− 6.1k = 5.34k
R1
R2
R3
R4
SERIES
LT4180
4V
RUN
FB
R1 = 37.5k − 5.34k − 6.1k = 26.06k
⎛
⎜
⎝
⎞
⎟
⎠
OV
5V • 6.1k
1.22 V −
37.5k
4180 F09
R3 =
= 3.05k
5V
Figure 9. Voltage Divider for Output Voltage, UVL and OVL
37.5k
The voltage divider resistors can be calculated from the
following equations:
VOV
200µA
1.22V
200µA
R
SELECTION
RT =
, R4 =
SENSE
Select the value of R
so that it produces a 100mV
SENSE
voltage drop at maximum load current. For best accuracy,
IN
Where R is the total divider resistance and V is the
T
OV
V andSENSEshouldbeKelvinconnectedtothisresistor.
overvoltage set point.
Find the equivalent series resistance for R2 and R3 (R
IES
SER-
). This resistance will determine the RUN voltage level.
5V
POWER SUPPLY
OUTPUT VOLTAGE
⎛
⎜
⎝
⎞
⎟
⎠
1.22 • RT
RSERIES
=
−R4
VUVL
10Vw
POWER SUPPLY
INPUT VOLTAGE
R1=RT −RSERIES −R4
4180 F08
200ms/DIV
⎛
⎞
⎟
⎠
R4
RT
1.22V − V
•
Figure 10. Soft-Correct Operation, CHOLD4 = 1µF
⎜
OUT(NOM)
⎝
R3 =
VOUT(NOM)
Soft-Correct Operation
RT
The LT4180 has a soft-correct function which insures
orderly start-up. When the RUN pin rising threshold is
first exceeded (indicating V has crossed its undervolt-
age lockout threshold), power supply output voltage is set
to a value corresponding to zero wiring voltage drop (no
correction for wiring). Over a period of time (determined
by CHOLD4), the power supply output voltage ramps up
to account for wiring voltage drops, providing best load-
end voltage regulation. A new soft-correct cycle is also
initiated whenever an overvoltage condition occurs.
Where V
is the RUN voltage and V
is the
OUT(NOM)
UVL
IN
nominal output voltage desired.
For example, with V = 4V, V = 7.5V and V = 5V,
OUT(NOM)
UVL
OV
7.5V
R
=
= 37.5k
T
200µA
1.22V
R4 =
= 6.1k
200µA
4180fb
12
For more information www.linear.com/4180
LT4180
applicaTions inForMaTion
Using Guard Rings
REGULATOR
SYNC
LT4180
OSC
The LT4180 includes a total of four track/holds in the
Virtual Remote Sense path. For best accuracy, all leakage
sources on the CHOLD pins should be minimized.
4180 F12
Figure 12. Clock Interface for Synchronization
At very low dither frequencies, the circuit board layout
may include guard rings which should be tied to their
respective guard ring drivers.
Spread Spectrum Operation
To betterunderstandthepurposeofguardrings,asimplified
model of hold capacitor leakage (with and without guard
rings) is shown in Figure 11. Without guard rings, a large
difference voltage may exist between the hold capacitor
(Pin 1) node and adjacent conductors (Pin 2) producing
substantialleakagecurrentthroughtheleakageresistance
Virtual Remote Sense functionality relies on sampling
techniques. Because switching power supplies are com-
monly used, the LT4180 uses a variety of techniques to
minimize potential interference (in the form of beat notes
which may occur between the dither frequency and power
supply switching frequency). Besides several types of
internal filtering, and the option for Virtual Remote Sense/
power supply synchronization, the LT4180 also provides
spread spectrum operation.
(R ). By adding a guard ring driver with approximately
LKG
thesamevoltageasthevoltageontheholdcapacitornode,
thedifferencevoltageacrossR
isreducedsubstantially
LKG1
thereby reducing leakage current on the hold capacitor.
By enabling spread spectrum operation, low modula-
tion index pseudo-random phasing is applied to
Virtual Remote Sense timing. This has the effect of
converting any remaining narrow-band interference into
broadband noise, reducing its effect.
R
LKG
R
LKG1
R
LKG2
1
2
1
2
Increasing Voltage Correction Range
WITHOUT
WITH
GUARD RING
Correction range may be slightly improved by regulating
GUARD RING
4180 F11
INTV to5V.ThismaybedonebyplacinganLDObetween
CC
Figure 11. Simplified Leakage Models
(with and without Guard Rings)
V and INTV . Contact Linear Technology Applications
IN
CC
for more information.
Synchronization
Linear and switching power supplies and regulators may
be used with the LT4180. In most applications regulator
interference should be negligible. For those applications
where accurate control of interference spectrum is de-
sirable, an oscillator output has been provided so that
switching supplies may be synchronized to the LT4180
(Figure 12). The OSC pin was designed so that it may di-
rectly connect to most regulators, or drive opto-isolators
(for isolated power supplies).
4180fb
13
For more information www.linear.com/4180
LT4180
Typical applicaTions
12V, 500mA Linear Regulator
R1
0.2Ω
1%
Q1
IRLZ440
OUTPUT TO WIRING AND LOAD
V
IN
500mA
INTV
CC
20V
R2
63.4k
1%
C1
4.7µF
25V
8Ω MAX R
WIRE
100µF LOAD CAPACITANCE
C3
1µF
C2
1µF
R3
27k
R4
3.74k
1%
FB
RUN
V
IN
SENSE
DIV2 DIV1 DIV0
V
INTV
PP
CC
R5
5.36k
1%
R6
C4
10µF
25V
2.2k
1%
SPREAD
OSC
OV
U2
R7
10k
LT4180EGN
INTV
CC
GND
DRAIN
Q2
VN2222
COMP GND CHOLD1GUARD2 CHOLD2 GUARD3 CHOLD3 GUARD4 CHOLD4
C
OSC
R
OSC
C10
33nF
R9
41.7k
1%
C6
330pF
R8
200k
C7
47nF
C8
470pF
C9
470pF
C11
470pF
4180 TA02
12V, 500mA Boost Regulator
R1
0.2Ω
1%
D1
DFLS220
L1
OUTPUT TO WIRING AND LOAD
(100mA MINIMUM)
4.7µH
V
IN
5V
500mA, 6Ω MAX R
WIRE
INTV
VISHAY
IHLP2525CZ-11
CC
C2
10µF
25V
R13
1.5k
R3
61.9k
1%
100µF LOAD CAPACITANCE
C1
4.7µF
16V
R2
191k
C4
1µF
C3
1µF
R5
3.65k
1%
R4
100k
GATE SW1 SW1 SW1 SW2 SW2 SW2
V
SENSE
INTV
C
FB RUN
DIV2 DIV1 DIV0
V
IN
PP
CC
R6
24.3k
R7
2k
1%
V
CC
SPREAD
U2
U1
SHDN
FB
LT4180EGN
LT3581EMSE
OV
DRAIN
FAULT
VC
R9
5.36k
1%
OSC
R
COMP GND CHOLD1 GUARD2 CHOLD2 GUARD3 CHOLD3 GUARD4 CHOLD4
R8
10k
SYNC RT
SS CLKOUT GND
OSC OSC
C7
47pF
C12
R12
41.7k
1%
C6
0.1µF
R10
84.5k
47nF
C9
C10
470pF
C11
GND
C13
470pF
47nF
470pF
4180 TA03
C8
10nF
R11
15k 1%
4180fb
14
For more information www.linear.com/4180
LT4180
Typical applicaTions
4180fb
15
For more information www.linear.com/4180
LT4180
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
GN Package
24-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
.337 – .344*
(8.560 – 8.738)
.033
(0.838)
REF
24 23 22 21 20 19 18 17 16 15 1413
.045 .005
.150 – .165
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
.254 MIN
1
2
3
4
5
6
7
8
9 10 11 12
.0165 .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
.015 .004
(0.38 0.10)
.0532 – .0688
(1.35 – 1.75)
× 45°
.004 – .0098
(0.102 – 0.249)
.0075 – .0098
(0.19 – 0.25)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.008 – .012
.0250
(0.635)
BSC
GN24 REV B 0212
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
4180fb
16
For more information www.linear.com/4180
LT4180
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
6/11
Revised Typical Applications drawings
Revised Electrical Characteristics
1, 13, 14, 18
2, 3
4
Replaced curves G08 and G09 in Typical Performance Characteristics
Replaced text for CHOLD Capacitor Selection and Compensation section and deleted Power Supply Current Limiting
paragraph in Applications Information section
10, 11
B
4/13
Revised schematics
14, 15, 18
4180fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
17
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT4180
Typical applicaTion
12V 1.5A Buck Regulator
E1
V
IN
R1
0.067Ω
1%
C2
1µF
50V
+
C1
22µF
50V
22V TO 36V
E3
OUTPUT TO WIRING AND LOAD
12V, 1.5A
GND
C6
C4
1µF
R4
61.9k
1%
VISHAY
1HLP2020CZ-11
L1, 10µH
2.5Ω MAX R
WIRE
INTV
CC
0.47µF
R3
100k
470µF LOAD CAPACITANCE
V
IN
BD BOOST
C8
1µF
RUN/SD
SW
INTV
CC
R6
3.65k
1%
C5
0.1µF
50V
C7
R5
30.1k
22µF
UI
PG
25V
D1
DFLS240
FB
RUN
V
SENSE
DIV2 DIV1 DIV0
LT4180EGN
V
INTV
PP
CC
IN
LT3685EDD
R9
2.01k
1%
FB
RT
SPREAD
INTV
CC
R8
68.1k
1%
R7
10k
OV
DRAIN
SYNC
VC
R10
5.36k
1%
OSC
R
D2
CMDSH-3
COMP GND CHOLD1 GUARD2 CHOLD2 GUARD3 CHOLD3 GUARD4 CHOLD4
C
OSC
OSC
C9
47pF
C13
R11
1k
R12
22.1k
1%
47nF
C10
C11
470pF
C12
C14
330pF
47nF
470pF
R13
28k
1%
4180 TA05
C15
3.3nF
relaTeD parTs
PART NUMBER
DESCRIPTION
COMMENTS
LT3581
Boost/Inverting DC/DC Converter with 3.3A Switch,
Soft-Start and Synchronization
2.5V ≤ V ≤ 22V, Current Mode Control, 200kHz to 2.5MHz, MSOP-16E and
IN
3mm × 4mm DFN-14 Packages
LT3685
LT3573
LT3757
LT3758
36V, 2A, 2.4MHz Step-Down Switching Regulator
3.6V≤ V ≤ 36V (60V ), Integrated Boost Diode, MSOP-10E and
IN PK
3mm × 3mm DFN Packages
Isolated Flyback Switching Regulator with 60V
Integrated Switch
3V ≤ V ≤ 40V, Up to 7W, No Opto-Isolator or Third Winding Required,
IN
MSOP-16E Package
Boost, Flyback, SEPIC and Inverting Controller
2.9V ≤ V ≤ 40V, Current Mode Control, 100kHz to 1MHz Programmable
IN
Operation Frequency, MSOP-10E and 3mm × 3mm DFN-10 Packages
Boost, Flyback, SEPIC and Inverting Controller
5.5V ≤ V ≤ 100V, Current Mode Control, 100kHz to 1MHz Programmable
IN
Operation Frequency, MSOP-10E and 3mm × 3mm DFN-10 Packages
LTC3805/
LTC3805-5
Adjustable Fixed 70kHz to 700kHz Operating
Frequency Flyback Controller
V
and V
Limited Only by External Components, MSOP-10E and
IN
OUT
3mm × 3mm DFN-10 Packages
4180fb
LT 0413 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
18
(408)432-1900 FAX: (408) 434-0507 www.linear.com/4180
●
●
LINEAR TECHNOLOGY CORPORATION 2010
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