LT4256-2IS8#PBF_技术文档

LT4256-1/LT4256-2

Positive High Voltage

Hot Swap Controllers

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DESCRIPTIO

FEATURES

The LT^®4256-1/LT4256-2 are high voltage Hot Swap^TM

controllers that allow a board to be safely inserted and

removedfromalivebackplane.Aninternaldriverdrivesan

external N-channel MOSFET switch to control supply

voltages ranging from 10.8V to 80V.

■

Allows Safe Board Insertion and Removal from a

Live Backplane

■

Controls Supply Voltage from 10.8V to 80V

■

Foldback Current Limiting

Overcurrent Fault Detection

■

Drives an External N-Channel MOSFET

The LT4256-1/LT4256-2 features an adjustable analog

foldbackcurrentlimit.Ifthesupplyremainsincurrentlimit

for more than a programmable time, the N-channel

MOSFETshutsoffandthePWRGDoutputassertslow.The

LT4256-2 automatically restarts after a time-out delay.

The LT4256-1 latches off until the UV pin is cycled low.

■

Programmable Supply Voltage Power-Up Rate

■

Undervoltage Protection

■

Latch Off Operation Mode (LT4256-1)

■

Automatic Retry (LT4256-2)

■

Available in an 8-Pin SO Package

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The PWRGD output indicates when the output voltage

rises above a programmed level. An external resistor

string from V_CCprovides programmable undervoltage

protection.

APPLICATIO S

■

Hot Board Insertion

■

Electronic Circuit Breaker/Power Bussing

■

TheLT4256canbeusedasanupgradetoLT1641designs.

See Table 1 on page 14 for upgraded specifications.

Industrial High Side Switch/Circuit Breaker

■

24V/48V Industrial/Alarm Systems

■

Ideally Suited for 12V, 24V and 48V Distributed

The LT4256-1 and LT4256-2 are available in an 8-pin SO

package that is pin compatible with the LT1641.

Power Systems

■

48V Telecom Systems

, LTC and LT are registered trademarks of Linear Technology Corporation.

Hot Swap is a trademark of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

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TYPICAL APPLICATIO

48V, 2A Hot Swap Controller

LT4256 Start-Up Behavior

0.02Ω

IRF530

V

48V

2A

OUT

V

IN

48V

SMAT70A

(SHORT PIN)

CMPZ5241B

11V

C

L

V_IN

8

7

50V/DIV

10Ω

36.5k

4.02k

27k

V

SENSE

CC

64.9k

10nF

100Ω

1

6

V_OUT

50V/DIV

UV

GATE

LT4256-1/

LT4256-2

0.1µF

8.06k

INRUSH

CURRENT

500mA/DIV

2

3

FB

PWRGD

50V/DIV

C_L= 225µF

PWRGD

GND

4256 TA01

5

2.5ms/DIV

4256 TA02

UV = 36V

PWRGD = 40V

TIMER

33nF

GND

4

425612fa

1

LT4256-1/LT4256-2

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W

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ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

(Note 1)

ORDER PART

NUMBER

Supply Voltage (V_CC) ................................ –0.3 to 100V

SENSE, PWRGD ....................................... –0.3 to 100V

GATE (Note 2) ................................ –0.3V to V_CC+ 10V

Maximum Input Current (GATE) ......................... 200µA

FB, UV ........................................................ –0.3 to 44V

TIMER ..................................................... –0.3V to 4.3V

Maximum Input Current (TIMER) ....................... 100µA

Operating Temperature

LT4256C................................................. 0°C to 70°C

LT4256I ............................................. –40°C to 85°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

LT4256-1CS8

TOP VIEW

LT4256-1IS8

LT4256-2CS8

UV

FB

1

2

3

4

8

7

6

5

V

CC

LT4256-2IS8

SENSE

GATE

PWRGD

GND

S8 PART MARKING

TIMER

42561

42561I

42562

42562I

S8 PACKAGE

8-LEAD PLASTIC SO

T_JMAX= 125°C, θ_JA= 110°C/W

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The

●

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T = 25°C. V = 48V unless otherwise noted.

A

CC

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

80

UNITS

V

Operating Voltage

Operating Current

Undervoltage Threshold

Hysteresis

●

10.8

V

mA

V

CC

I

1.8

4

3.9

CC

V

Low-to-High Transition

CC

3.96

0.25

4.04

0.55

UVLH

UVHYS

INUV

0.4

V

I

UV Input Current

UV ≥ 1.2V

UV = 0V

–0.1

–1.5

–1

–3

µA

V

Fault Latch Reset Threshold Voltage

●

0.4

0.85

1.2

V

UVRTH

SENSE Pin Trip Voltage (V – V

)

FB = 0V

FB ≥ 2V

●

5.5

45

14

55

22

65

mV

SENSETRIP

CC

SENSE

I

SENSE Pin Input Current

GATE Pull-Up Current

GATE Pull-Down Current

V

= V

CC

40

–32

62

70

–63

80

µA

mA

INSNS

SENSE

Charge Pump On, ∆V

Any Fault, V

= 7V

●

–16

40

PU

PD

GATE

= 3V

GATE

∆V

GATE

External N-Channel Gate Drive (Note 2)

V

– V , 10.8V ≤ V ≤ 20V

CC

●

4.5

10

8.8

11.6

12.5

12.8

V

GATE

CC

20V ≤ V ≤ 80V

V

FB Voltage Threshold

FB High-to-Low Transition

FB Low-to-High Transition

●

3.95

4.2

3.99

4.45

4.03

4.65

V

FB

V

FB Hysteresis Voltage

0.3

0.45

0.6

V

FBHYS

OLPGD

PWRGD Output Low Voltage

I

= 1.6mA

0.25

0.6

0.4

1

V

O

I = 5mA

O

I

PWRGD Pin Leakage Current

FB Input Current

V

= 80V

PWRGD

0.1

–0.1

–105

3

1

–1

–147

5

µA

V

PWRGD

INFB

FB = 4.5V

TIMER Pull-Up Current

TIMER Pull-Down Current

TIMER Shut-Down Threshold

Duty Cycle (RETRY Mode)

TIMER = 3V, During Fault

TIMER = 3V

●

–63

1.5

4.3

1.5

TIMERPU

TIMERPD

V

C

= 10nF

TIMER

4.65

3

5

THTIMER

D

4.5

%

TIMER

425612fa

2

LT4256-1/LT4256-2

ELECTRICAL CHARACTERISTICS

The

●

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T = 25°C. V = 48V unless otherwise noted.

A

CC

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

1.7

6

MAX

UNITS

µs

t

UV Low to GATE Low

UV High to GATE High

FB Low to PWRGD Low

FB High to PWRGD High

3

9

2

5

3

PHLUV

PLHUV

PHLFB

C

= 0

µs

GATE

0.8

3.2

1

PLHFB

(V – V

CC

) High to GATE Low

V

– V = 275mV

SENSE

PHLSENSE

SENSE

CC

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: An internal clamp limits the GATE pin to a minimum of 10V above

V . Driving this pin to a voltage beyond the clamp voltage may damage

CC

the part.

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Specifications are at T = 25°C unless

A

otherwise noted.

SENSE Pin Regulation Voltage

vs Temperature

UV Thresholds vs Temperature

I vs V

CC CC

4.1

4.0

3.9

3.8

3.7

3.6

3.5

58

53

48

20

15

10

3.5

3.0

L-H THRESHOLD

FB > 2V

2.5

2.0

1.5

1.0

0.5

H-L THRESHOLD

FB = 0V

25

0

–50

0

25

50

75

100

–50

0

50

75

100

10 20

30

40

V

50

60

70

80

–25

TEMPERATURE (°C)

(V)

CC

4256 G01

4256 G02

4256 G03

PWRGD Thresholds

vs Temperature

PWRGD Output Voltage

I

CC

vs Temperature

vs I

PWRGD

2.5

2.0

1.5

1.0

0.5

0

4.5

4.4

4.3

4.2

4.1

4.0

3.9

6

5

4

3

2

1

0

V

= 48V

CC

L-H THRESHOLD

H-L THRESHOLD

–50

0

25

50

75

100

–50

0

25

50

75

100

0

4

6

8

10

12

–25

2

TEMPERATURE (°C)

I

(mA)

PWRGD

4256 G04

4256 G05

4256 G06

425612fa

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LT4256-1/LT4256-2

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TYPICAL PERFOR A CE CHARACTERISTICS

Specifications are at T = 25°C unless

A

otherwise noted.

GATE Pin Pull-Up Current

vs Temperature

GATE Pin Pull-Down Current

vs Temperature

UV Pin Current vs UV Pin Voltage

0

–5

63

62

61

60

59

58

57

56

0.4

0.2

0

–10

–15

–20

–25

–30

–35

–40

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–50

0

25

50

75

100

–50

0

25

50

75

100

–25

0

1

2

3

4

50

20 30 40

TEMPERATURE (°C)

V

(V)

UV

4256 G07

4256 G08

4256 G09

V

– V Voltage

V

– V Voltage

TIMER Pin Currents

vs Temperature

GATE

CC

GATE

CC

vs Temperature

10

5

14

12

10

8

14.0

13.5

13.0

12.5

12.0

11.5

11.0

10.5

10.0

V

= 18V

= 12V

CC

PULL-DOWN CURRENT

0

V

CC

–80

–100

–120

–140

V

= 20V

CC

V

= 10.8V

CC

6

V

= 48V

V

= 80V

CC

PULL-UP CURRENT

CC

4

2

0

–50

0

25

50

75

100

–25

–50

0

25

50

75

100

–50

0

25

50

75

100

–25

TEMPERATURE (°C)

4256 G12

4256 G10

4256 G11

Timer Shutdown Threshold

vs Temperature

TIMER Pin Currents vs V

CC

5.0

2.5

0

5.4

5.2

5.0

4.8

4.6

4.4

4.2

0

PULL-DOWN CURRENT

–80

PULL-UP CURRENT

–100

–120

–140

50

70

80

–50

0

25

50

75

100

10 20

30

40

V

60

–25

TEMPERATURE (°C)

(V)

CC

4256 G13

4256 G14

425612fa

4

LT4256-1/LT4256-2

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TYPICAL PERFOR A CE CHARACTERISTICS

otherwise noted.

Specifications are at T = 25°C unless

A

Gate Pull-Down Capability vs V

CC

FB Pin Current vs FB Pin Voltage

Below Minimum Operating Voltage

0.2

0.1

60

50

40

30

20

10

0

–0.1

–0.2

–0.3

–0.4

0

10

20

30

(V)

40

50

0

4

6

8

10

12

2

V

(V)

FB

CC

4256 G15

4256 G16

425612fa

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LT4256-1/LT4256-2

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PI FU CTIO S

UV (Pin 1): Undervoltage Sense. UV is an input that

enables the output voltage. When UV is driven above 4V,

GATE will start charging and the output turns on. When

UV goes below 3.6V, GATE discharges and the output

shuts off.

GATE (Pin 6): High Side Gate Drive for the External N-

Channel MOSFET. An internal charge pump guarantees at

least 10V of gate drive for V_CCsupply voltages above 20V

and 4.5V of gate drive for V_CCsupply voltages between

10.8V and 20V. The rising slope of the voltage on GATE is

set by an external capacitor connected from GATE to GND

and an internal 32µA pull-up current source from the

charge pump output.

Pulsing UV low for a minimum of 5µs after a current limit

fault cycle resets the fault latch (LT4256-1) and allows the

part to turn back on. This command is only accepted after

TIMER has discharged below 0.65V. To disable UV sens-

ing, connect UV to a voltage beween 5V and 44V.

If the current limit is reached, the GATE voltage is adjusted

to maintain a constant voltage across the sense resistor

while the timing capacitor starts to charge. If the TIMER

voltage ever exceeds 4.65V, GATE is pulled low.

FB (Pin 2): Power Good Comparator Input. FB monitors

the output voltage through an external resistive divider.

When the voltage on FB is lower than the high-to-low

threshold of 3.99V, PWRGD is pulled low and released

when FB is pulled above the 4.45V low-to-high threshold.

GATE is also pulled to GND whenever UV is pulled low, the

V_CCsupplyvoltagedropsbelowtheexternallyprogrammed

undervoltage threshold, or V_CCdrops below the internal

UVLO threshold (9.8V).

The voltage present on FB affects foldback current limit

(see Figure 7 and related discussion).

GATEisclampedinternallytoamaximumvoltageof11.6V

(typ) above V_CCunder normal operating conditions. Driv-

ing this pin beyond the clamp voltage may damage the

part. A Zener diode is needed between the gate and source

of the external MOSFET to protect its gate oxide under

instantaneous short-circuit conditions. See Applications

Information.

PWRGD (Pin 3): Power Good Output. PWRGD is pulled

lowwheneverthevoltageonFBfallsbelowthe3.99Vhigh-

to-low threshold voltage. It goes into a high impedance

state when the voltage on FB exceeds the low-to-high

threshold voltage. An external pull-up resistor can pull

PWRGD to a voltage higher or lower than V_CC.

SENSE (Pin 7): Current Limit Sense Input. A sense

resistor is placed in the supply path between V_CCand

SENSE. The current limit circuit regulates the voltage

across the sense resistor (V_CC– SENSE) to 55mV while in

current limit when FB is 2V or higher. If FB drops below

2V, the regulated voltage across the sense resistor de-

creases linearly to 14mV when FB is 0V.

GND (Pin 4): Device Ground. This pin must be tied to a

ground plane for best performance.

TIMER (Pin 5): Timing Input. An external timing capacitor

from TIMER to GND programs the maximum time the part

is allowed to remain in current limit. When the part goes

into current limit, a 105µA pull-up current source starts to

charge the timing capacitor. When the voltage on TIMER

reaches 4.65V (typ), GATE pulls low; the TIMER pull-up

current will be turned off and the capacitor is discharged

bya3µApull-downcurrent.WhenTIMERfallsbelow0.65V

(typ), GATE turns on again for the LT4256-2. UV must be

cycled low after TIMER has discharged below 0.65V (typ)

to reset the LT4256-1. If UV is not cycled low (LT4256-1),

GATEremainslatchedoffandTIMERisdischargedtonear

GND. Under an output short-circuit condition, the

LT4256-2 cycles on and off with a 3% duty cycle.

To defeat current limit, connect SENSE to V_CC.

V_CC(Pin 8): Input Supply Voltage. The positive supply

input ranges from 10.8V to 80V for normal operation.

I_CCis typically 1.8mA. An internal circuit disables the

LT4256-1/LT4256-2 for inputs less than 9.8V (typ).

425612fa

6

LT4256-1/LT4256-2

W

BLOCK DIAGRA

V

SENSE

7

CC

8

V

P

V

P

GEN

2

FB

–

CURRENT

LIMIT

+

14mV ~ 55mV

CHARGE

PUMP

AND

GATE

DRIVER

6

3

GATE

+

FOLDBACK

2V

+

–

REF GEN

3.99V

–

PWRGD

3.99V

1

UV

–

V

CC

INTERNAL

UV

9.8V

+

–

+

4V

LOGIC

UV

+

0.65V

TIMER LOW

V

P

–

108µA

+

TIMER HIGH

4.65V

–

5

TIMER

3µA

4

4256 BD

GND

425612fa

7

LT4256-1/LT4256-2

TEST CIRCUIT

48k

48V

+

–

PWRGD

FB

V

CC

SENSE

GATE

100pF

UV

TIMER

GND

4256 F01

Figure 1

W U

W

TI I G DIAGRA S

4.45V

3.99V

4V

3.6V

FB

UV

t

PHLFB

PLHFB

t

PLHUV

PHLUV

PWRGD

GATE

1V

V

OUT

+2V

V

+2V

OUT

4256 F03

4256 F02

Figure 2. UV to GATE Timing

Figure 3. V

to PWRGD Timing

OUT

V

CC

– SENSE

GATE

55mV

t

PHLSENSE

V

CC

4256 F04

Figure 4. SENSE to GATE Timing

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APPLICATIO S I FOR ATIO

Hot Circuit Insertion

device also provides undervoltage as well as overcurrent

protection while a power good output signal indicates

whentheoutputsupplyvoltageisreadywithahighoutput.

When circuit boards are inserted into a live backplane, the

supply bypass capacitors on the boards draw high peak

currents from the backplane power bus as they charge.

The transient currents can permanently damage the con-

nector pins and glitch the system supply, causing other

boards in the system to reset.

Power-Up Sequence

An external N-channel MOSFET pass transistor (Q1) is

placed in the power path to control the power up of the

supply voltage (Figure 5). Resistor R5 provides current

detection and capacitor C1 controls the GATE slew rate.

Resistor R7 compensates the current control loop while

TheLT4256-1/LT4256-2aredesignedtoturnonaboard’s

supply voltage in a controlled manner, allowing the board

tobesafelyinsertedorremovedfromalivebackplane.The

R6 prevents high frequency oscillations in Q1.

425612fa

8

LT4256-1/LT4256-2

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APPLICATIO S I FOR ATIO

Q1

R5

0.025Ω

IRF530

V

OUT

V

IN

48V

+

D2

D1

1.6A

C

L

SMAT70A

CMPZ5241B

11V

8

7

V

CC

SENSE

R1

64.9k

(SHORT PIN)

R6

10Ω

R8

36.5k

1

6

UV

GATE

R7

100Ω

R4

27k

LT4256-1/

LT4256-2

C3

0.1µF

R2

8.06k

C1

10nF

2

3

FB

R9

4.02k

5

PWRGD

GND

4

TIMER

4256 F05

C2

33nF

GND

UV = 36V

PWRGD = 40V

Figure 5. 1600mA, 48V Application

When the power pins first make contact, transistor Q1 is

held off. If the voltage on V_CCis above the externally

programmed undervoltage threshold, V_CCis above 9.8V,

and the voltage on TIMER is less than 4.65V (typ), transis-

tor Q1 will be turned on (Figure 6). The voltage on GATE

rises with a slope equal to 32µA/C1 and the supply inrush

current is set at:

I

OUT

500mA/DIV

PWRGD

50V/DIV

V

OUT

50V/DIV

I_INRUSH= C_L• 32µA/C1

(1)

where C_Lis the total load capacitance.

GATE

50V/DIV

C

= 125µF

L

4256 F06

To reduce inrush current, increase C1 or decrease load

capacitance. If the voltage across the current sense resis-

tor R5 reaches V_SENSETRIP, the inrush current will be

limited by the internal current limit circuitry. The voltage

on GATE is adjusted to maintain a constant voltage across

the sense resistor and TIMER begins to charge.

5ms/DIV

Figure 6. Start-Up Waveforms

LT4256-2 more susceptible to noise (V_CCmust be at least

9.8V when UV is at its 3.6V threshold). UV is filtered with

C3topreventnoisespikesandcapacitivelycoupledglitches

from shutting down the LT4256-1/LT4256-2 output

erroneously.

When the FB voltage goes above the low-to-high V_FB

threshold, PWRGD goes high.

TocalculatetheUVthreshold,usethefollowingequations:

Undervoltage Detection

V

⎛

⎝

⎞

⎠

R1= R2 ^THUVLH− 1

(2)

(3)

(4)

The LT4256-1/LT4256-2 uses UV to monitor the V_CC

voltage to determine when it is safe to turn on the load and

allow the user the greatest flexibility for setting the thresh-

old. AnytimethatUVgoesbelow3.6V, GATEwillbepulled

low until UV goes above 4V again.

⎜

⎟

4V

20kΩ ≤ R1+ R2 ≤ 200kΩ

R1

R2

⎛

⎞

⎟

⎠

V_THUVLH= 3.6 1+

⎜

⎝

The UV threshold should never be set below the internal

UVLO threshold (9.8V typically) because the benefit of

UV’s hysteresis will be lost, making the LT4256-1/

where V_THUVLHis the desired UV threshold voltage when

V_CCis rising (L-H), etc.

425612fa

9

LT4256-1/LT4256-2

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APPLICATIO S I FOR ATIO

V

CC

– V

SENSE

12

10

8

55mV

6

4

2

14mV

4256 F08

0V

2V

FB

4256 F07

0

50

100

150

(mV)

200

V

– V

CC

SENSE

Figure 7. Current Limit Sense Voltage vs Feedback Pin Voltage

Figure 8. Response Time to Overcurrent

Figure 11 shows how the LT4256-1/LT4256-2 are com-

manded to shut off with a logic signal. This is accom-

plished by pulling the gate of the open-drain MOSFET, Q2,

(tied to the UV pin) high.

For a 0.025Ω sense resistor, the current limit is set at

2200mA and folds back to 560mA when the output is

shorted to ground. Thus, MOSFET peak power dissipation

under short-circuit conditions is reduced from 105.6W to

26.5W. See the Layout Considerations section for impor-

tant information about board layout to minimize current

limit threshold error.

Short-Circuit Protection

TheLT4256-1/LT4256-2featuresaprogrammablefoldback

currentlimitwithanelectroniccircuitbreakerthatprotects

against short circuits or excessive load currents. The

current limit is set by placing a sense resistor (R5)

between V_CCand SENSE. The current limit threshold is

calculated as:

The LT4256-1/LT4256-2 also features a variable

overcurrent response time. The time required for the part

to regulate the GATE voltage is a function of the voltage

across the sense resistor connected between V_CCand

SENSE. This helps to eliminate sensitivity to current

spikes and transients that might otherwise unnecessarily

trigger a current limit response and increase MOSFET

dissipation. Figure 8 shows the response time as a func-

tion of the overdrive at SENSE.

I_LIMIT= 55mV/R5

(5)

where R5 is the sense resistor.

To limit excessive power dissipation in the pass transistor

and to reduce voltage spikes on the input supply during

short-circuit conditions at the output, the current folds

back as a function of the output voltage, which is sensed

internally on FB.

TIMER

TIMERprovidesamethodforprogrammingthemaximum

time the part is allowed to operate in current limit. When

the current limit circuitry is not active, the TIMER pin is

pulled to GND by a 3µA current source. When the current

limit circuitry becomes active, a 108µA pull-up current

sourceisconnectedtoTIMERandthevoltagewillrisewith

a slope equal to 105µA/C_TIMERas long as the circuitry

stays active. Once the desired maximum current limit time

is known, the capacitor value is:

If the LT4256-1/LT4256-2 go into current limit when the

voltage on FB is 0V, the current limit circuit drives the

GATE pin to force a constant 14mV drop across the sense

resistor. As the output at FB increases, the voltage across

the sense resistor increases until the FB pin reaches 2V, at

which point the voltage across the sense resistor is held

constant at 55mV (see Figure 7).

105µA

4.65V

C[nF] = 25 • t[ms]; C =

• t

(6)

425612fa

10

LT4256-1/LT4256-2

U

W U U

APPLICATIO S I FOR ATIO

I

OUT

500mA/DIV

TIMER

5V/DIV

TIMER

5V/DIV

V

OUT

V

OUT

50V/DIV

GATE

50V/DIV

GATE

50V/DIV

4256 F09

4256 F10

10ms/DIV

Figure 9. LT4256-1 Current Limit Waveforms

Figure 10. LT4256-2 Current Limit Waveforms

WhentheTIMERpinreaches4.65V(typ), theinternalfault

latch is set causing GATE to be pulled low and TIMER to be

discharged to GND by the 3µA current source. The part is

not allowed to turn on again until the voltage on TIMER

falls below 0.65V (typ).

start back up. This is accomplished by cycling UV to

ground and then back high (this command can only be

accepted after TIMER discharges back below the 0.65V

typical threshold, to prevent overheating transistor Q1).

Automatic Restart

TIMER must never be pulled high by a low impedance

becausewheneverTIMERrisesabovetheupperthreshold

(typically 4.65V) the pin characteristics change from a

high impedance current source to a low impedance.

TheLT4256-2willautomaticallyrestartafteranovercurrent

fault. These waveforms are shown in Figure 10.

The LT4256-2 functionality is as follows: When an

overcurrent condition occurs, the GATE pin is servoed to

maintain a constant voltage across the sense resistor, and

the capacitor C2 at the TIMER pin will begin to charge.

When the voltage at the TIMER pin reaches 4.65V (typ),

the GATE pin is pulled low. When the voltage at the TIMER

pin ramps back down to 0.65V (typ), the LT4256-2 turns

on again. If the short-circuit condition at the output still

exists, the cycle will repeat itself indefinitely. The duty

cycle under short-circuit conditions is 3% which prevents

Q1 from overheating.

Whenever GATE is commanded off by any fault condition,

it is discharged rapidly, turning off the external MOSFET.

ThewaveforminFigure9showshowtheoutputlatchesoff

following a current fault (LT4256-1). The drop across the

senseresistorisheldat55mVasthetimerrampsup. Once

TIMER reaches its shutdown threshold (4.65V typically),

the circuit latches off.

The LT4256-1 latches off after a current limit fault. After

the LT4256-1 latches off, the part may be commanded to

425612fa

11

LT4256-1/LT4256-2

U

W U U

APPLICATIO S I FOR ATIO

R5

0.010Ω

Q1

IRF530

V

OUT

48V

4A

V

IN

48V

D2

SMAT70A

D1

CMPZ5241B

11V

C

L

(SHORT PIN)

8

7

R1

V

SENSE

CC

R6

R8

36.5k

64.9k

10Ω

1

6

UV

GATE

OFF SIGNAL

FROM MPU

VN2222

Q2

R7

100Ω

C3

0.01µF

LT4256-1/

LT4256-2

R2

8.06k

C1

10nF

2

3

R9

R4

51k

FB

4.02k

5

TIMER

PWRGD

4256 F07

C2

33nF

GND

4

GND

UV = 36V

PWRGD = 40V

Figure 11. How to Use a Logic Signal to Control LT4256 Turn-On/-Off

R5

100mΩ

Q1

IRF530

V

IN

OUT

D2

D1

C

SMAT70A

CMPZ5241B

11V

L

8

7

V

SENSE

R1

64.9k

(SHORT PIN)

CC

R6

LOGIC

10Ω

1

6

R10

27k

UV

GATE

R7

100Ω

C3

0.1µF

R2

8.06k

LT4256-1/

LT4256-2

C1

10nF

R8

36.5k

2

3

PWRGD

FB

R9

4.02k

R4

27k

5

Q2

TIMER

PWRGD

2N3904

C2

33nF

GND

4

UV = 36V

GND

4256 F11

PWRGD = 40V

Figure 12. Active Low Enable PWRGD Application

Power Good Detection

The thresholds for the FB pin are 4.45V (low to high) and

3.99V (high to low). To calculate the PWRGD thresholds,

use the following equations:

The LT4256-1/LT4256-2 includes a comparator for moni-

toring the output voltage. The output voltage is sensed

through the FB pin via an external resistor string. The

comparator’s output (PWRGD) is an open collector ca-

pable of operating from a pull-up as high as 80V.

V

⎛

⎜

⎝

⎞

THPWRGD

R8 =

– 1 •R9, high to low

(7)

(8a)

(8b)

⎟

⎠

3.99V

20kΩ ≤ R8 + R9 ≤ 200kΩ

PWRGD can be used to directly enable/disable a power

module with an active high enable input. Figure 12 shows

how to use PWRGD to control an active low enable input

power module. Signal inversion is accomplished by tran-

sistor Q2 and R10.

R8

R9

⎛

⎝

⎞

⎟

⎠

V_THPWRGD= 4.45V 1+

, low to high

⎜

425612fa

12

LT4256-1/LT4256-2

U

W

U U

APPLICATIO S I FOR ATIO

Supply Transient Protection

Higher current applications, especially where the output

load is physically far away from the LT4256-1/LT4256-2

willbemoresusceptibletothesetransients.Thisisnormal

and the LT4256-1/LT4256-2 have been designed to allow

for some ringing below ground. However, if the applica-

tion is such that V_OUTcan ring more than 10V below

ground, damage may occur to the LT4256-1 and an

external diode from ground (anode) to V_OUT(cathode)

must be added to the circuit as shown in Figure 14 (it is

critical that the reverse breakdown voltage of the diode be

higher than the highest expected V_CCvoltage). A capacitor

placed from ground to V_OUTdirectly at the LT4256-1/

LT4256-2 can help reduce the amount of ringing on V_OUT

but it may not be enough for some applications.

The LT4256-1/LT4256-2 is 100% tested and guaranteed

to be safe from damage with supply voltages up to 80V.

However, voltage transients above 100V may cause per-

manent damage. During a short-circuit condition, the

largechangeincurrentsflowingthroughthepowersupply

traces can cause inductive voltage transients which could

exceed 100V. To minimize the voltage transients, the

power trace parasitic inductance should be minimized by

using wider traces or heavier trace plating and a 0.1µF

bypass capacitor should be placed between V_CCand GND.

Asurgesuppressor,asshownintheapplicationdiagrams,

(Transzorb) at the input can also prevent damage from

voltage transients.

During a fault condition, the LT4256-1/LT4256-2 pulls

down on GATE with a switch capable of sinking about

60mA. Once GATE drops below the output voltage by a

diode forward voltage, the external Zener will forward bias

and V_OUTwill also be discharged to GND. In addition to the

GATE capacitance, the output capacitance will be dis-

charged through the LT4256-1/LT4256-2.

GATE Pin

A curve of gate drive vs V_CCis shown in Figure 13. GATE

isclampedtoamaximumvoltageof12.8VaboveV_CC.This

clamp is designed to sink the internal charge pump cur-

rent. An external Zener diode must be used as shown in all

applications. At a minimum input supply voltage of 12V,

the minimum gate drive voltage is 4.5V. When the input

supply voltage is higher than 20V, the gate drive voltage is

at least 10V and a standard threshold MOSFET can be

used. In applications from 12V to 15V range, a logic level

MOSFET must be used.

In applications utilizing very large external N-channel

MOSFETs, the possibility exists for the MOSFET to turn on

when initially inserted into a live backplane (before the

LT4256-1/LT4256-2 becomes active and pulls down on

GATE). This is due to the drain to gate capacitance forcing

current into R7 and C1 when the drain voltage steps up

from ground to V_INwith an extremely fast rise time. To

alleviate this situation, a diode, D3, should be put

across R7 with the cathode connected to C1 as shown in

Figure 15.

In some applications it may be possible for the V_OUTpin to

ring below ground (due to the parasitic trace inductance).

12

11

10

9

8

7

6

5

30

10

20

40

V

50

(V)

60

70

80

CC

4256 F13

Figure 13. ∆V

vs V

GATE

CC

425612fa

13

LT4256-1/LT4256-2

U

W U U

APPLICATIO S I FOR ATIO

R5

0.033Ω

Q1

IRF530

V

IN

V

OUT

D2

SMAT70A

D1

C

L

CMPZ5241B

11V

100µF

8

7

V

SENSE

R1

(SHORT PIN)

CC

R6

R8

64.9k

10Ω

36.5k

1

6

D3

UV

GATE

MRA4003T3

R7

100Ω

C3

0.1µF

LT4256-1/

LT4256-2

R2

8.06k

C1

10nF

2

3

FB

R9

4.02k

R4

27k

5

TIMER

PWRGD

4256 F14

C2

33nF

GND

4

GND

UV = 36V

PWRGD = 40V

Figure 14. Negative Output Voltage Protection Diode Application

Notes on Using the LT4256 in LT1641 Applications

circuit) is recommended. The minimum trace width for

1oz copper foil is 0.02" per amp to make sure the trace

stays at a reasonable temperature. 0.03" per amp or wider

is recommended. Note that 1oz copper exhibits a sheet

Even though the LT4256 and LT1641 have the same

pinout, several changes were made to improve overall

system accuracy and increase noise immunity. These

changes are spelled out in Table 1 and must be accounted

for if using the LT4256 in an LT1641 application.

resistance of about 530µΩ/ . Small resistances can

❏

cause large errors in high current applications. Noise

immunity will be improved significantly by locating resis-

tor dividers close to the pins with short V_CCand GND

traces. A 0.1µF decoupling capacitor from UV to GND is

also required.

Layout Considerations

To achieve accurate current sensing, a Kelvin connection

to the current sense resistor (R5 in typical application

Table 1. Differences Between LT1641 and LT4256

SPECIFICATION

UV Threshold

LT1641

1.313V

1.233V

±70%

1.233V

10µA

LT4256

4V

COMMENTS

Higher 1% Reference for Better Noise Immunity and System Accuracy

More Accurate TIMEOUT

FB Threshold

3.99V

±40%

4.65V

30µA

100Ω

14mV

55mV

0.85V

TIMER Current

TIMER Shutdown V

Higher Trip Voltage for Better Noise Immunity

Higher Current to Accommodate Higher Leakage MOSFETs or Parallel Devices

Different Compensation for Current Limit Loop

Slightly Different Current Limit Trip Point

GATE I

PU

GATE Resistor

Foldback I

1kΩ

12mV

47mV

1.233V

LIM

I

Threshold

Slightly Different Current Limit Trip Point

LIM

Fault Latch Reset

Threshold Voltage

Better Noise Immunity

425612fa

14

LT4256-1/LT4256-2

U

PACKAGE DESCRIPTIO

S8 Package

8-Lead Plastic Small Outline (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1610)

.189 – .197

(4.801 – 5.004)

.045 ±.005

NOTE 3

.050 BSC

7

5

8

6

.245

MIN

.160 ±.005

.150 – .157

(3.810 – 3.988)

NOTE 3

.228 – .244

(5.791 – 6.197)

.030 ±.005

TYP

1

3

4

2

RECOMMENDED SOLDER PAD LAYOUT

.010 – .020

(0.254 – 0.508)

× 45°

.053 – .069

(1.346 – 1.752)

.004 – .010

(0.101 – 0.254)

.008 – .010

(0.203 – 0.254)

0°– 8° TYP

.016 – .050

(0.406 – 1.270)

.050

(1.270)

BSC

.014 – .019

(0.355 – 0.483)

TYP

NOTE:

INCHES

1. DIMENSIONS IN

(MILLIMETERS)

2. DRAWING NOT TO SCALE

3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)

SO8 0303

425612fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

15

LT4256-1/LT4256-2

U

W U U

APPLICATIO S I FOR ATIO

R5

0.033Ω

Q1

IRF530

V

IN

V

OUT

D2

D1

C

L

SMAT70A

CMPZ5241B

11V

100µF

8

7

V

SENSE

R1

(SHORT PIN)

CC

R6

R8

64.9k

10Ω

36.5k

1

6

UV

GATE

R7

100Ω

D3

1N4148W

C3

0.1µF

LT4256-1/

LT4256-2

R2

8.06k

C1

10nF

2

3

FB

R9

4.02k

R4

27k

5

TIMER

PWRGD

4256 TA03

C2

33nF

GND

4

GND

UV = 36V

PWRGD = 40V

Figure 15. High dV/dT MOSFET Turn-On Protection Circuit

RELATED PARTS

PART NUMBER

LT1641-1/LT1641-2

LTC4211

DESCRIPTION

Positive 48V Hot Swap Controller in SO-8

Single Hot Swap Controller with Multifunction Current Control 2.5V to 16.5V, Active Inrush Limiting, Dual Level Cicuit Breaker

COMMENTS

9V to 80V Operation, Active Current Limit, Autoretry/Latchoff

LTC4251

–48V Hot Swap Controller in SOT-23

Floating Supply from –15V, Active Current Limiting,

Fast Circuit Breaker

LTC4252-1/LTC4252-2 –48V Hot Swap Controller in MSOP

Floating Supply from –15V, Active Current Limiting,

Power Good Output

LTC4253

LT4254

–48V Hot Swap Controller and Supply Sequencer

Floating Supply from –15V, Active Current Limiting,

Enables Three DC/DC Converters

Positive High Voltage Hot Swap Controller

10.8V to 36V, Open-Circuit Detection

425612fa

LT/LWI/LT 0705 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

16

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT4256-2IS8#PBF
厂家：	Linear
描述：	LT4256-1 and LT4256-2 - Positive High Voltage Hot Swap Controllers; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C 光电二极管
文件：	总16页 (文件大小：195K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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