LT4256-3CGN [Linear]
Positive High Voltage Hot Swap Controller with Open-Circuit Detect; 正高电压热插拔控制器开路检测
| 型号： | LT4256-3CGN |
| 厂家： | 
Linear |
| 描述： | Positive High Voltage Hot Swap Controller with Open-Circuit Detect |
| 文件： | 总20页 (文件大小：306K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT4256-3
Positive High Voltage
Hot Swap Controller
with Open-Circuit Detect
U
FEATURES
DESCRIPTIO
■
Allows Safe Board Insertion and Removal from a
TheLT®4256-3isahighvoltageHotSwapTM controllerthat
allows a board to be safely inserted and removed from a
live backplane. An internal driver controls the high side
N-channel MOSFET gate for supply voltages ranging from
10.8V to 80V. The part features an open-circuit detect
(OPEN) output that indicates abnormally low load current
conditions.
Live Backplane
■
Controls Supply Voltage from 10.8V to 80V
■
Foldback Current Limiting
■
Open Circuit and Overcurrent Fault Detect
■
Drives an External N-Channel MOSFET
■
Automatic Retry or Latched Off Operation
After Overcurrent Fault
The LT4256-3 also features an adjustable analog foldback
currentlimit.Ifthesupplyremainsincurrentlimitformore
than a programmable time, the N-channel MOSFET shuts
off, the PWRGD output asserts low and the LT4256-3
either automatically restarts after a time-out delay or
latches off until the UV pin is cycled low (depending on the
status of the RETRY pin).
■
Programmable Supply Voltage Power-Up Rate
■
Open MOSFET Detection
■
1% Over and Undervoltage Detection Accuracy
■
Available in a 16-Lead SSOP Package
U
APPLICATIO S
■
Hot Board Insertion
The PWRGD output indicates when the output voltage
rises above a programmed level. An external resistor
stringfromVCC providesprogrammableundervoltageand
overvoltage protection.
■
Electronic Circuit Breaker/Power Bussing
■
Industrial High Side Switch/Circuit Breaker
■
24V/48V Industrial/Alarm Systems
■
Ideally Suited for 12V, 24V and 48V Distributed
The LT4256-3 is available in a 16-lead SSOP package.
Power Systems
48V Telecom Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
Hot Swap is a trademark of Linear Technology Corporation.
U
TYPICAL APPLICATIO
48V, 2A Hot Swap Controller
0.020Ω
V
IRF540
OUT
LT4256-3 Start-Up Behavior
V
IN
48V
48V
+
2A
SMAT70A
C
CMPZ5241BS
11V
L
V
(SHORT PIN)
IN
50V/DIV
CONTACT BOUNCE
V
SENSE
CC
51k
36.5k
4.02k
64.9k
10nF
10Ω
V
OUT
100Ω
50V/DIV
UV
OV
GATE
LT4256-3
INRUSH
CURRENT
500mA/DIV
V
0.01µF
OUT
4.02k
4.02k
FB
PWRGD
50V/DIV
PWRGD
OPEN
PWRGD
RETRY
42563 TA02
2.5ms/DIV
4256 TA01
UV = 36V
OV = 73V
PWRGD = 40V
TIMER
GND
33nF
GND
42563f
1
LT4256-3
W W
U W
U
W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
Supply Voltage (VCC) ................................ –0.3 to 100V
SENSE, PWRGD ....................................... –0.3 to 100V
GATE Voltage (Note 2).................... –0.3V to VCC + 10V
GATE Maximum Current ..................................... 200µA
VOUT .......................................................... –3V to 100V
FB, UV, OPEN ............................................. –0.3 to 44V
OV .............................................................. –0.3 to 18V
RETRY ........................................................ –0.3 to 15V
TIMER Voltage......................................... –0.3V to 4.3V
Maximum Input Current (TIMER) ....................... 100µA
Operating Temperature
ORDER PART
TOP VIEW
NUMBER
1
2
3
4
5
6
7
8
V
CC
16
15
14
13
12
11
10
9
UV
OV
SENSE
NC
LT4256-3CGN
LT4256-3IGN
NC
GATE
OPEN
PWRGD
NC
V
OUT
NC
GN PART MARKING
FB
RETRY
GND
TIMER
42563
42563I
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 130°C/W
LT4256-3C ............................................. 0°C to 70°C
LT4256-3I ......................................... –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 48V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
80
UNITS
V
CC
Operating Voltage
Operating Current
Undervoltage Threshold
Hysteresis
●
●
10.8
V
mA
V
I
1.8
4
3.9
CC
V
V
V
CC
Low-to-High Transition
3.96
0.25
4.04
0.55
UVLH
UVHYS
INUV
0.4
V
I
UV Input Current
UV ≥ 1.2V
UV = 0V
–0.1
–1.5
–1
–3
µA
µA
V
V
V
Fault Latch Reset Threshold Voltage
Overvoltage Threshold
Hysteresis
●
●
0.4
0.85
4
1.2
4.04
0.55
1
V
V
UVRTH
V
Low-to-High Transition
3.96
0.25
OVLH
CC
0.4
0.1
3
V
OVHYS
INOV
I
OV Input Current
0V ≤ OV < 7V
µA
mV
V
V
Open-Circuit Voltage Threshold (V – V
)
●
1.5
6.5
OPEN
CC
SENSE
OPEN Output Low Voltage
I = 2mA
0.20
0.75
0.5
1.3
V
V
OLOPEN
O
I = 5mA
O
I
Leakage Current
V
OPEN
= 5V
0.1
1
µA
INOPEN
V
SENSE Pin Trip Voltage (V – V
)
FB = 0V
FB ≥ 2V
●
●
7
45
14
55
22
65
mV
mV
SENSETRIP
CC
SENSE
I
I
I
I
SENSE Pin Input Current
GATE Pull-Up Current
GATE Pull-Down Current
V
= V
CC
40
–30
62
70
–55
80
µA
µA
INSNS
PU
SENSE
Charge Pump On, ∆V
= 7V
●
–16
40
GATE
Any Fault, V
> V
= V
mA
µA
PD
GATE
GATE
OUT
V
OUT
Pull-Down Current, Fault Condition
Any Fault, V
+ ∆V ,
GATEL
130
PDL
OUT
V
V
= 48V
OUT
∆V
∆V
External N-Channel Gate Drive (Note 2)
External N-Channel Gate Drive, Fault Condition
– V , 10.8V ≤ V ≤ 20V
●
●
4.5
10
8.8
11.6
12.5
12.8
V
V
GATE
GATE
OUT
CC
20V ≤ V ≤ 80V
CC
V
GATE
– V , V = 48V
OUT OUT
–2
V
GATEL
42563f
2
LT4256-3
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 48V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
FB Voltage Threshold
FB High-to-Low Transition
FB Low-to-High Transition
●
●
3.95
4.20
3.99
4.45
4.03
4.65
V
V
FB
V
V
FB Hysteresis Voltage
0.3
0.45
0.60
V
FBHYS
OLPGD
PWRGD Output Low Voltage
I
= 1.6mA
0.25
0.60
0.4
1.0
V
V
O
I = 5mA
O
I
I
I
I
PWRGD Pin Leakage Current
FB Input Current
V
= 80V
PWRGD
0.1
–0.1
–115
3
1
–1
–145
5
µA
µA
µA
µA
V
PWRGD
INFB
FB = 4.5V
TIMER Pull-Up Current
TIMER Pull-Down Current
TIMER Shutdown Threshold
Duty Cycle (RETRY Mode)
RETRY Threshold
●
●
●
●
●
–85
1.5
4.3
1.5
0.4
TIMERPU
TIMERPD
V
C
= 10nF
TIMER
4.65
3
5
THTIMER
D
4.5
1.2
–130
3
%
V
TIMER
RETRYTH
INRTR
V
0.85
–87
1.7
6
I
t
t
t
t
t
RETRY Input Current
RETRY = GND
µA
µs
µs
µs
µs
µs
UV Low to GATE Low
UV High to GATE High
FB Low to PWRGD Low
FB High to PWRGD High
C
C
= 100pF
= 100pF
PHLUV
PLHUV
PHLFB
GATE
GATE
9
0.8
3.2
1
2
5
PLHFB
(V – V
CC
) High to GATE Low
SENSE
V
– V = 275mV
SENSE
3
PHLSENSE
CC
Note 2: An internal clamp limits the GATE pin to a minimum of 10V above
. Driving this pin to a voltage beyond the clamp voltage may damage
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
V
CC
the part.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Specifications are at TA = 25°C unless otherwise noted.
SENSE Regulation Voltage
vs Temperature
ICC vs VCC
ICC vs Temperature
58
53
48
20
15
10
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 48V
CC
FB > 2V
2.5
2.0
1.5
1.0
0.5
FB = 0V
25
0
–50
0
50
75
100
10 20
30
40
V
50
60
70
80
–50
0
25
50
75
100
–25
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
(V)
CC
42563 G01
42563 G02
42563 G03
42563f
3
LT4256-3
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Specifications are at TA = 25°C unless otherwise noted.
GATE Pull-Down Current
vs Temperature
GATE Pull-Down Capability vs VCC
Below Minimum Operating Voltage
GATE Pull-Up Current
vs Temperature
60
50
40
30
20
10
0
63
62
61
60
59
58
57
56
0
–5
–10
–15
–20
–25
–30
–35
–40
0
4
6
8
10
12
2
–50
0
25
50
75
100
–25
–50
0
25
50
75
100
–25
V
CC
(V)
TEMPERATURE (°C)
TEMPERATURE (°C)
42563 G17
42563 G05
42563 G04
VGATE – VOUT Voltage
vs Temperature
VGATE – VOUT Voltage
vs Temperature
TIMER Currents vs Temperature
14
12
10
8
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
5.0
2.5
PULL-DOWN CURRENT
V
= 18V
CC
0
V
= 12V
CC
–80
–100
–120
–140
V
= 20V
= 48V
CC
6
V
V
= 10.8V
CC
CC
V
= 80V
CC
PULL-UP CURRENT
4
2
0
–50
0
25
50
75
100
–50
0
25
50
75
100
–50
0
25
50
75
100
–25
–25
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
42563 G06
42563 G07
42563 G08
TIMER Shutdown Threshold
vs Temperature
TIMER Currents vs VCC
UV Current vs UV Voltage
0.4
0.2
5.0
2.5
0
5.4
5.2
5.0
4.8
4.6
4.4
4.2
0
PULL-DOWN CURRENT
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–80
–100
–120
–140
PULL-UP CURRENT
50
70
80
–50
0
25
50
75
0
1
2
3
4
10 20 30
50
40
10 20
30
40
V
60
100
–25
TEMPERATURE (°C)
V
(V)
(V)
UV
CC
42563 G09
42563 G10
42563 G18
42563f
4
LT4256-3
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Specifications are at TA = 25°C unless otherwise noted.
UV Thresholds vs Temperature
OV Current vs OV Voltage
OV Thresholds vs Temperature
250
200
4.1
4.0
3.9
3.8
3.7
3.6
3.5
4.1
4.0
3.9
3.8
3.7
3.6
3.5
L-H THRESHOLD
L-H THRESHOLD
150
100
50
0
H-L THRESHOLD
H-L THRESHOLD
–50
0
5
10
(V)
15
20
–50
0
25
50
75
100
–50
0
25
50
75
100
–25
–25
V
OV
TEMPERATURE (°C)
TEMPERATURE (°C)
42563 G19
42563 G11
42563 G12
OPEN Threshold Voltage
vs Temperature
PWRGD Output Voltage
vs IPWRGD
OPEN Output Voltage vs IOPEN
6
5
4
3
2
1
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
10
9
8
7
6
5
4
3
2
1
0
V
CC
– V
SENSE
0
4
6
8
10
12
2
0
2
6
8
10
12
–50
0
25
50
75
100
4
–25
I
(mA)
I
(mA)
TEMPERATURE (°C)
PWRGD
OPEN
42563 G15
42563 G13
42563 G14
FB Thresholds vs Temperature
FB Current vs FB Voltage
0.2
4.5
4.4
4.3
4.2
4.1
4.0
3.9
L-H THRESHOLD
0.1
0
–0.1
–0.2
–0.3
–0.4
H-L THRESHOLD
0
10
20
30
(V)
40
50
–50
0
25
50
75
100
–25
V
FB
TEMPERATURE (°C)
42563 G20
42563 G16
42563f
5
LT4256-3
U
U
U
PI FU CTIO S
UV (Pin 1): Undervoltage Sense Input. UV is an input that
enables the output voltage. When UV is driven above 4V,
GATE will start charging and the output turns on. When
UV goes below 3.6V, GATE discharges and the output
shuts off.
GND (Pin 8): Device Ground. This pin must be tied to a
ground plane for best performance.
TIMER (Pin 9): Timing Input. An external timing capacitor
from TIMER to GND programs the maximum time the part
is allowed to remain in current limit. When the part goes
into current limit, a 115µA pull-up current source starts to
charge the timing capacitor. When the voltage on TIMER
reaches 4.65V (typ), GATE is pulled low; the TIMER pull-
upcurrentwillbeturnedoffandthecapacitorisdischarged
bya3µApull-downcurrent.WhenTIMERfallsbelow0.65V
(typ), GATE turns on again if RETRY is high (if RETRY is
low, UV must be pulsed low to reset the internal fault latch
before GATE will turn on). If RETRY is grounded and UV is
not cycled low, GATE remains latched off and TIMER will
bedischargedtonearground. UVmustbecycledlowafter
TIMER has discharged below 0.65V (typ) to reset the part.
Pulsing UV to below 0.4V for at least 5µs after a current
limit fault cycle resets the fault latch (when RETRY pin is
low, commanding latch off operation) and allows the part
to turn back on. This command is only accepted after
TIMER is discharged below 0.65V. To disable UV sensing,
connect the pin to a voltage between 5V and 44V.
OV (Pin 2): Overvoltage Sense Input. OV is an input that
disables the output voltage. If OV ever goes above 4V,
GATE is discharged and the output shuts off. When OV
goes below 3.6V, GATE starts charging and the output
turnsbackon.Todisableovervoltagesensing,connectpin
to ground.
If RETRY is floating or connected to a voltage above its
1.2V threshold, the LT4256-3 automatically restarts after
acurrentfault.Underanoutputshort-circuitcondition,the
LT4256-3 cycles on and off with a 3% on-time duty cycle.
NC (Pins 3, 6, 11, 14): No Connect. Not connected to any
internal circuitry.
OPEN (Pin 4): Open Circuit Detect Output. This pin is an
open collector output that releases and is pulled high
through an external resistor if the load current is less than
(3mV)/R5.
FB (Pin 10): Power Good Comparator Input. FB monitors
the output voltage through an external resistive divider.
When the voltage on FB is lower than the high-to-low
threshold of 3.99V, PWRGD is pulled low and released
when FB is pulled above the 4.45V low-to-high threshold.
PWRGD (Pin 5): Power Good Output. PWRGD is pulled
lowwheneverthevoltageonFBfallsbelowthehigh-to-low
threshold voltage. It goes into a high impedance state
when the voltage on FB exceeds the low-to-high threshold
voltage. An external pull-up resistor can pull PWRGD to a
voltage higher or lower than VCC.
The voltage present on FB affects foldback current limit
(see Figure 8 and related discussion).
VOUT (Pin 12): Output Voltage Sense Input. This pin
shouldbeconnectedtothesourceoftheexternalMOSFET.
ItisusedtosensewhentheMOSFETisshutoff(duringany
fault mode) and to reduce the pull-down current on GATE.
ThisprotectstheLT4256-3fromexcessivepowerdissipa-
tion when large output capacitors are used.
RETRY (Pin 7): Current Fault Retry Input. RETRY com-
mands the operational mode of the current limit. If RETRY
is floating, the LT4256-3 automatically restarts after a
current fault. If it is connected to a voltage below 0.4V, it
willlatchoffafteracurrentfault(whichrequiresthatUVbe
cycled low in order to start normal operation again).
42563f
6
LT4256-3
U
U
U
PI FU CTIO S
GATE (Pin 13): High Side Gate Drive for the External
N-Channel MOSFET. An internal charge pump guarantees
at least 10V of gate drive for VCC supply voltages above
20V and 4.5V of gate drive for VCC supply voltages
between 10.8V and 20V. The rising slope of the voltage on
GATE is set by an external capacitor connected from GATE
to GND and an internal 30µA pull-up current source from
the charge pump output.
GATE is 2V (typ) below VOUT. When GATE is below VOUT
by 2V, the 62mA is reduced to 130µA to protect the
LT4256-3 against damage if VOUT has large capacitance.
AZenerdiodeisneededbetweenthegateandsourceofthe
external MOSFET to protect its gate oxide under instanta-
neous short-circuit conditions. See Applications Informa-
tion.
SENSE (Pin 15): Current Limit Sense Input. A sense
resistor is placed in the supply path between VCC and
SENSE. The current limit circuit regulates the voltage
across the sense resistor (VCC – SENSE) to 55mV while in
current limit when FB is 2V or higher. If FB drops below
2V, the regulated voltage across the sense resistor de-
creases linearly and stops at 14mV when FB is 0V. The
OPEN output also uses SENSE to detect when the output
current is less than (3mV)/R5.
If the current limit is reached, the GATE voltage is adjusted
to maintain a constant voltage across the sense resistor
while the timing capacitor starts to charge. If the TIMER
voltage ever exceeds 4.65V, GATE is pulled low.
GATE is also pulled to GND whenever UV is pulled low; the
VCC supplyvoltagedropsbelowtheexternallyprogrammed
undervoltage threshold, above the overvoltage threshold
or below the internal UVLO threshold (9.8V).
To defeat current limit, connect SENSE to VCC.
GATEisclampedinternallytoamaximumvoltageof11.6V
(typ) above VOUT under normal operating conditions.
Drivingthispinbeyondtheclampvoltagemaydamagethe
part. GATE is also clamped to 2V (typ) below VOUT. When
the gate is commanded off due to a fault condition, it is
discharged quickly by a 62mA (typ) capable switch until
VCC (Pin 16): Input Supply Voltage. The positive supply
input ranges from 10.8V to 80V for normal operation. ICC
istypically1.8mA.AninternalcircuitdisablestheLT4256-3
for inputs less than 9.8V (typ).
42563f
7
LT4256-3
W
BLOCK DIAGRA
V
SENSE
15
CC
16
+
OPEN
CIRCUIT
4
OPEN
3mV
–
V
P
V
GEN
P
10
FB
–
CURRENT
LIMIT
+
14mV TO 55mV
12
13
V
OUT
CHARGE
PUMP
AND
GATE
+
GATE
DRIVER
FOLDBACK
2V
+
–
REF GEN
4V
–
5
PWRGD
4V
7V
100k
7
1
2
RETRY
UV
OV
–
V
CC
INTERNAL
UV
9.8V
+
–
4V
LOGIC
UV
+
+
0.65V
TIMER LOW
V
P
–
–
118µA
OV
4V
+
+
TIMER HIGH
4.65V
–
9
TIMER
3µA
8
4256 BD
GND
42563f
8
LT4256-3
TEST CIRCUIT
48V
+
–
PWRGD
V
CC
OPEN SENSE
FB
GATE
100pF
48V
3V
+
+
+
OV
UV
V
–
–
–
OUT
TIMER
3V
RETRY
GND
4256 F01
Figure 1
W U
W
TI I G DIAGRA S
4V
3.6V
UV
t
t
PLHUV
PHLUV
GATE
2V
4256 F02
2V
Figure 2. UV to GATE Timing
4V
3.65V
FB
t
t
PLHFB
PHLFB
PWRGD
1V
1V
4256 F03
Figure 3. VOUT to PWRGD Timing
V
CC
– SENSE
55mV
t
PHLSENSE
V
CC
GATE
4256 F04
Figure 4. SENSE to GATE Timing
42563f
9
LT4256-3
U
W U U
APPLICATIO S I FOR ATIO
Hot Circuit Insertion
When the power pins first make contact, transistor Q1 is
held off. If the voltage on VCC is between the externally
programmed undervoltage and overvoltage thresholds,
When circuit boards are inserted into a live backplane, the
supply bypass capacitors on the boards draw high peak
currents from the backplane power bus as they charge.
The transient currents can permanently damage the con-
nector pins and glitch the system supply, causing other
boards in the system to reset.
V
CC is above 9.8V and the voltage on TIMER is less than
4.65V (typ), transistor Q1 will be turned on (Figure 6). The
voltage on GATE rises with a slope equal to 30µA/C1 and
the supply inrush current is set at:
IINRUSH = CL • 30µA/C1
(1)
The LT4256-3 is designed to turn on a board’s supply
voltage in a controlled manner, allowing the board to be
safely inserted or removed from a live backplane. The
device also provides undervoltage and overvoltage as well
as overcurrent protection while a power good output
signal indicates when the output supply voltage is ready
with a high output.
where CL is the total load capacitance.
I
OUT
500mA/DIV
PWRGD
50V/DIV
Power-Up Sequence
V
OUT
An external N-channel MOSFET pass transistor (Q1) is
placed in the power path to control the power up of the
supply voltage (Figure 5). Resistor R5 provides current
detection and capacitor C1 controls the GATE slew rate.
Resistor R7 compensates the current control loop while
R6 prevents high frequency oscillations in Q1.
50V/DIV
GATE
50V/DIV
4256 F06
5ms/DIV
Figure 6. Start-Up Waveforms
Q1
IRF530
R5
V
0.025Ω
OUT
V
IN
48V
48V
+
D1
1.6A
D2
SMAT70A
C
CMPZ5241BS
11V
L
(SHORT PIN)
16
15
V
CC
SENSE
R1
64.9k
R6
R8
36.5k
10Ω
1
13
UV
GATE
LT4256-3
R7
100Ω
R4
51k
C3
0.01µF
R2
C1
4.02k
10nF
12
10
2
OV
V
OUT
FB
R3
4.02k
R9
4.02k
4
7
5
OPEN
RETRY
9
PWRGD
PWRGD
TIMER
4256 F05
C2
33nF
GND
8
GND
UV = 36V
OV = 73V
PWRGD = 40V
Figure 5. 1.6A, 48V Latchoff Application
42563f
10
LT4256-3
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APPLICATIO S I FOR ATIO
To reduce inrush current, increase C1 or decrease load
capacitance. If the voltage across the current sense resis-
tor R5 reaches VSENSETRIP, the inrush current will be lim-
ited by the internal current limit circuitry. The voltage on
GATEisadjustedtomaintainaconstantvoltageacrossthe
sense resistor and TIMER begins to charge.
noise spikes and capacitively coupled glitches from shut-
ting down the LT4256-3 output erroneously.
To calculate UV and OV thresholds, use the following
equations:
V
R1= R2 +R3 THUVLH – 1
2a
( )
(
)
When the FB voltage goes above the low-to-high VFB
threshold, PWRGD goes high.
4V
R1+R2
R3 =
2b
( )
V
THOVLH – 1
Undervoltage and Overvoltage Detection
4
The LT4256-3 uses UV and OV to monitor the VCC voltage
to determine when it is safe to turn on the load and allow
the user the greatest flexibility for setting the operational
thresholds. UV and OV are internally connected to an
analog window comparator. Any time that UV goes below
3.6VorOVgoesabove4V,GATEwillbepulledlowuntilthe
UV/OV voltages return to the normal operation voltage
window (4V and 3.6V, respectively).
20kΩ ≤ R1+R2 +R3 ≤ 200kΩ
3
( )
R1
V
THUVHL = 3.6V 1+
;
4
( )
R2 +R3
R1+R2
R3
VTHOVHL = 3.6V 1+
where VTHULH and VTHOVLH are the desired UV and OV
threshold voltages when VCC is rising (L – H).
The UV threshold should never be set below the internal
UVLO threshold (9.8V typically) because the benefit of the
UV’s hysteresis will be lost, making the LT4256-3 more
susceptible to noise (VCC must be at least 9.8V when UV
is at its 3.6V threshold). UV is filtered with C3 to prevent
Figure 7 shows how the LT4256-3 is commanded to shut
off with a logic signal. This is accomplished by pulling the
gate of the open-drain MOSFET, Q2, (tied to UV) high.
R5
0.010Ω
Q1
IRF540
V
OUT
48V
4A
V
CC
48V
D2
D1
+
SMAT70A
CMPZ5241BS
11V
C
L
(SHORT PIN)
16
15
SENSE
R1
V
CC
R6
R8
64.9k
10Ω
36.5k
1
13
UV
GATE
LT4256-3
OFF SIGNAL
FROM MPU
R7
100Ω
Q2
VN2222
C3
0.01µF
R2
4.02k
C1
10nF
12
10
2
OV
V
OUT
FB
R4
51k
R3
4.02k
R9
4.02k
4
9
7
5
OPEN
RETRY
TIMER
PWRGD
4256 F07
C2
33nF
GND
GND
UV = 36V
OV = 73V
8
PWRGD = 40V
Figure 7. How to Use a Logic Signal to Control the LT4256-3 Turn On/Off
42563f
11
LT4256-3
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APPLICATIO S I FOR ATIO
Short-Circuit Protection
voltage across the sense resistor is held constant at 55mV
(see Figure 8).
The LT4256-3 features a programmable foldback current
limitwithanelectroniccircuitbreakerthatprotectsagainst
short circuits or excessive load currents. The current limit
is set by placing a sense resistor (R5) between VCC and
SENSE. The current limit threshold is calculated as:
For a 0.025Ω sense resistor, the typical current limit is set
at 2200mA and folds back to 560mA when the output is
shorted to ground. Thus, MOSFET peak power dissipation
under short-circuit conditions is reduced from 106W to
27W. SeetheLayoutConsiderationssectionforimportant
information about board layout to minimize current limit
threshold error.
ILIMIT = 55mV/R5
(5)
To limit excessive power dissipation in the pass transistor
and to reduce voltage spikes on the input supply during
short-circuit conditions at the output, the current folds
back as a function of the output voltage, which is sensed
internally on FB.
The LT4256-3 also features a variable overcurrent re-
sponse time. The time required for the part to regulate the
GATE voltage is a function of the voltage across the sense
resistor connected between VCC and SENSE. This helps to
eliminate sensitivity to current spikes and transients that
might otherwise unnecessarily trigger a current limit re-
sponse and increase MOSFET dissipation. Figure 9 shows
the response time as a function of the overdrive at SENSE.
IftheLT4256-3goesintocurrentlimitwhenthevoltageon
FB is 0V, the current limit circuit drives GATE to force a
constant 14mV drop across the sense resistor. As the
output at FB increases, the voltage across the sense
resistor increases until FB reaches 2V, at which point the
V
– V
SENSE
CC
12
10
8
55mV
6
4
2
14mV
4256 F09
0
50
100
150
(mV)
200
0V
2V
FB
4256 F08
V
– V
CC
SENSE
Figure 9. Response Time to Overcurrent
Figure 8. Current Limit Sense Voltage vs Feedback Pin Voltage
42563f
12
LT4256-3
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APPLICATIO S I FOR ATIO
TIMER
across the sense resistor is held at 55mV as the timer
ramps up. Once TIMER reaches its shutdown threshold
(4.65V typically), the circuit latches off.
TIMERprovidesamethodforprogrammingthemaximum
time the part is allowed to operate in current limit. When
the current limit circuitry is not active, TIMER is pulled to
GND by a 3µA current source. When the current limit
circuitry becomes active, a 118µA pull-up current source
isconnectedtoTIMERandthevoltagewillrisewithaslope
equalto115µA/CTIMER aslongasthecircuitrystaysactive.
Once the desired maximum current limit time is known,
the capacitor value is:
Automatic Restart
If RETRY is floating, then the device automatically restarts
after a current overload fault.
When the voltage at TIMER ramps back down to 0.65V
(typ), the LT4256-3 turns on again. If the short-circuit
condition at the output still exists, the cycle will repeat
itself indefinitely. The duty cycle under short-circuit con-
ditions is 3% which prevents Q1 from overheating. Fig-
ure 11 shows representative waveforms during a short
circuit.
115µA
4.65V
C nF = 25 • t ms ; C =
[ ]
• t
(6)
[
]
Whenever TIMER reaches 4.65V (typ), the internal fault
latch is set causing GATE to be pulled low and TIMER to be
discharged to GND by the 3µA current source. The part is
not allowed to turn on again until the voltage on TIMER
falls below 0.65V (typ).
Latch Off Operation
If RETRY is grounded, the LT4256-3 will latch off after a
current fault. After the part latches off, it may be com-
manded to start back up. This is accomplished by cycling
UV to ground and then back high (this command can only
be accepted after TIMER discharges below the 0.65V typ
threshold, which prevents overheating transistor Q1).
Whenever GATE is commanded off by any fault condition,
itisdischargedwithahighcurrent, turningofftheexternal
MOSFET. The waveform in Figure 10 shows how the
output latches off following a current fault. The drop
I
I
OUT
OUT
500mA/DIV
500mA/DIV
TIMER
5V/DIV
TIMER
5V/DIV
V
V
OUT
OUT
50V/DIV
50V/DIV
GATE
50V/DIV
GATE
50V/DIV
4256 F11
4256 F10
10ms/DIV
10ms/DIV
Figure 10. Latch Off Waveforms
Figure 11. RETRY Waveforms
42563f
13
LT4256-3
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APPLICATIO S I FOR ATIO
Therefore, using RETRY only, the LT4256-3 will either
latch off after an overcurrent fault condition or it will go
into a hiccup mode.
VTHPWRGD
3.99V
20kΩ ≤ R8 +R9 ≤ 200kΩ
R8 =
– 1 •R9, high to low
(7)
(8a)
(8b)
Power Good Detection
R8
V
THPWRGD = 4.45V 1+
, low to high
R9
The LT4256-3 includes a comparator for monitoring the
output voltage. The output voltage is sensed through the
FB pin via an external resistor string. The comparator’s
output (PWRGD) is an open collector capable of operating
from a pull-up as high as 80V.
OPEN Pin/Open FET Detection
OPEN is an output which signals abnormally low load
currents. When the voltage across the sense resistor is
less than 3mV, the open collector pull-down device is shut
off allowing OPEN to be externally pulled high. OPEN is
always active when VCC is above 9.8V. If VCC is below 9.8V
(the internal UVLO threshold), OPEN is pulled low.
PWRGD can be used to directly enable/disable a power
module with an active high enable input. Figure 12 shows
how to use PWRGD to control an active low enable input
power module. Signal inversion is accomplished by tran-
sistor Q2 and R10.
Open-circuit MOSFETs are detected with the LT4256-3 by
monitoring the voltage across R5 with OPEN while moni-
toring the output voltage with PWRGD. An open FET
condition is signalled when OPEN is high and PWRGD is
low (after the part has completed its start-up cycle).
The thresholds for the FB pin are 4.45V (low to high) and
3.99V (high to low). To calculate the PWRGD thresholds,
use the following equations:
R5
Q1
IRFZ34VS
V
100mΩ
OUT
V
CC
24V
24V
+
D1
D2
400mA
CMPZ5241BS
11V
SMAT70A
C
L
(SHORT PIN)
16
15
V
SENSE
R1
CC
R6
V
LOGIC
32.4k
10Ω
1
13
R10
51k
UV
GATE
LT4256-3
R7
100Ω
C3
0.01µF
R2
4.02k
C1
10nF
12
V
R8
14k
OUT
FB
2
PWRGD
10
7
OV
R3
4.02k
4
R9
4.02k
R4
27k
OPEN
RETRY
9
5
Q2
ZN3904
TIMER
PWRGD
C2
33nF
GND
8
UV = 20V
OV = 40V
GND
4256 F12
PWRGD = 18V
Figure 12. Active Low Enable PWRGD Application
42563f
14
LT4256-3
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APPLICATIO S I FOR ATIO
This open FET condition can be falsely signalled during
start-up if the load is not activated until after PWRGD goes
high. To avoid this false indication, OPEN and PWRGD
should not be polled for a period of time, tSTARTUP, given
by:
Supply Transient Protection
The LT4256-3 is 100% tested and guaranteed to be safe
from damage with supply voltages up to 80V. However,
voltage transients above 100V may cause permanent
damage.Duringashort-circuitcondition,thelargechange
in currents flowing through the power supply traces can
cause inductive voltage transients which could exceed
100V. To minimize the voltage transients, the power trace
parasitic inductance should be minimized by using wider
traces or heavier trace plating and a bypass capacitor
should be placed between VCC and GND. A surge suppres-
sor (TransZorb®) at the input can also prevent damage
from voltage transients.
3 • VCC •C1
tSTARTUP
=
(9)
30µA
This can be accomplished either by a microcontroller (if
available) or by placing an RC filter as shown in Figure 13.
OncetheOPENvoltageexceedsthemonitoringlogicthresh-
old, VTHRESH, and PWRGD is low, an open FET condition
is signalled. In order to prevent a false indication, the RC
product should be set with the following equation:
GATE Pin
A curve of gate drive vs VCC is shown in Figure 14. GATE
3 • VCC •C1
RC >
is clamped to a maximum voltage of 12.8V above VOUT
.
VLOGIC
(10)
This clamp is designed to withstand the internal charge
pump current. An external Zener diode must be used as
shown in all applications. At a minimum input supply
voltage of 10.8V, the minimum gate drive voltage is 4.5V.
When the input supply voltage is higher than 20V, the gate
drive voltage is at least 10V and a standard threshold
MOSFET can be used. In applications from 12V to 15V
range, a logic level MOSFET must be used.
30µA ln
VLOGIC – VTHRESH
Another condition that can cause a false indication is if the
LT4256-3 goes into current limit during start-up. This will
cause tSTARTUP to be longer than calculated. Also, if the
LT4256-3 stays in current limit long enough for TIMER to
fully charge up to its threshold, the LT4256-3 will either
latch off (RETRY = 0) or go into the current limit hiccup
mode (RETRY = floating). In either case, an open FET
condition will be falsely signalled. If the LT4256-3 does go
intocurrentlimitduringstart-up, C1canbeincreased(see
Power-Up Sequence).
TransZorb is a registered trademark of General Instruments, GSI.
13
12
11
10
9
8
V
LOGIC
R
7
6
LT4256-3
TO
5
OPEN
MONITORING
LOGIC
4
4
C
INTERNAL
OPEN COLLECTOR
PULL-DOWN
3
10
30
40
50
60
70
80
20
4256 F13
V
CC
(V)
4256 F14
Figure 13. Delay Circuit for OPEN FET Detection
Figure 14. ∆VGATE vs VCC
42563f
15
LT4256-3
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APPLICATIO S I FOR ATIO
In some applications it may be possible for VOUT to ring
below ground (due to the parasitic trace inductance).
Higher current applications, especially where the output
load is physically far away from the LT4256-3 will be more
susceptible to these transients. This is normal and the
LT4256-3 has been designed to allow for some ringing
below ground. However, if the application is such that
LT4256-3 becomes active and pulls down on GATE). This
is due to the MOSFET intrinsic drain to gate capacitance
forcing current into R7 and C1 when the drain voltage
steps up from ground to VCC with an extremely fast rise
time. To alleviate this situation, a diode, D3, should be put
across R7 with the cathode connected to C1 as shown in
Figure 16.
V
OUT can ring more than 3V below ground, damage may
WhenevertheLT4256-3turnstheMOSFEToff,GATEpulls
theMOSFETgatetogroundwithanopencollectorcapable
of sinking 62mA. If the output is held up by a large
reservoir capacitor, the stored energy is dissipated in the
pull-down transistor via a sneak path through the (now
forward biased) Zener, D1. The LT4256-3 has a propri-
etary feature that reduces on-chip power dissipation by
sensing when the MOSFET is off and reducing the pull-
down current significantly. See VGATE Turn-Off for more
information about using this feature.
occur to the LT4256-3 and an external diode, D2, from
ground (anode) to VOUT (cathode) will have to be added to
the circuit as shown in Figure 15 (it is critical that the
reverse breakdown voltage of the diode be higher than the
highest expected VCC voltage). A capacitor placed from
ground to VOUT directly at the LT4256-3 pins can help
reduce the amount of ringing on VOUT but it may not be
enough for some applications.
During a fault condition, the LT4256-3 pulls down on
GATE with a switch capable of sinking about 62mA. Once
GATE drops below the output voltage by a diode forward
voltage, the external Zener will forward bias and VOUT will
also be discharged to GND. In addition to the GATE
capacitance, the output capacitance will be discharged
through the LT4256-3.
VGATE Turn-Off
The LT4256-3 has a proprietary feature that reduces
power dissipation by sensing when the MOSFET is off and
reducing the pull-down current significantly. As the GATE
pin is discharged during any fault, the LT4256-3 monitors
theGATEpinandVOUT pin. WhentheGATEpinis2Vbelow
VOUT, the pull-down current is reduced from 62mA to
about 130µA.
In applications utilizing very large external N-channel
MOSFETs, the possibility exists for the MOSFET to turn on
when initially inserted into a live backplane (before the
R5
0.010Ω
Q1
IRF540
V
OUT
48V
4A
V
CC
48V
D1
+
D2
SMAT70A
CMPZ5241BS
11V
C
L
(SHORT PIN)
16
15
V
SENSE
R1
CC
R6
R8
64.9k
10Ω
36.5k
1
13
D3
MRA4003T3
UV
GATE
LT4256-3
R7
100Ω
C3
0.01µF
R2
4.02k
C1
10nF
12
10
7
V
OUT
2
FB
OV
R9
4.02k
R4
51k
R3
4.02k
4
OPEN
RETRY
9
5
TIMER
PWRGD
4256 F14
C2
33nF
GND
GND
UV = 36V
OV = 73V
8
PWRGD = 40V
Figure 15. Negative Output Voltage Protection Diode Application
42563f
16
LT4256-3
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APPLICATIO S I FOR ATIO
In order to use this feature as designed, a bidirectional
Zener diode is needed for D1. When the LT4256-3 com-
mands the MOSFET off (and a bidirectional Zener is used),
the output discharges very slowly (tOFF = (CLOAD • VOUT)/
130µA). Several variations can be implemented to dis-
charge the output faster. The recommeded method is
shown in Figure 17 and uses an external PNP transistor,
diode and resistor to discharge the output quickly.
The equation to set the nominal discharge current is:
5000
IDISCHG
=
130µA
(
)
(11)
(12)
RPROG
where RPROG must be less than 1k.
The maximum current equation is:
7000
IMAX
=
350µA
(
)
RPROG
Q1
IRF530
R5
V
0.033Ω
OUT
V
CC
48V
48V
+
D2
SMAT70A
D1
1.2A
C
CMPZ5241BS
11V
L
(SHORT PIN)
16
15
V
SENSE
R1
CC
R6
10Ω
R8
64.9k
36.5k
1
2
13
UV
OV
GATE
C3
0.1µF
D3
1N4148W
R7
100Ω
R2
4.02k
LT4256-3
C1
10nF
12
10
V
OUT
R3
4.02k
FB
R9
4.02k
R4
27k
4
9
7
5
OPEN
RETRY
TIMER
PWRGD
4256 F16
C2
33nF
GND
8
UV = 36V
OV = 73V
PWRGD = 40V
GND
Figure 16. High dV/dt MOSFET Turn-On Protection Circuit
R5
0.010Ω
Q1
IRF540
V
OUT
48V
4A
V
CC
48V
D1
+
D2
CMPZ5241BS
11V
R
PROG
SMAT70A
C
L
(SHORT PIN)
16
15
SENSE
R
18k
B
D3
1N4148
R1
V
R6
CC
64.9k
1k
Q2
2N4920
1
13
UV
GATE
LT4256-3
R7
100Ω
C3
0.01µF
R2
4.02k
C1
10nF
12
10
2
OV
V
OUT
R3
R8
36.5k
4.02k
FB
R9
R4
51k
4
7
5
4.02k
OPEN
RETRY
9
TIMER
PWRGD
4256 F17
C2
33nF
GND
8
GND
UV = 36V
OV = 73V
PWRGD = 40V
Figure 17. Enhanced Output Pull-Down Circuit
42563f
17
LT4256-3
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APPLICATIO S I FOR ATIO
Layout Considerations
immunity will be improved significantly by locating resis-
tor dividers close to the pins with short VCC and GND
traces. The minimum trace width for 1oz copper foil is
0.02" per amp to make sure the trace stays at a reasonable
temperature. 0.03" per amp or wider is recommended.
Figure 18 shows a layout that meets these requirements.
To achieve accurate current sensing, a Kelvin connection
to the current sense resistor (R5 in typical application
circuit) is recommended. Note that 1oz copper exhibits a
sheetresistanceofabout530µΩ/
cause large errors in high current applications. Noise
o
. Smallresistancescan
D1
Q1
V
IN
R6
R5
R1
R3
D2
V
OUT
R7
R8
R2
LT4256-3
R9
C1
GND
42563 F18
Figure 18. Recommended Component Placement
42563f
18
LT4256-3
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 ±.0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 ± .004
(0.38 ± 0.10)
× 45°
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
GN16 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
42563f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LT4256-3
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APPLICATIO S I FOR ATIO
Dual 48V Supply Sequencing Application
R5
0.020Ω
Q2
IRF540
V
OUT2
48V
2A
+
D3
C
L2
CMPZ5241BS
11V
R1
C1
V
SENSE
R8
R4
CC
64.9k
R6
10Ω
R7
100Ω
10nF
36.5k
51k
UV
OV
GATE
LT4256-3
C3
0.01µF
R9
4.02k
V
R2
4.02k
OUT
FB
V
IN
50V/DIV
R3
4.02k
PWRGD2
OPEN
PWRGD
RETRY
UV = 36V
OV = 73V
PWRGD = 40V
TIMER
GND
33nF
V
OUT1
50V/DIV
R5
0.020Ω
Q1
IRF540
V
48V
2A
OUT1
V
IN
48V
PWRGD1
50V/DIV
+
D2
SMAT70A
D1
C
L1
CMPZ5241BS
(SHORT PIN)
11V
V
SENSE
C1
R1
R8
R4
CC
R7
100Ω
R6
10Ω
V
10nF
64.9k
OUT2
36.5k
51k
50V/DIV
UV
OV
GATE
LT4256-3
4256 TA04
5ms/DIV
C3
0.01µF
R9
4.02k
V
R2
4.02k
OUT
FB
R3
4.02k
PWRGD1
OPEN
PWRGD
RETRY
4256 TA03
UV = 36V
OV = 73V
PWRGD = 40V
TIMER
C2
33nF
GND
GND
RELATED PARTS
PART NUMBER
LT1641-1/LT1641-2
LTC4211
DESCRIPTION
Positive 48V Hot Swap Controller in SO-8
Single Hot Swap Controller with Multifunction Current Control 2.5V to 16.5V, Active Inrush Limiting, Dual Level Cicuit Breaker
COMMENTS
9V to 80V Operation, Active Current Limit, Autoretry/Latchoff
LTC4251
–48V Hot Swap Controller in SOT-23
Floating Supply from –15V, Active Current Limiting,
Fast Circuit Breaker
LTC4252-1/LTC4252-2 –48V Hot Swap Controller in MSOP
Floating Supply from –15V, Active Current Limiting,
Power Good Output
LTC4253
–48V Hot Swap Controller and Supply Sequencer
Floating Supply from –15V, Active Current Limiting,
Enables Three DC/DC Converters
LT4254
Positive High Voltage Hot Swap Controller
Positive High Voltage Hot Swap Controller
10.8V to 36V Operation, Open-Circuit Detection
LT4256-1/LT4256-2
10.8V to 80V Operation, Active Current Limit, Autoretry/Latchoff
42563f
LT/TP 0304 1K • PRINTED IN USA
20 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
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(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2004
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