LT4276CHUFD#PBF [Linear]
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| 型号： | LT4276CHUFD#PBF |
| 厂家： | 
Linear |
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LT4276
++
+
LTPoE /PoE /PoE
PD Forward/Flyback Controller
FeaTures
DescripTion
IEEE802.3af/at and LTPoE ™ 90W Powered Device
(PD) with Forward/Flyback Controller
The LT®4276 is a pin-for-pin compatible family of IEEE
n
++
++
802.3 and LTPoE Powered Device (PD) controllers. It
n
LT4276A Supports All of the Following Standards:
includesanisolatedswitchingregulatorcontrollercapable
of synchronous operation in both forward and flyback
topologies with auxiliary power support.
n
++
LTPoE 38.7W, 52.7W, 70W and 90W
n
n
IEEE 802.3at 25.5W Compliant
IEEE 802.3af up to 13W Compliant
++
TheLT4276AemploystheLTPoE classificationscheme,
n
n
n
n
n
n
n
LT4276B is IEEE 802.3at/af Compliant
LT4276C is IEEE 802.3af Compliant
receiving 38.7W, 52.7W, 70W or 90W of power at the PD
RJ45 connector, and is backwards compatible with IEEE
802.3. The LT4276B is a fully 802.3at compliant, 25.5W
Superior Surge Protection (100V Absolute Maximum)
Wide Junction Temperature Range (–40°C to 125°C)
Auxiliary Power Support as Low as 9V
No Opto-Isolator Required for Flyback Operation
External Hot Swap™ N-Channel MOSFET for Lowest
Power Dissipation and Highest System Efficiency
>94% End-to-End Efficiency with LT4321 Ideal Bridge
Available in a 28-Lead 4mm × 5mm QFN Package
+
Type 2 (PoE ) PD. The LT4276C is a fully 802.3af compli-
ant, 13W Type 1 (PoE) PD.
The LT4276 supports both forward and flyback power
supply topologies, configurable for a wide range of PoE
applications. The flyback topology supports No-Opto
feedback. Auxiliaryinputvoltagecanbeaccuratelysensed
with just a resistor divider connected to the AUX pin.
n
n
applicaTions
The LT4276 utilizes an external, low R
N-channel
DS(ON)
n
High Power Wireless Data Systems
MOSFET for the Hot Swap function, maximizing power
delivery and efficiency, reducing heat dissipation, and
easing the thermal design.
n
Outdoor Security Camera Equipment
n
Commercial and Public Information Displays
High Temperature Applications
n
++,
L, LT, LTC, LTM, LTPoE
Linear Technology and the Linear logo are registered trademarks of
Linear Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
+
++
LTPoE 70W Power Supply in a Forward Mode
AUX
LT4276 Family
37V-57V
–
+
–
LT4276
GRADE
+
•
•
MAX DELIVERED
POWER
V
22µF
+
PORT
5V
13A
FMMT723
100µH
A
l
l
l
l
l
l
B
C
0.1µF
3.3k
10nF
–
++
LTPoE 90W
BAV19WS
RR
10µF
V
++
LTPoE 70W
(T ≤50ns)
++
LTPoE 52.7W
VPORT HS
GATE
AUX
V
IN
HS SW
SRC VCC
FFS PG
DLY
CC
V
CC
+
ISEN
++
LTPoE 38.7W
20mΩ
10k
l
l
25.5W
13W
LT4276A
–
ISEN
R
R
CLASS
l
SG
++
CLASS
100pF
100k
0.1µF
GND FB31 SS ROSC
T2P
ITHB
4276 TA01
OPTO
TO MICROPROCESSOR
4276fa
1
For more information www.linear.com/LT4276
LT4276
absoluTe MaxiMuM raTings
pin conFiguraTion
(Notes 1, 2)
TOP VIEW
VPORT, HSSRC, V Voltages .....................–0.3 to 100V
IN
HSGATE Current.................................................. 20mA
V
Voltage.................................................... –0.3 to 8V
CC
28 27 26 25 24 23
++
RCLASS, RCLASS
Voltages.................................–0.3 to 8V (and ≤ VPORT)
SFST, FFSDLY, ITHB, T2P Voltages ......–0.3 to V +0.3V
GND
AUX
1
2
3
4
5
6
7
8
22
21
20
19
18
17
16
15
DNC
V
CC
++
RCLASS /NC*
PG
CC
29
GND
RCLASS
GND
SG
+
–
ISEN , ISEN Voltages........................................... 0.3V
T2P/NC**
FB31 Voltage..................................................+12V/–30V
+
–
V
CC
ISEN
++
RCLASS/RCLASS Current .............................. –50mA
V
ISEN
CC
AUX Current........................................................ 1.4mA
ROSC Current ..................................................... 100µA
RLDCMP Current ................................................ 500µA
T2P Current.........................................................–2.5mA
Operating Junction Temperature Range (Note 3)
V
RLDCMP
CC
9
10 11 12 13 14
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
LT4276AI/LT4276BI/LT4276CI..............–40°C to 85°C
LT4276AH/LT4276BH/LT4276CH ....... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
T
= 150°C, θ = 3.4°C/W
JMAX
JC
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
++
*RCLASS is not connected in the LT4276B and LT4276C
**T2P is not connected in the LT4276C
orDer inForMaTion
LEAD FREE FINISH
LT4276AIUFD#PBF
LT4276AHUFD#PBF
LT4276BIUFD#PBF
LT4276BHUFD#PBF
LT4276CIUFD#PBF
LT4276CHUFD#PBF
TAPE AND REEL
PART MARKING* MAX PD POWER PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT4276AIUFD#TRPBF
4276A
90W
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
LT4276AHUFD#TRPBF 4276A
LT4276BIUFD#TRPBF 4276B
LT4276BHUFD#TRPBF 4276B
LT4276CIUFD#TRPBF 4276C
LT4276CHUFD#TRPBF 4276C
90W
25.5W
25.5W
13W
13W
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
4276fa
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For more information www.linear.com/LT4276
LT4276
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VVPORT = VHSSRC = VVIN = 40V, VVCC = VCCREG, ROSC, PG, and SG Open,
RFFSDLY = 5.23kΩ to GND. AUX connected to GND unless otherwise specified. (Note 2)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
60
UNITS
l
l
l
l
l
l
l
l
l
l
VPORT, HSSRC, V Operating Voltage
At VPORT Pin
V
V
V
V
V
V
V
V
V
V
IN
V
V
V
VPORT Signature Range
At VPORT Pin
1.5
12.5
5.6
8
10
SIG
VPORT Classification Range
VPORT Mark Range
At VPORT Pin
21
CLASS
MARK
At VPORT Pin, After 1st Classification Event
10
VPORT AUX Range
At VPORT Pin, V
≥ 6.45V
60
AUX
Signature/Class Hysteresis Window
Reset Threshold
1.0
2.6
5.6
37
V
V
Hot Swap Turn-On Voltage
Hot Swap Turn-Off Voltage
Hot Swap On/Off Hysteresis Window
35
31
HSON
30
3
HSOFF
Supply Current
VPORT, HSSRC & V Supply Current
l
l
l
V
= V
= V = 60V
2
mA
mA
mA
IN
VPORT
VPORT
VPORT
HSSRC
VIN
++
= 17.5V, RCLASS, RCLASS Open
VPORT Supply Current During Classification V
0.7
0.4
1.0
1.3
2.2
VPORT Supply Current During Mark Event
Signature and Classification
V
= V after 1st Classification Event
MARK
l
l
l
l
Signature Resistance
V
V
(Note 4)
23.6
5.2
24.4
8.3
25.5
11.4
1.43
2
kΩ
kΩ
V
SIG
Signature Resistance During Mark Event
(Note 4)
MARK
++
RCLASS/RCLASS Voltage
–10mA ≥ I
≥ –36mA
1.36
1.40
RCLASS
Classification Stability Time
V
Step to 17.5V, R
= 35.7Ω
ms
VPORT
CLS
Digital Interface
l
l
l
l
V
AUX Threshold
AUX Pin Current
T2P Output High
T2P Leakage
V
V
V
V
= 17.5V, V = V
= 18.5V
6.05
3.3
6.25
5.3
6.45
7.3
0.3
1
V
µA
V
AUXT
AUXH
PORT
IN
HSSRC
I
= 6.05V, V
= 17.5V, V = 9V, V = 0V
PORT IN CC
AUX
VCC
T2P
- V , –1mA Load
T2P
= 0V
–1
µA
Hot Swap Control
l
l
l
I
HSGATE Pull Up Current
HSGATE Voltage
V
- V = 5V (Note 5)
HSSRC
–27
10
–22
7.6
–18
14
µA
V
GPU
HSGATE
–10µA Load, with respect to HSSRC
- V = 5V
HSGATE Pull Down Current
V
400
µA
HSGATE
HSSRC
V
Supply
CC
l
l
VCCREG
V
Regulation Voltage
7.2
8.0
V
CC
Feedback Amplifier
V
FB31 Regulation Voltage
FB31 Pin Bias Current
3.11
3.17
-0.1
–40
3.23
V
µA
FB
RLDCMP Open
Time Average, –2µA < I
l
l
gm
Feedback Amplifier Average Trans-
Conductance
< 2µA
–52
4.4
–26
µA/V
ITHB
I
ITHB Average Sink Current
Time Average, V
= 0V
8.0
13.4
µA
µA
SINK
FB31
Soft-Start
l
I
Charging Current
V
SFST
= 0.5V, 3.0V
–49
–42
–36
SFST
4276fa
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For more information www.linear.com/LT4276
LT4276
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VVPORT = VHSSRC = VVIN = 40V, VVCC = VCCREG, ROSC, PG, and SG Open,
RFFSDLY = 5.23kΩ to GND. AUX connected to GND unless otherwise specified. (Note 2)
SYMBOL PARAMETER
Gate Outputs
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
PG, SG Output High Level
I = –1mA
V
CC
–0.1
V
V
PG, SG Output Low Level
PG Rise Time, Fall Time
SG Rise Time, Fall Time
I = 1mA
1
PG = 1000pF
SG = 400pF
15
15
ns
ns
Current Sense/Overcurrent
l
l
V
Overcurrent Fault Threshold
V + - V –
ISEN ISEN
125
140
155
–98
mV
FAULT
ΔV
ΔV
/
Current Sense Comparator Threshold with
–130
–111
mV/V
SENSE
ITHB
Respect to V
ITHB
l
V
V
Offset
ITHB
3.03
3.17
3.33
V
ITHB(OS)
Timing
l
l
f
Default Switching Frequency
Switching Frequency
ROSC Pin Open
= 45.3kΩ to GND
200
280
214
300
223
320
kHz
kHz
OSC
R
OSC
++
f
t
LTPoE Signal Frequency
f
/256
SW
T2P
l
l
Minimum PG On Time
175
63
250
66
330
70
ns
%
MIN
D
Maximum PG Duty Cycle
PG Turn-On Delay-Flyback
MAX
t
5.23kΩ from FFSDLY to GND
52.3kΩ from FFSDLY to GND
45
171
92
ns
ns
ns
ns
PGDELAY
PG Turn-On Delay-Forward
10.5kΩ from FFSDLY to V
52.3kΩ from FFSDLY to V
CC
CC
391
t
t
t
Feedback Amp Enable Delay Time
Feedback Amp Sense Interval
350
550
ns
ns
FBDLY
FB
PG Falling to SG Rising Delay Time-Flyback Resistor from FFSDLY to GND
PG Falling to SG Falling Delay Time-
Forward
20
67
301
ns
ns
ns
PGSG
10.5kΩ from FFSDLY to V
52.3kΩ from FFSDLY to V
CC
CC
l
l
l
t
t
I
Start Timer (Note 6)
Fault Timer (Note 6)
MPS Current
Delay After Power Good
80
80
10
86
86
12
93
93
14
ms
ms
mA
START
FAULT
MPS
Delay After Overcurrent Fault
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4. Signature resistance specifications do not include resistance
added by the external diode bridge which can add as much as 1.1kΩ to the
port resistance.
Note 5. I
available in PoE powered operation. That is, available after
GPU
Note 2. All voltages with respect to GND unless otherwise noted. Positive
currents are into pins; negative currents are out of pins unless otherwise
noted.
V(VPORT) > V
and V(AUX) < V
and 60V.
, over the range where V(VPORT)
HSON
AUXT
is between V
HSOFF
Note 6. Guaranteed by design, not subject to test.
Note 3. This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature can exceed 150°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
4276fa
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For more information www.linear.com/LT4276
LT4276
Typical perForMance characTerisTics
Input Current vs Input Voltage
25k Detection Range
Signature Resistance
vs Input Voltage
VCC Current vs Temperature
0.5
0.4
0.3
0.2
0.1
0
26.25
25.75
25.25
24.75
24.25
23.75
12
10
8
125°C
85°C
25°C
–40°C
125°C
85°C
25°C
–40°C
300KHz
214KHz
6
4
2
0
0
2
4
6
8
10
1
2
3
4
5
6
7
8
9
–50 –25
0
25
50
75 100 125
VPORT VOLTAGE (V)
VPORT VOLTAGE (V)
TEMPERATURE (°C)
4276 G01
4276 G02
4276 G03
Feedback Amplifier Output Current
vs VFB31
Switching Frequency
vs Temperature
VFB31 vs Temperature
3.178
3.176
3.174
3.172
3.170
3.168
3.166
3.164
3.162
15
10
5
325
300
275
250
225
200
175
125°C
85°C
25°C
–40°C
R
OSC
= 45.3k
0
–5
–10
–15
ROSC OPEN
–50 –25
0
25
50
75 100 125
2.57 2.77 2.97 3.17 3.37 3.57 3.77
FB31 VOLTAGE (V)
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
4276 G04
4276 G05
4276 G06
Current Sense Voltage
vs Duty Cycle, ITHB
PG Delay Time vs Temperature in
Flyback Mode
PG Delay Time vs Temperature in
Forward Mode
160
140
120
100
80
250
400
350
300
250
200
150
100
50
V
= 0.96V (FB31 = 0V)
ITHB
T
, R
= 52.3k
PGDELAY FFSDLY
200
150
100
50
V
= 1.8V
R
= 52.3k
ITHB
FFSDLY
T
, R
= 52.3k
PGSG FFSDLY
V
= 2.3V
= 2.6V
ITHB
ITHB
60
T
T
, R
= 10.5k
PGDELAY FFSDLY
40
R
= 5.23k
FFSDLY
V
20
, R
= 10.5k
PGSG FFSDLY
V
= 2.9V
30
ITHB
0
0
0
0
10
20
40
50
60
70
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
DUTY CYCLE (%)
TEMPERATURE (°C)
TEMPERATURE (°C)
4276 G07
4276 G08
4276 G09
4276fa
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For more information www.linear.com/LT4276
LT4276
pin FuncTions
GND(Pins 1, 19, Exposed Pad Pin 29): Device Ground.
ExposedPadmustbeelectricallyandthermallyconnected
to PCB GND and Pin 19.
FET. Note that the voltage gain from ITHB to the input of
the current sense comparator (V ) is negative.
SENSE
FB31 (Pin 14): Feedback Input. In flyback mode, connect
external resistive divider from the third winding feedback.
Reference voltage is 3.17V. Connect to GND in forward
mode.
++
++
++
RCLASS (Pin 3, LT4276A Only): LTPoE Class Select
Input. Connect a resistor between RCLASS to GND per
Table 1.
AUX (Pin 2): Auxiliary Sense. Assert AUX via a resistive
divider from the auxiliary power input to set the voltage
at which the auxiliary supply takes over. Asserting AUX
pulls down HSGATE, disconnects the signature resistor
RLDCMP (Pin 15): Load Compensation Adjustment. Op-
tional resistor to GND controls output voltage set point
as a function of peak switching current. Leave RLDCMP
open if load compensation is not needed.
and disables classification. The AUX pin sinks I
when
AUXH
–
ISEN (Pin 16): Current Sense, Negative Input. Route as
belowitsthresholdvoltageofV
Connect to GND if not used.
toprovidehysteresis.
AUXT
a dedicated trace to the current sense resistor.
+
ISEN (Pin 17): Current Sense, Positive Input. Route as
RCLASS (Pin 4): Class Select Input. Connect a resistor
between RCLASS to GND per Table 1.
a dedicated trace to the current sense resistor.
SG(Pin18):Secondary(Synchronous)GateDrive,Output.
PG (Pin 20): Primary Gate Drive, Output.
T2P(Pin5,LT4276AandLT4276Bonly):PSETypeIndica-
tor.LowimpedancetoV indicates2-eventclassification.
CC
++
Alternating low/high impedance indicates LTPoE clas-
V
(Pins 6, 7, 8, 9, 21): Switching Regulator Controller
CC
sification (LT4276A only, see Applications Information).
High impedance indicates 1-event classification. This pin
is not connected on the LT4276C. See the Applications
Information Section for pin behavior when using the AUX
pin.
Supply Voltage. Connect a local 1µF ceramic capacitor
from V pin 21 to GND pin 19 as close as possible to
CC
LT4276 as shown in Table 2.
SWVCC(Pin 23): Switch Driver for V ’s Buck Regulator.
CC
This pin drives the base of a PNP in a buck regulator to
DNC (Pin 22): Do Not Connect. Leave pin open.
generate V .
CC
ROSC (Pin 10): Programmable Frequency Adjustment.
Resistor to GND programs operating frequency. Leave
open for default frequency of 214kHz.
V
(Pin 24): Buck Regulator Supply Voltage. Usually
IN
separated from HSSRC by a pi filter.
HSSRC (Pin 25): External Hot Swap MOSFET Source.
Connect to source of the external MOSFET.
SFST (Pin 11): Soft-Start. Capacitor to GND sets soft-
start timing.
HSGATE (Pin 26): External Hot Swap MOSFET Gate Con-
trol, Output. Capacitance to GND determines inrush time.
FFSDLY (Pin 12): Forward/Flyback Select and Primary
GateDelayAdjustment.ResistortoGNDadjustsgatedrive
NC (Pin 27): No Connection. Not internally connected.
delay for a flyback topology. Resistor to V adjusts gate
CC
drive delay for a forward topology.
VPORT(Pin28):PDInterfaceSupplyVoltageandExternal
Hot Swap MOSFET Drain Connection.
ITHB (Pin 13): Current Threshold Control. The voltage on
this pin corresponds to the peak current of the external
4276fa
6
For more information www.linear.com/LT4276
LT4276
block DiagraM
VPORT
V
IN
SWVCC
CP
INTERNAL
BUCK
CONTROLLER
START-UP
REGULATOR
V
CC
HSGATE
11V
V
CC
PD INTERFACE
CONTROLLER
HSSRC
VPORT
T2P
+
–
1.4V
TSD
GND
RCLASS
VPORT
+
–
1.4V
PG
SG
++
RCLASS
+
AUX
–
V
AUXT
I
AUXH
FB31
+
–
ITHB
SFST
V
FB
V
CC
FEEDBACK AMP
gm = –40µA/V
SWITCHING
REGULATOR
CONTROLLER
FFSDLY
ROSC
LOAD
COMP
OSC
+
–
V
V
ITHB(OS)
CURRENT
FAULT
COMPARATOR
CURRENT
SENSE
COMPARATOR
∆V
∆V
SENSE
ITHB
A
=
V
A
= 10
V
SLOPE
COMP
SENSE
V
FAULT
+
+
ISEN
–
A
V
= 1
4276 BD
–
ISEN
RLDCMP
4276fa
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For more information www.linear.com/LT4276
LT4276
applicaTions inForMaTion
OVERVIEW
V
SENSE
Power over Ethernet (PoE) continues to gain popularity
as products take advantage of DC power and high speed
data available from a single RJ45 connector. The LT4276A
allowshigherpowerwhilemaintainingbackwardscompat-
ibility with existing PSE systems. The LT4276 combines
a PoE PD controller and a switching regulator controller
capable of either flyback or forward isolated power sup-
ply operation.
∆V
SENSE
∆V
ITHB
V
ITHB
V
ITHB(OS)
4276 F01
SIGNIFICANT DIFFERENCES FROM PREVIOUS
PRODUCTS
Figure 1. VSENSE vs. VITHB
Flyback/Forward Mode Is Pin Selectable
The LT4276 has several significant differences from pre-
vious Linear Technology products. These differences are
briefly summarized below. See Applications Information
for more detail.
The LT4276 operates in flyback mode if FFSDLY is pulled
down by a resistor to GND. It operates in forward mode
if FFSDLY is pulled up by a resistor to V . The value of
CC
and t
this resistor determines the t
.
PGDELAY
PGSG
ITHB Is Inverted from the Usual ITH pin
T2P Pin Polarity Is Reversed
TheITHBpinvoltagehasaninverserelationshiptothecur-
rentsensecomparatorthreshold,V
.Furthermore,the
SENSE
The T2P pin pulls up to V when active rather than pull-
CC
ITHB pin offset voltage, V
, is 3.17V. See Figure 1.
ITHB(OS)
ing down to GND.
Duty-Cycle Based Soft-Start
V
CC
Is Powered by Internally Driven Buck Regulator
The LT4276 uses a duty cycle ramp soft-start that injects
charge into ITHB. This allows startup without appreciable
overshoot and with inexpensive external components.
The LT4276 includes a buck regulator controller that must
be used to generate the V supply voltage.
CC
PoE MODES OF OPERATION
The Feedback Pin (FB31) is 3.17V rather than 1.25V
The LT4276 has several modes of operation, depending
on the input voltage sequence applied to the VPORT pin.
The error amp feedback voltage (V ) is 3.17V.
FB
Table 1. Classification Codes, Power Levels and Resistor Selection
LT4276 GRADE CAPABILITY
RESISTOR (1%)
PD POWER
AVAILABLE
13W
3.84W
6.49W
13W
25.5W
38.7W
52.7W
70W
NOMINAL CLASS
CURRENT
++
CLASS
0
1
2
3
PD TYPE
Type 1
Type 1
Type 1
Type 1
Type 2
A
√
√
√
√
√
√
√
√
√
B
√
√
√
√
√
C
√
√
√
√
R
R
CLS
CLS
0.7mA
10.5mA
18.5mA
28mA
40mA
40mA
40mA
40mA
40mA
Open
150Ω
80.6Ω
52.3Ω
35.7Ω
Open
150Ω
80.6Ω
52.3Ω
Open
Open
Open
Open
Open
35.7Ω
47.5Ω
64.9Ω
118Ω
4
++
4*
4*
4*
4*
LTPoE
++
LTPoE
++
LTPoE
++
90W
LTPoE
++
*An LTPoE PD classifies as class 4 by an IEEE 802.3 compliant PSE.
4276fa
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For more information www.linear.com/LT4276
LT4276
applicaTions inForMaTion
Detection
POWER ON
During detection, the PSE looks for a 25kΩ signature
resistor which identifies the device as a PD. The LT4276
signature resistor is smaller than 25k to compensate for
the additional series resistance introduced by the IEEE
required bridge.
V
HSON
V
HSOFF
CLASS
V
CLASSMIN
V
SIGMAX
Classification
DETECT
The detection/classification process varies depending on
V
RESET
++
whether the PSE is Type 1, Type 2, or LTPoE . A Type 1
V
SIGMIN
PSE, after a successful detection, may apply a classifica-
tion probe voltage of 15.5V to 20.5V and measure current.
4276 F02
Figure 2. Type 1 Detect/Class Signaling Waveform
In 2-event classification, a Type 2 PSE probes for power
classification twice as shown in Figure 3. The LT4276A or
POWER ON
LT4276BrecognizesthisandpullstheT2PpinuptoV to
CC
signal the load that Type 2 power is available. Otherwise it
V
HSON
does not pull up on the T2P pin, indicating that only Type
V
HSOFF
++
1 power is available. If an LT4276A senses an LTPoE
PSE it alternates between pulling T2P up and floating T2P
++
1ST CLASS 2ND CLASS
V
CLASSMIN
at a rate of f to indicate the LTPoE power is available.
T2P
V
SIGMAX
++
LTPoE Classification
DETECT
The LT4276A allows higher power allocation while main-
tainingbackwardscompatibilitywithexistingPSEsystems
by extending the classification signaling of IEEE 802.3.
1ST MARK 2ND MARK
V
RESET
V
SIGMIN
4276 F03
++
Linear Technology PSE controllers capable of LTPoE
Figure 3. Type 2 Detect/Class Signaling Waveform
are listed in the Related Parts section. IEEE PSEs classify
++
an LTPoE PD as a Type 2 PD.
POWER ON
Classification Resistors (R
and R
)
++
CLS
CLS
V
HSON
The R
and R
resistors set the classification cur-
++
CLS
CLS
V
HSOFF
rent corresponding to the PD power classification. Select
1ST CLASS 2ND CLASS 3RD CLASS
the value of R
from Table 1 and connect the resistor
CLS
++,
V
between the RCLASS pin and GND. For LTPoE
use
CLASSMIN
the LT4276A and select the value of R
from Table
++
CLS
V
SIGMAX
1 in addition to R . The resistor tolerance must be 1%
CLS
DETECT
or better to avoid degrading the overall accuracy of the
1ST MARK 2ND MARK 3RD MARK
V
RESET
classification circuit.
V
SIGMIN
Signature Corrupt During Mark
4276 F04
++
Figure 4. LTPoE Detect/Class Signaling Waveform
During the mark state, the LT4276 presents <11kΩ to the
port as required by the IEEE specification.
4276fa
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For more information www.linear.com/LT4276
LT4276
applicaTions inForMaTion
Inrush and Powered On
EXTERNAL V SUPPLY
CC
Once the PSE detects and optionally classifies the PD, the
PSE then powers on the PD. When the port voltage rises
The external V supply must be configured as a buck
CC
regulatorshowninFigure6.Tooptimizethebuckregulator,
use the external component values in Table 2 correspond-
above the V
threshold, it begins to source I
out
HSON
GPU
of the HSGATE pin. This current flows into an external
capacitor (C in Figure 5) that causes a voltage to ramp
ing to the V operating range. This buck regulator runs
IN
in discontinuous mode with the inductor peak current
GATE
up the gate of the external MOSFET. The external MOSFET
acts as a source follower and ramps the voltage up on
considerably higher than average load current on V .
CC
Thus, the saturation current rating of the inductor must
the output bulk capacitor (C
in Figure 5), thereby
exceed the values shown in Table 2. Place the capacitor, C,
PORT
determining the inrush current (I
in Figure 5). To
to be ~100mA.
as close as possible to V pin 21 and GND pin 19. For
INRUSH
INRUSH
CC
meet IEEE requirements, design I
optimal performance, place the external components as
close as possible to the LT4276.
The LT4276 internal charge pump provides an N-channel
MOSFET solution, eliminating a larger and more costly
V
IN
V
IN
P-channel FET. The low R
MOSFET also maximizes
DS(ON)
R
e
power delivery and efficiency, reduces power and heat
dissipation, and eases thermal design.
FMMT723
PBSS9110T
SWVCC
LT4276
I
INRUSH
L(µH)
VPORT
+
V
GND
V
CC
3.3k
C
PORT
CC
C(µF)
C
GATE
I
GPU
4276 F06
HSGATE
Figure 6. VCC Buck Regulator
VPORT
HSSRC
Table 2 . Buck Regulator Component Selection
LT4276
GND
CPORT
CGATE
IINRUSH =IGPU •
V
IN
C
L
I
R
e
1Ω
20Ω
SAT
9V-57V
PoE
22µF
10µF
22µH
100µH
≥1.2A
≥300mA
4276 F05
AUXILIARY SUPPLY OVERRIDE
Figure 5. Programming IINRUSH
If the AUX pin is held above V
, the LT4276 enters
AUXT
DELAY START
auxiliary power supply override mode. In this mode the
signature resistor is disconnected, classification is dis-
abled, and HSGATE is pulled down. The T2P pin pulls up
After the HSGATE charges up to approximately 7V above
HSSRC, fully enhancing the external Hot Swap MOSFET,
the switching regulator controller operates after a delay
++
to V on the LT4276B (or the LT4276A when no R
CC
CLS
resistorispresent).TheT2Ppinalternatesbetweenpulling
of t
. During this delay, the LT4276 draws I
from
START
MPS
++
CLS
up and floating at f on the LT4276A when the R
VPORT to ensure that the PSE does not DC disconnect
T2P
resistor is present.
the PD due to Maintain Power Signature requirements.
The AUX pin allows for setting the auxiliary supply turn on
(V ) and turn off (V ) voltage thresholds. The
AUXON
AUXOFF
auxiliary supply hysteresis voltage (V
sinking current (I
) is set by
AUXHYS
) only when the AUX pin voltage is
AUXH
4276fa
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For more information www.linear.com/LT4276
LT4276
applicaTions inForMaTion
lessthanV
.UsethefollowingequationstosetV
AUXT
AUXON
and V
via R1 and R2 in Figure 7. A capacitor up to
t
PGon
AUXOFF
PG
SG
1000pF may be placed between the AUX pin and GND to
improve noise immunity.
t
PGDELAY
t
PGSG
V
must be lower than V
.
AUXON
HSOFF
4276 F07
VAUXON − VAUXOFF VAUXHYS
+
R1=
=
IAUXH
R1
IAUXH
Figure 8: PG and SG Relationship in Flyback Mode
LT4276
GND
R1
R2
R2 =
R1≥
V
AUX
VAUXOFF
VAUXT
•
AUX
+
−1
•
VAUX(MAX) − VAUXT
–
4276 F08a
PG
1.4mA
Figure 7. AUX Threshold and Hysteresis Calculation
LT4276
+
–
ISEN
SWITCHING REGULATOR CONTROLLER OPERATION
ISEN
GND FFSDLY SG
The switching regulator controller portion of the LT4276
is a current mode controller capable of implementing
either a flyback or a forward power supply. When used in
flyback mode, no opto-isolator is required for feedback
becausetheoutputvoltageissensedviathetransformer’s
third winding.
•
•
R
FFSDLY
4276 F08
Figure 9: Example PG and SG Connections in Flyback Mode
Flyback Mode
Forward Mode
The LT4276 is programmed into flyback mode by placing
The LT4276 is programmed into forward mode by placing
a resistor R
from the FFSDLY pin to GND. This resis-
FFSDLY
aresistorR
fromtheFFSDLYpintoV . TheR
FFSDLY CC FFSDLY
tor must be in the range of 5.23kΩ to 52.3kΩ. If using a
potentiometer to adjust R , ensure the adjustment
resistormustbeintherangeof10.5kΩto52.3kΩ. Ifusing
a potentiometer to adjust R ensure the adjustment
FFSDLY
FFSDLY
of the potentiometer does not exceed 52.3kΩ.The value
of the potentiometer does not exceed 52.3kΩ.
The value of R determines t and t ac-
PGSG
of R determines t according to the following
FFSDLY
PGDELAY
FFSDLY
PGDELAY
equations:
cording to the following equations:
t
t
PGDELAY ≈2.69ns/kΩ•RFFSDLY +30ns
PGSG ≈20ns
t
t
≈ 7.16ns/kΩ • R
+ 17ns
PGDELAY
FFSDLY
≈ 5.60ns/kΩ • R
+ 7.9ns
PGSG
FFSDLY
The PG and SG relationships in flyback mode are shown
in Figure 8.
The PG and SG relationships in forward mode are shown
in Figure 10.
The SG pin must be connected to the secondary side
MOSFET through a gate drive transformer as shown in
Figure 9. Add a Schottky diode from PG to GND as shown
in Figure 9 to prevent PG from going negative.
4276fa
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For more information www.linear.com/LT4276
LT4276
applicaTions inForMaTion
THIRD
LT4276
ITHB
R
R
FEEDBACK
FB1
•
•
FB31
PG
SG
V
+
–
OUT
V
IN
V
FB
FB2
PRIMARY
SECONDARY
•
PG
t
PGDELAY
t
PGSG
+
–
ISEN
ISEN
A
= 10
V
4276 F09
+
–
+
–
R
SENSE
Figure 10: PG and SG relationship in Forward Mode
RLDCMP
4276 F11
R
LDCMP
V
CC
•
•
R
FFSDLY
Figure 12: Feedback and Load Compensation Connection
V
FFSDLY
CC
PG
LT4276
+
–
ISEN
ISEN
FB31
VOLTAGE
V
FB
GND
SG
GND
PG
SG
4276 F10
Figure 11: Example PG and SG Connections in Forward Mode
4276 F09
t
t
FBDLY FB
In forward mode, the SG pin has the correct polarity to
drivetheactiveclampP-channelMOSFETthroughasimple
level shifter as shown in Figure 11. Add a Schottky diode
from the PG to GND as shown in Figure 11 to prevent PG
from going negative.
Figure 13: Feedback Amplifier Timing Diagram
FEEDBACK AMPLIFIER OUTPUT, ITHB
As shown in the Block Diagram, V
is the input of
SENSE
the Current Sense Comparator. V
is derived from
SENSE
FEEDBACK AMPLIFIER
the output of a linear amplifier whose input is the voltage
on the ITHB pin, V
.
In the flyback mode, the feedback amplifier senses the
output voltage through the transformer’s third winding as
showninFigure12.Theamplifierisenabledonlyduringthe
ITHB
This linear amplifier inverts its input, V
, with a gain,
ITHB
ΔV
/ΔV
, and with an offset voltage of V
SENSE
to yield its output, V
graphically in Figure 1. Note the slope ΔV
is a negative number and is provided in the electrical
ITHB ITHB(OS)
fixed interval, t , as shown in Figure 13. This eliminates
FB
. This relationship is shown
SENSE
theopto-isolatorinisolateddesigns,thusgreatlyimproving
/ΔV
SENSE
ITHB
the dynamic response and stability over lifetime. Since t
FB
is a fixed interval, the time-averaged transconductance,
gm, varies as a function of the user-selected switching
frequency.
characteristics table.
–1
⎛
⎞
ΔVSENSE
V
ITHB = VITHB(OS) + VSENSE •
⎜
⎟
ΔV
⎝
⎠
ITHB
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LT4276
applicaTions inForMaTion
The block diagram shows V
is compared against
Where: ΔV
is the desired change to V
OUT OUT
FB2 FB2
SENSE
+
the voltage across the current sense resistor, V(ISEN )-
ΔR is the required change to R
–
V(ISEN ) modified by the internal slope compensation
N
/N
is the transformer third
THIRD SECONDARY
voltage discussed subsequently.
winding to secondary winding
LOAD COMPENSATION
OPTO-ISOLATOR FEEDBACK
As can be seen in Figure 13, the voltage on the FB31 pin
droops slightly during the flyback period. This is mostly
caused by resistances of components of the secondary
Forforwardmodeoperation, theflybackvoltagecannotbe
sensed across the transformer. Thus, opto-isolator feed-
back must be used. When using opto-isolator feedback,
connect the FB31 pin to GND and leave the RLDCMP pin
open. In this condition, the feedback amplifier sinks an
side such as: the secondary winding, R
of the syn-
DS(ON)
chronous MOSFET, ESR of the output capacitor, etc. These
resistances cause a feedback error that is proportional to
the current in the secondary loop at the time of feedback
sample window. To compensate for this error, the LT4276
places a voltage proportional to the peak current in the
primary winding on the RLDCMP pin.
average current of I
into the ITHB pin. An example for
SINK
feedback connections is shown in Figure 14. Note that
since I is time-averaged over the switching period,
SINK
the sink current varies as a function of the user-selected
switching frequency.
Determining Feedback and Load Compensation
Resistors
V
OUT
V
CC
Because the resistances of components on the secondary
side are generally not well known, an empirical method
must be used to determine the feedback and load com-
pensation resistor values.
C
X
LT4276
R
X
ITHB
GND
FB31
INITIALLY SET RFB2 = 2kΩ
4276 F13
VOUT NTHIRD
VFB NSECONDARY
RFB1≈RFB2
–RFB2
Figure 14: Opto-isolator Feedback
Connections in the Forward Mode
SOFT-START
ConnecttheresistorR
betweentheRLDCMPpinand
LDCMP
GND. R
must be at least 10kΩ. Adjust R
for
LDCMP
LDCMP
In PoE applications, a proper soft-start design is required
to prevent the PD from drawing more current than the
PSE can provide.
minimumchangeofV overthefullinputandoutputload
OUT
range. Apotentiometerinserieswith10kΩmaybeinitially
used for R
and adjusted. The potentiometer+10kΩ
LDCMP
The soft-start time, t
, is approximately the time in
SFST
may then be removed, measured, and replaced with the
equivalent fixed resistor. The resulting V differs from
which the power supply output voltage, V , is charg-
OUT
OUT
ing its output capacitance, C . This results in an inrush
OUT
the desired V
due to offset injected by load compensa-
OUT
current at the port of the PD, Iport_inrush. Care must be
tion. The change to R to correct this is predicted by:
FB2
taken in selecting t
more current than the PSE can provide.
to prevent the PD from drawing
SFST
2
ΔVOUT NTHIRD RFB2
VFB NSECONDARY RFB1
ΔRFB2
=
4276fa
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LT4276
applicaTions inForMaTion
In the absence of an output load current, the Iport_inrush,
SLOPE COMPENSATION
is approximated by the following equation:
The LT4276 incorporates current slope compensation.
Slope compensation is required to ensure current loop
stability when the duty cycle is greater than or near 50%.
The slope compensation of the LT4276 does not reduce
the maximum peak current at higher duty cycles.
2
Iport_inrush ≈ (C
• V
)/(η • t • V )
SFST IN
OUT
OUT
where η is the power supply efficiency,
V is the input voltage of the PD
IN
Iport_inrush plus the port current due to the load current
must be below the current the PSE can provide. Note that
the PSE current capability depends on the PSE operating
standard.
CONTROL LOOP COMPENSATION
In flyback mode, loop frequency compensation is per-
formed by connecting a resistor/capacitor network from
the output of the feedback amplifier (ITHB pin) to GND as
shown in Figure 12. In forward mode, loop compensation
The LT4276 contains a soft-start function that controls
t
by connecting an external capacitor, C
, between
is performed by varying R and C in Figure 14.
SFST
SFST
X X
theSFSTpinandGND. TheSFSTpinispulledupwithI
SFST
when the LT4276 begins switching. The voltage ramp on
the SFST pin is proportional to the duty cycle ramp for PG.
ADJUSTABLE SWITCHING FREQUENCY
TheLT4276hasadefaultswitchingfrequency,f ,of214
OSC
For flyback mode, the soft-start time is:
kHz when the ROSC pin is left open. If a higher switching
frequency, f , is desired (up to 300 kHz), a resistor no
SW
⎛
⎞
CSFST
600µA
nF
smaller than 45.3kΩ may be added between the ROSC pin
tSFST
=
tPGon + tPGDELAY – tMIN
(
)
⎜
⎟
I
⎝
⎠
to GND. The resistor can be calculated below:
SFST
where t
is the time when PG is high as shown in
3900kΩ•kHz
PGon
ROSC
=
kΩ
( )
Figure 8 once the power supply is in steady-state.
fSW – fOSC
Inforwardmode, eachofthebackpageapplicationssche-
matics provides a chart with t
vs. C
SFST
. Select the
SHORT CIRCUIT RESPONSE
SFST
SFST
application and choose a value of C
that corresponds
If the power supply output voltage is shorted, overloaded,
or if the soft-start capacitor is too small, an overcurrent
fault event occurs when the voltage across the sense pins
to the desired soft-start time.
CURRENT SENSE COMPARATOR
exceeds V
(after the blanking period of t ). This
FAULT
MIN
begins the internal fault timer t
. For the duration
The LT4276 uses a differential current sense comparator
to reduce the effects of stray resistance and inductance
FAULT
of t
, the LT4276 turns off PG and SG and pulls the
FAULT
SFST pin to GND. After t
ates soft-start.
expires, the LT4276 initi-
+
on the measurement of the primary current. ISEN and
FAULT
–
ISEN mustbeKelvinconnectedtothesenseresistorpads.
The fault and soft-start sequence repeats as long as the
shortcircuit oroverload conditionspersist. This condition
is recognized by the PG waveform shown in Figure 15
Like most switching regulator controllers, the current
sense comparator begins sensing the current t
after
MIN
PG turns on. Then, the comparator turns PG off after the
repeating at an interval of t
.
+
voltage across ISEN and ISEN– exceeds the current
sensecomparatorthreshold,V .Notethatthevoltage
FAULT
SENSE
t
FAULT
+
across ISEN and ISEN– is modified by LT4276’s internal
slope compensation.
4276 F14
Figure 15: PG Waveform with Output Shorted
4276fa
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LT4276
applicaTions inForMaTion
For high efficiency applications, the LT4276 supports
an LT4321-based PoE ideal diode bridge that reduces
the forward voltage drop from 0.7V to nearly 20mV per
diode in normal operation, while maintaining IEEE 802.3
compliance.
OVERTEMPERATURE PROTECTION
The IEEE 802.3 specification requires a PD to withstand
any applied voltage from 0V to 57V indefinitely. During
classification,however,thepowerdissipationintheLT4276
may be as high as 1.5W. The LT4276 can easily tolerate
this power for the maximum IEEE classification timing but
overheats if this condition persists abnormally.
Auxiliary Input Diode Bridge
Some PDs are required to receive AC or DC power from an
auxiliarypowersource. Adiodebridgeistypicallyrequired
to handle the voltage rectification and polarity correction.
The LT4276 includes an over-temperature protection
feature which is intended to protect the device during
momentaryoverloadconditions.Ifthejunctiontemperature
exceedstheover-temperaturethreshold, theLT4276pulls
down HSGATE pin, disables classification, and disables
the switching regulator operation.
In high efficiency applications, the voltage dropacrossthe
rectifiercannotbetolerated. TheLT4276canbeconfigured
with an LT4320-based ideal diode bridge to recover the
diode voltage drop and ease thermal design.
MAXIMUM DUTY CYCLE
Input Capacitor
The maximum duty cycle of the PG pin is modified by the
A 0.1µF capacitor is needed from VPORT to GND to meet
the input impedance requirement in IEEE 802.3 and to
properlybypasstheLT4276.Thiscapacitormustbeplaced
as close as possible to the VPORT and GND pins.
chosen t
and f . It is calculated below:
PGDELAY
SW
MAX POWER SUPPLY DUTY CYCLE
=DMAX – tPGDELAY •fSW
Transient Voltage Suppressor
The LT4276 specifies an absolute maximum voltage of
100V and is designed to tolerate brief overvoltage events
due to Ethernet cable surges.
For an appropriate margin during transient operation, the
forward or flyback power supply should be designed so
that its maximum steady-state duty cycle should be about
10%lowerthantheLT4276MaximumPowerSupplyDuty
Cycle calculated above.
To protect the LT4276, install a unidirectional transient
voltage suppressor (TVS) such as an SMAJ58A between
theVPORTandGNDpins.ThisTVSmustbeplacedasclose
as possible to the VPORT and GND pins of the LT4276.
For PD applications that require an auxiliary power input,
EXTERNAL INTERFACE AND COMPONENT SELECTION
PoE Input Diode Bridge
and GND as close as possible
install a TVS between V
to the LT4276.
IN
PDs are required to polarity-correct its input voltage.
When diode bridges are used, the diode forward voltage
drops affect the voltage at the VPORT pin. The LT4276
is designed to tolerate these voltage drops. The voltage
parameters shown in the Electrical Characteristics are
specified at the LT4276 package pins.
For extremely high cable discharge and surge protection
contact Linear Technology Applications.
4276fa
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For more information www.linear.com/LT4276
LT4276
Typical applicaTions
13W (TYPE 1) PoE Power Supply in Flyback Mode with 5V, 2.3A Output
L1: COILCRAFT, DO1813P-181HC
L2: COILCRAFT, DO1608C-103
2.2nF
2kV
L4: COILCRAFT, DO1608C-104
C2: 22µF, 6.3V, MURATA GRM31CR70J226KE19
C5: 47µF, 6.3V, PANASONIC 6SVP47M
C7: 2.2µF, 100V, MURATA GRM32ER72A225KA35
T1: WÜRTH, 750313109
Q1: PSMN075-100MSE
T2: PCA EPA4271GE OR PULSE PE-68386NL
•
•
L2
10µH
L1
180nH
Q1
V
OUT
VPORT
5V AT 2.3A
+
C2
22µF
C5
47µF
6.3V
47pF
630V
270Ω
1/4W
10µF
100V
C7
2.2µF
20Ω
FMMT723
L4
100µH
6.04k
•
–V
T1
OUT
3.3k
10nF
100V
2k
10µF
10V
BAV19WS
FDN86246
BAT54WS
HSSRC
V
IN
SWVCC
V
FB31
CC
PSMN4R2-30MLD
PG
1nF
HSGATE
VPORT
11Ω
1/4W
8.2Ω
+
–
ISEN
LT4276C
60mΩ
1/4W
1µF
MMBT3906 MMBT3904
15Ω
ISEN
0.1µF
100V
2.2nF
100Ω
T2
PTVS58VP1UTP
SG
GND RCLASS FFSDLY
52.3Ω 5.23k
SFST
ROSC
ITHB
•
•
1µF
10k
BAT46WS
107k
4.7nF
20k
330pF
0.1µF
GND
4276 TA02
2.2nF
2KV
Efficiency vs Load Current
Output Regulation vs Load Current
92
90
88
86
84
82
80
78
76
5.20
5.15
5.10
5.05
5.00
4.95
4.90
4.85
4.80
VPORT = 37V
VPORT = 48V
VPORT = 57V
VPORT = 37V
VPORT = 48V
VPORT = 57V
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
LOAD CURRENT (A)
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
LOAD CURRENT (A)
4276 TA02a
4276 TA02b
4276fa
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LT4276
Typical applicaTions
O U T
V
( V )
E F F I C I E N C Y ( % )
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LT4276
Typical applicaTions
O U T
V
( V )
E F F I C I E N C Y ( % )
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For more information www.linear.com/LT4276
LT4276
Typical applicaTions
O U T
V
( V )
E F F I C I E N C Y ( % )
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For more information www.linear.com/LT4276
LT4276
Typical applicaTions
O U T
V
( V )
E F F I C I E N C Y ( % )
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For more information www.linear.com/LT4276
LT4276
Typical applicaTions
O U T
V
( V )
E F F I C I E N C Y ( % )
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For more information www.linear.com/LT4276
LT4276
Typical applicaTions
O U T
V
( V )
E F F I C I E N C Y ( % )
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For more information www.linear.com/LT4276
LT4276
Typical applicaTions
O U T
V
( V )
E F F I C I E N C Y ( % )
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For more information www.linear.com/LT4276
LT4276
package DescripTion
Please refer to http://www.linear.com/product/LT4276#packaging for the most recent package drawings.
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 ±0.05
4.50 ±0.05
3.10 ±0.05
2.50 REF
2.65 ±0.05
3.65 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ±0.05
5.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
2.50 REF
R = 0.115
TYP
R = 0.05
TYP
0.75 ±0.05
4.00 ±0.10
(2 SIDES)
27
28
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ±0.10
(2 SIDES)
3.50 REF
3.65 ±0.10
2.65 ±0.10
(UFD28) QFN 0506 REV B
0.25 ±0.05
0.200 REF
0.50 BSC
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
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LT4276
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
12/15 Changed diode type of diode between SWVCC and V from Schottky to regular (BAV19WS) on all applicable
1, 10, 16-20,
22, 23
CC
schematics.
Added additional conditions to V
and I
parameters.
3
AUXT
AUXH
Revised graph: PG Delay Time vs Temperature in Flyback Mode.
Added T2 transformer part number recommendation to all flyback schematics.
Updated parts list for 25.5W (12V/1.9A) flyback schematic.
5
16, 17, 19-23, 26
21
4276fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
25
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT4276
Typical applicaTion
+
25.5W (Type 2) PoE Power Supply in Flyback Mode with 12V, 1.9A Output
2.2nF
2kV
L1: COILCRAFT, DO1813P-181HC
L2: COILCRAFT, DO1608C-103
L4: COILCRAFT, DO1608C-104
C2: 10µF, 16V, MURATA GRM31CR61C106KA88
C5: 22µF, 16V, PANASONIC 16SVP22M
C7: 2.2µF, 100V, MURATA GRM32ER72A225KA35
T1: WÜRTH, 750310742 OR PCA EPC3410G
Q1-Q9: PSMN075-100MSE
•
•
T2: PCA EPA4271GE OR PULSE PE-68386NL
L2
10µH
L1
180nH
Q1
V
OUT
12V AT 1.9A
+
C2
10µF
C5
22µF
20Ω
10µF
100V
C7
2.2µF
47pF
630V
•
L4
FMMT723
100µH
6.49k
T1
–V
OUT
Q2 Q3
Q4 Q5
150V
1/4W
DATA
PAIRS
10µF
10V
2.00kΩ
1
BAV19WS
BSZ520N15NS3G
BAT54WS
V
SWVCC
V
FB31
PG
IN
CC
FDMC86160
2
3
HSSRC
HSGATE
470pF
13Ω
1/4W
TG12 BG12
IN12
BG36 TG36
OUTP
3.3k
10nF
100V
EN
+
–
6
4
ISEN
ISEN
1µF
IN36
IN45
IN78
47nF
100V
40mΩ
1/4W
LT4321
24V
SPARE
PAIRS
LT4276B
MMBT3906 MMBT3904
15Ω
8.2Ω
VPORT
EN
OUTN
TG78 BG78
2.2nF
100Ω
T2
SG
5
7
BG45 TG45
•
•
T2P
1µF
10k
BAT46WS
GND RCLASS FFSDLY
35.7Ω 5.23k
SFST
ROSC
107k
ITHB
Q6 Q7
Q8 Q9
PTVS58VP1UTP
3.3nF
26.1k
8
47nF
100V
0.1µF
10k
220pF
2.2nF
2KV
V
OUT
47k
TO MICROPROCESSOR
MOC207M
4276 TA11
Efficiency vs Load Current
Output Regulation vs Load Current
92
90
88
86
84
82
80
78
76
74
72
70
12.5
12.4
12.3
12.2
12.1
12.0
11.9
11.8
11.7
11.6
11.5
VPORT = 42.5V
VPORT = 50V
VPORT = 57V
VPORT = 42.5V
VPORT = 50V
VPORT = 57V
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
LOAD CURRENT (A)
LOAD CURRENT (A)
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relaTeD parTs
PART NUMBER
DESCRIPTION
IEEE 802.3af PD Interface With Integrated Internal 100V, 400mA Switch, Programmable Class, 200/300kHz Constant Frequency
Switching Regulator PWM
COMMENTS
LTC4267/
LTC4267-1/
LTC4267-3
LTC4269-1
IEEE 802.3af PD Interface With Integrated 2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller,
Flyback Switching Regulator 50kHz to 250kHz, Aux Support
LTC4269-2
IEEE 802.3af PD Interface With Integrated 2-Event Classification, Programmable Class, Synchronous Forward Controller, 100kHz to
Forward Switching Regulator 500kHz, Aux Support
++
+
++
External Switch, LTPoE Support
LT4275A/B/C
LTC4278
LTPoE /PoE /PoE PD Controller
IEEE 802.3af PD Interface With Integrated 2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller,
Flyback Switching Regulator 50kHz to 250kHz, 12V Aux Support
++
+
++
LTC4290/LTC4271 8-Port PoE/PoE /LTPoE PSE Controller Transformer Isolation, Supports IEEE 802.3af, IEEE 802.3at and LTPoE PDs
LT4320/LT4320-1 Ideal Diode Bridge Controller
9V-72V ,DC to 600Hz Input. Controls 4-NMOSFETs, Voltage Rectification without Diode Drops
LT4321
PoE Ideal Diode Bridge Controller
Controls 8-NMOSFETs for IEEE-required PD Voltage Rectification without Diode Drops
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LT 1215 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
26
●
●
LINEAR TECHNOLOGY CORPORATION 2015
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LT4276
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