LT4294IMS#PBF_技术文档

LT4294

IEEE 802.3bt

PD Interface Controller

FEATURES

DESCRIPTION

TheLT^®4294isanIEEE802.3af/at/bt(Draft2.3)-compliant

powered device (PD) interface controller. The T2P output

indicates the number of classification events received

during IEEE 802.3bt-compliant mutual identification and

negotiation of available power.

n

IEEE 802.3af/at/bt (Draft 2.3) Powered Device (PD)

Controller

n

Supports Up to 71W PDs

n

5-Event Classification Sensing

n

Superior Surge Protection (100V Absolute Maximum)

n

Wide Junction Temperature Range (–40°C to 125°C)

The LT4294 utilizes an external, low R

N-channel

DS(ON)

n

Overtemperature Protection

Integrated Signature Resistor

hot swap MOSFET and supports the LT4320/LT4321 ideal

diode bridges, to extend the end-to-end power delivery

efficiency and eliminate costly heat sinks. The LT4294

also includes a power good output, onboard signature

resistor, undervoltage lockout, and thermal protection.

Start-up inrush current is adjustable with an external

capacitor. Auxiliary power override is supported as low

as 9V with the AUX pin.

n

External Hot Swap N-Channel MOSFET for Lowest

Power Dissipation and Highest System Efficiency

n

Configurable Aux Power Support as Low as 9V

Easy Migration Between LTPoE ^®PDs and IEEE

++

n

802.3bt PDs

n

Pin Compatible with LT4275A/B/C

Available in 10-Lead MSOP and 3mm × 3mm DFN

Packages

The LT4294 can be configured to support all possible

802.3bt, 802.3at and 802.3af power levels with external

component changes. Pin-for-pin compatibility with the

LT4275 family of PD Interface Controllers enables easy

++

APPLICATIONS

n

High Power Wireless Data Systems

migration between LTPoE

compliant PDs.

PDs and IEEE 802.3bt-

n

Outdoor Security Camera Equipment

n

Commercial and Public Information Displays

High Temperature Industrial Applications

++,

L, LT, LTC, LTM, Linear Technology and the Linear logo and LTPoE

trademarks of Analog Devices, Inc. All other trademarks are the property of their

respective owners.

are registered

n

TYPICAL APPLICATION

Single-Signature

Power Classification

IEEE 802.3bt Single-Signature Powered Device Interface

AVAILABLE

POWER

CLASS AT PD INPUT

V

(9V TO 60V)

AUX

+

C

PORT

PSMN040-100MSE

~

+

–

+

–

0

1

2

3

13W

3.84W

6.49W

13W

DATA

PAIR

C

PD

0.1µF

V

PORT

3.3k

V

IN

47nF

ISOLATED

POWER

SUPPLY

+

SPARE

PAIR

VPORT HSGATE

HSSRC

V

OUT

4

5

6

7

8

25.5W

40W

51W

62W

71W

AUX

PWRGD

RUN

–

LT4294

RCLASS

++

PSE TYPE

(TO µP)

OPTO

T2P

GND

++

R

CLS

4294 TA01a

4294f

1

For more information www.linear.com/LT4294

LT4294

ABSOLUTE MAXIMUM RATINGS

(Notes 1, 3)

VPORT, HSSRC Voltages ......................... –0.3V to 100V

HSGATE Current.................................................. 20mA

Operating Junction Temperature Range (Note 4)

LT4294I................................................–40°C to 85°C

LT4294H ............................................ –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec.)..................300°C

++

RCLASS, RCLASS

Voltages.......................... –0.3V to 8V (and ≤ VPORT)

AUX Current........................................................ 1.4mA

T2P, PWRGD Voltage ............................... –0.3V to 100V

T2P, PWRGD Current ...............................................5mA

PIN CONFIGURATION

TOP VIEW

GND

AUX

1

2

3

4

5

10 VPORT

GND 1

AUX 2

10 VPORT

9

8

7

6

HSGATE

HSSRC

PWRGD

T2P

9

8

7

6

HSGATE

HSSRC

PWRGD

T2P

11

RCLASS 3

RCLASS

GND

++

GND 5

RCLASS

4

++

RCLASS

GND

MS PACKAGE

10-LEAD PLASTIC MSOP

DD PACKAGE

10-LEAD (3mm × 3mm) PLASTIC DFN

T

= 150°C, θ = 45°C/W

JC

JMAX

T

= 150°C, θ = 5°C/W

JC

EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB GND

JMAX

http://www.linear.com/product/LT4294#orderinfo

ORDER INFORMATION

LEAD FREE FINISH

LT4294IDD#PBF

LT4294HDD#PBF

LT4294IMS#PBF

LT4294HMS#PBF

TAPE AND REEL

PART MARKING* PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 85°C

LT4294IDD#TRPBF

LT4294HDD#TRPBF

LT4294IMS#TRPBF

LT4294HMS#TRPBF

LHBX

10-Lead (3mm × 3mm) Plastic DFN

10-Lead Plastic MSOP

–40°C to 125°C

–40°C to 85°C

LTHBW

10-Lead Plastic MSOP

–40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL PARAMETER

VPORT Operating Input Voltage

CONDITIONS

MIN

TYP

MAX

60

UNITS

l

At VPORT Pin

V

VPORT Signature Range

VPORT Classification Range

VPORT Mark Range

At VPORT Pin

1.5

12.5

5.6

10

SIG

At VPORT Pin

21

CLASS

MARK

At VPORT Pin, Preceded by V

10

CLASS

4294f

2

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LT4294

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL PARAMETER

VPORT Aux Mode Range

CONDITIONS

MIN

8

TYP

MAX

UNITS

l

At VPORT Pin, AUX > V

60

V

AUXT

Signature/Class Hysteresis Window

Reset Threshold

1.0

2.6

V

RESET

V

HSON

V

HSOFF

At VPORT Pin, Preceded by V

5.6

37

CLASS

Hot Swap Turn-On Voltage

Hot Swap Turn-Off Voltage

Hot Swap On/Off Hysteresis Window

35

31

30

3

Supply Current

l

V

= V

= 57V

2

mA

VPORT

HSSRC

++

= 17.5V, RCLASS and RCLASS Open

Supply Current During Classification

Supply Current During Mark Event

Detection and Classification Signature

Detection Signature Resistance

0.4

0.5

0.7

0.9

2.2

= V After 1st Classification Event

MARK

l

V

(Note 2)

23.7

5.8

24.4

8.3

25.2

11

kΩ

V

SIG

Resistance During Mark Event

(Note 2)

MARK

++

RCLASS/RCLASS Operating Voltage

–10mA ≥ I

≥ –36mA, V

1.32

1.40

1.43

2

RCLASS

CLASS

Classification Signature Stability Time

V

Step to 17.5V,

ms

VPORT

34.8Ω from RCLASS or RCLASS++ to GND

Analog/Digital Interface

l

V

AUX Threshold

6.1

3.2

6.3

5

6.5

7

V

µA

V

AUXT

AUXH

I

AUX Pin Hysteresis Current

T2P Output Low

V

= 6.1V

AUX

1mA Load

0.8

5

PWRGD Output Low

PWRGD Leakage Current

T2P Leakage Current

V

= 60V

µA

PWRGD

T2P = 60V

5

Hot Swap Control

l

I

HSGATE Pull-Up Current

V

– V = 5V (Note 6)

HSSRC

–27

10

–22

840

–18

18

µA

V

GPU

HSGATE

V

HSGATE Open Circuit Voltage

HSGATE Pull-Down Current

–10µA Load, with Respect to HSSRC

– V = 5V

GOC

V

200

µA

HSGATE

HSSRC

Timing

l

f

T2P Frequency

After PWRGD Valid, if IEEE802.3bt PSE Is Mutually Identified

690

990

Hz

T2P

T2P Duty Cycle in PoE Operation (Note 5) After 4-Event Classification

50

25

%

After 5-Event Classification

++

(RCLASS Has Resistor to GND)

++

, and RCLASS Has Resistor to GND

AUXT

T2P Duty Cycle in Auxiliary

Supply Operation (Note 5)

V

> V

25

%

AUX

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: Signature resistance specifications do not include resistance

added by the external diode bridge which can add as much as 1.1k to the

port resistance.

Note 4: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 150°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

Note 5: Specified as the percentage of the period which T2P is low

impedance with respect to GND.

Note 3: All voltages with respect to GND unless otherwise noted. Positive

currents are into pins; negative currents are out of pins unless otherwise

noted.

Note 6: I

available in PoE powered operation. That is, available after

GPU

V

> V

and V

< V

over the range where V

is

VPORT

HSON

AUX

AUXT,

VPORT

between V

and 60V.

HSOFF

4294f

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LT4294

TYPICAL PERFORMANCE CHARACTERISTICS

Input Current vs Input Voltage 25k

Detection Signature Range

VPORT Hot Swap Thresholds

Supply Current During Power-On

2.0

1.5

1.0

0.5

0

0.5

0.4

0.3

0.2

0.1

0

37

36

35

34

33

32

31

30

T = –40°C

T = 25°C

T = 75°C

T = 125°C

T = –40°C

T = 25°C

T = 75°C

T = 125°C

Hot Swap ON

Hot Swap OFF

35

40

45

50

55

60

0

2

4

6

8

10

–50 –25

0

25

50

75 100 125

VPORT VOLTAGE (V)

TEMPERATURE (°C)

4294 G03

4294 G01

4294 G02

Detection Signature Resistance

vs Input Voltage

Reset Threshold

26.25

25.75

25.25

24.75

24.25

23.75

5.6

5.1

4.6

4.1

3.6

3.1

2.6

T = –40°C

T = 25°C

T = 75°C

T = 125°C

1

3

5

7

9

–50 –25

0

25

50

75 100 125

VPORT VOLTAGE (V)

TEMPERATURE (°C)

4294 G04

4294 G05

PWRGD, T2P Output Low

Voltage vs Current

VPORT Classification Thresholds

T2P Frequency

4

3

2

1

0

12.5

12.0

11.5

11.0

10.5

10.0

990

940

890

840

790

740

690

T = –40°C

T = 25°C

T = 75°C

T = 125°C

DETECT OR MARK TO CLASS

CLASS TO MARK

0

1

2

3

4

5

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

CURRENT (mA)

TEMPERATURE (°C)

4294 G06

4294 G07

4294 G08

4294f

4

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LT4294

PIN FUNCTIONS

GND(Pins1,5,DFNExposedPadPin11):DeviceGround.

ExposedPadmustbeelectricallyandthermallyconnected

to pin 5 and PCB GND.

++

RCLASS (Pin4):ConfigurablePoEClassificationResis-

tor. See Table 2.

T2P (Pin 6): PSE Type Indicator, Open-Drain Output. See

the Applications Information section for pin behavior.

AUX (Pin 2): Auxiliary Sense. A resistive divider from the

auxiliary power input to AUX sets the voltage at which the

auxiliary supply takes over. In auxiliary power operation,

HSGATE pulls down, the signature resistor disconnects,

classification is disabled, the PWRGD pin is high imped-

ance and T2P indicates max available power. The AUX pin

PWRGD(Pin7):PowerGoodIndicator,Open-DrainOutput.

Pulls to GND during V

and inrush.

CLASS

HSSRC (Pin 8): External Hot Swap MOSFET Source. Con-

nect to source of the external MOSFET.

sinks I

when below its threshold voltage of V

to

AUXH

AUXT

HSGATE(Pin9):ExternalHotSwapMOSFETGateControl,

Output. Connect to gate of the external MOSFET.

provide hysteresis. Connect to GND when not used.

RCLASS(Pin3):ConfigurablePoEClassificationResistor.

See Table 2.

VPORT(Pin10): PDinterfaceupperpowerrailandexternal

Hot Swap MOSFET drain connection.

BLOCK DIAGRAM

V

PORT

VPORT

VOLTAGE AND

CURRENT REFERENCES

PWRGD

CONTROL

LOGIC

HSGATE

HSSRC

CHARGE

PUMP

ON

V

GOC

AUX

+

–

OVERTEMP

T2P

6.3V

~6.5V

1.4V

V

PORT

V

PORT

CLASSIFICATION

LOGIC

+

–

1.4V

EN

–

RCLASS++

RCLASS

GND

4294 BD

4294f

5

For more information www.linear.com/LT4294

LT4294

APPLICATIONS INFORMATION

OVERVIEW

POWER ON

V

HSON

Power over Ethernet (PoE) continues to gain popularity

as products take advantage of DC power and high speed

data available from a single RJ45 connector. Powered

device(PD)equipmentvendorsarerunningintothe25.5W

power limit established by the IEEE 802.3at standard.

V

HSOFF

1ST CLASS

V

CLASSMIN

V

SIGMAX

DETECT

The LT4294 is an IEEE 802.3bt (Draft 2.3)-compliant PD

interface controller, and allows up to 71W operation while

maintaining backwards compatibility with existing PSE

systems. The T2P output indicates the number of clas-

sification events received during IEEE 802.3bt-compliant

mutual identification and negotiation of available power.

1ST MARK

V

RESET

V

SIGMIN

4294 F01

Figure 1. 1-Event Classification Signaling Waveform

The LT4294 controls a low R

) N-channel MOSFET

DS(ON

smaller than 25k to compensate for the additional series

resistance introduced by the IEEE required bridge or the

LT4321-based ideal diode bridge.

to maximize efficiency and delivered power.

Linear Technology also provides the LT4295, an IEEE

802.3bt-compliantPDwithanintegratedswitchingregula-

tor to service applications that require a more compact

and integrated solution.

IEEE 802.3bt Single-Signature vs Dual-Signature PDs

IEEE 802.3bt defines two PD topologies: single-signature

and dual-signature. The LT4294 primarily targets single-

signaturePDtopologies,eliminatingtheneedforasecond

PDcontroller. AllPDdescriptionsandIEEE802.3standard

references in this data sheet are limited in scope to single-

signature PDs.

++

IEEE 802.3bt vs LTPoE Available Power

The LT4294 supports IEEE 802.3bt PD power levels up

to 71W.

TheLT4275andLT4276areavailabletosupportPDpower

++

levels up to 90W under the LTPoE standard. See the

The LT4294 may be deployed in dual-signature PD appli-

cations. For more information, contact Linear Technology

Applications.

++

Related Parts section for a list of LTPoE products.

MODES OF OPERATION

Detection Signature

Classification Signature and Mark

The classification/mark process varies depending on the

PSE type. A PSE, after a successful detection, may ap-

ply a classification probe voltage of 14.5V to 20.5V and

measure the PD classification signature current. Once the

PSEappliesaclassificationprobevoltage, thePSEreturns

the PD voltage to the mark voltage range before applying

anotherclassificationprobevoltage,orpoweringupthePD.

During detection, the PSE looks for a 25k signature resis-

tor which identifies the device as a PD. The PSE will apply

two voltages in the range of 2.7V to 10.1V and measure

the corresponding currents. Figure 1 shows the detection

voltages.ThePSEcalculatesthesignatureresistanceusing

a ∆V/∆I measurement technique.

The LT4294 presents its precision, temperature-compen-

sated 24.4k resistor between the VPORT and GND pins,

allowing thePSEtorecognize aPDispresentand request-

ing power to be applied. The LT4294 signature resistor is

An example of 1-Event classification is shown in Figure 1.

In2-Eventclassification,aPSEprobesforpowerclassifica-

tion twice as shown in Figure 2. An IEEE 802.3bt PSE may

apply as many as 5 events before powering up the PD.

4294f

6

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LT4294

APPLICATIONS INFORMATION

POWER ON

IEEE 802.3bt Physical Classification and Demotion

V

HSON

IEEE 802.3bt defines physical classification to allow a PD

to request a power allocation from the connected PSE and

to allow the PSE to inform the PD of the PSE’s available

power. Demotion is provided if the PD requested power

level is not available at the PSE. If demoted, the PD must

operate in a lower power state.

V

HSOFF

1ST CLASS 2ND CLASS

V

CLASSMIN

V

SIGMAX

DETECT

The number of class/mark events issued by the PSE

directly indicates the power allocated to the PD and is

summarized in Table 1.

1ST MARK 2ND MARK

V

RESET

V

SIGMIN

4294 F02

IEEE 802.3bt provides nine PD classes and four PD types,

as shown in Table 2. The LT4294 class is configured by

Figure 2. 2-Event Classification/Mark Signaling Waveform

setting the R

and R

resistor values.

++

CLS

POWER ON

V

HSON

Table 1. PSE Allocated Class Power

V

HSOFF

NUMBER OF PSE CLASS/MARK EVENTS

PD REQUESTED

CLASS

1ST CLASS 2ND CLASS 3RD CLASS

1

2

3

4

5

0

1

2

3

4

5

6

7

8

13W

V

CLASSMIN

3.84W

6.49W

13W

V

SIGMAX

DETECT

1ST MARK 2ND MARK 3RD MARK

13W

25.5W

V

RESET

25.5W

40W

51W

V

SIGMIN

4294 F03

25.5W

51W

62W

71W

Figure 3. 3-Event Classification/Mark Signaling Waveform

Note: Bold indicates the PD has been demoted.

Table 2. Single-Signature Classification Codes, Power Levels and Resistor Selection

RESISTOR (1%)

++

CLASS

PD POWER AVAILABLE

PD TYPE

Type 1

NOMINAL CLASS CURRENT

2.5mA

R

CLS

0

1

2

3

4

5

6

7

8

13W

3.84W

6.49W

13W

25.5W

40W

51W

62W

71W

1.00kΩ

140Ω

Open

37.4Ω

46.4Ω

64.9Ω

118Ω

Type 1 or 3

Type 2 or 3

Type 3

Type 4

10.5mA

18.5mA

28mA

40mA

76.8Ω

49.9Ω

34.8Ω

1.00kΩ

140Ω

40mA/2.5mA

40mA/10.5mA

40mA/18.5mA

40mA/28mA

76.8Ω

49.9Ω

4294f

7

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LT4294

APPLICATIONS INFORMATION

IEEE802.3btPSEspresentasingleclassificationevent(see

Figure1)toClass0thru3PDs.AClass0thru3PDpresents

its class signature to the PSE and is then powered on if

sufficient power is available. Power limited IEEE 802.3bt

PSEs may issue a single event to Class 4 and higher PDs

in order to demote those PDs to Class 3 (13W).

IEEE 802.3bt PSEs present five classification events (see

Figure 5) to Class 7 and 8 PDs. Class 7 and 8 PDs present

a class signature 4 on the first two events, then present a

classsignature2or3,respectively,ontheremainingevents.

Thenumberofclassification/markeventsiscommunicated

through the LT4294 T2P pin. See T2P Output section for

more details.

IEEE802.3btPSEspresentuptothreeclassificationevents,

dependingonPSEType,toClass4PDs(seeFigure3).Class

4 PDs present a class signature 4 on all events. The third

event differentiates a Class 4 PD from a higher Class PD.

Power-limited IEEE 802.3bt PSEs may issue three events

to Class 5 and higher PDs in order to demote those PDs

to Class 4 (25.5W).

Classification Resistors (R

and R

)

++

CLS

The R and R

resistors set the classification currents

++

CLS

corresponding to the PD power classification. Select the

value of R and R

from Table 2 and connect each 1%

++

CLS

++

resistor between the RCLASS, RCLASS pins and GND.

IEEE 802.3bt PSEs present four classification events (see

Figure 4) to Class 5 and 6 PDs. Class 5 and 6 PDs present

a class signature 4 on the first two events, then present

a class signature 0 or 1, respectively, on the remaining

events. Power limited IEEE 802.3bt PSEs may issue four

events to Class 7 and higher PDs in order to demote those

PDs to Class 6 (51W).

Detection Signature Corrupt During Mark Event

During the mark event, the LT4294 presents <11kΩ to the

port as required by the IEEE 802.3 specification.

Inrush and Power On

Once the PSE detects and classifies the PD, the PSE then

powers on the PD. When the port voltage rises above the

POWER ON

V

threshold,itbeginstosourceI

outoftheHSGATE

HSON

GPU

V

HSON

pin. This current flows into an external capacitor, C

in

GATE

V

HSOFF

1ST

CLASS

2ND

CLASS

3RD

CLASS

4TH

CLASS

Figure 6, that causes a voltage to ramp up the gate of the

external MOSFET. The external MOSFET acts as a source

follower and ramps the voltage up on the output bulk

V

CLASSMIN

V

SIGMAX

capacitor, C

INRUSH

See equation below:

, thereby determining the inrush current,

INRUSH

PORT

. Design I

DETECT

I

to be approximately ~100mA.

1ST

MARK

2ND

MARK

3RD

MARK

4TH

MARK

V

RESET

V

SIGMIN

4294 F04

C_PORT

C_GATE

I_INRUSH= I_GPU

•

Figure 4. 4-Event Classification/Mark Signaling Waveform

POWER ON

I

INRUSH

V

VPORT

+

HSON

3.3k

C

PORT

V

HSOFF

1ST

2ND

3RD

4TH

5TH

C

GATE

CLASS CLASS CLASS

CLASS CLASS

V

HSGATE

CLASSMIN

VPORT

HSSRC

V

SIGMAX

LT4294

GND

DETECT

1ST

MARK

2ND

MARK

3RD

MARK

4TH

MARK

5TH

MARK

V

RESET

4294 F06

V

SIGMIN

4294 F05

Figure 6. Configuring I_INRUSH

Figure 5. 5-Event Classification/Mark Signaling Waveform

4294f

8

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LT4294

APPLICATIONS INFORMATION

The LT4294 internal charge pump provides an N-channel

MOSFET solution, eliminating a larger and more costly

A capacitor up to 1000pF may be placed between the AUX

pin and GND to improve noise immunity. V

must be

AUXON

P-channel MOSFET. The low R

MOSFET also maxi-

lower than V

DS(ON)

HSOFF.

mizes power delivery and efficiency, reduces power and

T2P OUTPUT

heat dissipation, and eases thermal design.

The LT4294 communicates the available power to the PD

application via the T2P pin. The T2P pin state is deter-

mined by the number of classification/mark events, the

PD classification signature, and whether the PD is in PoE

or auxiliary power operation. The LT4294 uses a 4-state

encoding on the T2P pin.

Power Good

The PWRGD pin is held low by its open drain output until

HSGATE charges up to approximately 7V above HSSRC.

The PWRGD pin is used to hold off the isolated power

supply until inrush is complete and the external MOSFET

is fully enhanced. The HSGATE pin remains high and the

PWRGD pin remains open-drain until the port voltage

During PoE operation after completing inrush, the T2P

pin configured for Class 0-4 presents a high impedance

(Hi-Z) to GND to indicate 1-Event classification. The T2P

presents a low impedance (Low-Z) to GND to indicate

2-Event or more classification events. This feature is

summarized in Table 3.

falls below V

HSOFF.

Delay Start

When the PSE powers up the port, the PD application

should not draw more than 350mA for 80ms to comply

with the IEEE 802.3 standard.

The T2P pin configured for Class 5 to 8 presents Hi-Z

to GND to indicate 1-Event classification. The T2P pin

presents Low-Z to GND to indicate 2-Event or 3-Event

classification. The T2P pin presents an alternating low/

high impedance at 50% duty cycle to indicate 4-Event

classification. The T2P pin presents an alternating 25%

low/75% high impedance duty cycle to indicate 5-Event

Auxiliary Supply Override

If the AUX pin is held above V

, the LT4294 enters

AUXT

auxiliary power supply override mode. In this mode the

signature resistor disconnects, classification is disabled,

HSGATE pulls down, the PWRGD pin is open drain and

T2P pin indicates max available power.

classification. The T2P pin toggles at a rate of f . This

T2P

feature is summarized in Table 4.

The AUX pin allows for setting the auxiliary supply turn

During auxiliary power operation, when configured for

on and turn off voltage thresholds, V

, and V

AUXON

AUXOFF

++

Class 4 or lower (i.e. RCLASS pin is floating), the T2P

respectively. The auxiliary supply hysteresis voltage,

presents low impedance to GND. When configured for

V

, is generated with sinking current, I , and is

AUXHYS

AUXH

++

Class 5 or higher (i.e. with a resistor on the RCLASS pin

active only when the AUX pin voltage is less than V

.

AUXT

AUXOFF

to GND), the T2P presents a 25% duty cycle. This feature

Use the following equations to set V

and V

AUXON

is summarized in Table 5.

via R1 and R2 in Figure 7. Note that an internal 6.5V Zener

limits the voltage on the AUX pin.

V

CC

V_AUXON− V_AUXOFFV_AUXHYS

LT4294

+

V

R1=

R2 =

=

CC

I_AUXH

T2P

25%

Low-Z

75%

Hi-Z

V(T2P)

LT4294

AUX

R1

R2

R1

V

AUX





GND

4294 F08

V_AUXOFF

V_AUXT

−1

TIME









GND

V_AUX(MAX)− V_AUXT

Figure 8. Response Example for 25% Low-Z, 75% Hi-Z

–

R1≥

4294 F07

1.4mA

Figure 7. AUX Threshold and Hysteresis Calculation

4294f

9

For more information www.linear.com/LT4294

LT4294

APPLICATIONS INFORMATION

For high efficiency applications, the LT4294 supports

an LT4321-based PoE ideal diode bridge that reduces

the forward voltage drop from 0.7V to nearly 20mV per

diode in normal operation, while maintaining IEEE 802.3

compliance.

Table 3. T2P Response vs Number of Class/Mark Events During

PoE Operation, Class 0-4

NUMBER OF

CLASSIFICATION/

MARK EVENTS

T2P WITH RESPECT

TO GND

PD POWER

1

Hi-Z

Low-Z

13W

25.5W

2 or More

Auxiliary Input Diode Bridge

Table 4. T2P Response vs Number of Class/Mark Events During

Some PDs are required to receive AC or DC power from an

auxiliarypowersource.Adiodebridgeistypicallyrequired

to handle the voltage rectification and polarity correction.

PoE Operation, Class 5-8

NUMBER OF

CLASSIFICATION/

MARK EVENTS

T2P WITH RESPECT

TO GND

PD POWER

In high efficiency applications, or in low auxiliary input

voltage applications, the voltage drop across the rectifier

cannot be tolerated. The LT4294 can be configured with

an LT4320-based ideal diode bridge to recover the diode

voltage drop and ease thermal design.

1

2 or 3

4

Hi-Z

13W

Low-Z

25.5W

50% Hi-Z/50% Low-Z Minimum(PD Class, 51W)

25% Low-Z, 75% Hi-Z Minimum(PD Class, 71W)

5

Table 5. T2P Response During Auxiliary Power Operation

For applications with auxiliary input voltages below 10V,

theLT4294mustbeconfiguredwithanLT4320-basedideal

diodebridgetorecoverthevoltagedropandguaranteethe

minimum VPORT voltage is within the VPORT AUX Mode

Range as specified in the Electrical Characteristics table.

PD CLASS

T2P WITH RESPECT TO GND

0 – 4

5 – 8

Low-Z

25% Low-Z, 75% Hi-Z

Overtemperature Protection

The IEEE 802.3 specification requires a PD to withstand

any applied voltage from 0V to 57V indefinitely. During

classification,however,thepowerdissipationintheLT4294

may be as high as 1.5W. The LT4294 can easily tolerate

this power for the maximum IEEE classification timing but

overheats if this condition persists abnormally.

An example of a high efficiency typical application circuit

is show in the Typical Applications section.

Input Capacitor

A 0.1μF capacitor is needed from VPORT to GND to meet

the input impedance requirement in IEEE 802.3 and to

properly bypass the LT4294.

TheLT4294includesanovertemperatureprotectionfeature

which is intended to protect the device during momentary

overload conditions. If the junction temperature exceeds

the overtemperature threshold, the LT4294 pulls down

HSGATE pin, and disables classification.

When operating the LT4294 with the LT4321, exchange

the 0.1μF capacitor with two 0.047μF capacitors. See

Layout Considerations section for capacitor placement.

Transient Voltage Suppressor

EXTERNAL INTERFACE AND COMPONENT SELECTION

PoE Input Diode Bridge

The LT4294 specifies an absolute maximum voltage of

100V and is designed to tolerate brief overvoltage events

due to Ethernet cable surges. To protect the LT4294 from

APDisrequiredtopolarity-correctitsinputvoltage. When

diode bridges are used, the diode forward voltage drops

affectthevoltageattheVPORTpin.TheLT4294isdesigned

to tolerate these voltage drops. The voltage parameters

shown in the Electrical Characteristics are specified at the

LT4294 package pins.

-

anovervoltageevent,installaunidirectionaltransientvolt

age suppressor (TVS) such as an SMAJ58A between the

VPORT and GND pins. See Layout Considerations section

for TVS placement.

4294f

10

For more information www.linear.com/LT4294

LT4294

APPLICATIONS INFORMATION

For PD applications that require an auxiliary power input,

LAYOUT CONSIDERATIONS

Avoid excessive parasitic capacitance on the RCLASS

install a TVS between V and GND as close as possible

IN

to the LT4294. For extremely high cable discharge and

and RCLASS++ pins and place resistors R

close to the LT4294.

and R

CLS

CLS++

surgeprotection, contactLinearTechnologyApplications.

Exposed Pad

It is strictly required for maximum protection to place the

0.1μF input capacitor, C , and transient voltage suppres-

PD

The LT4294 DFN package has an exposed pad that is

internally electrically connected to GND. The exposed pad

mayonlybeconnectedtoGNDontheprintedcircuitboard.

sor as close to the LT4294 as possible. When operating

the LT4294 with the LT4321, place a 0.047μF capacitor,

C

, as close as possible to the LT4294 V

and GND

PORT

PD1

pins (pin 10 and pin 5, respectively), and a 0.047μF ca-

pacitor, C , as close as possible to the LT4321 OUTP

and OUTN pins.

PD2

TYPICAL APPLICATIONS

High Efficiency 25.5W PD Solution with 12V_DCand 24V_ACAuxiliary Input

BSZ110N06NS3 ×4

TG2

TG1

OUTP

LT4320

V

AUX

IN1

IN2

9V TO 57VDC

OR 24VAC

1µF

PSMN075-100MSE ×4

BG2

BG1

OUTN

MMSD4148

×3

PSMN075-100MSE

1

C

PD1

0.047µF

+

680µF

2

3

V

IN

TG12 BG12

BG36 TG36

OUTP

VPORT

HSGATE

LT4294

HSSRC

DATA

PAIRS

3.3k

150nF

158k

SMAJ58A

+

EN

ISOLATED

POWER

SUPPLY

IN12

AUX

RCLASS

100k

V

C

0.1µF

OUT

PD2

0.047µF

6

4

–

931k

34.8Ω

IN36

IN45

LT4321

RUN

EN

PWRGD

GND

4294 TA03

IN78

OUTN

5

7

SPARE

PAIRS

BG78 TG78

TG45 BG45

8

WURTH 749022017

PSMN075-100MSE ×4

4294f

11

For more information www.linear.com/LT4294

LT4294

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LT4294#packaging for the most recent package drawings.

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699 Rev C)

0.70 ±0.05

3.55 ±0.05

2.15 ±0.05 (2 SIDES)

1.65 ±0.05

PACKAGE

OUTLINE

0.25 ±0.05

0.50

BSC

2.38 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

R = 0.125

0.40 ±0.10

TYP

6

10

3.00 ±0.10

(4 SIDES)

1.65 ±0.10

(2 SIDES)

PIN 1 NOTCH

R = 0.20 OR

PIN 1

TOP MARK

(SEE NOTE 6)

0.35 × 45°

CHAMFER

(DD) DFN REV C 0310

5

1

0.25 ±0.05

0.50 BSC

0.75 ±0.05

0.200 REF

2.38 ±0.10

(2 SIDES)

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).

CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

4294f

12

For more information www.linear.com/LT4294

LT4294

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LT4294#packaging for the most recent package drawings.

MS Package

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1ꢀꢀ1 Rev F)

0.889 0.127

(.035 .005)

5.10

3.20 – 3.45

(.201)

(.12ꢀ – .13ꢀ)

MIN

3.00 0.102

(.118 .004)

(NOTE 3)

0.497 0.07ꢀ

(.019ꢀ .003)

REF

0.50

(.0197)

BSC

0.305 0.038

(.0120 .0015)

TYP

10 9

8

7 ꢀ

RECOMMENDED SOLDER PAD LAYOUT

3.00 0.102

(.118 .004)

(NOTE 4)

4.90 0.152

(.193 .00ꢀ)

DETAIL “A”

0.254

(.010)

0° – ꢀ° TYP

GAUGE PLANE

1

2

3

4 5

0.53 0.152

(.021 .00ꢀ)

0.8ꢀ

(.034)

REF

1.10

(.043)

MAX

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.101ꢀ 0.0508

(.004 .002)

0.50

(.0197)

BSC

MSOP (MS) 0213 REV F

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.00ꢀ") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.00ꢀ") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

4294f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

13

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/LT4294

LT4294

TYPICAL APPLICATION

IEEE 802.3bt-Compliant > 99% Efficiency 71W Powered Device

PSMN075-100MSE ×4

PSE TYPE

(TO µP)

OPTO

PSMN040-100MSE

1

C

PD1

0.047µF

+

22µF

2

3

V

IN

TG12 BG12

BG36 TG36

OUTP

VPORT HSGATE HSSRC

AUX

T2P

DATA

PAIRS

SMAJ58A

3.3k

+

EN

ISOLATED

POWER

IN12

100k

LT4294 RCLASS++

RCLASS

V

OUT

C

PD2

0.047µF

SUPPLY

6

4

–

47nF

IN36

IN45

EN

PWRGD

LT4321

++

R

RUN

CLS

118Ω

GND

R

GND

CLS

49.9Ω

4294 TA02

IN78

OUTN

5

7

SPARE

PAIRS

BG78 TG78

TG45 BG45

8

WÜRTH 749022016

PSMN075-100MSE ×4

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LT4295

IEEE 802.3bt PD with Forward/Flyback

Switching Regulator Controller

External Switch, IEEE 802.3bt Support, Configurable Class, Forward or No-Opto Flyback

Operation, Frequency, PG/SG Delays, Soft-Start, and Aux Support as Low as 9V,

Including Housekeeping Buck, Slope Compensation

LT4321

PoE Ideal Diode Bridge Controller

Ideal Diode Bridge Controller

Controls 8-NMOSFETs for IEEE-Required PD Voltage Rectification without Diode Drops

LT4320/LT4320-1

9V – 72V, DC to 600Hz Input. Controls 4-NMOSFETs, Voltage Rectification without

Diode Drops

+

++

LTC4279

Single PoE/PoE /LTPoE PSE Controller Supports IEEE 802.3af, IEEE 802.3at, LTPoE and Proprietary PDs

++

+

++

LT4276A/B/C

LTPoE /PoE /PoE PD with Forward/

Flyback Switching Regulator Controller

External Switch, LTPoE Support, User-Configurable Class, Forward or No-Opto

Flyback Operation, Frequency, PG/SG Delays, Soft-Start, and Aux Support as Low as 9V,

Including Housekeeping Buck, Slope Compensation

++

+

++

External Switch, LTPoE Support

LT4275A/B/C

LTC4269-1

LTPoE /PoE /PoE PD Controller

IEEE 802.3at PD Interface with Integrated 2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller,

Flyback Switching Regulator 50kHz to 250kHz, Aux Support

LTC4269-2

LTC4278

IEEE 802.3at PD Interface with Integrated 2-Event Classification, Programmable Class, Synchronous Forward Controller, 100kHz

Forward Switching Regulator

to 500kHz, Aux Support

IEEE 802.3at PD Interface with Integrated 2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller,

Flyback Switching Regulator 50kHz to 250kHz, 12V Aux Support

LTC4267/LTC4267-1/ IEEE 802.3af PD Interface with Integrated Internal 100V, 400mA Switch, Programmable Class, 200/300kHz Constant

LTC4267-3

Switching Regulator

Frequency PWM

+

++

LTC4290/LTC4271

8-Port PoE/PoE /LTPoE PSE Controller

Transformer Isolation, Supports IEEE 802.3af, IEEE 802.3at and LTPoE PDs

4294f

LT 0417 • PRINTED IN USA

www.linear.com/LT4294

14

For more information www.linear.com/LT4294

 LINEAR TECHNOLOGY CORPORATION 2017


型号：	LT4294IMS#PBF
厂家：	Linear
描述：	LT4294 - IEEE 802.3bt PD Interface Controller; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C 光电二极管
文件：	总14页 (文件大小：561K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT4294IMS#PBF [Linear]

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