LT4351CMS#PBF [Linear]
LT4351 - MOSFET Diode-OR Controller; Package: MSOP; Pins: 10; Temperature Range: 0°C to 70°C;
| 型号： | LT4351CMS#PBF |
| 厂家： | 
Linear |
| 描述： | LT4351 - MOSFET Diode-OR Controller; Package: MSOP; Pins: 10; Temperature Range: 0°C to 70°C 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总20页 (文件大小：330K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT4351
MOSFET Diode-OR
Controller
DESCRIPTION
The LT®4351 creates a near ideal diode using external
single or back-to-back N-channel MOSFETs. This ideal
diode function permits low loss ORing of multiple power
sources. Power sources can easily be ORed together to
increase total system power and reliability with minimal
effect on supply voltage or efficiency. Disparate power
supplies can be efficiently ORed together.
FEATURES
n
Low Loss Replacement for ORing Diode in Multiple
Sourced Power Supplies
n
External N-Channel MOSFETs for High Current
Capability
n
Internal Boost Regulator Supply for MOSFET
Gate Drive
n
Wide Input Range: 1.2V to 18V
n
Fast Switching MOSFET Gate Control
The IC monitors the input supply with respect to the load
and turns on the MOSFET(s) when the input supply is
n
Input Under and Overvoltage Detection
n
STATUS and FAULT Outputs for Monitoring
higher. If the MOSFET’s R
is sufficiently small, the
DS(ON)
n
Internal MOSFET Gate Clamp
Available in a 10-pin MSOP Package
LT4351 will regulate the voltage across the MOSFET(s)
to 15mV. A STATUS pin indicates the MOSFET on-state.
n
APPLICATIONS
An internal boost regulator generates the MOSFET gate
drive voltage. Low operating voltage allows for ORing of
supplies as low as 1.2V.
n
Paralleled Power Supplies
n
Uninterrupted Supplies
n
High Availability Systems
N + 1 Redundant Power Supplies
The LT4351 will disable power passage during undervolt-
age or overvoltage conditions. These voltages are set by
resistivedividersontheUVandOVpins.Theundervoltage
thresholdhasuserprogrammablehysteresis.Overvoltage
detection is filtered to reduce false triggering.
n
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks
and PowerPath and ThinSOT are trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
The LT4351 is available in a 10-pin MSOP package.
TYPICAL APPLICATION
Dual 5V Redundant Supply
Si4862DY
Si4862DY
5V COMMON
POWER
SUPPLY
1
POWER
SUPPLY
2
5V
10µF
1µF
5V
10µF
4.7µH
1×
1×
C
LOAD
LOAD
4.7µH
1µF
V
IN
GATE
OUT
OUT
GATE
V
IN
MBR0530
MBR0530
MBR0530
MBR0530
V
V
DD
DD
LT4351
LT4351
SW
UV
STATUS
STATUS
SW
UV
24.9k
1%
24.9k
1%
FAULT
FAULT
232Ω
1%
232Ω
1%
GND
GND
OV
OV
1.47k
1%
1.47k
1%
4351 TA01
4351fd
1
LT4351
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
V Voltage................................................ –0.3V to 19V
IN
GATE
DD
1
2
3
4
5
10 OUT
OUT Voltage............................................. –0.3V to 19V
V
9
8
7
6
STATUS
V
FAULT
UV
OV
IN
V
DD
Voltage.............................................. –0.3V to 30V
SW
GND
FAULT, STATUS Voltages.......................... –0.3V to 30V
FAULT, STATUS Current .......................................... 8mA
UV, OV Voltages......................................... –0.3V to 9V
SW Voltage .............................................. –0.3V to 32V
Operating Temperature Range
MS PACKAGE
10-LEAD PLASTIC MSOP
T
= 125°C, θ = 120°C/W
JA
JMAX
LT4351C .................................................. 0°C to 70°C
LT4351I ............................................... –40°C to 85°C
Junction Temperature (Note 2) ............................ 125°C
Storage Temperature Range.................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
ORDER INFORMATION
LEAD FREE FINISH
LT4351CMS#PBF
LT4351IMS#PBF
TAPE AND REEL
PART MARKING
LTZZ
PACKAGE DESCRIPTION
10-Lead Plastic MSOP
10-Lead Plastic MSOP
TEMPERATURE RANGE
LT4351CMS#TRPBF
LT4351IMS#TRPBF
0°C to 70°C
LTA1
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = VOUT = 5V, VDD = 16.1V, VUV = 0.4V, VOV = 0.2V, GATE Open, unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Supply and Protection
l
V
Operating Range
Supply Current
1.2
18
V
IN
l
l
I
V
V
IN
V
IN
= 1.2V, V
= 1.1V, V = 12.3V
1.41
1.71
2
2.1
mA
mA
VIN
IN
OUT
OUT
DD
= 18V, V
= 17.9V, V = 29.1V
DD
l
V
Undervoltage Turn-Off Voltage
Threshold
UV Falling
290
7
300
310
13
mV
UV(TH)
UV(HYST)
UV
l
I
I
I
Hysteresis
Difference Between I at V
+ 10mV and
UV(TH)
10
µA
UV
UV
V
V
– 10mV
UV(TH)
l
l
UV Input Bias Current
Overvoltage Threshold
= V
+ 10mV
UV(TH)
–100
300
–400
310
nA
UV
V
OV Rising
290
mV
OV(TH)
4351fd
2
LT4351
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = VOUT = 5V, VDD = 16.1V, VUV = 0.4V, VOV = 0.2V, GATE Open, unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
= V – 10mV
OV(TH)
MIN
TYP
–100
0.14
0.04
MAX
–400
0.25
1
UNITS
l
l
l
I
OV
OV Input Bias Current
FAULT Pin On-Voltage
FAULT Pin Leakage Current
V
V
V
OV
V
F(ON)
I = 5mA in Fault Condition
F
I
V = 30V, V = 4.9V
µA
F(OFF)
F
IN
Boost Supply
l
l
V
Boost Regulation Trip Voltage
Boost Supply Off-Time
Measured as V to V , Rising Edge
10.2
350
4
10.7
600
450
11.4
650
V
ns
BR
DD
IN
t
OFF
I
Boost Supply Switch Current Limit
mA
SWLIM
Gate Drive
l
l
V
IOR
Input-to-Output Regulated Voltage
Gate Voltage Limit
15
25
–3
mV
V
∆V
V
= 5V, V
= 4.9V, V = 13V Measured with
–2.3
GL
IN
OUT
DD
Respect to V
DD
l
l
∆V
Maximum Gate Voltage
V
= 5V, V
= 4.9V, V = 16.1V Measured with
OUT
7
7.4
7.8
V
G(MAX)
IN
OUT
DD
Respect to V
V
G(OFF)
Gate Off-Voltage
Gate Source Current
Gate Sink Current
Operating Range
V
V
V
= 5.1V
0.16
0.670
0.670
0.30
V
A
A
V
OUT
OUT
OUT
I
I
= 4.9V, V
= 5.1V, V
= 9V
= 9V
GSO
GATE
GATE
GSK
l
V
30
DD
l
l
I
V
Supply Current
V
IN
V
IN
= 1.2V, V
= 1.1V, V = 12.3V, GATE Open
3
3.6
4
5.6
mA
mA
VDD
DD
OUT
OUT
DD
= 18V, V
= 17.9V, V = 29.1V, GATE Open
DD
Status Functions
l
∆V
Minimum Gate Voltage for Turning
On Status
V
V
= 4.9V, I = 1mA
STATUS
0.75
210
1
V
GIS
OUT
OUT
V
IOGF
V
to V
Fault Voltage with
Falling, Measured with Respect to V
IN
185
230
mV
IN
OUT
Open Gate
l
l
V
Status Pin On-Voltage
I
= 5mA, V = 4.9V, Status On
OUT
0.13
0.04
0.25
1
V
ST(ON)
ST(OFF)
ST
I
Status Pin Leakage Current
V
= 30V, Status Off, V = 4.9V
µA
ST
IN
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: T is calculated from the ambient temperature T and power
J A
dissipation P according to the following formula:
D
T = T + (P • 120°C/W)
J
A
D
4351fd
3
LT4351
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Undervoltage Threshold
vs Temperature
Overvoltage Threshold
vs Temperature
Undervoltage Threshold vs VIN
310
308
306
304
302
300
298
296
294
292
290
305
303
301
299
297
295
293
310
308
306
304
302
300
298
296
294
292
290
V
V
V
V
= 1.2V
= 5V
= 12V
= 20V
V
IN
V
IN
V
IN
V
IN
= 1.2V
= 5V
= 12V
= 20V
IN
IN
IN
IN
–50
0
25
50
75 100 125
–50
0
25
50
75
125
–25
–25
100
2
4
12 14
0
6
8
10
16
18
20
TEMPERATURE (°C)
TEMPERATURE (°C)
V
(V)
IN
4351 G01
4351 G02
4351 G03
Overvoltage Hysteresis
vs Temperature
Overvoltage Turn-Off Delay
vs Overvoltage Overdrive
Overvoltage Threshold vs VIN
25
20
15
10
5
20
18
16
14
12
10
8
310
308
306
304
302
300
298
296
294
292
290
V
IN
= 5V
V
= 5V
IN
6
4
2
0
0
–50 –25
0
25
50
75 100 125
0
10
15
20
25
30
35
0
2
4
6
8
10 12 14 16 18 20
(V)
5
TEMPERATURE (°C)
OV VOLTAGE ABOVE THRESHOLD (mV)
V
IN
4351 G05
3451 G06
4351 G04
IVDD vs Temperature
I
VIN vs Temperature
Gate Off-Voltage vs Temperature
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
4.5
4.0
3.5
3.0
2.5
2.0
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
V
V
V
V
= 1.2V
= 5V
= 12V
= 20V
V
V
V
V
= 1.2V
= 5V
= 12V
= 20V
IN
IN
IN
IN
IN
IN
IN
IN
V
OUT
= 5V
IN
V
= 5V
V
OUT
= 5V
= 5.1V
IN
V
–50
0
25
50
75 100 125
–50
0
25
50
75 100 125
–50
0
25
50
75
125
–25
–25
–25
100
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4351 G07
4351 G08
4351 G09
4351fd
4
LT4351
TA = 25°C, unless otherwise noted.
Typical SW Pin Waveform
TYPICAL PERFORMANCE CHARACTERISTICS
GATE Pin Turn On and Off Waveform
with 10nF Capacitor Load
TURN ON
V
V
SW
GATE
5V/DIV
2V/DIV
TURN OFF
4351 G11
4351 G10
500ns/DIV
50ns/DIV
= 4.9V TO 5.1V SQUARE WAVE
V
= 5V
V
V
= 5V
OUT
IN
IN
L = 4.7µH
SW Pin Waveform at Maximum
Boost Regulator Output
Typical SW Pin Waveform
V
SW
5V/DIV
V
SW
5V/DIV
4351 G12
4351 G13
10µs/DIV
10µs/DIV
V
= 5V
V = 5V
IN
4.7µH INDUCTOR
IN
4.7µH INDUCTOR
4351fd
5
LT4351
PIN FUNCTIONS
GATE (Pin 1): MOSFET Gate Drive Pin. This pin is tied to
fault. Overvoltage detection has filtering on it to prevent
false triggering. The filtering depends on the level of over-
drive. Filtered tripping will occur when OV exceeds 0.3V.
If OV exceeds 0.33V, the gate immediately turns off (no
filtering). If overvoltage detection is not required, ground
the OV pin. See the Applications Information section for
further information.
thegate(s)oftheexternalN-channelMOSFET(s).TheGATE
pin drives high when UV is above the V
threshold,
UV(TH)
IN
OV is below the V
threshold and V is greater than
OV(TH)
OUT by 15mV. When not driven high, GATE actively pulls
to GND. GATE can sink or source up to 600mA.
V
DD
(Pin 2): Gate Drive Supply Pin. This is the supply
pin for the gate drive amplifier. It is either generated by
the onboard boost regulator or supplied externally. When
turning on the MOSFET(s), a large high current pulse
flows through this pin. Bypass the pin with a 1µF capaci-
tor placed in close proximity to the part. The voltage on
this pin is also the feedback for the boost regulator. If the
UV (Pin 7): Undervoltage Shutdown Pin. This pin is used
for the undervoltage detect function. It is connected to
a resistive divider from V . When the voltage is below
IN
the UV threshold, GATE pulls to GND disabling power
transfer. In addition, the FAULT pin pulls low indicating a
fault. When the UV pin voltage drops below the threshold,
a 10µA current is pulled from the divider to provide hys-
teresis. If undervoltage detection is not required, tie the
UV pin to a voltage greater than 320mV and not greater
V
voltage exceeds the V voltage by 10.7V, the boost
DD
IN
switch is held off.
V (Pin 3): Input Supply Pin. This pin is the supply pin
IN
than V . Do not force more than 9V on UV due to an
IN
for the control circuitry and the boost regulator. It is also
one input in conjunction with OUT for controlling the
MOSFET(s). Bypassing should include a low ESR/ESL
capacitor placed in close proximity to the part.
internal clamp. See the Applications Information section
for further information.
FAULT (Pin 8): Fault Comparator Status Pin. This pin pulls
low when a fault occurs. A fault has occurred if the UV pin
is below threshold or the OV pin is above threshold. The
FAULT pin low indicates that there is a problem with the
SW (Pin 4): Boost Regulator Switch Pin. This pin is the
boost regulator switch output. It is connected to the boost
inductorandtheboostdiode.Peakswitchcurrentislimited
internally to 450mA. A Schottky diode between GND and
SW is required. If an external V supply is used, leave
this pin open.
V (source) supply. GATE is pulled to GND during a fault,
IN
disabling the MOSFET(s) and prohibits common supply
DD
contamination. If the GATE pin goes to compliance (GATE
equals the lesser of V – 2.3V or OUT + 7.4V) and V is
DD
IN
GND (Pin 5): Device Ground Pin. This pin is ground for the
boost switch, gate driver as well as the control circuitry.
Tie the V and V bypass capacitors and ground plane
greater than OUT by more than 0.21V, FAULT turns on as
an indicator that the MOSFETs are probably not function-
ing. Leave this pin open if not used.
IN
DD
close to this pin to minimize the effects of switching cur-
rents on part performance.
STATUS (Pin 9): MOSFET Status Pin. This pin pulls low
when GATE is above V by more than 0.7V and V is
IN
IN
OV (Pin 6): Overvoltage Shutdown Pin. This pin is used
greater than OUT by 15mV. This indicates the MOSFET is
for input overvoltage detection. It is connected to a resis-
on. Leave this pin open if not used.
tive divider from V . When the voltage exceeds the OV
IN
OUT (Pin 10): Common Supply Pin. This pin is connected
threshold (0.3V), GATE is pulled to GND disabling power
to the supply common and is used in conjunction with V
as one input controlling the MOSFET(s).
IN
transfer. In addition, the FAULT pin pulls low indicating a
4351fd
6
LT4351
BLOCK DIAGRAM
TO COMMON SUPPLY
FROM INDIVIDUAL SUPPLY
V
V
OUT
IN
4
2
3
1
V
DD
V
GATE
SW
IN
10.7V
REG
–
+
ENABLE
+
–
600ns
ONE
SHOT
ENABLE
DRIVER
QSW
+
–
+
–
15mV
OUT
10
9
R2
OPEN
MOSFET
DETECT
V
IN
OUT
UV
C
UV
7
6
+
–
R
B
STATUS
+
R1
0.3V
OV
ST
C
–
+
OVF
–
R
A
FAULT
C
OV
8
–
+
0.33V
0.3V
GND
5
4351 BD
4351fd
7
LT4351
OPERATION
Increasingly, system designers have to deal with multiple
supply sources. The multiplicity may provide parallel,
redundant supplies for increased reliability or provide
a means of connecting disparate supplies. In all cases
the desire is for behavior like a diode but with no loss or
voltage drop.
OV just exceeds the reference, an internal capacitor starts
charging, delaying the signal to turn off the MOSFET(s).
The second occurs when the OV pin exceeds 330mV. The
OVFcomparatorwillimmediatelytrippullingGATEtoGND.
Thisaffordsadelayinverselyproportionaltotheamountof
overdrive. This also provides for glitch immunity without
compromising response time in the event of a serious
overvoltage condition.
ORing diodes have been the conventional means of con-
necting these supplies. The disadvantage of this approach
is that diodes introduce efficiency loss because of their
forward voltage drop. This variable voltage drop also de-
generates supply tolerance. Additionally, diodes provide
no information concerning the status of the sourcing
supply. Separate control must also be added to ensure
that a supply that is out of range is not allowed to affect
the common supply.
The FAULT output indicates the status of the C , C
OV
OVF
and C comparators. It pulls low during a fault condi-
UV
tion. It also pulls low when GATE is at compliance and
V
> OUT by more than 0.21V indicating a probable
IN
nonfunctioning MOSFET. Compliance occurs when GATE
is at the lesser of OUT + 7.4V or V – 2.3V. FAULT derives
DD
its drive from the greater of V or OUT. It is active if V
IN
IN
TheLT4351eliminatestheseproblemsbyusingN-channel
MOSFETs as the pass elements. The MOSFET is turned on
when power is being passed, allowing for a low voltage
drop from the supply to the load. When the input source
voltage drops below the output common supply voltage it
turns off the MOSFET, thereby matching the function and
performance of an ideal diode.
or OUT is greater than 0.9V. If V or OUT is below this
IN
level, the output state is not guaranteed.
The gate drive consists of a high current, wide bandwidth
amplifier(driver).Whentheamplifierisenabled,itattempts
to regulate the GATE voltage such that the voltage across
the MOSFET(s) is approximately 15mV. If the MOSFET(s)
on resistance is so high as to prevent regulation, then
GATE goes to compliance and the MOSFET(s) fully turns
The LT4351 drives either a single MOSFET or dual back-
to-back MOSFETs. Dual MOSFETs are chosen to eliminate
current flow from the input supply to the output supply
on. The inputs to the amplifier are V and OUT. The GATE
IN
pin sources current from V and sinks current to GND.
DD
when the V voltage is greater than OUT.
IN
The maximum GATE to V voltage is the lesser of V
–
IN
DD
2.3V or 7.4V above V
or V (internal clamp voltage).
OUT
IN
A driver amplifier monitors the input (V ) and output
IN
IN
(OUT) and controls the MOSFETs. If V exceeds OUT
The STATUS comparator, ST, pulls low when GATE ex-
ceeds V by 0.7V. This occurs when V > OUT + 15mV.
by 15mV, GATE goes high and turns on the MOSFET(s)
IN
IN
allowing for power passage.
The STATUS pin pulls low as an indication that power is
passing through the MOSFET(s).
Undervoltage and overvoltage comparators C , C
UV
OV
and C
also control power passage. A resistive divider
OVF
If V is greater than OUT by 0.21V and GATE > V + 7.4V
IN
IN
in conjunction with the UV and OV pins sets appropriate
thresholds such that the MOSFET(s) is off when the UV
pin is below 300mV or OV pin is above 300mV.
or at compliance (GATE = V – 2.3V), STATUS will go
DD
high as an indication of a likely open MOSFET. FAULT will
pull low in this state indicating the probable fault.
To help deal with the transients on the supply lines, the UV
input has current hysteresis. When the UV voltage drops
below the 300mV threshold, a 10µA current is pulled from
the pin. Thus the user can set the hysteresis level through
appropriate values in the divider.
ThegatedriveamplifierandSTATUSfunctionderivepower
fromV .ThecircuitrequiresV >2.5V.IfV ispresent,
DD
DD
DD
thegatedriveamplifierandSTATUSareactiveindependent
of the state of V . If in a fault, GATE pulls actively low. In
IN
the event of V collapse there still is an active pull-down
DD
Overvoltage shutdown occurs in two stages. The first oc-
curswhentheOVpinexceedsthe300mVreference. When
(though of lesser strength) of GATE powered from OUT,
guaranteeing turn off.
4351fd
8
LT4351
OPERATION
The on-chip boost regulator uses a constant off-time
control scheme. When V is below the regulation trip
voltage, the switch turns on after a 600ns off-time. When
the switch turns on current ramps up in the inductor until
the current limit is reached (450mA). The switch turns
off and the inductor’s current flows through the external
diode to charge up the V capacitor. If V is still too low,
the switch turns on again after a fixed off-time of 600ns.
The boost regulator regulates V to approximately 10.7V
DD
above V When V is above this level, the SW transistor
IN
DD
DD
turn-on is disabled. When V falls below this level by the
DD
hysteresis level, the SW transistor is allowed to turn on.
There is approximately 0.15V of hysteresis.
DD
DD
APPLICATIONS INFORMATION
Setting Fault Thresholds
age at the input. V is the part undervoltage trip point
UV
HYSTUV
(10µA). See Figure 1.
(0.3V) and I
is the undervoltage hysteresis current
The gate drive amplifier implements the ideal diode func-
tion. The fault comparators (UV and OV) prevent out of
rangeinputvoltagesfromaffectingtheoutputbydisabling
the amplifier during these conditions. Think of the UV and
OV as gating the ideal diode function, something a regular
diode cannot do.
The divider on the OV pin is a straightforward resistive
divider (Figure 2):
OVFAULT
VOV
RB =
RA =
– 1 RA
A resistive divider from V to UV and one from V to OV
IN
IN
0.3V
RA,RB Divider Current
are the usual way of setting the FAULT thresholds. For UV
the resistor values are set by:
where OV
is the desired overvoltage trip point at the
FAULT
UVHYST
R2 =
input and V is the OV pin threshold (0.3V). The OV pin
OV
IUVHYST
has 7mV of voltage hysteresis at room.
VUV
R1=
•R2
It is possible to do both dividers together using only three
resistors though with more interdependence in compo-
nents (Figure 3). The input bias current for UV and OV is
less than 200nA, so keep resistor values less than 10k.
where UV
is the desired undervoltage hysteresis at
FAULT
HYST
the input. UV
is the desired undervoltage trip volt-
V
IN
V
V
V
IN
IN
IN
V
IN
R3
R2
R2B
R2A
R2
UV
R2
UV
R
B
V
V
UV
UV
UV
OV
300mV
300mV
OV
V
OV
300mV
C1
R1
R1
UV
I
I
HYS
10µA
R
A
HYS
10µA
R1
R1
4351 F02
4351 F01
4351 F03
4351 F04
UV TURNING ON
UV TURNING OFF
Figure 1
Figure 2
Figure 3
Figure 4
4351fd
9
LT4351
APPLICATIONS INFORMATION
In that case, the resistor values are set by:
Boost Regulator
UVHYST
IUVHYST
The boost regulator will start working as soon as V is
IN
R3 =
greater than 0.85V. The regulator will supply all the cur-
rent for the gate drive amplifier. While the amplifier itself
requiresonlyabout3mA,largercurrentpulsesarerequired
when charging the MOSFET gate. The reservoir capacitor
UV
OV
FAULT
VUV –
• VOV
FAULT
R2 =
R1=
•R3
UV
– VUV
FAULT
on V will provide this current (Figure 6).
DD
VOV •UV
FAULT
•R3
V
IN
OV
• UV
– VUV
FAULT
FAULT
Hysteresis helps prevent erratic behavior due to the noise
on V . Two of the most common noise sources are: V
dipping when the MOSFETs first turn on and draw down
the voltage on the V capacitors, and the boost regulator
switch turning on and drawing current from the V ca-
pacitors. UselowESRcapacitorsforV andOUTfiltering.
L1
LT4351
SW
D1
IN
IN
V
DD
QSW
D2
C
DD
IN
IN
GND
4351 F06
IN
Note that because the UV pin uses current hysteresis,
placing a capacitor on UV to ground to filter noise will
reduce the effective hysteresis. Filtering can be achieved
by splitting the R2 resistor, as shown in Figure 4.
Figure 6
The regulator performance is relatively insensitive to the
inductor value. The inductor value does control the fre-
quency of operation. A 4.7µH inductor is recommended
To defeat undervoltage fault detection, the UV pin should
be tied higher than 0.33V. UV can be tied to V provided
for V voltages less than 10V and 10µH for V voltages
IN
IN IN
V
< 9V. Overvoltage fault detection can be defeated by
greater than 10V. Several inductors that work well with
the LT4351 are listed in Table 1. Many different sizes and
shapes are available. Consult each manufacturer for more
detailedinformationandfortheirentireselectionofrelated
parts. The switching frequency for the boost regulator is
around 1MHz so ferrite core inductors should be used
to obtain the best efficiency. The inductor must handle a
peak current of 0.7A minimum and have a DC resistance
of 0.5Ω or less. Shielded inductors are recommended to
reduce the noise due to inductive switching.
IN
grounding the OV pin. Do not exceed V .
IN
INPUT
REFERRED
OV
UV
REFERRED REFERRED
OVERVOLTAGE FAULT:
GATE LOW
V
V
= 0.33V
= 0.3V
UV
OVERVOLTAGE FILTERED FAULT
OV
FAULT
UV
GATE CONTROLLED
V
V
> 0.3V
= 0.3V
V
UV
< 0.3V
OV
BY V – V
IN
OUT
UV
FAULT
+ UV
UV
HYST
UNDERVOLTAGE HYSTERESIS
OV
FAULT
Table 1. Recommended Inductors
UNDERVOLTAGE FAULT:
GATE LOW
4351 F05
PART NUMBER
IND (µH)
DCR (mΩ)
VENDOR
LPS3314-472ML
LPS4012-103ML
4.7
10
175
350
Coilcraft
847-639-6400
Figure 5. Graphical Representation of the UV and OV Functions
www.coilcraft.com
744029004
744042100
4.7
10
200
150
Würth Elektronik
www.we-online.com
External Shutdown
SD3112-4R7-R
SD3118-100-R
4.7
10
246
295
Coiltronics
www.coiltronics.com
To externally turn off the MOSFETs, such as to disable the
supply, use an open-collector transistor pulling down on
the UV pin. Note this will not turn off the boost regulator
which will continue to operate.
4351fd
10
LT4351
APPLICATIONS INFORMATION
ForV lessthan2V,chooseaDCresistancelessthan0.2Ω.
V
Capacitor Selection
DD
IN
NotethatV currentreferredtotheinputsupplyishigher.
LowESR(EquivalentSeriesResistance)capacitorsshould
DD
A first order approximation of the input current is:
be used on V to minimize the output ripple voltage.
DD
Multilayer ceramic capacitors are the best choice, as
they have a very low ESR and are available in very small
packages. Always use a capacitor with a voltage rating at
10.6 IVDD
IVINVDD = 1+
•
V
80%
IN
least 12V greater than V .
IN
Under normal operation, the V current is under 10mA
DD
andtheboostregulatoroperatesinBurstMode® operation.
If any additional load is added, ensure that the regulator is
capable of supplying that load. As the load is increased,
the boost regulator will switch into continuous mode op-
eration. Further increases in load will collapse the boost
regulator voltage.
Capacitors
Two types of input capacitors are generally needed for the
LT4351. The first is a large bulk capacitor that takes care
of ringing associated with inductance of the input supply
lines and provides charge for the load when switching the
MOSFET.Theinputparasiticinductanceinconjunctionwith
Operating the regulator with increased load will cause
increased IC power dissipation and temperature, which
must be taken into consideration.
C and its ESR create an LCR network. The input LCR can
B
bestimulatedbytheboostregulatorswitchcurrentorload
current transients when the MOSFETs are on. To reduce
A 100ns delay from detecting the switch current limit to
turning off the power switch produces an overshoot of the
inductor current from the 0.45A switch limit. The amount
of overshoot depends on the boost regulator inductance.
Choosing an inductor that can handle 0.75A peak current
will be sufficient for the recommended inductors.
ringing associated with input inductance, C should be:
B
4 •LIN
RE2SR
CB ≥
where C is the capacitor value, R
is the capacitor’s
ESR
B
ESR and L is the inductance of the input lines.
IN
Diode Selection
While damped ringing is not necessarily bad, it may pro-
duce unexpected results as the LT4351 ideal diode reacts
Schottky diodes, with their low forward voltage drop and
fast switching speed, are the best match for the LT4351
boost regulator. Select a diode that can handle 0.75A peak
current and a reverse breakdown of 15V greater than the
to the varying V to OUT voltage. Typically an electrolytic
IN
or tantalum low ESR capacitor would be used. Figure 7a
illustrates V for a low value of C and Figure 7b shows
IN
B
it with a correctly sized value.
maximum V .
IN
V
V
IN
IN
200mV
200mV
4351 F07a
4351 F07b
10µs/DIV
10µs/DIV
Figure 7a. Example of Input Voltage Ringing
with Low CIN Capacitor at MOSFET Turn Off
Figure 7b. Example of Input Voltage with
Sufficient CIN Capacitor at MOSFET Turn Off
4351fd
11
LT4351
APPLICATIONS INFORMATION
Asanexample, for500nHofinductanceandR ofabout
MOSFET Selection
ESR
100mΩ, then:
The LT4351 uses either a single N-channel MOSFET or
back-to-back N-channel MOSFETs as the pass element.
Back-to-back MOSFETs prevent the MOSFET body diode
from passing current.
4 • 500nF
C ≥
= 200µF
2
Check vendor data for ESR and iterate to get the best
Use a single MOSFET if current flow is allowable from
input to output when the input supply is above the output
(limited overvoltage protection). In this case the MOSFET
should have a source on the input side so the body diode
conducts current to the load. Back-to-back MOSFETs are
normally connected with their sources tied together to
provide added protection against exceeding maximum
gate to source voltage.
value. Additional C capacitance may be required for load
B
concerns.
If the boost regulator is being used, place a 10µF low ESR
ceramic capacitor from V to GND. Place a 10µF and a
IN
0.1µF ceramic capacitor close to V and GND. These
IN
capacitors should have low ESR (less than 10mΩ for the
10µF and 40mΩ for the 0.1µF). These capacitors help to
eliminateproblemsassociatedwithnoiseproducedbythe
Selection of MOSFETs should be based on R
, BV
DSS
DS(ON)
boost regulator. They are decoupled from the V supply
and BV . BV
should be high enough to prevent
IN
GSS
DSS
by a small 1Ω resistor, as shown in Figure 8. The LT4351
will perform better with a small ceramic capacitor (10µF)
on OUT to GND.
breakdown when V or OUT are at their maximum value.
IN
R
should be selected to keep within the MOSFET
DS(ON)
2
power rating at the maximum load current (I • R
)
DS(ON)
BV
should be at least 8V. The LT4351 will clamp the
GSS
External Boost Supply
GATE to 7.5V above the lesser of V or OUT. For back-
IN
to-back MOSFETs where sources are tied together, this
allows the use of MOSFETs with a VGS max rating of 8V
or more. If a single MOSFET is used, care must be taken
to ensure the VGS max rating is not exceeded. When the
MOSFET is turned off, the GATE voltage is near ground,
The V pin may be powered by an external supply. In
this case, simply omit the boost regulator inductor and
DD
diodeandleavetheSWpinopen.SuitableV capacitance
DD
(minimum of a 1µF ceramic) should remain due to the
current pulses required for the gate driver.
thesourceatV .Thus,MOSFETVGSmaxmustbegreater
IN
than V
.
The V current consists of 3.5mA of DC current with the
IN(MAX)
DD
current required to charge the MOSFET’s gate which is
dependent on the gate charge required and frequency of
switching.Typicallytheaveragecurrentwillbeunder10mA.
If a single MOSFET is used with source to V , then BV
IN
GSS
shouldbegreaterthanthemaximumV sincetheMOSFET
IN
gate is at 0.2V when off.
L
IN
PARASITIC
V
IN
C
V3
1Ω
10µF
GATE
IN
V
C
V1
C
B
10µF
LT4351
C
V2
0.1µF
GND
4351 F08
Figure 8. VIN Capacitors
4351fd
12
LT4351
APPLICATIONS INFORMATION
Thegatedriveamplifierwillattempttoregulatethevoltage
acrosstheMOSFETsto15mV.Regulationwillbeachievedif:
at the load and provides for a more accurate transition
from supply to supply and more accurate load sharing
between supplies.
15mV
2 •ILOAD
RDS
<
for two MOSFETs and
ORing can be done either at the load or at the source.
Figure 9 shows some examples. ORing at the load is usu-
ally the safest method since it protects against shorts in
interconnects.
15mV
ILOAD
RDS
<
for a single MOSFET
The LT4351 tighter forward-voltage tolerance makes it
easier to balance current between similar supplies using
the droop method. The droop method uses the supply
voltage and series resistance in the power path to provide
This requires very low R values. This may be achieved
DS
by paralleling MOSFETs, but be careful to keep intercon-
nection trace resistance low. In the event that regulation
cannotbeachieved,thegatedriveamplifierwilldriveGATE
load sharing. In this case, size the MOSFET’s R
to allow for regulation.
low
DS(ON)
to itsclampand achievethe bestR possible atthat level.
DS
STATUS
BACKPLANE
SOURCE 1
LT4351
LT4351
The STATUS pin sinks current when the input (V ) is
IN
above output (OUT) by 15mV and GATE is above V by
IN
BOARD
0.7V.Thiswillnormallyindicatethatpowerisbeingpassed
though the MOSFETs.
LOAD
In the event of a nonfunctional MOSFET, the GATE voltage
will be driven high (to the GATE clamp voltage). If V is
IN
SOURCE 2
greater than OUT by more than 0.21V, the FAULT pin will
sink current to signal the potential problem.
BACKPLANE
SOURCE 1
BOARD
LT4351
LT4351
There is no direct measurement or confirmation of cur-
rent flowing in the MOSFETs. Current is shared between
sources based on their voltage and series resistance. If
precision load sharing is desired, the LTC4350 may be a
more suitable part.
LOAD
SOURCE 2
Redundant Supplies
The LT4351 is an improved solution for ORing redundant
supplies because of its lower forward drop versus con-
ventional diodes. The lower forward drop significantly
improvesoverallefficiency,improvesthevoltagetolerance
4351 F09
Figure 9. Redundant Backplane Supplies
4351fd
13
LT4351
APPLICATIONS INFORMATION
ORing Disparate Supplies
Once V is greater than 1.2V and V is up, the part then
IN DD
operates normally. The UV and OV pins will control the
The LT4351 provides an easy solution for connecting
together different types of power sources. Again, because
of the low forward drop, the efficiency of the system is
improved and the voltage transition between supplies is
moreaccurate.Inaddition,theundervoltageandovervolt-
age features of the LT4351 provide options for enabling
and disabling the supplies that are not available from a
common diode. Figure 10 shows some examples of con-
necting disparate supplies.
enabling of the gate driver and once enabled, the V to
IN
OUT voltage controls MOSFET turn on.
If V is still being charged when the gate driver turns
DD
on the MOSFET, the GATE pin tracks with the V in-
DD
crease until it reaches either the gate clamp voltage or
the compliance of the gate driver. If V is present with-
DD
out V or OUT, the GATE pin actively sinks low.
IN
Power Dissipation
Isolated System Supply
The internal power dissipation of the LT4351 is comprised
of the following four major components: DC power dis-
from Wall Adapter
Isolated Battery Backup
sipation from V , DC power dissipation from V , the
IN
DD
WALL
ADAPTER
WALL
ADAPTER
dissipationintheboostswitchincludingthebasedrive,and
dynamic power dissipation due to current used to charge
and discharge the MOSFETs. The DC components are:
LT4351
LT4351
+
SYSTEM
SUPPLY
BATTERY
LOAD
LOAD
P
P
= I • V
VIN IN
DCVIN
= I
• V
DD
DCVDD
VDD
Figure 11 shows the internal dissipation of the boost
Three Source ORing Provides Protection
Against Out of Range Supplies
regulator as a function of V and inductor value. Figure
IN
11 represents the worst-case condition with the regulator
on all the time, which does not occur in normal practice.
LT4351
WALL
ADAPTER
0.30
0.25
LT4351
LT4351
+
SYSTEM
SUPPLY
BATTERY
LOAD
L = 10µH
4351 F10
0.20
L = 4.7µH
Figure 10
0.15
0.10
Start-Up Considerations
There is no inherent shutdown in the part. As V ramps
10
(V)
15
0
20
5
IN
V
IN
up, the boost regulator starts at about 0.85V and becomes
fully operational by 1.1V. The undervoltage and overvolt-
age comparators become accurate by 1.2V. The gate drive
amplifier keeps GATE low during this period with either
a passive pull-down, a weak active pull-down if OUT is
4351 F11
Figure 11. PBOOST(MAX)
greater than 0.8V or with the full gate drive sink if V is
DD
above 2.2V.
4351fd
14
LT4351
APPLICATIONS INFORMATION
Since the boost regulator supplies current for V , the
the gate is charged and discharged. Normally f is low and
DD
G
current is the V supply current (3.5mA) plus the aver-
the resulting power would be very low. Figure 13 shows
DD
age current to charge the gate. For a gate charge of 50nC
at a 10kHz rate, this adds 0.5mA of current. The power
dissipated by the boost regulator to supply the 4mA is
shown in Figure 12, representing a more typical situation.
P
for a 50nC gate charge at a 1kHz rate.
GATE
TotalpowerdissipationisthesumofallofP
,P
,
DCVIN DCVDD
. Figure 14 is representative of the total
P
and P
BOOST
GATE
power dissipation of a typical application at steady state.
The die junction temperature is then computed as:
T = T + θ • P
Finally, the gate driver dissipates power internally when
charging and discharging the gate of the MOSFETs. This
power depends on the input capacitance of the MOSFETs
and the frequency of charge and discharge. The power
associated with this can be approximated by:
J
A
JA
TOTAL
where T is the die junction temperature, T is the ambi-
J
A
ent temperature, θ is the thermal resistance of the part
JA
TOTAL
(120°C/W) and P
is ascertained from the above.
V
16
IN
PGATE = fG • VDD • QG • 1–
Therefore, a 0.1W power dissipation causes a 12° tem-
perature rise above ambient.
whereQ istherequiredgatechargetochargetheMOSFET
G
totheclampvoltage(7.4V)andf isthefrequencyatwhich
G
0.025
0.004
L = 4.7µH
f
= 1kHz
GATE
G
Q
= 50nC
0.020
0.015
0.010
0.005
0.003
0.002
0.001
0
10
(V)
15
0
20
5
10
(V)
15
0
20
5
V
V
IN
IN
4351 F12
4351 F13
Figure 12. PBOOST(TYP)
Figure 13. PGATE vs VIN (VDD = VIN + 10.7)
0.16
0.14
0.12
0.10
0.08
V
= V + 10
IN
DD
0.5mA GATE CURRENT
L = 10µH
L = 4.7µH
0.06
0
5
10
(V)
15
20
V
IN
4351 F14
Figure 14. Total Power (Typical)
4351fd
15
LT4351
APPLICATIONS INFORMATION
Design Example
For regulation, the MOSFETs must have:
The following demonstrates the calculations involved for
setting design components for a 5V system that requires
15mV
2 • 5A
RDS
<
= 1.5mΩ
5A. Two supplies are used to do this. The V supply will
IN
This very low value cannot be accomplished with a single
set of MOSFETs so a decision must be made whether to
use multiple MOSFETs or to live with an unregulated off-
bedeemedinspecwhenitiswithin 5ꢀofnominal. Allow
5ꢀ of hysteresis for UV.
So,
set. Since low mΩ R
is available, the IR drop using
DS(ON)
UV
OV
= 4.75V, UV
= 0.25V
HYST
FAULT
a single MOSFET would still be acceptable. For R
DS(ON)
= 4mΩ the drop is 2 • 5A • 4mΩ = 40mV. The finished
schematic is shown in Figure 15.
= 5.5
FAULT
Two separate resistive dividers are used.
For the UV divider:
Layout Considerations
There are two considerations for board layout. The first
UVHYST 0.25V
IUVHYST 10µA
R2 =
R1=
=
= 25k Use 24.9k
(
)
is that V and V bypass capacitors should be as close
IN
DD
to the part as possible. The GND pin should represent the
common tie point. The resistive dividers for UV and OV
should tie here as well.
R2 • VUV
UVFAULT – VUV 4.75V – 0.3V
24.9k • 0.3V
=
Take care that current flow to the load (both through V
and GND), does not inadvertently produce errors due to
IR drops in PCB traces.
R1 = 1.68k. The closest 1ꢀ value is 1.69k
The OV resistors are set as a straight resistive divider.
If the current in the R , R divider is 200µA, then:
IN
A
B
Keep the traces to the MOSFETs wide and short and close
to the part. The PCB traces associated with the power path
through the MOSFETs should have low resistance.
0.3V
RA =
= 1.5k use 1.47k (1%)
200mA
then
RB =
OVFAULT
VOV
5.5
0.3
– 1 RA =
– 1 1.47k
Si4838DY
R = 25.48, use 25.5k
B
V
IN
OUT
5V
1Ω
10µF
10µF
3
1
10
OUT
0.1µF
5V
R2
24.9k
1%
V
GATE
IN
7
UV
4.7µH
R
R1
B
25.5k 1.69k
LT4351
1%
1%
6
4
2k
2k
OV
9
8
SW
STATUS
MBR0530
MBR0530
2
R
A
V
FAULT
DD
10µF
220µF
1.47k
1%
GND
5
1µF
4351 F15
Figure 15. 5V/5A Design Example
4351fd
16
LT4351
TYPICAL APPLICATIONS
Lead Acid Battery Backup
14V
POWER
SUPPLY
Si4408DY
CHARGER
OUT
10µF
+
12V
1Ω
LOAD
LEAD-ACID
BATTERY
3
1
10
OUT
10µF
R2
12.7k
1%
V
GATE
0.1µF
IN
7
UV
R
R1
B
10µH
73.2k 365Ω
LT4351
1%
1%
6
4
10k
10k
OV
9
8
SW
STATUS
FAULT
MBR0530
MBR0530
10µF
2
V
DD
+
R
1.5k
1%
A
GND
5
1µF
UV
FAULT
OV
FAULT
= 10.8V
= 15V
220µF
4351TA02
5V Redundant Supply with External VDD
Si4838DY
5V
SOURCE
1Ω
10µF
3
1
10
10µF
R2
24.9k
1%
V
GATE
OUT
0.1µF
10µF
IN
7
UV
R
R1
B
25.5k 1.69k
+
1%
1%
6
4
LT4351
2k
2k
100µF
OV
R
A
1.47k
1%
9
8
SW
STATUS
2
12V
V
FAULT
DD
SOURCE
GND
5
1µF
4351 F15
1ST SOURCE
2ND
5V SOURCE
COMMON
2ND LT4351
CIRCUIT
LOAD
2ND
12V SOURCE
4351 TA03
4351fd
17
LT4351
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661 Rev E)
0.889 0.ꢀꢁ7
(.035 .005)
5.ꢁ3
3.ꢁ0 – 3.45
(.ꢁ0ꢂ)
(.ꢀꢁꢂ – .ꢀ3ꢂ)
MIN
3.00 0.ꢀ0ꢁ
(.ꢀꢀ8 .004)
(NOTE 3)
0.497 0.07ꢂ
(.0ꢀ9ꢂ .003)
REF
0.50
(.0ꢀ97)
BSC
0.305 0.038
(.0ꢀꢁ0 .00ꢀ5)
TYP
ꢀ0 9
8
7 ꢂ
RECOMMENDED SOLDER PAD LAYOUT
3.00 0.ꢀ0ꢁ
(.ꢀꢀ8 .004)
(NOTE 4)
4.90 0.ꢀ5ꢁ
(.ꢀ93 .00ꢂ)
DETAIL “A”
0.ꢁ54
(.0ꢀ0)
0° – ꢂ° TYP
GAUGE PLANE
ꢀ
ꢁ
3
4 5
0.53 0.ꢀ5ꢁ
(.0ꢁꢀ .00ꢂ)
0.8ꢂ
(.034)
REF
ꢀ.ꢀ0
(.043)
MAX
DETAIL “A”
0.ꢀ8
(.007)
SEATING
PLANE
0.ꢀ7 – 0.ꢁ7
(.007 – .0ꢀꢀ)
TYP
0.ꢀ0ꢀꢂ 0.0508
(.004 .00ꢁ)
0.50
(.0ꢀ97)
BSC
MSOP (MS) 0307 REV E
NOTE:
ꢀ. DIMENSIONS IN MILLIMETER/(INCH)
ꢁ. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.ꢀ5ꢁmm (.00ꢂ") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.ꢀ5ꢁmm (.00ꢂ") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.ꢀ0ꢁmm (.004") MAX
4351fd
18
LT4351
REVISION HISTORY (Revision history begins at Rev C)
REV
DATE
12/10 Reversed orientation of N-channel MOSFETs in Typical Application drawing.
12/11 Revised V Maximum value in Electrical Characteristics section
DESCRIPTION
PAGE NUMBER
C
1
3
D
BR
4351fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LT4351
TYPICAL APPLICATION
Primary Battery with Secondary Battery Backup
Si4408DY
CHARGER
OUT
10µF
+
1Ω
12.6V
BATTERY1
3
1
10
OUT
10µF
R2
40.1k
1%
0.1µF
V
GATE
IN
7
UV
R1
1.07k
1%
10µH
LT4351
6
4
10k
5%
10k
5%
OV
9
8
SW
STATUS
+
MBR0530
MBR0530
100µF
2
V
FAULT
DD
GND
5
100k
5%
10µF
1µF
UV
FAULT
= 11.8V
Si4408DY
CHARGER
OUT
10µF
+
120k
5%
1Ω
LOAD
100µF
12.6V
BATTERY2
3
1
10
10µF
0.1µF
V
GATE
OUT
IN
7
UV
10µH
300k
5%
1N914
LT4351
6
4
10k
10k
OV
9
8
SW
STATUS
+
MBR0530
MBR0530
100µF
2
V
FAULT
DD
GND
5
10µF
1µF
4351TA04
POWER IS SWITCHED TO BATTERY2 WHEN BATTERY1 DROPS TO 11.8V
RELATED PARTS
PART NUMBER
LTC4352
DESCRIPTION
COMMENTS
Ideal Diode Controller with Monitor
Negative Voltage Diode-OR Controller and Monitor
Positive Voltage Diode-OR Controller and Monitor
Positive High Voltage Ideal Diode Controller
Controls N-Channel MOSFET, 0V to 18V Operation
LTC4354
Controls Two N-Channel MOSFETs, 1µs Turn-Off, 80V Operation
Controls Two N-Channel MOSFETs, 0.5µs Turn-Off, 80V Operation
Controls Single N-Channel MOSFET, 0.5µs Turn-Off, 80V Operation
Integrated N-Channel MOSFET, 0.5µs Turn-Off, 9V to 26.5V
P-Channel MOSFET, 3V to 28V Range
LTC4355
LTC4357
LTC4358
LTC4412
5A Ideal Diode
Low Loss PowerPath™ Controller in ThinSOT™
4351fd
LT 1211 REV D • PRINTED IN USA
20 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2003
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号：
LT4351CMS#TRPBF
LT4351 - MOSFET Diode-OR Controller; Package: MSOP; Pins: 10; Temperature Range: 0°C to 70°C
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LT4351IMS#PBF
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LT4351IMS#TR
LT4351 - MOSFET Diode-OR Controller; Package: MSOP; Pins: 10; Temperature Range: -40°C to 85°C
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LT4351IMS#TRPBF
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