LT4356 [Linear]
Overvoltage/Overcurrent Protection Controller; 过压/过流保护控制器
| 型号： | LT4356 |
| 厂家： | 
Linear |
| 描述： | Overvoltage/Overcurrent Protection Controller |
| 文件： | 总16页 (文件大小：407K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4361-1/LTC4361-2
Overvoltage/Overcurrent
Protection Controller
FeaTures
DescripTion
n
2.5V to 5.5V Operation
TheLTC®4361overvoltage/overcurrentprotectioncontrol-
ler safeguards 2.5V to 5.5V systems from input supply
overvoltage. It is designed for portable devices with
multiple power supply options including wall adaptors,
car battery adaptors and USB ports.
n
Overvoltage Protection Up to 80V
n
No Input Capacitor or TVS Required for Most
Applications
n
2% Accurate 5.8V Overvoltage Threshold
n
10% Accurate 50mV Overcurrent Circuit Breaker
The LTC4361 controls an external N-channel MOSFET in
series with the input power supply. During overvoltage
transients, the LTC4361 turns off the MOSFET within
1µs, isolating downstream components from the input
supply. Inductive cable transients are absorbed by the
MOSFET and load capacitance. In most applications, the
LTC4361 provides protection from transients up to 80V
without requiring transient voltage suppressors or other
external components.
n
<1µs Overvoltage Turn-Off, Gentle Shutdown
n
Controls N-Channel MOSFET
n
Adjustable Power-Up dV/dt Limits Inrush Current
n
Reverse Voltage Protection
n
Power Good Output
n
Low Current Shutdown
n
Latchoff (LTC4361-1) or Auto-Retry (LTC4361-2)
After Overcurrent
n
Available in 8-Lead ThinSOT™ and 8-Lead
The LTC4361 has a delayed start-up and adjustable dV/dt
(2mm × 2mm) DFN Packages
ramp-upforinrushcurrentlimiting.APWRGDpinprovides
powergoodmonitoringforV .TheLTC4361featuresasoft
IN
applicaTions
shutdown controlled by the ON pin and drives an optional
externalP-channelMOSFETfornegativevoltageprotection.
Followinganovervoltagecondition,theLTC4361automati-
cally restarts with a start-up delay. After an overcurrent
fault, the LTC4361-1 remains off while the LTC4361-2
automatically restarts after a 130ms start-up delay.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
n
USB Protection
n
Handheld Computers
n
Cell/Smart Phones
n
MP3/MP4 Players
n
Digital Cameras
ThinSOT, Hot Swap, No R
and PowerPath are trademarks of Linear Technology
SENSE
Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
Protection from Overvoltage and Overcurrent
Output Protected from Overvoltage at Input
0.025Ω
V
Si1470DH
OUT
V
IN
V
IN
5V
5V
1.5A
C
OUT
GATE
SENSE OUT
V
OUT
IN
V
, V
IN OUT
5V/DIV
LTC4361
ON PWRGD
V
GATE
10V/DIV
GND
436112 TA01a
436112 TA01b
0.5µs/DIV
Si1470DH
= 10µF
C
OUT
436112fb
1
LTC4361-1/LTC4361-2
absoluTe maximum raTings
(Notes 1, 2)
Bias Supply Voltage (IN)............................ –0.3V to 85V
Input Voltages
SENSE ................................................... –0.3V to 85V
OUT, ON................................................... –0.3V to 9V
Output Voltages
Operating Temperature Range
LTC4361C ................................................ 0°C to 70°C
LTC4361I .............................................–40°C to 85°C
LTC4361H.......................................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
PWRGD.................................................... –0.3V to 9V
GATE (Note 3)........................................ –0.3V to 15V
GATEP.................................................... –0.3V to 85V
IN to GATEP ........................................... –0.3V to 10V
TSOT.................................................................300°C
pin conFiguraTion
TOP VIEW
TOP VIEW
1
2
3
4
8
7
6
5
IN
GND
GATEP
OUT
ON 1
OUT 2
GATEP 3
GND 4
8 PWRGD
7 GATE
6 SENSE
5 IN
SENSE
GATE
PWRGD
9
ON
TS8 PACKAGE
8-LEAD PLASTIC TSOT-23
DC PACKAGE
8-LEAD (2mm × 2mm) PLASTIC DFN
T
= 125°C, θ = 195°C/W
JA
JMAX
T
= 125°C, θ = 102°C/W
JA
EXPOSED PAD (PIN 9) IS GND, CONNECTION OPTIONAL
JMAX
orDer inFormaTion
Lead Free Finish
TAPE AND REEL (MINI)
LTC4361CTS8-1#TRMPBF
LTC4361CTS8-2#TRMPBF
LTC4361ITS8-1#TRMPBF
LTC4361ITS8-2#TRMPBF
LTC4361HTS8-1#TRMPBF
LTC4361HTS8-2#TRMPBF
LTC4361CDC-1#TRMPBF
LTC4361CDC-2#TRMPBF
LTC4361IDC-1#TRMPBF
LTC4361IDC-2#TRMPBF
LTC4361HDC-1#TRMPBF
LTC4361HDC-2#TRMPBF
TAPE AND REEL
PART MARKING*
LTDWN
LTFMN
LTDWN
LTFMN
LTDWN
LTFMN
LDWP
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4361CTS8-1#TRPBF
LTC4361CTS8-2#TRPBF
LTC4361ITS8-1#TRPBF
LTC4361ITS8-2#TRPBF
LTC4361HTS8-1#TRPBF
LTC4361HTS8-2#TRPBF
LTC4361CDC-1#TRPBF
LTC4361CDC-2#TRPBF
LTC4361IDC-1#TRPBF
LTC4361IDC-2#TRPBF
LTC4361HDC-1#TRPBF
LTC4361HDC-2#TRPBF
8-Lead Plastic TSOT-23
0°C to 70°C
8-Lead Plastic TSOT-23
0°C to 70°C
8-Lead Plastic TSOT-23
–40°C to 85°C
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
0°C to 70°C
8-Lead Plastic TSOT-23
8-Lead Plastic TSOT-23
8-Lead Plastic TSOT-23
8-Lead (2mm × 2mm) Plastic DFN
8-Lead (2mm × 2mm) Plastic DFN
8-Lead (2mm × 2mm) Plastic DFN
8-Lead (2mm × 2mm) Plastic DFN
8-Lead (2mm × 2mm) Plastic DFN
8-Lead (2mm × 2mm) Plastic DFN
LFMP
0°C to 70°C
LDWP
–40°C to 85°C
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
LFMP
LDWP
LFMP
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
436112fb
2
LTC4361-1/LTC4361-2
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VON = 0V, unless otherwise noted.
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
l
V
V
Input Voltage Range
2.5
1.8
80
2.47
400
10
V
V
IN
Input Undervoltage Lockout
Input Supply Current
V
V
V
Rising
= 0V
2.1
220
1.5
IN(UVL)
IN
I
IN
µA
µA
ON
ON
= 2.5V
Thresholds
l
l
l
l
V
V
IN Pin Overvoltage Threshold
IN Pin Overvoltage Recovery Threshold
Overvoltage Hysteresis
V
V
Rising
Falling
5.684
5.51
25
5.8
5.7
100
50
5.916
5.85
260
55
V
V
IN(OV)
IN
IN
IN(OVL)
mV
mV
∆V
∆V
OV
OC
Overcurrent Threshold
V
– V
45
IN
SENSE
External Gate Drive
l
l
External N-Channel MOSFET Gate Drive 2.5V ≤ V < 3V, I
= –1µA
= –1µA
3.5
4.5
4.5
6
6
7.9
V
V
∆V
GATE
IN
GATE
GATE
(V
– V
)
3V ≤ V < 5.5V, I
GATE
OUT
IN
l
l
V
GATE High Threshold for PWRGD Status
V
IN
V
IN
= 3.3V
= 5V
5.7
6.7
6.3
7.2
6.8
7.8
V
V
GATE(TH)
l
l
I
GATE Pull-Up Current
GATE Ramp-Up
V
V
= 1V
–4.5
1.3
–10
3
–15
4.5
µA
GATE(UP)
GATE
GATE
V
= 1V to 7V
V/ms
GATE(UP)
GATE(FST)
l
l
I
I
GATE Pull-Down Current
Fast Turn-Off, V = 6V, V
= 9V (C-, I-Grade)
(H-Grade)
15
12
30
30
60
60
mA
mA
IN
GATE
l
GATE Pull-Down Current
V
= 2.5V, V = 9V
GATE
5
40
80
µA
GATE(DN)
ON
Input Pins
I
I
SENSE Input Current
OUT Input Current
V
= 5V
SENSE
10
nA
SENSE(IN)
OUT(IN)
l
l
V
V
= 5V, V = 0V
5
10
0
20
3
µA
µA
OUT
OUT
ON
ON
= 5V, V = 2.5V
l
l
V
ON Input Threshold
0.4
2
1.5
10
V
ON(TH)
I
ON Pull-Down Current
V
= 2.5V
5
µA
ON
ON
Output Pins
l
l
V
IN to GATEP Clamp Voltage
GATEP Resistive Pull-Down
PWRGD Output Low Voltage
V
V
V
= 8V to 80V
5
5.8
2
7.9
3.2
V
GATEP(CLP)
IN
R
= 3V
0.6
MΩ
GATEP
GATEP
l
l
V
= 5V, I = 3mA
PWRGD
(C-, I-Grade)
(H-Grade)
0.23
0.23
0.4
0.5
V
V
PWRGD(OL)
IN
l
R
PWRGD Pull-Up Resistance to OUT
V
= 6.5V, V
= 1V
PWRGD
220
500
800
kΩ
PWRGD
IN
Delay
l
t
t
GATE On Delay
V
High to I = –5µA
GATE
50
5
130
219
ms
ON
IN
l
l
GATE Off Propagation Delay
V
V
= Step 5V to 6.5V to PWRGD High
0.25
10
1
20
µs
µs
OFF
IN
IN
– V
= Step 0mV to 100mV
SENSE
l
l
t
t
PWRGD Delay
V
V
= Step 5V to 6.5V
GATE
0.25
65
1
µs
PWRGD
IN
> V
to PWRGD Low
GATE(TH)
25
105
ms
l
ON High to GATE Off
V
= Step 0V to 2.5V
ON
2
5
µs
ON(OFF)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to GND unless otherwise
specified.
Note 3: An internal clamp limits V
to a minimum of 4.5V above V
.
GATE
OUT
Driving this pin to voltages beyond this clamp may damage the device.
436112fb
3
LTC4361-1/LTC4361-2
Typical perFormance characTerisTics
TA = 25°C, VIN = 5V, VON = 0V, unless otherwise noted.
Input Supply Current
vs Input Voltage
GATE Fast Pull-Down Current
vs Temperature
GATE Drive vs GATE Current
40
35
30
25
10000
1000
8
7
6
5
4
3
2
1
0
V
V
= 6V
IN
GATE
= 9V
V
= 0V
ON
V
= 5V
IN
100
V
= 3V
IN
V
V
= 2.5V
ON
10
1
= 2.5V
IN
20
0.1
–50 –25
0
25
50
75 100 125
1
10
(V)
100
0
2
4
6
8
10
12
TEMPERATURE (°C)
V
IN
I
(µA)
GATE
436112 G03
436112 G01
436112 G02
GATE Voltage and GATE High
PWRGD Voltage
vs PWRGD Current
GATE Off Propagation Delay
vs Overdrive
Threshold (for PWRGD Status)
vs Input Voltage
500
400
300
200
100
0
8
12
11
10
9
V
= STEP 5V TO (V
+ V
)
V
= V
IN
IN(OV)
OVDRV
IN OUT
7
6
5
4
3
2
1
0
V
GATE
8
V
GATE(TH)
7
6
5
4
2.5
0
1
2
3
(mA)
4
5
0
1
1.5
(V)
2
2.5
4
V
IN
4.5
(V)
5
5.5
6
0.5
3.5
3
I
V
PWRGD
OVDRV
436112 G04
436112 G05
436112 G06
Normal Start-Up Sequence
GATE Slow Ramp-Up
Entering Sleep Mode
V
ON
5V/DIV
V
V
IN
IN
5V/DIV
5V/DIV
V
V
V
OUT
OUT
OUT
5V/DIV
5V/DIV
5V/DIV
V
V
V
GATE
GATE
GATE
10V/DIV
10V/DIV
10V/DIV
I
I
I
CABLE
CABLE
CABLE
0.5A/DIV
0.5A/DIV
0.5A/DIV
436112 G07
436112 G08
436112 G09
20ms/DIV
1ms/DIV
50µs/DIV
FIGURE 5 CIRCUIT
FIGURE 5 CIRCUIT
FIGURE 5 CIRCUIT
R
R
= 150mΩ, L = 0.7µH
IN
SENSE
LOAD = 10Ω, C
IN
R
R
= 150mΩ, L = 0.7µH
R
R
= 150mΩ, L = 0.7µH
IN
SENSE
IN
IN
SENSE
IN
= 25mΩ
= 25mΩ
= 25mΩ
= 10µF
OUT
LOAD = 10Ω, C
= 10µF
LOAD = 10Ω, C
= 10µF
OUT
OUT
436112fb
4
LTC4361-1/LTC4361-2
pin FuncTions
ExposedPad(DFN):Ground.ConnectiontoPCBisoptional.
V
– ∆V to release the overvoltage lockout. Dur-
OV
IN(OV)
ing lockout, GATE is held low and the PWRGD pull-down
GATE: Gate Drive for External N-Channel MOSFET. An
internal charge pump provides a 10µA pull-up current to
charge the gate of the external N-channel MOSFET. An
additional ramp circuit limits the GATE ramp rate when
turning on to 3V/ms. For slower ramp rates, connect an
external capacitor from GATE to GND. An internal clamp
limits GATE to 6V above the OUT pin voltage. An internal
GATE high comparator controls the PWRGD pin.
releases.
ON:OnControlInput.AlogiclowatONenablestheLTC4361.
A logic high at ON activates a low current pull-down at the
GATE pin and causes the LTC4361 to enter a low current
sleep mode. An internal 5µA current pulls ON down to
ground. Connect to ground or leave open if unused.
OUT:OutputVoltageSenseInputforGATEClamp.Connect
to the source of the external N-channel MOSFET to sense
the output voltage for GATE to OUT clamp.
GATEP: Gate Drive for External P-Channel MOSFET. GATEP
connectstothegateofanoptionalexternalP-channelMOS-
FET to protect against negative voltages at IN. This pin is
internally clamped to 5.8V below V . An internal 2M resis-
tor connects this pin to ground. Connect to IN if not used.
PWRGD: Power Good Status. Open-drain output with
IN
internal 500k resistive pull-up to OUT. Pulls low 65ms
after GATE ramps above V
.
GATE(TH)
GND: Device Ground.
SENSE: Current Sense Input. Connect a sense resistor
between IN and SENSE. An overcurrent protection circuit
turns off the N-channel MOSFET when the voltage across
the sense resistor exceeds 50mV for more than 10µs.
IN: Supply Voltage Input. Connect this pin to the input
power supply. This pin has an overvoltage threshold of
5.8V. After an overvoltage event, this pin must fall below
436112fb
5
LTC4361-1/LTC4361-2
block Diagram
GATEP
200k
IN
SENSE
5.8V
CHARGE
PUMP
1.8M
10µA
GATE
5.8V
GATE HIGH
ON
+
–
COMPARATOR
1V
+
OUT
V
GATE(TH)
–
5µA
OVERCURRENT
COMPARATOR
+
–
50mV
–
+
CONTROL
OVERVOLTAGE
COMPARATOR
500k
+
–
5.8V
5.7V
PWRGD
GND
436112 BD
operaTion
Mobile devices like cell phones and MP3/MP4 players have
highly integrated subsystems fabricated from deep submi-
cronCMOSprocesses.Thesmallformfactorisaccompanied
by low absolute maximum voltage ratings. The sensitive
electronics are susceptible to damage from transient or DC
overvoltage conditions from the power supply.
If the voltage at the IN pin exceeds 5.8V (V
GATE is pulled low quickly to protect the load. The
incoming power supply must remain below 5.7V
),
IN(OV)
(V
– ∆V ) for the duration of the start-up delay to
IN(OV)
OV
restart the GATE ramp-up.
AsenseresistorplacedbetweenINandSENSEimplements
an overcurrent protection with a 50mV trip threshold and
a 10µs glitch filter. After an overcurrent, the LTC4361-
1 latches off while the LTC4361-2 restarts following a
130ms delay.
Failures or faults in the power adaptor can cause an overvolt-
age event. So can hot-plugging an AC adaptor into the power
input of the mobile device (see LTC Application Note 88).
Today’smobiledevicesderivetheirpowersupplyorrecharge
theirinternalbatteriesfrommultiplealternativeinputslikeAC
wall adaptors, car battery adaptors and USB ports. A user
may unknowingly plug in the wrong adaptor, damaging the
device with a high or even a negative power supply voltage.
The LTC4361 has a CMOS compatible ON input. When
driven low, the part is enabled. When driven high, the
external N-channel MOSFET is turned off and the supply
current of the LTC4361 drops to 1.5µA. The PWRGD pull-
down releases during this low current sleep mode, UVLO,
overvoltage or overcurrent and the subsequent 130ms
start-up delay. After the start-up delay, GATE starts its
The LTC4361 protects low voltage electronics from these
overvoltage conditions by controlling a low cost external
N-channel MOSFET configured as a pass transistor. At
power-up (V > 2.1V), a start-up delay cycle begins. Any
slow ramp-up and ramps higher than V
to trigger
IN
GATE(TH)
overvoltage condition causes the delay cycle to continue
until a safe voltage is present. When the delay cycle com-
pletes, an internal high side switch driver slowly ramps up
the MOSFET gate, powering up the output at a controlled
rateandlimitingtheinrushcurrenttotheoutputcapacitor.
a 65ms delay cycle. When that completes, PWRGD pulls
low.The LTC4361 has a GATEP pin that drives an optional
external P-channel MOSFET to provide protection against
negative voltages at IN.
436112fb
6
LTC4361-1/LTC4361-2
applicaTions inFormaTion
The typical LTC4361 application protects 2.5V to 5.5V
systems in portable devices from power supply overvolt-
age. The basic application circuit is shown in Figure 1.
Device operation and external component selection is
discussed in detail in the following sections.
The GATE ramp rate is limited to 3V/ms. V
follows at
OUT
a similar rate which results in an inrush current into the
load capacitor C
of:
OUT
dVGATE
dt
IINRUSH =COUT
•
=COUT •3 mA/µF
[
]
The servo loop is compensated by the parasitic capaci-
tance of the external MOSFET. No further compensation
components are normally required. In the case where
the parasitic capacitance is less than 100pF, a 100pF
compensation capacitor between GATE and ground may
be required.
R
M1
Si1470DH
SENSE
0.025Ω
V
OUT
V
IN
5V
5V
1.5A
C
OUT
10µF
GATE
SENSE OUT
LTC4361
IN
An even slower GATE ramp and lower inrush current can
be achieved by connecting an external capacitor, C , from
ON PWRGD
G
GND
GATE to ground. The voltage at GATE then ramps up with a
436112 F01
slopeequalto10µA/C [V/s].ChooseC usingtheformula:
G
G
10µA
IINRUSH
Figure 1. Protection from Input Overvoltage and Overcurrent
CG =
•COUT
Start-Up
Overvoltage
When power is first applied, V must remain below 5.7V
When V is less than the undervoltage lockout level of
IN
IN
2.1V,theGATEdriverisheldlowandthePWRGDpull-down
(V
– ∆V ) for more than 130ms before GATE is
IN(OV)
OV
is high impedance. When V rises above 2.1V and ON is
IN
ramped up to turn on the MOSFET. If V then rises above
IN
held low, a 130ms delay cycle starts. Any undervoltage or
5.8V (V
), the overvoltage comparator activates the
IN(OV)
overvoltage event at IN (V < 2.1V or V > 5.7V) restarts
IN
IN
30mA fast pull-down on GATE within 1µs. After an over-
the delay cycle. This delay allows the N-channel MOSFET
to isolate the output from any input transients that occur
at start-up. When the delay cycle completes, GATE starts
its slow ramp-up.
voltage condition, the MOSFET is held off until V once
IN
again remains below 5.7V for 130ms.
Overcurrent
GATE Control
The overcurrent comparator protects the MOSFET from
excessive current. It trips when the SENSE pin falls more
than 50mV below IN for 10µs. When the overcurrent
comparator trips, GATE is pulled low quickly and the
PWRGDpull-downreleases.TheLTC4361-2automatically
tries to apply power again after a 130ms start-up delay.
An internal charge pump provides a gate overdrive greater
than 3.5V when 2.5V ≤ V < 3V. If V ≥ 3V, the gate drive
is guaranteed to be greater than 4.5V. This allows the use
of logic-level N-channel MOSFETs. An internal 6V clamp
between GATE and OUT protects the MOSFET gate.
IN
IN
436112fb
7
LTC4361-1/LTC4361-2
applicaTions inFormaTion
The LTC4361-1 has an internal latch that maintains this
off state until it is reset. To reset this latch, cycle IN be-
PWRGD Output
PWRGD is an active low output with a MOSFET pull-down
togroundanda500kresistivepull-uptoOUT.ThePWRGD
pin pull-down releases during the low current sleep mode
(invoked by ON high), UVLO, overvoltage or overcurrent
and the subsequent 130ms start-up delay. After the start-
up delay, GATE starts its slow ramp-up and control of the
PWRGDpull-downpassesontotheGATEhighcomparator.
low 2.1V (V
) or ON above 1.5V (V
) for more
IN(UVL)
ON(TH)
than 500µs. After reset, the LTC4361-1 goes through the
start-up cycle.
Inapplicationsnotrequiringtheovercurrentprotection,tie
the SENSE pin to the IN pin. To implement an overcurrent
threshold I
, choose R
using the formula:
TRIP
SENSE
V
>V
formorethan65ms assertsthePWRGD
GATE
pull-down and V
GATE(TH)
∆VOC
ITRIP
RSENSE
=
< V
releases the pull-down.
GATE
GATE(TH)
The PWRGD pull-down is capable of sinking up to 3mA of
current allowing it to drive an optional LED. To interface
PWRGDtoanotherI/Orail,connectaresistorfromPWRGD
to the I/O rail with a resistance low enough to override
the internal 500k pull-up to OUT. Figure 2 details PWRGD
behaviorforaLTC4361-2with1kpull-upto5VatPWRGD.
After choosing the R , keep in mind that:
SENSE
∆VOC(MAX)
ITRIP(MAX)
=
RSENSE(MIN)
∆VOC(MIN)
ITRIP(MIN)
=
RSENSE(MAX)
OC
START-UP
FROM UVLO
RESTART
FROM OV
RESTART
FROM ON
RESTART
FROM OC
OV
ON
OC
THRESHOLD
I
CABLE
V
IN(OV)
V
–∆V
IN(OV)
OV
V
IN(UVL)
IN
OUT
V
V
V
V
V
GATE(TH)
GATE(TH)
GATE(TH)
GATE(TH)
GATE(TH)
GATE
ON
PWRGD
130ms
65ms
130ms 65ms
130ms
65ms
130ms 65ms
10µs (NOT TO SCALE)
436112 F02
Figure 2. PWRGD Behavior
436112fb
8
LTC4361-1/LTC4361-2
applicaTions inFormaTion
ON Input
Fornearzeroreverse-leakagecurrentprotectionwhenGATE
is pulled to ground, back-to-back N-channel MOSFETs
can be used. Adding an additional P-channel MOSFET
controlled by GATEP provides negative input voltage
ON is a CMOS compatible, active low enable input. It has
a default 5µA pull-down to ground. Connect this pin to
ground or leave open to enable normal device operation.
If it is driven high while the external MOSFET is turned on,
GATE is pulled low with a weak pull-down current (40µA)
to turn off the external MOSFET gradually, minimizing
inputvoltagetransients.TheLTC4361thengoesintoalow
current sleep mode, drawing only 1.5µA at IN. When ON
goes back low, the part restarts with a 130ms delay cycle.
protection down to the BV
of the P-channel MOSFET.
DSS
Another configuration consists of a P-channel MOSFET
controlled by GATEP and a N-channel MOSFET controlled
byGATE.Thisprovidesprotectionagainstovervoltageand
negative voltage but not reverse current.
OVERVOLTAGE
PROTECTION
R
R
SENSE
M1
SUPPLY
SUPPLY
GATEP Control
OUT
OUT
IN
IN
SENSE
GATEP has a 2M resistive pull-down to ground and a 5.8V
Zener clamp in series with a 200k resistor to IN. It con-
trols the gate of an optional external P-channel MOSFET
to provide negative voltage protection. The 2M resistive
GATE
OVERVOLTAGE, REVERSE-
CURRENT PROTECTION
SENSE
M1
M3
pull-down turns on the MOSFET once V – V
is
IN
GATEP
more than the MOSFET gate threshold voltage. The IN to
SENSE
GATEP Zener protects the MOSFET from gate overvoltage
GATE
by clamping its V to 5.8V when V goes high.
GS
IN
NEGATIVE
VOLTAGE
OVERVOLTAGE, REVERSE-
CURRENT PROTECTION
PROTECTION
R
MOSFET Configurations and Selection
SENSE
M2
M1
M3
SUPPLY
SUPPLY
The LTC4361 can be used with various external MOSFET
configurations (see Figure 3). The simplest configuration
is a single N-channel MOSFET. It has the lowest R
and voltage drop and is thus the most power efficient
solution. When GATE is pulled to ground, the N-channel
MOSFET can isolate OUT from a positive voltage at IN up
OUT
IN
SENSE
GATEP
GATE
DS(ON)
NEGATIVE
VOLTAGE
PROTECTION
M2
OVERVOLTAGE
PROTECTION
M1
R
SENSE
to the BV
of the N-channel MOSFET. However, reverse
OUT
IN
SENSE
DSS
GATEP
GATE
436112 F03
current can still flow from OUT to IN via the parasitic body
diode of the N-channel MOSFET.
Figure 3. MOSFET Configurations
436112fb
9
LTC4361-1/LTC4361-2
applicaTions inFormaTion
MOBILE
DEVICE
WALL ADAPTOR
AC/DC
R
L
IN
IN
IN
I
CABLE
V
IN
C
OUT
10V/DIV
+
CABLE
LOAD
I
CABLE
20A/DIV
436112 F04b
436112 F04a
5µs/DIV
= 10µF
R
= 150mΩ,
= 0.7µH
IN
IN
L
LOAD = 10Ω, C
OUT
Figure 4. 20V Hot-Plug into a 10µF Capacitor
MOBILE
DEVICE
WALL ADAPTOR
AC/DC
M1
Si1470DH
L
IN
R
R
IN
SENSE
IN
OUT
V
IN
10V/DIV
I
CABLE
C
OUT
GATE
+
SENSE OUT
LTC4361
CABLE
LOAD
V
OUT
1V/DIV
IN
GND
I
CABLE
20A/DIV
436112 F05b
436112 F05a
5µs/DIV
R
= 150mΩ,
= 0.7µH, R
IN
IN
L
= 25mΩ
SENSE
= 10µF
LOAD = 10Ω, C
OUT
Figure 5. 20V Hot-Plug into the LTC4361
Input Transients
L and R form an LC tank circuit with any capacitance
IN IN
at IN. If the wall adaptor is powered up first, plugging the
wall adaptor output to IN does the equivalent of applying
a voltage step to this LC circuit. The resultant voltage
overshoot at IN can rise to twice the DC output voltage
of the wall adaptor as shown in Figure 4. Figure 5 shows
the 20V adaptor output applied to the LTC4361. Due to
the low capacitance at the IN pin, the plug-in transient has
been brought down to a manageable level.
Figure 4 shows a typical setup when an AC wall adaptor
charges a mobile device. The inductor L represents the
IN
lumpedequivalentinductanceofthecableandtheEMIfilter
found in some wall adaptors. R is the lumped equivalent
IN
resistance of the cable, adaptor output capacitor ESR and
the connector contact resistance.
436112fb
10
LTC4361-1/LTC4361-2
applicaTions inFormaTion
As the IN pin can withstand up to 80V, a high voltage
N-channel MOSFET can be used to protect the system
against rugged abuse from high transient or DC voltages
85V absolute maximum voltage rating of the LTC4361.
The single, nonrepetitive, pulse of energy (E ) absorbed
AS
by the MOSFET during this avalanche breakdown with a
up to the BV
of the MOSFET. Figure 6 shows a 50V
peak current I is approximated by the formula:
DSS
AS
input plugged into the LTC4361 controlling a 60V rated
2
E
AS
= 0.5 • L • I
IN AS
MOSFET.
ForL =0.7μHandI =4A,thenE =5.6μJ.Thisiswithin
IN
AS
AS
Input transients also occur when the current through the
cableinductancechangesabruptly. Thiscanhappenwhen
theLTC4361turnsofftheN-channelMOSFETrapidlyinan
overvoltage or overcurrent event. Figure 7 shows an input
the I and E capabilities of most MOSFET’s including
AS
AS
the Si1470DH. So in most instances, the LTC4361 can
ride through such transients without a bypass capacitor,
transientvoltagesuppressororotherexternalcomponents
transientafteranovercurrent. ThecurrentinL willcause
IN
at IN. Note that if an IN bypass capacitor is used, the V
IN
V to overshoot and avalanche the N-channel MOSFET to
IN
transients will overshoot less but last longer. If V dips
IN
C
OUT
. Typically, IN will be clamped to a voltage of V
+
OUT
below V
for more than 10µs, the internal latch-off
IN(UVL)
1.3 • (BV
of Si1470DH) = 45V. This is well below the
DSS
latch in the LTC4361-1 could be inadvertently reset.
V
IN
20V/DIV
V
IN
20V/DIV
V
OUT
5V/DIV
V
GATE
V
10V/DIV
OUT
1V/DIV
I
I
CABLE
CABLE
5A/DIV
5A/DIV
436112 F07
436112 F06
2µs/DIV
5µs/DIV
FIGURE 5 CIRCUIT
FDC5612
R
R
= 150mΩ, L = 0.7µH
R
R
= 150mΩ, L = 0.7µH
IN
SENSE
IN
IN
SENSE
IN
= 25mΩ, LOAD = 10Ω, C
= 10µF
OUT
= 25mΩ, LOAD = 10Ω, C
= 10µF
OUT
Figure 6. 50V Hot-Plug into the LTC4361
Figure 7. Overcurrent Turn-Off and Resulting Input Transient
436112fb
11
LTC4361-1/LTC4361-2
applicaTions inFormaTion
Figure 8 shows a particularly severe situation which can
occur in a mobile device with dual power inputs. A 20V
wall adaptor is mistakenly hot-plugged into the 5V device
with the USB input already live. As shown in Figure 9, a
the MOSFET before V
overshoots to a dangerous volt-
OUT
age. A larger C
also helps to lower the ∆V
due to
OUT
OUT
the discharge of the energy in L if the MOSFET BV
is used as an input clamp.
IN
DSS
large current can build up in L to charge up C . When
IN
OUT
Layout Considerations
the N-channel MOSFET shuts off, the energy stored in L
IN
is dumped into C , causing a large 40V input transient.
OUT
Figure 10 shows an example PCB layout for the LTC4361
(TS8 package) with a single N-channel MOSFET (SC70
package) and a 0603 size sense resistor. Keep the traces
to the N-channel MOSFET wide and short. The PCB traces
associated with the power path through the N-channel
MOSFET should have low resistance. Use Kelvin connec-
The LTC4361 limits this to a 1V rise in the output voltage.
If the ∆V
OUT
due to the discharge of the energy in L into
IN
OUT
C
is not acceptable or the avalanche capability of the
MOSFET is exceeded, an additional external clamp such
as the SMAJ24A can be placed between IN and GND. C
OUT
tions to R
for an accurate overcurrent threshold.
is the decoupling capacitor of the protected circuits and
SENSE
its value will largely be determined by their requirements.
Using a larger C
will work with L to slow down the
IN
OUT
dV/dt at OUT, allowing time for the LTC4361 to shut off
V
IN
20V/DIV
R
L
IN
IN
+
–
V
OUT
20V
WALL
ADAPTER
I
CABLE
M1
Si1470DH
5V/DIV
R
SENSE
IN
OUT
V
GATE
10V/DIV
D1
B160
GATE
LTC4361
SENSE
C
OUT
I
CABLE
10A/DIV
LOAD
+
–
436112 F09
IN
OUT
GND
1µs/DIV
5V
USB
R1
100k
FIGURE 8 CIRCUIT
R
= 150mΩ
IN
IN
L
C
= 2µH, R
= 25mΩ, LOAD = 10Ω
SENSE
436112 F08
= 10µF (16V, SIZE 1210)
OUT
Figure 8. Setup for Testing 20V Plugged into 5V System
Figure 9. Overvoltage Protection Waveforms
When 20V Plugged into 5V System
LTC4361
GND
OUT
IN
R
SUPPLY
Si1470DH
SENSE
436112 F10
Figure 10. Layout for N-Channel MOSFET Configuration
436112fb
12
LTC4361-1/LTC4361-2
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DC8 Package
8-Lead Plastic DFN (2mm × 2mm)
(Reference LTC DWG # 05-08-1719 Rev A)
0.70 ±0.05
2.55 ±0.05
0.64 ±0.05
1.15 ±0.05
(2 SIDES)
PACKAGE
OUTLINE
0.25 ±0.05
0.45 BSC
1.37 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.115
TYP
5
8
R = 0.05
TYP
0.40 ±0.10
PIN 1 NOTCH
2.00 ±0.10 0.64 ±0.10
(4 SIDES)
(2 SIDES)
R = 0.20 OR
0.25 × 45°
CHAMFER
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
(DC8) DFN 0409 REVA
4
1
0.23 ±0.05
0.45 BSC
0.75 ±0.05
0.200 REF
1.37 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
436112fb
13
LTC4361-1/LTC4361-2
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
TS8 Package
8-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1637 Rev A)
2.90 BSC
(NOTE 4)
0.40
MAX
0.65
REF
1.22 REF
1.4 MIN
1.50 – 1.75
(NOTE 4)
2.80 BSC
3.85 MAX 2.62 REF
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.22 – 0.36
8 PLCS (NOTE 3)
0.65 BSC
0.80 – 0.90
0.20 BSC
DATUM ‘A’
0.01 – 0.10
1.00 MAX
0.30 – 0.50 REF
1.95 BSC
TS8 TSOT-23 0710 REV A
0.09 – 0.20
(NOTE 3)
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
436112fb
14
LTC4361-1/LTC4361-2
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
01/11 Revised conditions for V
and t in Electrical Characteristics section
3
GATE(CLP)
OFF
Revised GATE Control in Applications Information section
05/12 Added H-grade order information
7
B
2
Change to Electrical Characteristics Input Undervoltage Lockout
3
Added V
specifications
3
IN(OVL)
Change to Electrical Characteristics Overvoltage Hysteresis
Change to Electrical Characteristics GATE Pull-Up and Pull-Down Current
Change to Electrical Characteristics GATE Ramp-Up
3
3
3
Added I
specifications
3
SENSE(IN)
Change to Electrical Characteristics ON Pull-Down Current
Change to Electrical Characteristics IN to GATEP Clamp Voltage
Change to Electrical Characteristics GATEP Resistive Pull-Down
Change to Electrical Characteristics PWRGD Pull-Up Resistance to OUT
Change to Electrical Characteristics GATE On Delay
Change to Electrical Characteristics PWRGD Delay
Replaced GATE Fast Pull-Down Current vs Temperature Curve
Added PCB trace to short pin 3 to pin 5 in Figure 10
Added packaging link
3
3
3
3
3
3
4
12
13, 14
436112fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC4361-1/LTC4361-2
Typical applicaTion
5V System Protected from 24V Power Supplies and Overcurrent
5V System Protected from 24V Power Supplies,
Overcurrent and Reverse Current
FDC6561AN
M1
R
M2
Si1471DH
SENSE
Si3590DV
M1
R
V
0.05Ω
SENSE
OUT
M3
V
IN
V
0.05Ω
5V
OUT
M2
V
5V
IN
5V
0.5A
5V
C
OUT
0.5A
C
10µF
OUT
10µF
GATE
GATE
SENSE
OUT
SENSE
OUT
V
IO
V
IO
LTC4361
LTC4361
5V
5V
IN
IN
R1
1k
R1
1k
GATEP
GATEP
D1
LN1351CTR
D1
LN1351CTR
ON
PWRGD
ON
PWRGD
GND
GND
436112 TA02
436112 TA03
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
LTC2935
LT3008
LT3009
Ultralow Power Supervisor with Eight Pin-Selectable
Thresholds
500nA Quiescent Current, 2mm × 2mm 8-Lead DFN and TSOT-23 Packages
20mA, 45V, 3µA I Micropower LDO
280mV Dropout Voltage, Low I : 3µA, V = 2.0V to 45V, V
= 0.6V to 39.5V;
= 0.6V to 19.5V;
Q
Q
IN
OUT
ThinSOT and 2mm × 2mm DFN-6 Packages
20mA, 3µA I Micropower LDO
280mV Dropout Voltage, Low I : 3µA, V = 1.6V to 20V, V
Q
Q
IN
OUT
ThinSOT and SC-70 Packages
LTC3576/
LTC3576-1
Switching USB Power Manager with USB OTG + Triple Complete Multifunction PMIC: Bi-Directional Switching Power Manager + 3
Step-Down DC/DCs
Bucks + LDO
LTC4090/
LTC4090-5
High Voltage USB Power Manager with Ideal Diode
High Efficiency 1.2A Charger from 6V to 38V (60V Max) Input Charges Single
Controller and High Efficiency Li-Ion Battery Charger Cell Li-Ion Batteries Directly from a USB Port
LTC4098
USB-Compatible Switchmode Power Manager
with OVP
High V : 38V operating, 60V transient; 66V OVP. 1.5A Max Charge Current
IN
from Wall, 600mA Charge Current from USB
LTC4210
LTC4213
Single Channel, Low Voltage Hot Swap™ Controller
Operates from 2.7V to 16.5V, Active Current Limiting, SOT23-6
No R ™ Electronic Circuit Breaker
SENSE
Controls Load Voltages from 0V to 6V. 3 Selectable Circuit Breaker Thresholds.
Dual Level Overcurrent Fault Protection
LT4356
Surge Stopper- Overvoltage/Overcurrent Protection
Regulator
Wide Operation Range: 4V to 80V. Reverse Input Protection to –60V.
Adjustable Output Clamp Voltage
LTC4411
LTC4412
SOT-23 Ideal Diode
2.6A Forward Current, 28mV Regulated Forward Voltage
2.5V to 28V, Low Loss PowerPath™ Controller in
ThinSOT
More Efficient than Diode-ORing, Automatic Switching Between DC Sources,
Simplified Load Sharing
LTC4413-1/
LTC4413-2
Dual 2.6A, 2.5V to 5.5V Fast Ideal Diodes in
3mm × 3mm DFN
130mΩ On Resistance, Low Reverse Leakage Current, 18mV Regulated
Forward Voltage (LTC4413-2 with Overvoltage Protection Sensor)
436112fb
LT 0512 REV B • PRINTED IN USA
16 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2010
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号：
LT4356CDE-1#PBF
LT4356-1 and LT4356-2 - Surge Stopper; Package: DFN; Pins: 12; Temperature Range: 0°C to 70°C
Linear
LT4356CDE-2
LT4356-1 and LT4356-2 - Surge Stopper; Package: DFN; Pins: 12; Temperature Range: 0°C to 70°C
Linear
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