LT5514EFE#PBF [Linear]
LT5514 - Ultralow Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 85°C;
| 型号： | LT5514EFE#PBF |
| 厂家： | 
Linear |
| 描述： | LT5514 - Ultralow Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 85°C 光电二极管 |
| 文件： | 总20页 (文件大小：277K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT5514
Ultralow Distortion IF
Amplifier/ADC Driver with
Digitally Controlled Gain
U
FEATURES
DESCRIPTIO
TheLT®5514isaprogrammablegainamplifier(PGA)with
bandwidth extending from low frequency (LF) to 850MHz.
It consists of a digitally controlled variable attenuator,
followed by a high linearity amplifier. The amplifier is
configured with two identical transconductance amplifi-
ers, hard wired in parallel with individual dedicated enable
pins. When both amplifiers are enabled (Standard mode),
the LT5514 offers an OIP3 of +47dBm (at 100MHz).
Power dissipation can be reduced when a single amplifier
is enabled (Low Power mode). Four parallel digital inputs
control the gain over a 22.5dB range with 1.5dB step
resolution. An on-chip power supply regulator/filter helps
isolatetheamplifiersignalpathfromexternalnoisesources.
■
Output IP3 at 100MHz: 47dBm
■
Maximum Output Power: 21dBm
■
Bandwidth: LF to 850MHz
■
Propagation Delay: 0.8ns
■
Maximum Gain: 33dB
■
Noise Figure: 7.3dB (Max Gain)
■
Gain Control Range: 22.5dB
■
Gain Control Step: 1.5dB
■
Gain Control Settling Time: 500ns
■
Output Noise Floor: –134dBm/Hz (Max Gain)
■
Reverse Isolation: –80dB
Single Supply: 4.75V to 5.25V
■
■
Low Power Mode
Shutdown Mode
■
The LT5514’s open-loop architecture offers stable opera-
tion for any practical load conditions, including peaking-
free AC response when driving capacitive loads, and
excellent reverse isolation.
■
Enable/Disable Time: 1µs
■
Differential I/O Interface
■
20-Lead TSSOP Package
U
APPLICATIO S
The LT5514 may be operated broadband, where the out-
put differential RC time constant sets the bandwidth, or it
may be used as a narrowband driver with the appropriate
output filter.
■
High Linearity ADC Driver
■
IF Sampling Receivers
■
VGA IF Power Amplifier
50Ω Driver
Instrumentation Applications
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
■
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TYPICAL APPLICATIO
Output IP3 vs Frequency
(Standard Mode)
56
53
50
5V
CHOKE
CHOKE
0.1µF
0.1µF
0.1µF
R
OUT
= 200Ω
47
44
41
38
35
IF
AMP
RF
INPUT
IF
BPF
100Ω
LT5514
ADC
R = 100Ω
OUT
5514 TA01
LO
0.1µF
GAIN CONTROL
4 LINES
50
100
FREQUENCY (MHz)
200
0
150
5514 TA02
5514f
1
LT5514
W W
U W
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ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
(Notes 1, 2)
TOP VIEW
Power Supply Voltage (VCC1, VCC2) .......................... 6V
Output Supply Voltage (OUT+, OUT–) ....................... 8V
Control Input Voltage (ENA, ENB, PGAx) .. –0.5V to VCC
Signal Input Voltage (IN+, IN–) ................... –0.5V to 3V
Operating Ambient Temperature Range.. – 40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
ENA
1
2
3
4
5
6
7
8
9
20 ENB
V
19
V
CC2
CC1
LT5514EFE
GND
18 GND
17 GND
GND
+
–
IN
16 OUT
15 OUT
21
–
+
IN
GND
GND
14 GND
13 GND
12 PGA3
11 PGA2
PGA0
PGA1 10
FE PACKAGE
20-LEAD PLASTIC TSSOP
TJMAX = 150°C, θJA = 38°C/W
EXPOSED PAD (PIN 21) IS GND
MUST BE SOLDERED TO PCB
Consult LTC Marketing for parts specified with wider operating temperature ranges.
W
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ODES OF OPERATIO
MODES
ENA
High
High
Low
Low
ENB
High
Low
High
Low
AMP A
On
AMP B
On
LT5514 STATE
1
2
3
4
Full Power (Standard)
Low Power A
Low Power B
Shutdown
Enable Amp A and Amp B
Enable Amp A
On
Off
Off
On
Enable Amp B
Off
Off
Sleep, All Amps Disabled
W W
U
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PROGRA ABLE GAI SETTI GS
POWER GAIN
ATTENUATION STEP
RELATIVE TO MAX GAIN
0dB
PGA0
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
PGA1
High
High
Low
Low
High
High
Low
Low
High
High
Low
Low
High
High
Low
Low
PGA2
PGA3
High
High
High
High
High
High
High
High
Low
Low
Low
Low
Low
Low
Low
Low
STANDARD MODE*
LOW POWER MODE**
30.0dB
1
2
High
High
High
High
Low
Low
Low
Low
High
High
High
High
Low
Low
Low
Low
33.0dB
31.5dB
–1.5dB
28.5dB
3
–3.0dB
30.0dB
27.0dB
4
–4.5dB
28.5dB
25.5dB
5
–6.0dB
27.0dB
24.0dB
6
–7.5dB
25.5dB
22.5dB
7
–9.0dB
24.0dB
21.0dB
8
–10.5dB
–12.0dB
–13.5dB
–15.0dB
–16.5dB
–18.0dB
–19.5dB
–21.0dB
–22.5dB
22.5dB
19.5dB
9
21.0dB
18.0dB
10
11
12
13
14
15
16
19.5dB
16.5dB
18.0dB
15.0dB
16.5dB
13.5dB
15.0dB
12.0dB
13.5dB
10.5dB
12.0dB
9.0dB
10.5dB (Note 3)
7.5dB (Note 3)
*R
OUT
= 200Ω **R
= 400Ω
OUT
5514f
2
LT5514
DC ELECTRICAL CHARACTERISTICS
VCC = 5V, VCCO = 5V, ENA = ENB = 3V, TA = 25°C, unless otherwise
noted. (Note 7) (Test circuits shown in Figures 9 and 10)
SYMBOL PARAMETER
Normal Operating Conditions
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
Supply Voltage (Pins 2, 19)
(Note 4)
4.75
3
5
5
5.25
6
V
V
CC
+
–
+
–
OUT , OUT Output Pin DC Common Mode Voltage OUT , OUT Connected to V
via
OSUP
CCO
Choke Inductors or Resistors (Note 5)
+
–
V
OUT , OUT Pin Instantaneous Voltage with
Respect to GND
Min/Max Limits Apply
2
8
V
OUT
Shutdown DC Characteristics, ENA = ENB = 0.6V
+
–
V
IN , IN Bias Voltage
Max Gain (Note 6)
1.15
1.3
44
1.5
20
V
µA
µA
µA
µA
IN(BIAS)
IL(PGA)
IH(PGA)
OUT
I
I
I
I
PGAO, PGA1, PGA2, PGA3 Input Current
V
V
= 0.6V
= 5V
IN
IN
PGAO, PGA1, PGA2, PGA3 Input Current
20
+
–
OUT , OUT Current
Supply Current
All Gain Settings
20
V
All Gain Settings (Note 4)
100
CC
CC
Enable and PGA Inputs DC Characteristics
V
V
ENA, ENB and PGAx Input Low Voltage
ENA, ENB and PGAx Input High Voltage
PGAO, PGA1, PGA2, PGA3 Input Current
PGAO, PGA1, PGA2, PGA3 Input Current
ENA, ENB Input Current
x = 0, 1, 2, 3
x = 0, 1, 2, 3
0.6
V
V
IL
3
IH
I
I
I
I
V
V
V
= 0.6V
20
30
20
µA
µA
µA
IL(PGA)
IH(PGA)
IL(EN)
IH(EN)
IN
IN
IN
= 3V and 5V
= 0.6V
15
4
ENA, ENB Input Current
V
V
= 3V
= 5V
18
38
µA
µA
IN
IN
100
Standard Mode DC Characteristics, ENA = ENB = 3V
+
–
V
IN , IN Bias Voltage
Max Gain (Note 6)
All Gain Settings (DC)
Max Gain
1.34
33
1.49
108
0.3
1.65
V
Ω
IN(BIAS)
R
Input Differential Resistance
IN
g
Amplifier Transconductance
S
m
+
–
I
I
I
OUT , OUT Quiescent Current
Output Current Mismatch
All Gain Settings, V
= 5V
–
40
47
mA
µA
OUT
OUT
+
All Gain Settings, IN , IN Open
200
OUT(OFFSET)
CC
V
+ V
Supply Current
Max Gain (Note 4)
Min Gain (Note 4)
64
68
75
80
mA
mA
CC1
CC2
I
Total Supply Current
I
+ 2 • I (Max Gain)
OUT
148
174
mA
CC(TOTAL)
CC
Low Power Mode DC Characteristics, ENA = O.6V, ENB = 3V or ENA = 3V, ENB = 0.6V
+
–
V
IN , IN Bias Voltage
Max Gain (Note 6)
All Gain Settings (DC)
Max Gain
1.34
17
1.48
122
0.15
20
1.65
V
Ω
IN(BIAS)
R
Input Differential Resistance
IN
g
Amplifier Transconductance
S
m
+
–
I
I
I
OUT , OUT Quiescent Current
Output Current Mismatch
All Gain Settings, V
= 5V
–
24
mA
µA
OUT
OUT
+
All Gain Settings, IN , IN Open
100
OUT(OFFSET)
CC
V
+ V
Supply Current
Max Gain (Note 4)
Min Gain (Note 4)
34
36
40
43
mA
mA
CC1
CC2
I
Total Supply Current
I
+ 2 • I (Max Gain)
OUT
76
91
mA
CC(TOTAL)
CC
5514f
3
LT5514
AC ELECTRICAL CHARACTERISTICS (Standard Mode)
V
CC = 5V, VCCO = 5V, ENA = ENB = 3V, TA = 25°C, ROUT = 200Ω. Maximum gain specifications are with respect to differential inputs
and differential outputs, unless otherwise noted. (Note 7) (Test circuits shown in Figures 9 and 10)
SYMBOL PARAMETER
Dynamic Performance
CONDITIONS
MIN
TYP
MAX
UNITS
BW
Large-Signal –3dB Bandwidth
All Gain Settings (Note 8)
R
OUT
R
OUT
= 100Ω
LF to 850
LF to 500
MHz
MHz
= 200Ω; L1, L2 = 33nH (Figure 9)
P
Clipping Limited Maximum Sinusoidal
Output Power
All Gain Settings, Single Tone, R
= 150Ω
21
dBm
OUT(MAX)
OUT
f
= 100MHz (Note 10)
IN
g
Amplifier Transconductance
Max Gain, f = 100MHz
0.30
0.21
S
S
m
IN
PGA1 = Low, f = 100MHz
IN
S12
t , t
Reverse Isolation
f
f
= 100MHz (Note 9)
= 400MHz (Note 9)
–92
–78
dB
dB
IN
IN
Step Response Rise and Fall Time
Group Delay
All Gain Settings, 10% to 90%, R
OUT
= 100Ω
500
800
±50
ps
ps
ps
r
f
All Gain Settings, R
= 100Ω
OUT
Group Delay Variation
30MHz to 300MHz Frequency Range,
R
OUT
= 100Ω
PGA Settling Time
500
600
ns
ns
Enable/Disable Time
Distortion and Noise
OIP3
Output Third Order Intercept Point for
PGA0 = High (PGA1, PGA2, PGA3 Any State)
P
P
= 9dBm (Each Tone), 200kHz Tone Spacing
= 100MHz
= 200MHz
OUT
f
IN
f
IN
+47.0
+40.5
dBm
dBm
Output Third Order Intercept Point for
= 9dBm (Each Tone), 200kHz Tone Spacing
OUT
PGA0 = Low (PGA1, PGA2, PGA3 Any State)
f
IN
f
IN
= 100MHz
= 200MHz
+42.0
+37.5
dBm
dBm
HD2
HD3
Second Harmonic Distortion
Third Harmonic Distortion
P
P
= 11dBm (Single Tone), f = 50MHz
–82
–72
dBc
dBc
OUT
OUT
IN
= 11dBm (Single Tone), f = 50MHz
IN
N
FLOOR
Output Noise Floor
(PGAO, PGA2, PGA3 Any State)
PGA1 = High, f = 100MHz
–134
–136
dBm/Hz
dBm/Hz
IN
PGA1 = Low, f = 100MHz
IN
NF
Noise Figure
Max Gain, f = 100MHz
7.4
7.7
dB
dB
IN
–3dB Step, f = 100MHz
IN
Amplifier Power Gain and Gain Step
G
G
G
Maximum Gain
Minimum Gain
Gain Step Size
f
f
f
f
= 20MHz and 200MHz
= 20MHz and 200MHz
= 20MHz and 200MHz
= 20MHz and 200MHz
33
dB
dB
dB
dB
MAX
MIN
IN
IN
IN
IN
10.5
1.5
1.05
1.95
STEP
Gain Step Accuracy
±0.1
Amplifier I/O Impedance (Parallel Values Specified Differentially)
R
Input Resistance
Input Capacitance
Output Resistance
Output Capacitance
f
f
f
f
= 100MHz
= 100MHz
= 100MHz
= 100MHz
108
2.8
3.4
1.9
Ω
pF
IN
IN
IN
IN
IN
IN
C
R
O
kΩ
pF
C
O
5514f
4
LT5514
AC ELECTRICAL CHARACTERISTICS (Low Power Mode)
V
CC = 5V, VCCO = 5V, ENA = 3V, ENB = 0.6V, TA = 25°C, ROUT = 200Ω. Maximum gain specifications are with respect to differential
inputs and differential outputs, unless otherwise noted. (Note 7) (Test circuits shown in Figures 9 and 10)
SYMBOL PARAMETER
Dynamic Performance
CONDITIONS
MIN
TYP
MAX
UNITS
BW
Large-Signal –3dB Bandwidth
All Gain Settings (Note 8),
R
OUT
= 100Ω
LF to 540
16
MHz
dBm
P
Clipping Limited Maximum Sinusoidal
Output Power
All Gain Settings, Single Tone,
= 100MHz (Note 10)
OUT(MAX)
f
IN
g
Amplifier Transconductance
Reverse Isolation
Max Gain, f = 100MHz
0.15
–92
S
m
IN
S12
f
= 100MHz (Note 9)
dB
IN
Distortion and Noise
OIP3
Output Third Order Intercept Point for
PGA0 = High (PGA1, PGA2, PGA3 Any State)
P
f
= 4dBm (Each Tone), 200kHz Tone Spacing,
OUT
= 100MHz
+40
dBm
IN
Output Third Order Intercept Point for
PGA0 = Low (PGA1, PGA2, PGA3 Any State)
P
= 4dBm (Each Tone), 200kHz Tone Spacing,
OUT
= 100MHz
f
+36
–76
–72
dBm
dBc
dBc
IN
HD2
HD3
Second Harmonic Distortion
Third Harmonic Distortion
P
P
= 5dBm (Single Tone), f = 50MHz
IN
OUT
OUT
= 5dBm (Single Tone), f = 50MHz
IN
N
FLOOR
Output Noise Floor
(PGAO, PGA2, PGA3 Any State)
PGA1 = High, f = 100MHz
–138
–140
dBm/Hz
dBm/Hz
IN
PGA1 = Low, f = 100MHz
IN
NF
Noise Figure
Max Gain Setting, f = 100MHz
8.6
dB
IN
Amplifier Power Gain and Gain Step
G
G
G
Maximum Gain
Minimum Gain
Gain Step Size
f
f
f
f
= 20MHz and 200MHz
= 20MHz and 200MHz
= 20MHz and 200MHz
= 20MHz and 200MHz
27
4.5
dB
dB
dB
dB
MAX
MIN
IN
IN
IN
IN
1.05
1.5
1.95
STEP
Gain Step Accuracy
±0.1
Amplifier I/O Impedance
R
Input Resistance
Input Capacitance
Output Resistance
Output Capacitance
f
= 100MHz, Parallel Values Specified
122
2
Ω
pF
IN
IN
Differentially
f = 100MHz, Parallel Values Specified
IN
Differentially
C
IN
R
O
f
= 100MHz, Parallel Values Specified
5
kΩ
pF
IN
Differentially
C
f
= 100MHz, Parallel Values Specified
1.7
O
IN
Differentially
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2: All voltage values are with respect to ground.
Note 3: Default state for open PGA inputs.
Note 7: Specifications over the –40°C to 85°C operating temperature
range are assured by design, characterization and correlation with
statistical process controls. Gain always refers to power gain. Input
matching is assumed. P is the available input power. P
is the power
IN
OUT
into the external load, R , as seen by the LT5514 differential outputs. All
OUT
Note 4: V
and V
(Pins 2 and 19) are internally connected.
CC2
CC1
dBm figures are with respect to 50Ω.
Note 5: External V
is adjusted such that V
output pin common
OSUP
CCO
Note 8: High frequency operation is limited by the RC time constants at
the input and output ports. The low frequency (LF) roll-off is set by I/O
interface choice.
Note 9: Limited by package and board isolation.
Note 10: See “Clipping Free Operation” in the Applications Information
mode voltage is as specified when resistors are used. For choke inductors
or transformer, V = V = 5V typ.
OSUP
CCO
Note 6: Internally generated common mode input bias voltage requires
capacitive or transformer coupling to the signal source.
section. Refer to Figure 7.
5514f
5
LT5514
U W
TYPICAL PERFOR A CE CHARACTERISTICS (Standard Mode) TA = 25°C, VCC = 5V, VCCO = 5V,
ENA = ENB = 3V, control input levels VIL = 0.6V, VIH = 3V unless otherwise noted. (Test circuit shown in Figure 9)
Max Gain Frequency Response
Frequency Response for All Gain
Steps, ROUT = 100Ω
Frequency Response for All Gain
Steps, ROUT = 200Ω
with COUT as Parameter,
ROUT = 200Ω
33
30
27
24
21
18
15
12
9
36
33
30
27
24
21
18
15
12
9
36
33
30
27
24
21
18
15
12
9
C
C
C
C
C
= OPEN
= 2.2pF
= 4.7pF
= 10pF
= 22pF
OUT
OUT
OUT
OUT
OUT
6
6
6
3
3
3
0
0
0
10
100
1000
10
100
1000
10
100
FREQUENCY (MHz)
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
5514 G01
5514 G02
5514 G03
Frequency Response at 3dB
Attenuation Step with COUT as
Parameter, ROUT = 200Ω
Gain Error vs Attenuation at
Gain Error vs Attenuation at
25MHz, ROUT = 200Ω
100MHz, ROUT = 200Ω
36
33
30
27
24
21
18
15
12
9
0.8
0.6
0.8
0.6
25°C
–40°C
85°C
25°C
–40°C
85°C
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–0.2
–0.4
–0.6
–0.8
C
C
C
C
C
= OPEN
= 2.2pF
= 4.7pF
= 10pF
= 22pF
OUT
OUT
OUT
OUT
OUT
6
3
0
12
ATTENUATION STEP (dB)
12
ATTENUATION STEP (dB)
0
3
6
9
15
18
21
0
3
6
9
15
18
21
10
100
FREQUENCY (MHz)
1000
5514 G04
1544 G05
1544 G06
Maximum Gain vs Frequency,
ROUT = 100Ω and 200Ω
Minimum Gain vs Frequency,
ROUT = 100Ω and 200Ω
POUT vs PIN at 50MHz, Max Gain
36
33
30
27
13
10
7
25
20
15
10
5
25°C
–40°C
85°C
25°C
–40°C
85°C
STANDARD
OUT
R
= 200Ω
OUT
R
= 200Ω
= 100Ω
R
= 100Ω
OUT
STANDARD
= 200Ω
R
OUT
LOW POWER
= 200Ω
R
= 100Ω
OUT
R
R
OUT
OUT
0
4
–5
–16 –13
10
100
1000
10
100
1000
–31 –28 –25 –22 –19
–10 –7
FREQUENCY (MHz)
FREQUENCY (MHz)
P
IN
(dBm)
5514 G07
5514 G08
5514 G09
5514f
6
LT5514
U W
TYPICAL PERFOR A CE CHARACTERISTICS (Standard Mode) TA = 25°C, VCC = 5V, VCCO = 5V,
ENA = ENB = 3V, control input levels VIL = 0.6V, VIH = 3V unless otherwise noted. (Test circuit shown in Figure 9)
Harmonic Distortion vs
Minimum Gain vs VCC at 120MHz,
ROUT = 100Ω
Maximum Gain vs VCC at
120MHz, ROUT = 100Ω
Attenuation Step at POUT = 7dBm,
Freq = 50MHz, ROUT = 200Ω
30.4
30.2
30.0
29.8
29.6
29.4
29.2
29.0
7.8
7.6
–72
–75
–78
–81
FIGURE 10 TEST CIRCUIT
HD3
PGA0 = LOW
7.4
7.2
7.0
6.8
6.6
6.4
HD3
PGA0 = HIGH
–40°C
–40°C
25°C
25°C
85°C
HD2
–84
–87
–90
85°C
4.7
4.9
5.1
(V)
5.5
4.7
4.9
5.1
(V)
5.5
4.5
5.3
4.5
5.3
12
ATTENUATION STEP (dB)
18
21
0
3
6
9
15
V
CC
V
CC
5514 G11
5514 G10
5514 G12
Harmonic Distortion vs Attenuation
Step at POUT = 7dBm,
Freq = 50MHz, ROUT = 200Ω
Harmonic Distortion vs POUT at
50MHz, Max Gain, ROUT = 200Ω
Harmonic Distortion vs POUT at
50MHz, Max Gain, ROUT = 100Ω
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
–72
–75
–78
–81
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
HD3
PGA0 = LOW
HD3
HD2
HD3
HD2
HD3
–84
–87
–90
PGA0 = HIGH
HD2
HD5
HD4
HD5
HD4
7
10
–5 –2
1
4
P
13 16 19
12
6
ATTENUATION STEP (dB)
18
21
9
12
0
3
9
15
–3
0
3
6
P
15 18 21
(dBm)
(dBm)
OUT
OUT
5514 G15
5514 G12
5514 G14
NF vs Attenuation Step at
Freq = 100MHz
Output Noise Floor vs Attenuation
Step, Freq = 100MHz, ROUT = 200Ω
Noise Figure vs Frequency
30
27
24
21
18
15
12
9
–133
–134
–135
–136
–137
–138
–139
9.0
8.5
8.0
7.5
7.0
6.5
6.0
FIGURE 10 TEST CIRCUIT
FIGURE 10 TEST CIRCUIT
FIGURE 10 TEST CIRCUIT
1.5dB ATTENUATION STEP
(PGA0 = LOW)
PGA1 = HIGH
PGA1 = LOW
MAX GAIN
3dB ATTENUATION STEP
6
(PGA1 = LOW)
3
0
250 300
0
50 100 150 200
350 400
0
3
6
9
12
15
18
21
0
6
9
12 15 18 21
3
FREQUENCY (MHz)
ATTENUATION STEP (dB)
ATTENUATION STEP (dB)
5514 G16
5514 G17
5514 G18
5514f
7
LT5514
U W
TYPICAL PERFOR A CE CHARACTERISTICS (Standard Mode) Two tones, 200kHz spacing,
TA = 25°C, ENA = ENB = 5V, VCC = 5V, VCCO = 3V, control input levels VIL = 0.6V, VIH = 3V unless otherwise noted. (Test circuit shown
in Figure 10)
OIP3 vs Frequency at PIN = –23dBm
OIP3 vs Frequency at PIN = –23dBm
Max Gain, ROUT = 200Ω
OIP3 vs Frequency at PIN = –23dBm
Max Gain, ROUT = 100Ω
Max Gain and 1.5dB Attenuation
Step, ROUT = 200Ω
57
54
51
57
54
51
57
54
51
25°C
–40°C
85°C
25°C
–40°C
85°C
MAX GAIN
48
45
42
39
36
48
45
42
39
36
48
45
42
39
36
1.5dB
ATTENUATION
STEP
50
100
200
50
100
200
50
100
200
0
150
0
150
0
150
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
5514 G19
5514 G20
5514 G21
OIP3 vs Attenuation Step at
Freq = 100MHz, PIN = –23dB,
ROUT = 200Ω
ICC Shutdown Current vs VCC
,
Total ICC vs Attenuation Step
ENA = ENB = 0.6V
160
155
150
145
140
135
130
49
48
47
46
45
44
43
42
41
70
60
85°C
25°C
50
40
30
20
10
0
85°C
25°C
3dB ATTENUATION STEP
(PGA0 = HIGH)
–40°C
1.5dB ATTENUATION STEP
(PGA0 = LOW)
–40°C
12
ATTENUATION STEP (dB)
0
3
6
9
15
18
21
4.7
4.9
5.1
5.5
0
6
9
12 15 18 21
4.5
5.3
3
ATTENUATION STEP (dB)
INPUT V (V)
CC
1544 G22
5514 G24
5514 G23
Single-Ended Output Current
vs Attenuation Step
VIN(BIAS) vs Attenuation Step
41
40
39
38
1.60
1.55
1.50
1.45
1.40
85°C
25°C
–40°C
25°C
85°C
–40°C
0
6
9
12 15 18 21
3
0
6
9
12 15 18 21
3
ATTENUATION STEP (dB)
ATTENUATION STEP (dB)
5514 G25
5514 G26
5514f
8
LT5514
U W
TYPICAL PERFOR A CE CHARACTERISTICS (Standard Mode) TA = 25°C, VCC = 5V, VCCO = 5V,
ENA = ENB = 3V, control input levels VIL = 0.6V, VIH = 3V unless otherwise noted. Test circuit shown in Figure 10 unless otherwise
noted. Note 1: Subtract 0.75ns calibration delay from output plots to estimate the LT5514 group delay. Note 2: When specified, COUT
is connected differentially across the LT5514 OUT+, OUT– output pins.
Pulse Response vs COUT at Max
Gain. Output Level is 2VP-P into
50Ω External Load
Pulse Response vs Output Level at
Max Gain. Indicated Voltage
Levels are into 50Ω External Load
Pulse Response vs Attenuation,
Output Level is 4VP-P at Max Gain
into 50Ω External Load
C
OUT
= 0.82pF
0pF
C
OUT
0pF
1pF
1.8pF
3.3pF
4.7pF
6.8pf
10pF
11pF
18pF
INPUT
22pF TO
GROUND
EACH
OUTPUT
R
= 255Ω
MATCH
2ns/DIV
5514 G27
2ns/DIV
5514 G28
1ns/DIV
5514 G29
Pulse Response vs Attenuation,
Output Level is 2VP-P at Max Gain
into 50Ω External Load
Pulse Response vs Attenuation,
Output Level is 2VP-P at Max Gain
into 50Ω External Load
R
= 255Ω
R
= 255Ω, C
= 1.8pF
OUT
MATCH
MATCH
1ns/DIV
5514 G30
1ns/DIV
5514 G31
Pulse Response vs Attenuation,
LT5514 Levels are: VIN = 66mVP-P
VOUT = 2VP-P at Max Gain
Pulse Response vs Attenuation,
LT5514 Levels are: VIN = 66mVP-P
VOUT = 4VP-P at Max Gain
,
,
R
= 100Ω
R
= 200Ω
OUT
OUT
FIGURE 9 TEST CIRCUIT
1ns/DIV
FIGURE 9 TEST CIRCUIT
1ns/DIV
5514 G32
5514 G33
5514f
9
LT5514
U W
TYPICAL PERFOR A CE CHARACTERISTICS (Low Power Mode) TA = 25°C, VCC = 5V, VCCO = 5V,
ENA = 3V, ENB = 0.6V or ENA = 0.6V, ENB = 3V, control input levels VIL = 0.6V, VIH = 3V unless otherwise noted. (Test circuit shown in
Figure 10)
OIP3 vs Frequency at Pin = –23dBm,
Harmonic Distortion vs POUT at
50MHz, Max Gain, ROUT = 200Ω
Max Gain and 1.5dB Attenuation
Noise Figure vs Frequency
Step, ROUT = 200Ω
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
10.0
9.5
9.0
8.5
8.0
7.5
7.0
54
51
48
45
42
39
36
33
30
1.5dB ATTENUATION STEP
(PGA0 = LOW)
MAX GAIN
HD3
HD2
MAX GAIN
1.5dB
ATTENUATION
STEP
3dB ATTENUATION STEP
(PGA1 = LOW)
HD5
6
HD4
12
250 300
0
50 100 150 200
350 400
–6
0
3
9
15
–3
100
0
50
150
200
FREQUENCY (MHz)
P
OUT
(dBm)
FREQUENCY (MHz)
5514 G36
5514 G35
5514 G34
Pulse Response vs Output Level at
Max Gain. Indicated Voltage Levels
are into 50Ω External Load
NF vs Attenuation Step at
Freq = 100MHz
Output Noise Floor vs Attenuation
Step, Freq = 100MHz, ROUT = 200Ω
30
27
24
21
18
15
12
9
–136
–137
–138
–139
–140
–141
–142
C
= 0.82pF
OUT
PGA1 = HIGH
PGA1 = LOW
6
3
0
0
3
6
9
12
15
18
21
0
6
9
12 15 18 21
3
2ns/DIV
5514 G39
ATTENUATION STEP (dB)
ATTENUATION STEP (dB)
5514 G37
5514 G38
Single-Ended Output Current
vs Attenuation Step
Total ICC vs VCC
V
IN(BIAS) vs Attenuation Step
80
78
75
73
70
68
65
1.60
1.55
1.50
1.45
1.40
21.0
20.5
20.0
19.5
19.0
85°C
25°C
–40°C
85°C
25°C
–40°C
25°C
85°C
–40°C
0
6
9
12 15 18 21
0
6
9
12 15 18 21
3
0
6
9
12 15 18 21
3
3
ATTENUATION STEP (dB)
ATTENUATION STEP (dB)
ATTENUATION STEP (dB)
5514 G40
5514 G42
5514 G41
5514f
10
LT5514
U
U
U
PI FU CTIO S
ENA (Pin 1): Enable Pin for Amplifier A. When the input
voltage is higher than 3V, amplifier A is turned on. When
the input voltage is less than or equal to 0.6V, amplifier A
is turned off. This pin is internally pulled to ground if not
connected.
Input is high when input voltage is greater than 3V. Input
islowwheninputvoltageislessthanorequalto0.6V. This
pin is internally pulled to ground if not connected.
PGA3 (Pin 12): Amplifier PGA Control Input Pin for 12dB
Attenuation Step (see Programmable Gain table). Input is
high when input voltage is greater than 3V. Input is low
when input voltage is less than or equal to 0.6V. This pin
is internally pulled to ground if not connected.
V
CC1(Pin2):PowerSupply.Thispinisinternallyconnected
toVCC2 (Pin19).Decouplingcapacitors(1000pFand0.1µF
for example) may be required in some applications.
GND (Pins 3, 4, 7, 8, 13, 14, 17, 18): Ground.
IN+ (Pin 5): Positive Signal Input Pin with Internal DC
Bias.
IN– (Pin 6): Negative Signal Input Pin with Internal DC
Bias.
OUT+ (Pin 15): Positive Amplifier Output. A transformer
with center tap tied to VCC or a choke inductor is recom-
mended to source the DC quiescent current.
OUT– (Pin 16): Negative Amplifier Output. A transformer
with center tap tied to VCC or a choke inductor is recom-
mended to source the DC quiescent current.
PGA0 (Pin 9): Amplifier PGA Control Input Pin for the
1.5dB Attenuation Step (see Programmable Gain table).
Input is high when input voltage is greater than 3V. Input
islowwheninputvoltageislessthanorequalto0.6V. This
pin is internally pulled to ground if not connected.
VCC2 (Pin 19): Power Supply. This pin is internally con-
nected to VCC1 (Pin 2).
ENB (Pin 20): Enable Pin for Amplifier B. When the input
voltage is higher than 3V, amplifier B is turned on. When
the input voltage is less than or equal to 0.6V, amplifier B
is turned off. This pin is internally pulled to ground if not
connected.
PGA1 (Pin 10): Amplifier PGA Control Input Pin for the
3dB Attenuation Step (see Programmable Gain table).
Input is high when input voltage is greater than 3V. Input
islowwheninputvoltageislessthanorequalto0.6V. This
pin is internally pulled to ground if not connected.
Exposed Pad (Pin 21): Ground. This pin must be soldered
to the printed circuit board ground plane for good heat
transfer.
PGA2 (Pin 11): Amplifier PGA Control Input Pin for the
6dB Attenuation Step (see Programmable Gain table).
W
BLOCK DIAGRA
LT5514
AMPLIFIER A
+
ATTENUATOR
–
IN
IN
OUT
5
6
16
R
IN
100Ω
+
–
OUT
15
AMPLIFIER B
VOLTAGE REGULATOR
AND BIAS
GAIN CONTROL
LOGIC
ENABLE
CONTROL
GND (3, 4, 7, 8
13, 14, 17, 18)
V
CC1
V
PGA3 PGA2 PGA1 PGA0
12 11 10
ENB
ENA
CC2
21
2
19
9
20
1
5514 F01
Figure 1. Functional Block Diagram
5514f
11
LT5514
W U U
U
APPLICATIO S I FOR ATIO
Circuit Operation
where:
The LT5514 is a high linearity amplifier with high imped-
ance output (Figure 1). It consists of the following
sections:
gm is the LT5514 transconductance = 0.3S in Standard
mode (0.15S in Low Power mode).
RIN is the LT5514 differential input impedance 108Ω
in Standard mode (122Ω in Low Power mode). Input
impedance matching is assumed.
• An input variable attenuator “gain-control” block with
100Ω input impedance
• Two parallel, differential transconductance amplifiers,
each with independent enable inputs
ROUT is the external differential output impedance as
seen by the LT5514’s differential outputs. ROUT should
bedistinguishedfromtheactualloadimpedance,RLOAD
,
• An internal bias block with internal voltage regulator
• A gain control logic block
which will typically be coupled to the LT5514 output by
an impedance transformation network.
The LT5514 amplifier provides amplification with very low
distortion using a linearized open-loop architecture. In
contrast with high linearity amplifiers employing negative
feedback, the LT5514 offers:
The power gain as a function of ROUT is plotted in Figure 2.
The ideal curves are straight lines. The curved lines
indicate the roll-off due to the finite (noninfinite) output
resistance of the LT5514.
45
40
35
30
25
20
15
• Stable operation for any practical load
• A capacitive output reactance (not inductive) that pro-
vides peaking free AC response to capacitive loads
• Exceptional reverse isolation of –100dB at 50MHz and
–78dB at 300MHz (package and board leakage limited)
TheLT5514isatransconductanceamplifieranditsopera-
tion can be understood conceptually as consisting of two
steps: First, the input signal voltage is converted to an
output current. The intermodulation distortion (in dBc) of
the LT5514 output current is determined by the input
signal level, and is almost independent of the output load
conditions. Thus, the LT5514’s input IP3 is also nearly
independent of the output load.
STANDARD MODE
10
LOW POWER MODE
STD WITH R
5
O
LP WITH R
O
0
20
100
1000 2000
R
(Ω)
OUT
5514 F02
Figure 2. Power Gain as a Function of ROUT
Next, the external output load (ROUT) converts the output
current to output voltage (or power). The LT5514’s volt-
The actual available output power (as well as power gain
andOIP3)willbereducedbylossesintheoutputinterface,
consisting of:
age and power gain both increase with increasing ROUT
.
Accordingly, the output power and output IP3 also im-
prove with increasing ROUT. The actual output linearity
performance in the application will thus be set by the
choice of output load, as well as by the output network.
• The insertion loss of the output impedance transforma-
tion network (for example the transformer insertion
loss in Figure 6)
• About –3dB loss if a matching resistor (RMATCH in
Figure 6) is used to provide output load impedance
back-matching (for example when driving transmis-
sion lines)
Maximum Gain Calculation
The maximum power gain (with the 0dB attenuation step)
is:
GPWR(dB) = 10 • log(gm2 • RIN • ROUT
)
5514f
12
LT5514
W U U
APPLICATIO S I FOR ATIO
Input Interface
U
V
OSUP
C3
C1
R1
51Ω
R2
51Ω
R
For the lowest noise and highest linearity, the LT5514
should be driven with a differential input signal. Single-
ended drive will severely degrade linearity and noise
performance.
LOAD
LT5514
+
–
50Ω
IN
–
R
IN
R
R
LOAD
C2
OUT
100Ω
50Ω
IN
+
LT5514 F05
Example input matching networks are shown in Figures 3
and 4.
Figure 5. Output Impedance-Matched
and Capacitively Coupled to a Differential Load
Input matching network design criteria are:
Note: In Figure 5, (choke) inductors may be placed in
parallel with or used to replace resistors R1 and R2, thus
eliminating the DC voltage drop across these resistors.
• DC block the LT5514 internal bias voltage (see Input
Bias Voltage section for DC coupling information)
• MatchthesourceimpedancetotheLT5514,RIN 108Ω
V
OSUP
C1
• Provide well balanced differential input drive (capacitor
C2 in Figure 4)
R
MATCH
255Ω
R
LOAD
50Ω
T2
4:1
LT5514
+
–
(OPTIONAL)
IN
–
•
•
•
• Minimize insertion loss to avoid degrading the noise
figure (NF)
R
IN
R
OUT
100Ω
IN
+
LT5514 F06
R1
C1
LT5514
+
–
50Ω
IN
IN
Figure 6. Output Impedance-Matched and
Transformer-Coupled to a Single-Ended Load
–
R
IN
R2
50Ω
V
C2
SRC
100Ω
+
LT5514 F03
Output network design criteria are:
• Provide DC isolation between the LT5514 DC output
voltage and RLOAD
• ProvideapathfortheoutputDCcurrentfromtheoutput
voltage source VOSUP
Figure 3. Input Capacitively-Coupled to a Differential Source
.
R
T1
1:2
SRC
LT5514
+
–
50Ω
.
IN
IN
–
•
•
•
R
IN
V
SRC
• Provide an impedance transformation, if required, be-
tween the load impedance, RLOAD, and the optimum
100Ω
+
LT5514 F04
C2
0.33µF
ROUT loading.
• Set the bandwidth of the output network.
Figure 4. Input Transformer-Coupled to a Single-Ended Source
• Optional: Provide board output impedance matching
using resistor RMATCH (when driving a transmission
line).
Output Interface
The output interface network provides an impedance
transformationbetweentheactualloadimpedance,RLOAD
andtheLT5514outputloading, ROUT, chosentomaximize
powerorlinearity,ortominimizeoutputnoise,orforsome
other criteria as explained in the following sections.
,
• Use high linearity passive parts to avoid introducing
noninearity.
Note that there is a noise penalty of up to 6dB when using
power delivered by only one output in Figure 5.
Two examples of output matching networks are shown in
Figures 5 and 6 (as implemented in the LT5514 demo
boards).
5514f
13
LT5514
W U U
U
APPLICATIO S I FOR ATIO
Clipping Free Operation
bandwidthand,whenthefrequencyisgreaterthan50MHz,
reduced output power.
The LT5514 is a class A amplifier. To avoid signal distor-
tion, the user must ensure that the LT5514 outputs do not
enterintocurrentorvoltagelimiting.Thefollowingdiscus-
sionappliestostandardmodeoperationatmaximumgain.
Input Bias Voltage
The LT5514 IN+, IN– signal inputs are internally biased to
1.48V common mode when enabled, and to 1.26V in
shutdown mode. These inputs are typically coupled by
means of a capacitor or a transformer to a signal source,
and impedance matching is assumed. In shutdown mode,
the internal bias can handle up to 1µA leakage on the input
coupling capacitors. This reduces the turn-on delay due to
the input coupling RC time constant when exiting shut-
down mode.
To avoid current clipping, the output signal current should
not exceed the DC quiescent current, IOUT = 40mA (typi-
cal). Correspondingly, the maximum input voltage,
V
IN(MAX), is IOUT/gm = 133mV (peak). In power terms,
PIN(MAX) = –10.8dBm (assuming RIN = 108Ω).
To avoid output voltage clipping (due to LT5514 output
stage saturation or breakdown), the single-ended output
voltage swing should stay within the specified limits; i.e.,
2V ≤ VOUT ≤ 8V. For a DC output bias of 5V, the maximum
single ended swing will be 3Vpeak and the maximum
differential swing will be 6Vpeak. The simultaneous onset
of both current and voltage limiting occurs when ROUT
6Vpeak/40mA =150Ω (typ) for a maximum POUT
20.8dBm. This calculation applies for a sinusoidal signal.
For nonsinusoidal signals, use the appropriate crest fac-
tor to calculate the actual maximum power that avoids
output clipping.
If DC coupling to the input is required, the external
common mode bias should track the LT5514’s internal
common mode level. The DC current from the LT5514
inputsshouldnotexceedIIN(SINK) =–400µAandIIN(SOURCE)
= 800µA in Standard mode and half of these values in Low
Power mode.
=
=
Stability Considerations
The LT5514’s open-loop architecture allows it to drive any
practical load. Note that LT5514 gain is proportional to the
load impedance, and may exceed the reverse isolation at
frequencies above 1GHz if the LT5514’s outputs are left
unloaded,withinstabilityastheundesirableconsequence.
Insuchcases, placingaresistivedifferentialload(e.g., 2k)
or a small capacitor at the LT5514 outputs can be used to
limit the maximum gain.
For nonoptimal ROUT values, the maximum available out-
putpowerwillbelowerandcanbecalculated(considering
current limiting for ROUT < 150Ω, and voltage limiting for
ROUT > 150Ω). The result of this calculation is shown in
Figure 7.
The LT5514 input should not be overdriven (PIN
–10dBm). The consequences of overdrive are reduced
>
The LT5514 has about 30GHz gain-bandwidth product.
Hence, attention must be paid to the printed circuit board
layout to avoid output pin to input pin signal coupling (the
evaluation board layout is a good example). Due to the
LT5514’s internal power supply regulator, external supply
decouplingcapacitorstypicallyarenotrequired. Likewise,
decoupling capacitors on the LT5514 control inputs typi-
cally are not needed. Note, however, that the Exposed Pad
ontheLT5514packagemustbesolderedtoagoodground
plane on the PCB.
25
V
= V
= 5V
CCO
CC
CURRENT
LIMIT
VOLTAGE
LIMIT
20
15
10
5
STANDARD MODE
LOW POWER MODE
0
PGA Function, Linearity and NF
20
100
1000 2000
R
(Ω)
OUT
As described in the Circuit Operation section, the LT5514
5514 F07
consists of a variable (step) attenuator followed by a high
Figure 7. Maximum Output Power as a Function of ROUT
5514f
14
LT5514
W U U
APPLICATIO S I FOR ATIO
U
gain output amplifier. The overall gain of the LT5514 is
digitally controlled by means of four gain control pins with
internal pull-down. Minimum gain is programmed when
the gain control pins are set low or left floating. In
shutdown mode, these PGA inputs draw <10µA leakage
current, regardless of the applied voltage.
values. AsolutionisoutlinedintheBandpassApplications
section.
The LT5514 linearity degrades when common mode sig-
nal is present. The input transformer center tap should be
decoupled to ground to provide a balanced input differen-
tial signal and to avoid linearity degradation for high
attenuationsteps.Whenthesignalfrequencyislowerthan
50MHz, and there is significant common mode signal,
then high attenuation settings may result in degraded
linearity.
The6dBand12dBattenuationsteps(PGA2andPGA3)are
implemented by switching the amplifier inputs to an input
attenuator tap. The 3dB attenuation step (PGA1) changes
theamplifiertransconductance.TheoutputIP3isapproxi-
mately independent of the PGA1, PGA2 and PGA3 gain
settings. However, the 1.5dB attenuation step utilizes a
currentsteeringtechniquethatdisablestheinternallinear-
ity compensation circuit, and the OIP3 can be reduced by
as much as 6dB when PGA0 is low. Therefore, to achieve
the LT5514’s highest linearity performance, the PGA0 pin
should be set high.
At signal frequencies below 100MHz, the LT5514’s inter-
nal linearity compensation circuitry may provide “sweet
spots” with very high OIP3, in excess of +60dBm. This
almost perfect distortion correction cannot be sustained
over the full operating temperature range and with varia-
tions of the LT5514 output load (complex impedance
ZOUT). Users are advised to rely on data shown in the
TheLT5514noisefigureis7.3dBinthemaximumgainstate.
Forthe–3dBattenuationsetting,theNFis7.6dB.Thenoise
figure increases in direct proportion to the amount of pro-
grammedgainreductionforthe1.5dB,6dBand12dBsteps.
Typical Performance Characteristics curves to estimate
the dependable linearity performance.
Wideband Applications
Atlowfrequencies, thevalueofthedecouplingcapacitors,
choke inductors and choice of transformer will set the
minimum frequency of operation. Output DC coupling is
possible, but this typically reduces the LT5514’s output
DC bias voltage, and thus the output swing and available
power.
The output noise floor is proportional to the output load
impedance, ROUT. It is almost constant for PGA1 = high
and for any PGA0, PGA2, PGA3 state. When PGA1 = low,
the output noise floor is 2.7dB lower (see Typical Perfor-
mance Characteristics).
Other Linearity Considerations
At high frequencies, the output RC time constants set an
upper limit to the maximum frequency of operation in the
case of the wideband output networks presented so far.
ForexampletheLT5514outputcapacitance,COUT =1.9pF,
and a pure resistive load, ROUT = 200Ω, will set the –3dB
bandwidth to about 400MHz. In an actual application, the
RLOAD • CLOAD product may be even more restrictive. The
use of wideband output networks will not only limit the
bandwidth, but will also degrade linearity because part of
the available power is wasted driving the capacitive load.
LT5514 linearity is a strong function of signal frequency.
OIP3 decreases about 13dB for every octave of frequency
increase above 100MHz.
As noted in the Circuit Operation section, at any given
frequency and input level, the LT5514 provides a current
output with fairly constant intermodulation distortion fig-
ure in dBc, regardless of the output load value. For higher
ROUT values, more gain and output power is available, and
better OIP3 figures can be achieved. However, high ROUT
values are not easily implemented in practice, limited by
theavailabilityofhighratiooutputimpedancetransforma-
tion networks.
The LT5514’s output reactance is capacitive. Therefore
improvedACresponseispossiblebyusingexternalseries
output inductors. When driving purely resistive loads, an
inductor in series with the LT5514 output may help to
achieve maximally flat AC response as exemplified in the
Linearity can also be limited by the output RC time con-
stant (bandwidth limitations), particularly for high ROUT
characterization setup schematic (Figure 9).
5514f
15
LT5514
W U U
U
APPLICATIO S I FOR ATIO
For example, for ROUT = 200Ω, L1, L2 = 33nH results in
500MHz bandwidth.
The LC network is a bandpass filter, a useful feature in
many applications.
The series inductor can extend the application bandwidth,
but it provides no improvement in linearity performance.
A variety of bandpass matching network configurations
are conceivable, depending on the requirements of the
particular application. The design of these networks is
facilitated by the fact that the LT5514 outputs are not
destabilized by reactive loading.
Series inductance may also produce peaking in the AC
response. This can be the case when (high Q) choke
inductors are used in an output interface such as in
Figure 5, and the PCB trace (connection) to the load is too
long. Since the LT5514’s output impedance is relatively
high, the PCB trace acts as a series inductor. The most
direct solution is to shorten the connection lines by
placing the driver closer to the load. Another solution to
flatten the AC response is to place resistance close to the
LT5514 outputs. In this way the connection line behaves
more like a terminated transmission line, and the AC
peaking due to the capacitive load can be removed.
Note that these LC networks may distort the output signal
if their amplitude and phase response exhibit nonlinear
behavior. For example, if resistors R1 and R2 in Figure 5
are replaced with LC resonant tank circuits, then severe
OIP3degradationmayoccur(e.g.,4dBto6dBat200MHz).
Low Output Noise Floor Applications
In some applications the maximum output noise floor is
specified. The LT5514 outputnoise flooris elevated above
the available noise power (–174dBm/Hz into 50Ω) by the
NF+Gain. Consequently, reductionoftheLT5514’spower
gain is the only way to reduce the output noise floor.
Bandpass Applications
For narrow band IF applications, the LT5514’s output
capacitance and the application load capacitance can be
incorporated as part of an LC impedance transformation
network, giving improved linearity performance for signal
frequencies greater than 100MHz. Figure 8 is an example
of such a network.
In fixed gain applications, the LT5514 can be set to 3dB
attenuation relative to maximum gain. As shown in the
Typical Performance Characteristics, this gives a 2.8dB
reduction in the output noise floor with no loss of linearity.
In general, the output noise floor can be reduced by
decreasing ROUT (and hence power gain), at the cost of
reduced OIP3.
The network consists of two parallel resonant LC tank
circuits critically coupled by capacitors C1 and C2. The
ROUT to RLOAD transformation ratio in this particular
implementation is 2. The choice of impedance transfor-
mation ratio is more flexible than in the wideband case.
In some situations, it may be feasible to use two LT5514
parts in parallel. In this case, the effective gm doubles,
NOTE:
C3 + C
C4 + C
= 12pF
= 12pF
LOAD
LOAD
ENA ENB
V
OSUP
C7
0.1µF
V
CC
L5
L6
C1
C8
L3
56nH
56nH
56nH
C3
12pF
0.1µF
T1
LT5514
1:2
+
–
R
IN
–
LOAD
C
C
LOAD
50Ω
R
C6
2.2pF
C5
5.6pF L4
56nH
R
OUT
LOAD
100
DUT
C2
12pF
200Ω
100Ω
R
SRC
IN
+
50Ω
C9
0.33µF
R
LOAD
TC2-1T
V
LOAD
SRC
C4
50Ω
GAIN = 33dB
OIP3 (LOAD) = +41dBm
UP TO 9dBm PER TONE
1dB BANDWIDTH:
f
f
= 130MHz
= 220MHz
L
U
PGA0 PGA1 PGA2 PGA3
5514 F08
Figure 8. Bandpass Output Transformation Network Example
5514f
16
LT5514
W U U
APPLICATIO S I FOR ATIO
U
allowingallimpedancestobescaleddownwardbyafactor
of two. The NF and power gain remain the same in this
case, but the OIP3 increases by 3dB. Then, with a further
reduction of ROUT by a factor of two, the gain and output
noise floor decrease by 3dB, while yielding the same
linearity as for one part. As an added benefit, two LT5514
parts in parallel can drive an ROUT reduced by a factor of
four, thus relaxing or eliminating the need in some cases
for an output impedance transformation network.
refers to circuit operation with only a single block enabled.
An amplifier in Low Power mode will have the same basic
characteristics as in Standard mode (both gain blocks
enabled),exceptthatthegm decreasesfrom0.3Sto0.15S,
and the maximum output current is halved. In Low Power
mode, the standard LT5514 evaluation board will produce
about6dBlessgain,(becausetheLT5514’sgm isreduced,
while RIN and ROUT are the same) and 6dB lower OIP3.
LT5514 Characterization
Low Power Mode
The LT5514’s typical performance data are based on the
test circuits shown in Figures 9 and 10. Figure 9 does not
necessarily reflect the use of the LT5514 in an actual
application. (For that, see the Application Boards section.)
As described in the Circuit Operation section, the LT5514
consists of two parallel gain blocks. These blocks are in-
dependently enabled or disabled. “Low Power mode”
ENA ENB
V
V
OSUP
CC
C4
C3
4.7µF
C2
R1
R1
0.1µF
R10
R9
0.1µF
25Ω 25Ω
C1
35.7Ω
35.7Ω
0.33µF
C
OUT
C7
47nF
C5
47nF
L1
R3
37.4Ω
R7
(OPT)
(OPT)
LT5514
T1
1:1
35.7Ω
T1
1:1
+
IN
–
DUT
C8
47nF
C6
47nF
R
R
L2
(OPT)
LOAD
R8
OUT
R4
37.4Ω
50Ω
35.7Ω
–
R
50Ω
SRC
IN
+
C
ETC-1-
1-13
ATT =
7.7dB
ETC-1-
1-13
OUT
R5
R6
(OPT)
V
51k 51k
SRC
R
R3, R4 ATT
OUT
100Ω 37.4Ω 9dB
200Ω 87.4Ω 12dB
V
CCO
PGA0 PGA1 PGA2 PGA3
MONITOR
5514 F09
Figure 9. Characterization Board (Simplified Schematic)
V
CC
C2
ENA
ENB
20
V
OSUP
0.1µF
1
2
3
4
5
6
7
8
9
C4
0.1µF
C3
4.7µF
ENA
ENB
V
CC2
GND
IF
19
18
17
16
15
14
13
12
11
V
CC1
OUT
IF
IN
T2
4:1
T1
1:2
GND
GND
LT5514
GND
•
•
•
+
–
R
LOAD
IN
IN
OUT
OUT
R
R
MATCH
OUT
50Ω
–
+
255Ω
100Ω
GND
GND
PGA0
PGA1
GND
GND
PGA3
PGA2
C1
0.47µF
J2
0
J1
0
TC4-1W
TC2-1T
10
PGA0 PGA1
PGA2 PGA3
TRANSFORMER DEMO BOARD
5514 F10
Figure 10. Output Transformer Application Board (Simplified Schematic)
5514f
17
LT5514
W U U
U
APPLICATIO S I FOR ATIO
Rather, it represents a compromise that most accurately
measures the actual operation of the part by itself,
undistortedbytheartifactsoftheimpedancetransformation
network, or by external bandwidth limiting factors. Balun
transformers are used to interface with single-ended test
equipment. Input and output resistive attenuators (not
shown) provide broadband I/O impedance control. The
L1, L2 inductors are selected for maximally flat AC output
response. COUT (normally open) shows the placement of
capacitive loading when this is specified as a
characterization variable. The VCCO monitor pin allows
setting the output DC level (5V typical) by adjusting
in that case, T1 should be changed to a 1:1 center-tap
transformer to preserve 50Ω input matching. The demo
board is shipped with optional output back-matching
resistor RMATCH = 255Ω. This results in a net output load,
ROUT = 100Ω, presented to the LT5514.
The Output Transformer Application Board (Figure 10) is
one example of an output impedance transformation
(T2 transformer). For the Typical Performance Character-
istics curves, all linearity tests are performed on this
board. By removing RMATCH, the performance with ROUT
= 200Ω can be evaluated (provided the lack of impedance
back-matching is suitably remedied). Measured OIP3 for
bothcases,ROUT=100Ωand200Ω,isshowninFigure12.
voltage VOSUP
.
Application (Demo) Boards
58
DUT R
= 255Ω
MATCH
BOARD R
= 255Ω
MATCH
55
52
49
46
43
40
37
34
The LT5514 demo boards are provided in the versions
shown in Figure 10 (with output transformer) and Fig-
ure 11 (without output transformer). All I/O signal ports
are matched to 50Ω. Moreover, 1k resistors (not shown)
connect all six control pins (ENA, ENB, PGA0, PGA1,
PGA2, PGA3) to VCC, such that the LT5514 is shipped in
maximum gain state and with both amplifier blocks en-
abled (Standard mode).
DUT R
= OPEN
MATCH
BOARD R
= OPEN
MATCH
The gain setting can be changed by connecting the control
pins to ground. Test points (TP1, TP2, TP3) are provided
to monitor the input and output DC bias voltage. Jumper
J1 can be removed when differential input is desired, but
100
FREQUENCY (MHz)
0
50
150
200
5514 F12
Figure 12. Typical OIP3 for Transformer Board
V
CC
ENA
ENB
20
C2
V
0.1µF
OSUP
1
2
3
4
5
6
7
8
9
C4
0.1µF
C3
4.7µF
ENA
ENB
V
CC2
GND
R1
R2
IF
OUT
19
18
17
16
15
14
13
12
11
50Ω 50Ω
V
IF
IN
CC1
T1
1:2
GND
GND
LT5514
GND
+
–
C5
47nF
R
LOAD
IN
IN
OUT
OUT
R
OUT
100Ω
–
+
50Ω
GND
GND
PGA0
PGA1
GND
GND
PGA3
PGA2
C1
0.47µF
J1
0
TC2-1T
J2
0PEN
C6
47nF
10
DIFFERENTIAL OUTPUT
RESISTIVE DEMO BOARD
PGA0 PGA1
PGA2 PGA3
5514 F11
Figure 11. Wideband Differential Output Application Board (Simplified Schematic)
5514f
18
LT5514
W U U
APPLICATIO S I FOR ATIO
U
At high frequency, the difference between the top and
bottom curves in Figure 12 is simply power loss. Starting
from the LT5514 intrinsic performance at ROUT = 200Ω
(top curve), the next lower curve takes into account the
transformer insertion loss. The next curve below this
shows the LT5514 OIP3 with ROUT = 100Ω. The bottom
curve in the plot includes the effects of transformer
insertion loss, with ROUT = 100Ω, and the additional effect
The Wideband Differential Output Application Board (Fig-
ure 11) is an example of direct coupling (no transformer)
to the load, and has wider output bandwidth. This board
gives direct access to the LT5514’s output pins, and was
used for stability tests. Higher VOSUP (7V) is required to
compensate for the DC voltage drop on R1 and R2. Use
TP2, TP3 to monitor the actual LT5514 output bias volt-
age. ByreplacingR1andR2withinductors, thisboardcan
operate with a 5V supply. However, this may limit the
minimum signal frequency. For example, an 820nH choke
inductor will limit the lowest signal frequency to 40MHz.
of loss due to RMATCH
.
The transformer board can provide a differential output
when Jumper J2 is removed.
U
PACKAGE DESCRIPTIO
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation CB
6.40 – 6.60*
(.252 – .260)
3.86
(.152)
3.86
(.152)
20 1918 17 16 15 14 1312 11
6.60 ±0.10
2.74
(.108)
4.50 ±0.10
6.40
(.252)
BSC
2.74
(.108)
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
5
7
8
1
2
3
4
6
9 10
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
FE20 (CB) TSSOP 0204
0.195 – 0.30
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
5514f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LT5514
RELATED PARTS
PART NUMBER DESCRIPTION
Infrastructure
COMMENTS
LT5511
LT5512
LT5515
LT5516
LT5517
LT5519
High Linearity Upconverting Mixer
RF Output to 3GHz, 17dBm IIP3, Integrated LO Buffer
DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
20dBm IIP3, Integrated LO Quadrature Generator
21.5dBm IIP3, Integrated LO Quadrature Generator
21dBm IIP3, Integrated LO Quadrature Generator
DC-3GHz High Signal Level Downconverting Mixer
1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator
0.8GHz to 1.5GHz Direct Conversion Quadrature Demodulator
40MHz to 900MHz Quadrature Demodulator
0.7GHz to 1.4GHz High Linearity Upconverting Mixer
17.1dBm IIP3 at 1GHz, Integrated RF Output Transformer with 50Ω
Matching, Single-Ended LO and RF Ports Operation
LT5520
LT5522
1.3GHz to 2.3GHz High Linearity Upconverting Mixer
15.9dBm IIP3 at 1.9GHz, Integrated RF Output Transformer with 50Ω
Matching, Single-Ended LO and RF Ports Operation
600MHz to 2.7GHz High Signal Level Downconverting Mixer
4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB,
50Ω Single-Ended RF and LO Ports
RF Power Detectors
LT5504
800MHz to 2.7GHz RF Measuring Receiver
80dB Dynamic Range, Temperature Compensated,
2.7V to 5.25V Supply
LTC®5505
LTC5507
LTC5508
LTC5509
LTC5530
LTC5531
LTC5532
RF Power Detectors with >40dB Dynamic Range
100kHz to 1000MHz RF Power Detector
300MHz to 7GHz RF Power Detector
300MHz to 3GHz, Temperature Compensated, 2.7V to 6V Supply
100kHz to 1GHz, Temperature Compensated, 2.7V to 6V Supply
44dB Dynamic Range, Temperature Compensated, SC70 Package
36dB Dynamic Range, Low Power Consumption, SC70 Package
300MHz to 3GHz RF Power Detector
300MHz to 7GHz Precision RF Power Detector
300MHz to 7GHz Precision RF Power Detector
300MHz to 7GHz Precision RF Power Detector
Precision V
Precision V
Precision V
Offset Control, Shutdown, Adjustable Gain
Offset Control, Shutdown, Adjustable Offset
Offset Control, Adjustable Gain and Offset
OUT
OUT
OUT
Low Voltage RF Building Blocks
LT5500
LT5502
1.8GHz to 2.7GHz Receiver Front End
1.8V to 5.25V Supply, Dual-Gain LNA, Mixer, LO Buffer
400MHz Quadrature IF Demodulator with RSSI
1.8V to 5.25V Supply, 70MHz to 400MHz IF, 84dB Limiting Gain,
90dB RSSI Range
LT5503
LT5506
LT5546
1.2GHz to 2.7GHz Direct IQ Modulator and
Upconverting Mixer
1.8V to 5.25V Supply, Four-Step RF Power Control,
120MHz Modulation Bandwidth
500MHz Quadrature IF Demodulator with VGA
1.8V to 5.25V Supply, 40MHz to 500MHz IF, –4dB to 57dB
Linear Power Gain, 8.8MHz Baseband Bandwidth
500MHz Ouadrature IF Demodulator with
VGA and 17MHz Baseband Bandwidth
17MHz Baseband Bandwidth, 40MHz to 500MHz IF, 1.8V to 5.25V
Supply, –7dB to 56dB Linear Power Gain
5514f
LT/TP 0504 1K • PRINTED IN THE USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2004
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