LT6350IMS8#PBF_技术文档

LT6350

Low Noise

Single-Ended to Differential

Converter/ADC Driver

FeaTures

DescripTion

The LT^®6350 is a rail-to-rail input and output low noise

single-endedtodifferentialconverter/ADCdriverfeaturing

fast settling time. It converts a high or low impedance,

single-ended input signal to a low impedance, balanced,

differential output suitable for driving high performance

differentialsuccesiveapproximationregister(SAR)ADCs.

Thetwoopamptopologyfeaturesverylownoiseopamps,

that can support SNR >110dB in a 1MHz bandwidth.

n

Rail-to-Rail Input and Outputs

n

Fast Settling Time: 240ns, 0.01%, 8V Output Step

P-P

n

1.9nV/√Hz Input-Referred Op Amp Noise

n

High Impedance Input

–3dB Bandwidth: 33MHz

2.7V to 12V Supply Operation

n

No External Gain Resistors Required

4.8mA Supply Current

Low Power Shutdown

n

Theinputopampistrimmedforconstantlowinput-referred

n

Low Distortion (HD2/HD3): –102dBc/–97dBc at

voltage offset over the input range to prevent V steps

OS

100kHz, V

= 4V

OUTDIFF

P-P

from degrading distortion.

n

Low Offset Voltage: 400µV Max

High DC Linearity: < 1LSB, 16-Bit, 8V

Low Input Current Noise: 1.1pA/√Hz

Onasingle5Vsupply,theoutputscanswingfrom55mVto

4.945V. With the addition of a negative supply, the LT6350

canswingfrom0Vto4.945V.Outputcommonmodevoltage

is set by applying a voltage to the +IN2 pin.

P-P

3mm × 3mm 8-Pin DFN and 8-Lead MSOP Packages

applicaTions

TheLT6350draws4.8mAfroma5Vsupplyandconsumes

just 60µA in shutdown mode.

n

16-Bit and 18-Bit SAR ADC Drivers

n

Single-Ended to Differential Conversion

The LT6350 is available in a compact 3mm × 3mm, 8-pin

leadless DFN package and also in an 8-pin MSOP package

and operates over a –40°C to 125°C temperature range.

n

Differential Line Driver

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Protected by U.S. Patents including 5610557, 6344773.

Typical applicaTion

20kHz Sine Wave,

–1dBFS 8192-Point FFT

ADC Driver: Single-Ended Input to Differential Output

0

–10

–20

–30

–40

–50

–60

–70

5V

+

–

V

= 5V, V = –5V

= 7.3V

= 2.05V

OUTDIFF

P-P

249Ω

0.1µF

+IN2

SNR = 94.9dB

V

SINAD = 93.8dB

IN

+

5V

+

^{0V TO 4V}–

IN1 SHDN

V

OUT2

THD = –100.2dB

SFDR = 102.2dB

+

–

A

IN

–80

–90

2200pF

LTC2393-16

+

–

+

LT6350

A

IN

–100

–110

–120

–130

–140

–

+

–

V

OUT1

249Ω

IN2

IN1

0

100

200

300

400

500

FREQUENCY (kHz)

499Ω

0.1µF

6350 TA01

6350 TA02

2V

–5V

6350fc

1

For more information www.linear.com/LT6350

LT6350

(Note 1)

absoluTe MaxiMuM raTings

Total Supply Voltage

Speciﬁed Temperature Range

+

–

(V – V )............................................................12.6V

Input Current (Note 2).......................................... 20mA

Output Short-Circuit Current Duration

(Note 5)..................................................–40°C to 125°C

Maximum Junction Temperature........................... 150°C

Storage Temperature Range...................–65°C to 150°C

Lead Temperature (Soldering, 10 sec)

(Note 3)............................................................ Indeﬁnite

Operating Temperature Range

(Note 4)..................................................–40°C to 125°C

MSOP Package Only ............................................. 300°C

pin conFiguraTion

TOP VIEW

–IN1

+IN2

1

2

3

4

8

7

6

5

+IN1

–IN1

+IN2

V

1

2

3

4

8 +IN1

SHDN

9

7 SHDN

+

–

+

V

6 V

5 OUT2

OUT1

OUT2

MS8 PACKAGE

8-LEAD PLASTIC MSOP

= 150°C, θ = 250°C/W

DD PACKAGE

8-LEAD (3mm × 3mm) PLASTIC DFN

T

JMAX

JA

T

= 150°C, θ = 43°C/W

JA

JMAX

–

UNDERSIDE METAL CONNECTED TO V

orDer inForMaTion

LEAD FREE FINISH

LT6350CDD#PBF

LT6350IDD#PBF

LT6350HDD#PBF

LT6350CMS8#PBF

LT6350IMS8#PBF

LT6350HMS8#PBF

TAPE AND REEL

PART MARKING*

LFJT

PACKAGE DESCRIPTION

SPECIFIED TEMPERATURE RANGE

LT6350CDD#TRPBF

LT6350IDD#TRPBF

LT6350HDD#TRPBF

LT6350CMS8#TRPBF

LT6350IMS8#TRPBF

LT6350HMS8#TRPBF

0°C to 70°C

8-Lead (3mm × 3mm) Plastic DFN

8-Lead Plastic MSOP

LFJT

–40°C to 85°C

–40°C to 125°C

0°C to 70°C

LFJT

LTFJV

8-Lead Plastic MSOP

–40°C to 85°C

–40°C to 125°C

LTFJV

8-Lead Plastic MSOP

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

6350fc

2

For more information www.linear.com/LT6350

LT6350

elecTrical characTerisTics ^Theldenotes speciﬁcations that apply over the full speciﬁed temperature range,

otherwise speciﬁcations are at T_A= 25°C. Unless noted otherwise, V⁺= 5V, V^–= 0V, V_+IN1= V2 = Mid-Supply, V_SHDN= V⁺, R_L= OPEN, R_F=

SHORT, R_G= OPEN. V_Sis deﬁned as (V⁺– V^–). V_OUTCMis deﬁned as (V_OUT1+ V_OUT2)/2. V_OUTDIFFis deﬁned as (V_OUT1– V_OUT2). See Figure 1.

SYMBOL

PARAMETER

CONDITIONS

V = 5V

MIN

TYP

0.1

MAX

UNITS

V

Differential Input-Referred Offset Voltage

OSDIFF

S

V

+IN1

V

+IN1

V

+IN1

= V2 = Mid-Rail

–0.4

–0.45

–0.77

0.4

0.45

1.36

mV

–

+

= V2 = V +1.5V to V – 0.1V

–

l

V = 3V

S

+IN1

–

+

V

= V2 = V +1.5V to V – 0.1V

–0.45

–0.8

0.45

1.36

mV

V = 10V

S

+IN1

–

+

V

= V2 = V +1.5V to V – 0.1V

–0.52

–0.78

0.52

1.48

mV

V

Input Offset Voltage, Op Amp 1

V = 5V

OS1

S

–

+

l

V

= V +1.5V to V

–0.35

–1.5

0.08

0.28

0.68

1.5

mV

+IN1

+

= V to V

V = 3V

S

+IN1

–

l

V

= V +1.5V to V

= V to V

–0.35

–1.5

0.08

0.32

0.68

1.5

mV

+

V = 10V

S

+IN1

–

l

V

= V +1.5V to V

= V to V

–0.68

–1.5

0.07

0.28

0.68

1.5

mV

+

V

Input Offset Voltage, Op Amp 2 (Note 6)

/∆T Differential Offset Voltage Drift

V = 3V, 5V, 10V

+IN1

OS2

S

–

+

l

V

= V2 = V +1.5V to V – 0.1V

–1.0

0.1

0.66

mV

–

+

l

∆V

V

+IN1

V

+IN1

= V2 = V +1.5V

5

5.5

µV/°C

OSDIFF

= V2 = V –0.1V

l

I

Input Bias Current, Op Amp 1

(at +IN1, –IN1)

V

= Mid-Supply

–6.8

–8.0

–1.2

–3.0

1.4

µA

B1

+IN1

–

= V

+

= V

2.6

l

Input Offset Current, Op Amp 1

(at +IN1, –IN1)

V

+IN1

V

+IN1

V

+IN1

= Mid-Supply

–1

0.1

1

µA

OS1

–

+

= V

l

I

Input Bias Current, Op Amp 2 (at +IN2)

Input Offest Current, Op Amp 2

V

= V2 = Mid-Supply

2.5

0.1

1.9

1.1

2.1

1

4.4

µA

+IN2

+IN1

V2 = Mid-Supply

OS2

e

Input Voltage Noise Density, Op Amp 1

Input Current Noise Density, Op Amp 1

Input Voltage Noise Density, Op Amp 2

Input Current Noise Density, Op Amp 2

Differential Output Noise Voltage Density

Op Amp Input Referred

nV/√Hz

pA/√Hz

nV/√Hz

pA/√Hz

nV/√Hz

n1

i

n1

e

Op Amp Input Referred

n2

i

n2

e

Total Output Noise Including Both Op Amps

and On-Chip Resistors. Input Shorted. f = 10kHz

8.2

n(OUT)

Input Noise Voltage

0.1Hz to 10Hz

300

110

nV

P-P

SNR

Output Signal-to-Noise Ratio

Input Voltage Range, +IN1

Input Voltage Range, +IN2

Input Resistance

V

= 8V , 1MHz Noise Bandwidth

dB

OUTDIFF

P-P

–

+

l

V

Guaranteed by CMRR1

Guaranteed by CMRR2

Single-Ended Input at +IN1

V

+IN1

+IN2

–

+

V +1.5V

V –0.1V

R

IN

4

MΩ

6350fc

3

For more information www.linear.com/LT6350

LT6350

elecTrical characTerisTics ^Theldenotes speciﬁcations that apply over the full speciﬁed temperature range,

otherwise speciﬁcations are at T_A= 25°C. Unless noted otherwise, V⁺= 5V, V^–= 0V, V_+IN1= V2 = Mid-Supply, V_SHDN= V⁺, R_L= OPEN, R_F=

SHORT, R_G= OPEN. V_Sis deﬁned as (V⁺– V^–). V_OUTCMis deﬁned as (V_OUT1+ V_OUT2)/2. V_OUTDIFFis deﬁned as (V_OUT1– V_OUT2). See Figure 1.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

C

Input Capacitance

Single-Ended Input at +IN1

1.8

pF

IN

–

+

CMRR1

Common Mode Rejection Ratio, Op Amp 1 V = 5V, V

= V

= V +1.5V to V

82

77

72

67

94

88

82

dB

S

+IN1

–IN1

l

V = 5V, V

= V +1.5V to V

S

–

+

V = 5V, V

= V to V

S

–

V = 3V, V

= V to V

S

–

+

l

CMRR2

PSRR

Common Mode Rejection Ratio, Op Amp 2 V = 5V, V

= V2 = V +1.5V to V –0.1V

93

85

96

118

110

118

dB

S

+IN1

V = 3V, V

= V2 = V +1.5V to V –0.1V

S

–

+

V = 10V, V

= V2 = V +1.5V to V –0.1V

+IN1

S

l

Power Supply Rejection Ratio

(∆V /∆V

V = 2.7V to 12V

S

80

108

dB

)

OSDIFF

S

l

V

Supply Voltage (Note 7)

2.7

50

12

V

S

BAL

Output Balance (∆V

(Note 8)

/∆V

)

V = 2V

OUTDIFF

68

2

dB

OUTDIFF

OUTCM

l

GAIN

Closed-Loop Gain

∆(V

–V2) = 4V

V/V

+IN1

(∆V

/∆(V

–V2))

OUTDIFF

+IN1

l

GAIN

Closed-Loop Gain Error

–0.6

0.08

3

0.6

%

ERR

∆GAIN /∆T Closed-Loop Gain Error Drift

ppm/°C

ERR

+

–

INL

DC Linearity (Note 9)

V = 5V, V = 0V

230

125

1

µV

LSB

V = 5V, V = –2V

+

V = 5V, V– = –2V, 16-Bit, 8V

P-P

R

Internal Resistors

1000

Ω

INT

+

l

V

Output Swing to V , Either Output

(Note 10)

No Load

Sourcing 12.5mA

55

360

170

750

mV

OH

–

l

V

Output Swing to V , Either Output

No Load

Sourcing 12.5mA

55

260

170

460

mV

OL

(Note 10)

I

Output Short-Circuit Current

V

+IN1

= Mid-Rail 200mV, V

= Mid-Rail

SC

–IN1

V = 5V

27

15

45

40

mA

S

l

V = 5V

S

V = 3V

S

–

l

V

SHDN Input Logic Low

SHDN Input Logic High

SHDN Pin Current

V = 2.7V to 12V

V + 0.3

V

IL

S

–

V = 2.7V to 12V

V + 2.0

IH

S

+

l

I

SHDN = V

–1

1

µA

SHDN

–

SHDN = V

–45

–20

4.5

l

I

Supply Current

V = 3V

8.1

5.8

mA

S

V = 5V

S

l

V = 5V

4.8

5.4

8.3

S

V = 10V

10.4

S

l

I

Supply Current in Shutdown

V = 3V, V

= V

SHDN

43

60

70

220

240

260

µA

S(SHDN)

S

SHDN

IL

V = 5V, V

S

V = 10V, V

= V

IL

S

GBW

BW

Gain-Bandwidth Product

Frequency = 1MHz

Op Amp 1 (Noninverting)

Op Amp 2 (Inverting)

85

MHz

115

Differential –3dB Small-Signal Bandwidth

V

= 100mV

23

19

MHz

OUTDIFF

P-P

l

33

6350fc

4

For more information www.linear.com/LT6350

LT6350

elecTrical characTerisTics ^Theldenotes speciﬁcations that apply over the full speciﬁed temperature range,

otherwise speciﬁcations are at T_A= 25°C. Unless noted otherwise, V⁺= 5V, V^–= 0V, V_+IN1= V2 = Mid-Supply, V_SHDN= V⁺, R_L= OPEN, R_F=

SHORT, R_G= OPEN. V_Sis deﬁned as (V⁺– V^–). V_OUTCMis deﬁned as (V_OUT1+ V_OUT2)/2. V_OUTDIFFis deﬁned as (V_OUT1– V_OUT2). See Figure 1.

SYMBOL

PARAMETER

CONDITIONS

V = 8V

OUTDIFF

MIN

TYP

1.6

56

MAX

UNITS

MHz

pF

FPBW

Full-Power Bandwidth (Note 11)

Capacitive Load Drive, 20% Overshoot

Differential Slew Rate

P-P

C

No Series Output Resistors

L

SR

OUT1 Rising (OUT2 Falling)

OUT1 Falling (OUT2 Rising)

48

41

V/µs

10kHz Distortion

V = 5V, V

= 4V , R = 2kΩ

OUTDIFF P-P L

S

HD2

HD3

2nd Harmonic

3rd Harmonic

–115

dBc

100kHz Distortion

V = 5V, V

= 4V , R = 2kΩ

OUTDIFF P-P L

S

HD2

HD3

2nd Harmonic

3rd Harmonic

–102

–97

dBc

1MHz Distortion

V = 5V, V

= 4V , R = 2kΩ

OUTDIFF P-P L

S

HD2

HD3

2nd Harmonic

3rd Harmonic

–86

–75

dBc

t

Settling Time to a 4V Input Step

0.1%

0.01%

0.0015% ( 1LSB, 16-Bit, Falling Edge)

200

240

350

ns

S

–

+

t

Overdrive Recovery Time

Turn-On Time

+IN1 to V and V

200

400

ns

OVDR

ON

V

SHDN

V

SHDN

= 0V to 5V

Turn-Off Time

= 5V to 0V

OFF

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 6: V

is measured as the total output common mode voltage offset

OS2

(error between output common mode and voltage at V2). V

the combined effects of op amp 2’s voltage offset, I , I and mismatch

between on-chip resistors and the 499Ω external resistor, R1 (See Figure 1).

includes

OS2

B

OS

Note 2: Inputs are protected by diodes to each supply. Additionallly,

op amp inputs +IN1, –IN1 and +IN2 are protected by back-to-back diodes

across the op amp inputs. If inputs are taken beyond the supplies or if

either op amp’s differential input voltage exceeds 0.7V, the input current

must be limited to less than 20mA.

Note 7: Supply voltage range is guaranteed by the power supply rejection

ratio test.

Note 8: Output balance is calculated from gain error and gain as:

GAIN

GAIN_ERR

BAL =

Note 3: A heat sink may be required to keep the junction temperature

below the absolute maximum rating when the output is shorted indeﬁnitely.

Note 9: DC linearity is measured by measuring the differential output for

Note 4: The LT6350C/LT6350I are guaranteed functional over the

temperature range of –40°C to 85°C. The LT6350H is guaranteed

functional over the temperature range of –40°C to 125°C.

each input in the set V

= 0.5V, 2.5V, 4.5V, and calculating the maximum

+IN1

deviation from the least squares best ﬁt straight line generated from the

three data points.

Note 5: The LT6350C is guaranteed to meet speciﬁed performance from

0°C to 70°C. The LT6350C is designed, characterized and expected to

meet speciﬁed performance from –40°C to 85°C, but is not tested or

QA sampled at these temperatures. The LT6350I is guaranteed to meet

speciﬁed performance from –40°C to 85°C. The LT6350H is guaranteed to

meet speciﬁed performance from –40°C to 125°C.

Note 10: Output voltage swings are measured between the output and

power supply rails.

Note 11: Full- power bandwidth is calculated from the slew rate.

FPBW = SR/2�V .

P

6350fc

5

For more information www.linear.com/LT6350

LT6350

Typical perForMance characTerisTics

T_A= 25°C, V⁺= 5V, V^–= 0V, V_+IN1= V2 = Mid-Supply, V_SHDN= V⁺, R_F= SHORT, R_G= OPEN, R_L= OPEN. See Figure 1.

Offset Voltage vs Input Common

Mode Voltage, Op Amp 1

Offset Voltage vs Input Common

Mode Voltage, Op Amp 1

Differential V_OSDelta Distribution

100

90

80

70

60

50

40

30

20

10

0

0.2

0.1

0.2

0.1

+

–

434 TYPICAL UNITS

V = 5V, V = –5V

V

= 5V

S

V

A

= 5V

TYPICAL UNIT

S

T

= 25°C

V

= V2 =

+IN1

MID-RAIL TO

+

V

–0.1V

0.0

0

–0.1

–0.2

–0.3

–0.1

–0.2

–0.3

T

= 125°C

= 25°C

= –40°C

T

= 125°C

= 25°C

= –40°C

A

–0.3 –0.2 –0.1

0

0.1

0.2

0.3

–5 –4 –3 –2 –1

0

1

2

3

4

5

0

1

2

3

4

5

CHANGE OF INPUT REFERRED V (mV)

INPUT COMMON MODE VOLTAGE (V)

OS

6350 G02

6350 G11

6350 G10

DC Linearity

Differential V_OSDistribution

DC Linearity

0.5

0.4

100

90

80

70

60

50

40

30

20

10

0

0.5

0.4

–

+

434 TYPICAL UNITS

V

= 0V, V = 5V

T

= 125°C

= 85°C

= 25°C

= –40°C

A

V

A

= 5V

= 2.5V

S

+IN2

T

= 25°C

NO LOAD

0.3

V

= V2 =

+IN1

TYPICAL UNIT

MID-RAIL

LINEAR FIT FOR 0.25V < V < 4.75V

0.2

IN

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

–

+

V

= –5V, V = 5V

= 0V

+IN2

NO LOAD

T

= 125°C

= 85°C

= 25°C

= –40°C

A

TYPICAL UNIT

LINEAR FIT FOR

–4.75V < V < 4.75V

IN

–0.3 –0.2 –0.1

0

0.1

0.2

0.3

0 0.5

1

1.5

2

V

2.5 3 3.5 4 4.5 5

–6 –5 –4 –3 –2 –1

V

0

1

(V)

2

3

4

5

6

DIFFERENTIAL INPUT REFFERED V (mV)

(V)

+IN1

OS

+IN1

6350 G01

6350 G21

6350 G22

Common Mode V_OS

vs Input (+IN2) Voltage

Differential V_OSvs Temperature

0.5

0.4

0.3

0.2

0.1

0.6

0.4

0.2

0

V

= V

+IN2

+IN1

S

= 5V

V

= 10V

S

(NOTE 6)

T

= –40°C

= 25°C

A

V

= 5V

S

0

–0.1

–0.2

–0.3

–0.4

–0.2

–0.4

–0.6

T

= 125°C

4

A

V1 = V2 = MID-RAIL

TYPICAL UNIT

–0.5

0

1

2

3

5

6

–60

–20

20

60

100

140

+IN2 PIN VOLTAGE (V)

TEMPERATURE (°C)

6350 G07

6350 G09

6350fc

6

For more information www.linear.com/LT6350

LT6350

Typical perForMance characTerisTics

T_A= 25°C, V⁺= 5V, V^–= 0V, V_+IN1= V2 = Mid-Supply, V_SHDN= V⁺, R_F= SHORT, R_G= OPEN, R_L= OPEN. See Figure 1.

Input Bias Current

vs Temperature, Op Amp 1

vs Input Voltage, Op Amp 2

vs Input Voltage, Op Amp 1

4

3

2

1

2

1

0

3

2

V

= 5V

+IN1

V

= 5V

V = 5V

S

= V

+IN2

+

V

= V

+IN1

1

0

–1

V

= MID-RAIL

+IN1

–1

–2

–3

–4

–2

–3

–4

–

= V

T

= 125°C

= 25°C

T

= 125°C

= 25°C

A

= –40°C

0

1

2

3

4

5

0

1

2

3

4

5

–60 –40 –20

0

20 40 60 80 100 120 140

V

(V)

V

(V)

+IN1

TEMPERATURE (°C)

+IN2

3586 G35

6350 G08

6350 G13

Supply Current vs Supply Voltage

Supply Current vs Temperature

10

9

8

7

6

5

4

3

2

1

0

10

9

8

7

6

5

4

3

2

1

0

+

V

= V

SHDN

T

= 125°C

A

T

= 25°C

A

= –40°C

V

= 10V

= 5V

= 3V

S

0

1

2

3

4

5

6

7

8

9

10 11 12

–60

–20

20

60

100

140

SUPPLY VOLTAGE (V)

TEMPERATURE (°C)

6350 G04

6350 G03

Supply Current in Shutdown

vs Supply Voltage

Turn-On and Turn-Off

Transient Response

Supply Current vs SHDN Voltage

8

7

6

5

4

3

2

1

0

120

100

80

60

40

20

0

3

2

1

–

+

–

V

= 5V

V

= V

V

R

= 2.5V

= –2.5V

= 2k

S

SHDN

T

= –40°C

A

L

T

= 125°C

A

T

= 25°C

A

0

–1

–2

–3

T

= 25°C

A

T

= 125°C

A

V

T

= –40°C

SHDN

V

OUTDIFF

0

1

2

3

4

5

5µs/DIV

0

1

2

3

4

5

6

7

8

9

10 11 12

SHDN PIN VOLTAGE (V)

SUPPLY VOLTAGE (V)

6350 G05

6350 G06

6350 G43

6350fc

7

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LT6350

Typical perForMance characTerisTics

T_A= 25°C, V⁺= 5V, V^–= 0V, V_+IN1= V2 = Mid-Supply, V_SHDN= V⁺, R_F= SHORT, R_G= OPEN, R_L= OPEN. See Figure 1.

Differential Output Voltage Noise

vs Frequency

0.1Hz to 10Hz Differential

Output Settling Time

vs Output Step

Input-Referred Voltage Noise

100

10

1

600

400

300

250

200

150

V

= 5V

= 25°C

V

S

= 5V

V

= 5V

S

A

S

T

200

2mV

0

–200

–400

–600

100

50

20mV

0

1

1k

1M

100M

–8 –6 –4 –2

0

2

4

6

8

FREQUENCY (Hz)

TIME (2s/DIV)

DIFFERENTIAL OUTPUT STEP (V)

6350 G23

6350 G24

6350 G35

Output Saturation Voltage

vs Load Current, Output Low,

Either Output

Output Saturation Voltage

Output Settling Time

vs Output Step

vs Load Current, Output High,

Either Output

400

350

10

1

10

1

V

= 5V

V

= 10V

V

= 5V

S

300

250

0.01%

2mV

200

150

0.1

0.01

0.1

0.01

100

50

T

= 125°C

= 25°C

= –40°C

T

= 125°C

= 25°C

A

= –40°C

20mV

0

–20 –15 –10 –5

5

10 15 20

0.0.1

0.1

1

10

100

0.01

0.1

1

10

100

DIFFERENTIAL OUTPUT STEP (V)

LOAD CURRENT (mA)

6350 G36

6350 G14

6350 G15

Output Impedance

vs Frequency

Output Short-Circuit Current

vs Supply Voltage, Either Output

Overdrive Recovery

100

80

6

5

7

5

100

10

V

S

= 5V

V

= 5V

S

SINKING

60

4

3

40

20

3

1

T

= 85°C

= 25°C

= –40°C

A

0

1

2

–1

–3

–5

–7

OUT2

–20

–40

–60

–80

–100

OUT1

1

0.1

0

SOURCING

4

V

OUTDIFF

V

+IN1

–1

0.01

0

2

6

8

10

12

0

1

2

3

4

0.01

0.1

1

10

100

SUPPLY VOLTAGE (V)

TIME (µs)

FREQUENCY (MHz)

6350 G16

6350 G44

6350 G28

6350fc

8

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LT6350

Typical perForMance characTerisTics

T_A= 25°C, V⁺= 5V, V^–= 0V, V_+IN1= V2 = Mid-Supply, V_SHDN= V⁺, R_F= SHORT, R_G= OPEN, R_L= OPEN. See Figure 1.

Differential Frequency Response

vs Gain

Differential Frequency Response

vs Temperature

Closed-Loop Small-Signal

Frequency Response, Op Amp 1

40

30

10

5

30

20

V

= 5V

= 2k

V

= 5V

= 2k

V

S

L

= 5V

= 2k

S

L

S

R

L

R + R = 2k FOR A

> 2

R + R = 2k for A > 1

F

G

VDIFF

F

G

V1

A

= 10

= 5

V1

20

0

10

A

= 2

= 1

V1

–5

–10

–15

0

A

= 20

= 10

= 4

VDIFF

T

= 85°C

= 25°C

= –40°C

A

–10

–20

= 2

–10

0.1

1

10

FREQUENCY (MHz)

100

1000

0.1

1

10

FREQUENCY (MHz)

100

1000

0.1

1

10

100

1000

FREQUENCY (MHz)

6350 G37

6350 G38

6350 G19

Closed-Loop Small-Signal

Frequency Response, Op Amp 2

Closed-Loop Magnitude and

Output Balance vs Frequency

Group Delay Response, Op Amp 2

5

0

500

400

300

200

100

0

5

0

8

7

6

5

4

60

V

= 5V

V

= 5V

S

MAGNITUDE

50

40

MAGNITUDE

–5

GROUP DELAY

PHASE

–10

–15

–5

30

20

10

0

–10

–15

–20

–25

–100

0.1

1

10

100

1000

0.1

1

10

100

0.1

1

10

100

FREQUENCY (MHz)

6350 G20

6350 G40

6350 G41

Differential Slew Rate

vs Temperature

Small-Signal Step Response

Large-Signal Step Response

5

4

3

2

1

0

80

70

60

50

40

30

20

OUT2, CL = 56pF EACH OUTPUT TO GND

V

= 5V

S

OUT1 TIED TO –IN1

OUT2

50Ω SOURCE IMPEDANCE

R

= 1k

L

OUT1, NO LOAD

+

–

V

= 5V, V = 0V

OUT1 RISING

(OUT2 FALLING)

= 2.5V

+IN2

NO LOAD

OUT2, NO LOAD

OUT2 RISING

(OUT1 FALLING)

OUT1

OUT1, CL = 56pF EACH OUTPUT TO GND

200ns/DIV

–60 –40 –20

0

20 40 60 80 100 120 140

V

= 5V

200ns/DIV

S

TEMPERATURE (°C)

6350 G33

6350 G34

3586 G35

6350fc

9

For more information www.linear.com/LT6350

LT6350

Typical perForMance characTerisTics

T_A= 25°C, V⁺= 5V, V^–= 0V, V_+IN1= V2 = Mid-Supply, V_SHDN= V⁺, R_F= SHORT, R_G= OPEN, R_L= OPEN. See Figure 1.

Harmonic Distortion

vs Output Amplitude

Harmonic Distortion

vs Output Amplitude

Harmonic Distortion vs Frequency

–50

–60

–70

–60

–70

–40.0

–50.0

–60.0

–70.0

–80.0

–90.0

–100.0

+

–

V

= 5V, V = 0V, V

= 2.5V

f

= 100kHz

= 2k

f

= 1MHz

R = 2k

L

OUTCM

IN

L

IN

R

= 2k

R

L

+

–

V

= 5V, V = 0V, V

= 2.5V

OUTCM

+

–

V

= 5V, V = 0V, V

= 2.5V

OUTCM

V

= 8V

P-P

–80

OUTDIFF

–80

–90

HD3

HD2

HD3

HD2

–100

–110

–120

V

= 4V

10k

HD2

OUTDIFF

P-P

–100

–110

+

–

V

= 5V, V = –2V, V

= 2V

OUTCM

+

–

V

= 5V, V = –2V, V

= 2V

OUTCM

7

1k

100k

1M

4

5

6

8

2

3

4

5

6

)

7

8

FREQUENCY (Hz)

V

(V

)

V

(V

OUTDIFF P-P

6350 G47

6350 G45

6350 G46

pin FuncTions

–IN1 (Pin 1): Inverting Input. Normally used to take feed-

back from OUT1.

–

V (Pin 6): Negative Power Supply. Can be ground.

SHDN (Pin 7): Shutdown. If tied high or left ﬂoating, the

part is enabled. If tied low, the part is disabled and draws

less than 70μA of supply current.

+IN2 (Pin 2): High Impedance Input. Normally used as a

reference input.

+

V (Pin 3): Positive Power Supply.

+IN1 (Pin 8): High Impedance Input. Normally used as

the single-ended input.

OUT1 (Pin 4): Noninverting Output. In phase with +IN1.

OUT2 (Pin 5): Inverting Output.

–

Exposed Pad (Pin 9, DD8 Package Only): Tie to V

6350fc

10

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LT6350

block DiagraM

–

+

IN1

8

SHDN

V

6

OUT2

5

7

BIAS

+

OP AMP 1

1k

–

_

OP AMP 2

+

1

2

+

IN2

3

4

6350 BD

+

–

IN1

V

OUT1

Dc TesT circuiT

V

+

SHDN

+

V

+

–

V

0.1µF

+IN1

V

OUT2

–

+

V1

IN1

+

V

OUT2

SHDN

–

R

L

–

V

OUTDIFF

LT6350

–

+

–

+

IN2

IN1

V

OUT1

+

OUT1

6350 TC

R

F

V

R1

R

G

499Ω

0.1µF

–

+

V2

–

Figure 1. DC Test Circuit.

6350fc

11

For more information www.linear.com/LT6350

LT6350

operaTion

4.5V

The LT6350 is a low noise single-ended to differential

converter/ADCdriver.Itconvertsahighorlowimpedance,

single-ended input signal to a low impedance, balanced

differential output suitable for driving high performance

differentialsucessiveapproximationregister(SAR)ADCs.

Theclosedloop–3dBbandwidthforthetypicalgain-of-two

conﬁguration is 33MHz.

5V

V

IN

0.1µF

0.5V

V

OUT2

4.5V

V

IN

0.5V-4.5V

+

–

IN1

SHDN

V

OUT2

+

–

0.5V

–

+

LT6350

The LT6350 uses a two op amp topology as shown in

the Block Diagram: at the input is one fully uncommitted

op amp with both inputs and output brought out to pins.

This is followed by an op amp internally hardwired and

optimally compensated as a unity-gain inverter with its

input connected to the output of the ﬁrst op amp. The

noninvertinginputoftheinvertingopampisbroughtoutto

a pin and is used to set the output common mode voltage

level. The outputs of the two op amps are therefore 180°

out-of-phase and provide a low impedance differential

drive for differential-input analog to digital converters.

The outputs of the LT6350 can swing rail-to-rail and can

source or sink a transient 45mA of current. The outputs

aredesignedtodrive40pFtogroundor20pFdifferentially.

Load capacitances larger than 40pF should be decoupled

from each output with at least 25Ω of series resistance.

–

+

OUT1

IN2

V

IN1

V

OUT1

4.5V

2.5V

0.1µF

0.5V

6350 F02

Figure 2. Basic Connections

DESIGN EQUATIONS AND ALTERNATIVE CONNECTIONS

Because the input op amp presents its output and both

its inputs to LT6350 pins, alternative conﬁgurations are

possible. Consider the general conﬁguration shown in

Figure 3.

Ordinary op amp analysis gives the equations for V

OUT1

The LT6350 features very low noise op amps to support

signal-to-noise ratios >110dB.

and V

given the input voltages V1, V2, V and V :

OUT2

IN A

V

OUT1

V

OUT1

V

OUT2

= V • (1+R /R ) – V1 • (R /R )

IN F G F G

BASIC CONNECTIONS

= V • (1+R /R ) + V1

A

F

G

A typical use of the LT6350 is to convert a high impedance,

single-endedinputsignalintoalowimpedancedifferential

output. Theconﬁgurationforsuchanapplicationisshown

in Figure 2. Here, the input op amp is wired as a non-

inverting buffer with a high input impedance at +IN1. At

= –V

+ 2 • V2

OUT1

If we deﬁne the differential and common mode output

voltages as:

V

≡ V

– V

OUTDIFF

OUT1

OUT2

the outputs, V

follows the input, and V

provides

OUT1

OUT2

and

an inverted copy of V

for an overall differential gain

OUT1

V

≡ (V

+ V

)/2,

of two. The input op amp has a rail-to-rail input stage, and

both outputs are rail-to-rail, typically swinging to within

55mV of the rails at each output in this conﬁguration

OUTCM

OUT1

OUT2

then combining the expressions for V

thedeﬁnitionsgivestheresultingdifferentialandcommon

mode output voltages:

and V

with

OUT2

OUT1

allowing 8V differential outputs from a single 5V rail.

P-P

This provides a simple interface to differential input ADCs

V

= 2 • (V •(1+R /R )–V1•(R /R )–V2) (1)

IN F G F G

OUTDIFF

that accept a mid-rail input common mode voltage.

= 2 • (V • (1+R /R ) + V1 – V2)

(2)

(3)

A

F

G

= V2

OUTCM

6350fc

12

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LT6350

operaTion

Noticethattheoutputcommonmodevoltageisdetermined

sensed signals coming through an op amp running from

15V rails. The LT6350 can easily interface the high voltage

opamptoa5VADCbyusingtheinvertinggainconﬁguration.

For a clean interface, three conditions must be met:

simply by the voltage at +IN2. However, since the voltage

appliedat+IN2doesnotaffectthevoltageattheV

output,

OUT1

a differential offset voltage will develop for V = 0 when V1

A

does not equal V2. The value of the offset voltage will be

2 • (V1 – V2), as can be seen in Equation 2. For lowest

differential offset, therefore, the input signal to pin +IN1,

1. V

2. V

= 0 when OUT is centered at OUT

.

OUTDIFF

HV

HVNOM

= V

= V2 when OUT is centered at

HV

OUT1

OUT

OUTCM

.

V ,shouldbecenteredaroundthecommonmodevoltage

HVNOM

IN

applied to pin +IN2. Often this voltage is provided by the

ADC reference output. When the input is so centered and

V1 = V2, Equation 2 reduces to:

3. Full-scale signals at OUT are translated at the

HV

output of the LT6350 into the appropriate full-scale

range for the ADC.

V

= 2 • V • (1+R /R )

A F G

OUTDIFF

Applying the above constraints to the design Equations

(1) to (3) gives values for the ratio of R to R and for

ThesimpleconnectiondescribedintheBasicConnections

section can be seen as a special case of the general circuit

F

G

the value of V :

IN

inFigure3whereR isashortcircuit, R isanopencircuit,

F

IN

G

R_F/R_G=(OUT_MAX−OUT_MIN)/(OUT_HVMAX−OUT_HVMIN

)

and the voltage at V is centered around the voltage V2. If

V = V2 /(1+(R_F/R_G))+(OUT_HVNOM)/(1+(R_G/R_F))

differentialgaingreaterthantwoisneeded,thevaluesofR

F

IN

and R can be adjusted in accordance with Equation (2).

G

Additional information about feedback networks is given

in the next section and in the Input Ampliﬁer (Op Amp 1)

Feedback Components section.

OP AMP 1

4

OUT1

+IN1

8

R

INT

R

INT

+

–

–IN1

1

R

F

OP AMP 2

Inverting Gain Connections/Interfacing to High

Voltage Signals

–

+

R

OUT2

S

G

5

2

+IN2

+

–

V

A

6350 F03

+

–

V

V1

V2

Although the previous examples have assumed the input

signal is applied at +IN1, it is also possible to use the input

op amp in an inverting conﬁguration by ﬁxing the voltage

IN

–

Figure 3. General Conﬁguration

V andapplyingtheinputsignalatV1ofFigure3.Usingthe

IN

input op amp in the inverting conﬁguration ﬁxes its input

OUT

MAX

commonmodevoltageatthevoltageV ,whichallowsthe

IN

V2

input signal at V1 to traverse a swing beyond the LT6350

OUT

MIN

supply rails. To avoid unwanted differential offsets in this

OP AMP 1

+IN1

4

OUT1

OUT2

conﬁguration V should be chosen such that:

R

INT

R

INT

IN

8

+

–

+

V

IN

V = V2/(1+(R /R ))

–

IN

F

G

+15V

–15V

OP AMP 2

Then Equation (1) reduces to:

= –2 • V1 • (R /R ))

–

+

R

F

G

OUT

5

HV

1

SIGNAL

2

+IN2

V

OUTDIFF

F

G

–IN1

OUT

MAX

+

–

V2

Choosing R = R with the input at V1 leads to the gain

V2

F

G

OUT

HVMAX

HIGH VOLTAGE OP AMP

of –2 conﬁguration.

OUT

MIN

OUT

HVNOM

6350 F04

A practical application for the inverting gain conﬁguration is

interfacing a high voltage op amp to a 5V differential SAR

ADC.AsseeninFigure4,anindustrialapplicationmighthave

OUT

HVMIN

Figure 4. Interfacing to High Voltage Signals

6350fc

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LT6350

applicaTions inForMaTion

INPUT AMPLIFIER (OP AMP 1) CHARACTERISTICS

within 1.3V of the positive rail and only Q2/Q3 are active.

Typical total change in input bias current over the entire

input common mode range is approximately 4µA. These

changes in input bias current will generate corresponding

changes in voltage across the source and gain-setting

resistors. Because the LT6350 input offset current is less

than the input bias current, matching the effective source

and feedback resistances at the input pins will reduce total

offset errors generated by changes in input bias current

and will keep distortion to a minimum.

Figure5showsasimpliﬁedschematicoftheLT6350’sinput

ampliﬁer. The input stage has NPN and PNP differential

pairs operating in parallel. This topology allows the inputs

to swing all the way from the negative supply rail to the

positive supply rail. Both differential pairs are operational

when the common mode voltage is at least 1.3V from

either rail. As the common mode voltage swings higher

+

than V – 1.3V, current source I saturates, and current

1

in PNP differential pair Q1/Q4 drops to zero. Feedback is

maintained through the NPN differential pair Q2/Q3, but

INPUT AMPLIFIER (OP AMP 1) FEEDBACK

COMPONENTS

the input stage transconductance, g , is reduced by a

m

factor of 2. A similar effect occurs with I when the com-

2

mon mode voltage swings within 1.3V of the negative rail.

A precision, 2-point algorithm is used to maintain near

constant offset voltage over the entire input range (see

Offset Considerations).

When feedback resistors are used to set gain in op amp 1,

care should be taken to ensure that the pole formed by the

feedbackresistorsandthetotalcapacitanceattheinverting

input, –IN1, does not degrade stability. For instance, to

set the LT6350 in a differential gain of +4, R and R of

Figure 3 could be set to 1kΩ. If the total capacitance at

–IN1 (LT6350 plus PC board) were 3pF, a new pole would

be formed in the loop response at 106MHz, which could

leadtoringinginthestepresponse. Acapacitorconnected

across the feedback resistor and having the same value

Negative input bias current ﬂows into the +IN1 and –IN1

inputs when the input common mode is centered between

the rails. The magnitude of this current increases when

the input common mode voltage is within 1.3V of the

negative rail and only Q1/Q4 are active. The polarity of the

current reverses when the input common mode voltage is

F

G

+

V

+

R1

R2

V

I

BIAS

1

–

Q11

+

–

V

Q5

Q8

Q6

DESD1

+IN1

DESD2

DESD4

Q1

Q4

+

V

Q2

Q3

+

C

M

V

D1

D2

DESD5

OUT1

DIFFERENTIAL

DRIVE

GENERATOR

–IN1

Q9

DESD3

DESD6

Q7

+

–

V

R3

R4

R5

D3

Q10

I

2

–

V

6350 F05

Figure 5. Input Ampliﬁer (Op Amp 1) Simpliﬁed Schematic

6350fc

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LT6350

applicaTions inForMaTion

as the total –IN1 parasitic capacitance will eliminate

any ringing or oscillation. Special care should be taken

during layout, including using the shortest possible trace

lengths and stripping the ground plane under the –IN1

pin, to minimize the parasitic capacitance introduced at

that pin.

Since the inverting op amp is permanently conﬁgured

with a noise gain of two, the internal frequency compen-

sation has been adjusted such that the GBW product

of the inverting op amp is higher than that of the input

op amp. This allows the closed-loop bandwidths of the

two op amps to match more closely when the LT6350 is

used in the typical differential gain of two conﬁguration

and increases the closed-loop differential bandwidth in

that application.

Input bias current induced DC voltage offsets in the input

op amp can be minimized by matching the parallel imped-

anceofR andR totheimpedanceofthesourcethatdrives

F

G

+IN1. For example, in the typical gain-of-two application,

The input referred voltage offset of the inverting op amp,

which is equivalent to output common mode voltage

offset, and which could contribute to differential voltage

offset in accordance with Equation (2), is trimmed during

manufacture to within 125µV. To minimize the offset

contribution of the input bias current into pin +IN2, an

external 499Ω resistor should be installed at pin +IN2

for all applications. For more information, see the Setting

The Output Common Mode and Offset Considerations

sections.

whentheinputopampisconﬁguredasaunity-gainbuffer,

choosing R = R will minimize the differential offset at the

F

S

output. Since nonzero values of R will contribute to the

F

total output noise, R may be bypassed with a capacitor

F

to reduce the noise bandwidth.

INVERTING AMPLIFIER (OP AMP 2) CHARACTERISTICS

The operational ampliﬁer at pins OUT1, +IN2 and OUT2 is

internally conﬁgured as a unity-gain inverter and provides

on pin OUT2 an inverted copy of the voltage at pin OUT1.

The voltage applied to pin +IN2 sets the output common

mode voltage in accordance with Equation (3). The range

of useful output common mode voltages is limited by the

full-scale input range of A/D converters; values of output

common mode near mid-rail are most useful. The op amp

used for the inverting buffer therefore differs from the

input op amp primarily in that its input common mode

range is not rail-to-rail: the inverting op amp has an input

INPUT PROTECTION

There are back-to-back diodes across the + and – inputs

of both LT6350 op amps. The inputs of the LT6350 do not

have internal resistors in series with the input transistors,

a technique often used to protect the input transistors

from excessive current ﬂow during a differential overdrive

condition. Adding series input resistors would signiﬁ

-

cantly degrade the low noise performance. Therefore, if

the voltage across the op amp input stages is allowed to

exceed 0.7V, steady-state current conducted though the

protection diodes should be externally limited to 20mA.

The input diodes are rugged enough to handle transient

currentsduetoampliﬁerslewrateoverdriveormomentary

clipping without protection resistors.

–

stage that functions over the input range from V + 1.5V

+

to V – 0.1V.

The inverting op amp uses tightly matched, 1k on-chip re-

sistorstosetthegainof–1.Notethatduringoutputswings,

current ﬂows through these resistors, increasing the total

power dissipation of the LT6350. The worst-case increase

overquiescentpowerdissipationcanbefoundbyassuming

that the full power supply voltage appears between OUT1

and OUT2. In this case the extra power dissipated in the

2

internal feedback network will be V /2kΩ.

S

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LT6350

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Driving the input signal sufﬁciently beyond the power

supply rails will cause the input transistors to saturate.

When saturation occurs, the ampliﬁer loses a stage of

phase inversion and the output tries to invert. Diodes D1

and D2 (Figure 5) forward bias and hold the output within

a diode drop of the input signal. With very heavy input

overdrive the output of op amp 1 could invert. To avoid

this inversion, limit the input overdrive to 0.5V beyond

the power supply rails.

INTERFACING THE LT6350 TO A/D CONVERTERS

When driving an ADC, an additional single-pole passive

RC ﬁlter added between the outputs of the LT6350 and

the inputs of the ADC can sometimes improve system

performance.ThisisbecausethesamplingprocessofADCs

creates a charge transient at the ADC inputs that is caused

by the switching in of the ADC sampling capacitor. This

momentarilyshortstheoutputoftheampliﬁeraschargeis

transferred between ampliﬁer and sampling capacitor. For

anaccuraterepresentationoftheinputsignal,theampliﬁer

must recover and settle from this load transient before

the acquisition period has ended. An RC network at the

outputsofthedriverhelpsdecouplethesamplingtransient

of the ADC from the ampliﬁer reducing the demands on

the ampliﬁer’s output stage (see Figure 6). The resistors

at the inputs to the ADC minimize the sampling transients

that charge the RC ﬁlter capacitors.

OUTPUT VOLTAGE RANGE

The outputs of the LT6350 typically swing to within 55mV

of the upper and lower supply rails when driving a purely

capacitive load such as at the switched-capacitor input

stage of a SAR ADC. The LT6350 can therefore share a

single 5V supply with the SAR ADC and drive a full 8V

P-P

differentialaroundaninputcommonmodevoltagebetween

2.055V and 2.945V. A modest negative supply can be

added to allow the LT6350 to swing all the way to 0V in

systems where the ADC requires a true 0V-referenced

signal or when the input common mode range of the ADC

is restricted to be lower than 2.055V. Some SAR ADCs use

2V as the input common mode voltage with a full-scale

input signal range at each input of 0V to 4V. The outputs

5V

+

V

IN

–

R

FILT

0.1µF

+

C

+

–

CM

IN1

SHDN

V

OUT2

5V

+

–

R

S

+

–

+

LT6350

A

IN

C

ADC

–

of the LT6350 can swing 7.78V differentially around a

DIFF

P-P

–

IN

+

2V common mode voltage, which is a loss of only 0.24dB

OUT1

IN2

V

IN1

R

S

of the full-scale range of such ADCs.

R

FILT

C

0.1µF

2V

CM

6350 F06

Figure 6. Driving an ADC

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The capacitance serves to provide the bulk of the charge

duringthesamplingprocess, whilethetworesistorsatthe

outputs of the LT6350 are used to dampen and attenuate

any charge injected by the ADC. The RC ﬁlter can also be

used to the additional beneﬁt of band limiting broadband

output noise. See the Noise Considerations section for

more information.

SETTING THE OUTPUT COMMON MODE VOLTAGE

The output common mode voltage is set by the voltage

applied to pin +IN2 in accordance with Equation (3). The

usable output common mode range is determined by the

input common mode range of the inverting op amp and

–

+

is from V + 1.5V to V .

In single supply applications, the optimal common mode

input range to the ADC is often determined by the ADC’s

reference. IftheADChasanoutputpinforsettingtheinput

common mode voltage, it can be directly tied to the +IN2

pin, as long as it is capable of providing the input current

into +IN2 as listed in the Electrical Characteristics Table.

Alternatively, +IN2 may be driven by an external precision

reference such as the LT1790.

TheselectionoftheRCtimeconstantdependsontheADC;

but generally, longer time constants will improve SNR at

theexpenseoflongersettlingtime.Excessivesettlingtime

can introduce gain errors and can cause distortion if the

ﬁlter components are not perfectly linear. Note also that

too small of a resistor will not properly dampen the load

transient of the sampling process, prolonging the time

required for settling. 16-bit applications typically require

a minimum settling time of eleven RC time constants of

a ﬁrst order ﬁlter.

For lowest offset, the +IN2 pin should see 499Ω of driving

resistance in all applications (see Offset Considerations).

If the driving resistance is nominally less than 499Ω,

additional resistance can be added to make up the

difference. The resistor noise bandwidth can be reduced

by bypassing the +IN2 pin to the ground plane with a

chip ceramic capacitor of at least 0.1µF (see the Typical

Application on the front page). The bypass capacitance

also helps prevent AC signals on this pin from being

inadvertently converted to differential signals.

Note that the ﬁlter’s series resistance also serves to

decouple the LT6350 outputs from load capacitance. The

outputs of the LT6350 are designed to drive a maximum

of 40pF to ground or 20pF differentially; higher values

of ﬁlter capacitor should always be decoupled with ﬁlter

resistors of at least 25Ω.

High quality resistors and capacitors should be used in

the RC ﬁlter since these components can contribute to

distortion. For lowest distortion, choose capacitors with

a high quality dielectric, such as a C0G multilayer ceramic

capacitor. Metal ﬁlm surface mount resistors are more

linear than carbon types.

SHDN

If the SHDN pin (Pin 7), is pulled low within 300mV of the

negative supply rail, the LT6350 will power down. The pin

is connected through a diode to an internal current source

of 20µA. When pulled below the shutdown threshold, the

20µA current will ﬂow from the pin. If the pin is left open

–

or pulled high (above V + 2V), the part will enter normal

active operation, and the current into the pin will be very

small due to the reverse-biased diode.

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VOS

In shutdown, all biasing current sources are shut off,

and the output pins, OUT1 and OUT2, each appear as

open collectors with non-linear capacitors in parallel and

steering diodes to either supply. Because of the non-linear

capacitance, the outputs still have the ability to sink and

source small amounts of transient current if driven with

signiﬁcant voltage transients. The input protection diodes

between +IN1 and +IN2 can still conduct if voltage tran-

sients at the input exceed 700mV. All other inputs also

have ESD protection diodes that can conduct when the

applied voltage exceeds 700mV. Using the SHDN feature

to wire-OR outputs together is not recommended.

OUT1

IOS1

2

OP AMP 1

VOS1

+IN1

IB1 +

R

S

R

INT

+

–

INT

IOS1

IB1 –

2

–IN1

IOS2

2

OP AMP 2

IB2 –

R

F

–

+

IOS2

2

IB2 +

VOS

OUT2

R

G

6350 F07

+

VOS2

–

+IN2

R

+IN2

Figure 7. Offset Model

The turn-on and turn off times between the shutdown and

active states are typically 400ns.

The resulting DC offset voltages at pin OUT1 and OUT2

can be calculated:

ESD

The LT6350 has ESD protection diodes on all inputs and

outputs. The diodes are reverse biased during normal

operation. If input pins are driven beyond either supply,

largecurrentswillﬂowthroughthesediodes.Ifthecurrent

is transient and limited to 100mA or less, no damage to

the device will occur.

VOS

=VOS1•(1+R /R )+IB1•(R -R •(1+R /R ))

F G F S F G

OUT1

– (IOS1/2)•(R +R •(1+R /R ))

F

S

F

G

VOS

= –VOS

+ 2•VOS2 + IB2•(R –2•R

+IN2

)

OUT2

OUT1

INT

+IN2

– (IOS2/2)•(R + 2•R

)

INT

Using the above equations and Equations (2) and (3), the

outputcommonmodeandoutputdifferentialmodeoffsets

can be found. The common mode offset is found to be:

OFFSET CONSIDERATIONS

For excellent offset and distortion performance, both the

common mode and differential mode output voltage off-

sets are trimmed during manufacturing.

VOS = VOS2 + IB2•((R /2) – R ) – (IOS2/2)

+IN2

CM

INT

•((R /2) + R

)

INT

+IN2

Figure 7 shows the contributors to DC offset voltage in

the LT6350.

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Becausetheinputbiascurrentintoopamp2ismuchlarger

The LT6350 uses very low noise op amps, resulting in a

total differential output spot noise at 10kHz of 8.2nV/√Hz

when the LT6350 is in the noninverting gain-of-two con-

ﬁguration shown in Figure 2. This is equivalent to the

voltage noise of a 1015Ω resistor at the +IN1 input. For

source resistors larger than about 1k, voltage noise due to

the source resistance will start to dominate output noise.

Source resistors larger than about 13k will interact with

the input current noise and result in output noise that is

resistor noise and ampliﬁer current noise dominant.

thantheoffsetcurrent, choosingR

tobeR /2greatly

+IN2

INT

reducestheoffsetcontributionofopamp2’sinputcurrents

on all units. With R = R /2, VOS reduces to:

+IN2

INT

CM

VOS = VOS2 – (IOS2/2) • R

CM

INT

VOS is trimmed to within 125µV with a 499Ω resistor

CM

installed at +IN2.

The value of V

is trimmed to bring V

to 125µV.

OSDIFF

OS1

Because linear modulation of V

with input common

OS1

mode could degrade the common mode rejection ratio

speciﬁcation of op amp 1, and nonlinear modulation of

i

n1

e

OP AMP 1

e

no1

n1

+IN1

e

nRINT

V

could cause nonlinear gain error (distortion), V

R

INT

OS1

+

–

INT

+

is trimmed to a low constant value over as wide an input

common mode range as possible. A precision, 2-point

–IN1

R

S

e

i

n2

no

n1

trim algorithm is used that results in V

within 125µV

OS1

OP AMP 2

e

nRS

–

+

–

e

R

F

over the input range V + 1.3V ≤ V

≤ V and V

+IN1

OS1

–

+

e

n2

+IN2

–

+

no2

e

within 300µV over the input range V ≤ V

negative supply below –1.3V can be used to extend the

≤ V . A

nRF

+IN1

6350 F08

e

nR+IN2

i

n2

nRG

input range for which V

down to ground.

is within 125µV all the way

OS1

R

+IN2

G

As a result of the trim procedure, the lowest offsets, both

common mode and differential mode, will occur with a

499Ω resistor at +IN2. This resistor can be bypassed with

a capacitor to eliminate its noise contribution. The gain-

setting resistor network (R and R ) impedance should

Figure 8. Noise Model

Note that the parallel combination of gain-setting resis-

tors R and R behaves like the source resistance, R ,

from the point of view of noise calculations, and the value

should be kept below about 1k to avoid increasing the

output noise. Lower-value gain and feedback resistors,

F

G

S

G

F

be matched to that of the source to minimize op amp 1’s

input bias current contributions to the offsets.

NOISE CONSIDERATIONS

AmodelshowingthesourcesofoutputnoiseintheLT6350

is shown in Figure 8. The total output noise resulting from

all contributors is governed by the equation:

2

e = √(4 • [e + (i R ) + e

](1 + (R /R )) + 4 • (i R ) + 4e

(1 + (R /R )) + 4e + 4e

+

nR+IN2

no

2e

n1

n1 S

nRS

F

G

n1 F

nRF

F

G

n2

2

+ (i R ) + 4 • (i R

) )

nRINT

n2 INT

n2 +IN2

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R and R , will always result in lower output noise at the

OUTPUT PHASE BALANCE

G

F

expenseofincreaseddistortionduetoincreasedloadingof

op amp 1. Note that op amp 1 is loaded internally by the 1k

input resistor to op amp 2, and therefore external loading

should not be much heavier than 1k to avoid degrading

distortion performance.

The topology of the LT6350 is that of a noninverting stage

followed by an inverting stage. This topology presents

a high impedance single-ended input and provides low

impedancedifferentialoutputs. Theoutputoftheinverting

buffer, OUT2, is slightly delayed with respect to the output

of the noninverting buffer, OUT1. In the LT6350, the delay

from OUT1 to OUT2 over an input bandwidth from DC to

When using R equal to R (for low offsets) in the gain-

F

S

of-two conﬁguration, wideband noise can be substantially

reduced by bypassing across R . For lowest output noise

the differential f

frequency is a nearly constant 6.8ns,

F

–3dB

always bypass at the +IN2 pin with a capacitor of at least

0.1µF as seen in the Typical Application schematic on the

front page. Alternatively, for systems that can tolerate

asshowninthegroupdelayplotintheTypicalPerformance

Characteristics section of this data sheet. The delay is

equivalent to a small phase offset from the nominal 180°

phase of the differential outputs. The size of the phase

offset grows with frequency. The phase imbalance causes

a small frequency-dependent common mode component

to appear at the outputs. A practical measure of this effect

can be found in the balance speciﬁcation, which is deﬁned

to be the change in output common mode level caused by

the presence of an output differential signal:

output voltage offsets, omitting R

and R will mini-

+IN2

F

mize output noise at the expense of larger output offset

voltage.

Using a single pole passive RC ﬁlter network at the output

of the LT6350, as shown in Figure 6, reduces the output

noisebandwidthandtherebyincreasesthesignal-to-noise

ratio of the system. For example, in a typical system with

outputsignalsof8V , andasignalbandwidthof100kHz,

Balance ≡ ((V

/V )/(V

/V ))

OUTCM IN

P-P

OUTDIFF IN

an RC output ﬁlter with R

= 100Ω and C

= 6.8nF,

FILT

DIFF

The balance of the LT6350 at any frequency, f, can be

slightly increases the output spot noise from 8.2nV√Hz to

8.4nV√Hz, but will reduce the total integrated noise from

47µV (33MHz noise bandwidth) to 3.6µV (184kHz noise

bandwidth) and improve the SNR from 96dB to 118dB.

Keep in mind that long RC time constants in the output

ﬁlter can increase the settling time at the inputs of the

ADC;incompletesettlingcancausegainerrorsorincrease

apparent crosstalk in multiplexed systems.

approximated from the delay, t , between outputs:

d

Balance (dB) ≅ 20 • log((4)/(2 • π • f • t ))

d

The approximation is very good from low frequencies up

to frequencies where the balance approaches 20dB, about

10MHz for the LT6350. At DC, the balance is limited by

the matching of the internal resistors that set the gain in

the inverting buffer. 1% matching of the resistors limits

the balance to 52dB at DC. At frequencies near the f

–3dB

point of the differential transfer function, additional phase

lag and gain rolloff also contribute to balance. See the

balance plot in the Typical Performance Characteristics

for a detailed picture of Balance vs Input Frequency.

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BOARD LAYOUT AND BYPASS CAPACITORS/DC1538A

DEMOBOARD

Stray parasitic capacitance at the –IN1 pin should be kept

to a minimum to prevent degraded stability resulting in

excessive ringing or oscillations. Traces at –IN1 should be

kept as short as possible, and any ground plane should

be stripped from under the pin and pin traces.

For single-supply applications it is recommended that

a high quality X5R or X7R, 0.1μF bypass capacitor be

+

–

placed directly between the V and the V pin; the V pin

(includingtheExposedPadontheDD8package)shouldbe

tieddirectlytoalowimpedancegroundplanewithminimal

routing. For split power supplies, it is recommended that

additional high quality X5R or X7R, 0.1μF capacitors

Because the outputs operate differentially, load imped-

ances seen by both outputs (stray or intended) should

be as balanced and symmetric as possible. This will help

preserve the balanced operation that minimizes the gen-

eration of even-order harmonic distortion in the output

stage and maximizes the rejection of common mode

signals and noise.

+

–

be used to bypass pin V to ground and V to ground,

again with minimal routing. Small geometry (e.g., 0603)

surface mount ceramic capacitors have a much higher

self-resonant frequency than do leaded capacitors, and

perform best with the LT6350.

The DC1538A demoboard has been designed for the

evaluation of the LT6350 following the above layout prac-

tices. Its schematic and component placement are shown

in Figures 9 and 10.

The +IN2 pin should be bypassed to ground with a high

quality ceramic capacitor of at least 0.1μF, both to reduce

thenoisebandwidthoftherecommendedDCoffsetbalance

resistor and to prevent changes in the common mode

reference voltage from being converted into a differential

output signal.

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LT6350

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+IN2

E1

+

V

R8

30.1k

3

JP5

+IN2

R1

10k

R15

20k

2

+IN1

E3

EXT

GND

SHDN

E2

C10

1µF

+

JP2

+COUPLING

V

JP1

JP3

+IN1CM

1

3

1

SHDN

+IN2

NC

AC DC

1

3

2

OUT2

E2

ENABLE

SHDN

2

OUT2

FILT

E5

C2

1µF

R2

0Ω

2

C1

OPT

NPO

C5

OPT

NPO

J1

J2

BNC

R3

10Ω

R4

0Ω

3

+IN1

–

V

C3

OPT

–

V

BNC

R5

OPT

C4

OPT

8

7

6

5

+

+IN1

SHDN

LT6350CMS8

OUT2

V

GND

+

–

E7

C6

OPT

NPO

R6

OPT

GND

E6

–

+

OUT1

FILT

–

E10

–IN1

1

+IN2

2

V

OUT1

R7

499Ω

J4

JP4

–COUPLING

R9

10Ω

R10

0Ω

3

4

BNC

C11

OPT

NPO

C8

0.1µF

AC DC

–IN1

E8

C9

OPT

NPO

C7

OPT

NPO

3

1

+

V

C12

1µF

J3

OPT

2

R14

OPT

R11

0Ω

OUT1

E9

–IN1

R12

0Ω

BNC

R13

OPT

C16

OPT

GND

E11

–

+

V

–

+

C13

1µF

V

1

E12

E13

JP6

2

SINGLE SUPPLY

SPLIT SUPPLY

3

C14

0.1µF

–

+

V

C23

10µF

C21

10µF

C15

0.1µF

C17

1µF

C18

1µF

C19

0.1µF

C20

10µF

C22

10µF

6350 F09

LT6350 BYPASS

Figure 9. DC1538A Demoboard Schematic

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LT6350

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Figure 10. DC1538A Demoboard Layout

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LT6350

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Figure 11. DC1539A Demoboard Layout

0

–10

–20

–30

–40

–50

–60

–70

–80

DRIVING THE LTC239X-16 / DC1539A DEMOBOARD

f = 20kHz

+

–

V

= 5V, V = –5V

= 7.3V

+IN2

The DC1539A demoboard, shown in Figure 11, has been

developed to demonstrate the interfacing of the LT6350

to the LTC239x-16 family of 16-bit SAR ADCs.

OUTDIFF

P-P

= 2.05V

SNR = 94.9dB

SINAD = 93.8dB

THD = 100.2dB

SFDR = 102.2dB

Spurious-free dynamic range of 102.2dB is achievable on

the DC1539A as seen in the FFT in Figure 12.

–90

–100

–110

–120

–130

–140

0

100

200

300

400

500

FREQUENCY (kHz)

6350 F12

Figure 12. 8192-Point FFT LT6350 Driving the

LTC2393-16 on the DC1539A Demoboard

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LT6350

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100kHz, 3RD-ORDER BUTTERWORTH FILTER

20

0

The LT6350 can be conﬁgured as a single-ended to

differentialﬁlterincorporatingfeedbackfromtheinverting

output. Figure13showstheschematicoftheconﬁguration

with values giving a 3rd Order Butterworth characteristic

havinga100kHz–3dBpointwithadifferentialgainoffour.

Figure 14 shows the ﬁlter output response to 10MHz. As

an option, to match the source impedance and preserve

the low DC errors of the LT6350, connect a 2.10k series

resistor at +IN1. To reduce the resistor noise, the +IN1

pin can be bypassed with a 0.1µF capacitor. For similar

topologies please consult the LT1567 data sheet and

design guide.

–20

–40

–60

–80

–100

1K

10K

100K

FREQUENCY (Hz)

1M

10M

6350 F14

Figure 14. 100KHz, 3rd Order Butterworth Filter Response

5V

Low Noise, Low Power 1MΩ Single Supply Photo-

diode Differential Output Transimpedance Ampliﬁer

2.5V

8

0.1µF

5

V

OUT2

7

3

+

TheTypicalApplicationonthebackpageshowstheLT6350

applied as a differential output transimpedance ampliﬁer.

The LT6350 forces the BF862 ultralow noise JFET source

+

IN1 SHDN

V

OUT2

+

–

+

LT6350

to3V, withR2ensuringthattheJFEThasanI

of1mA.

DRAIN

The JFET acts as a source follower, buffering the input of

the LT6350 and making it suitable for the high impedance

–

+

IN2

2

–

OUT1

4

V

IN1

1

6

feedback element R1. The BF862 has a minimum I

of

DSS

V

OUT1

1000pF

10mA and a pinchoff voltage between –0.3V and –1.2V.

The JFET gate and OUT1 therefore sit at a point slightly

higher than one pinchoff voltage below 3V, about mid-

supply at 2.5V.

499Ω

0.1µF

C5

1000pF

2.5V

R3

523Ω

174Ω

2210Ω

0.01µF

Whenthephotodiodeisilluminated,thecurrentmustcome

from OUT1 through R1 as in a normal transimpedance

ampliﬁer. Ampliﬁer output noise density is dominated at

low frequency by the 130nV/√Hz of the feedback resistor,

rising to 210nV/√Hz at 1MHz. Note that because the JFET

+

4750Ω

V

IN

–

6350 F13

Figure 13. 100KHz, 3rd Order Butterworth Filter

hasahighg ,approximately1/30Ω,itsattenuationlooking

m

into R2 is only about 1%. The closed-loop bandwidth

using a 3pF photodiode was measured at approximately

1.35MHz. With the output taken differentially, the gain and

the noise are both doubled.

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For more information www.linear.com/LT6350

LT6350

package DescripTion

DD Package

8-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1698 Rev C)

R = 0.125

0.40 ± 0.10

TYP

5

8

0.70 ±0.05

3.5 ±0.05

2.10 ±0.05 (2 SIDES)

1.65 ±0.05

3.00 ±0.10

(4 SIDES)

1.65 ± 0.10

(2 SIDES)

PIN 1

TOP MARK

(NOTE 6)

PACKAGE

OUTLINE

(DD8) DFN 0509 REV C

4

1

0.25 ± 0.05

0.75 ±0.05

0.200 REF

0.25 ± 0.05

0.50 BSC

0.50

BSC

2.38 ±0.10

2.38 ±0.05

BOTTOM VIEW—EXPOSED PAD

0.00 – 0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

NOTE:

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON TOP AND BOTTOM OF PACKAGE

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

MS8 Package

8-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1660 Rev F)

3.00 0.ꢀ0ꢁ

(.ꢀꢀ8 .004)

(NOTE 3)

0.5ꢁ

(.0ꢁ05)

REF

8

7 ꢂ 5

3.00 0.ꢀ0ꢁ

(.ꢀꢀ8 .004)

(NOTE 4)

4.90 0.ꢀ5ꢁ

(.ꢀ93 .00ꢂ)

DETAIL “A”

0.ꢁ54

0.889 0.ꢀꢁ7

(.035 .005)

(.0ꢀ0)

0° – ꢂ° TYP

GAUGE PLANE

5.ꢁ3

(.ꢁ0ꢂ)

MIN

ꢀ

ꢁ

4

3

3.ꢁ0 – 3.45

(.ꢀꢁꢂ – .ꢀ3ꢂ)

0.53 0.ꢀ5ꢁ

(.0ꢁꢀ .00ꢂ)

ꢀ.ꢀ0

(.043)

MAX

0.8ꢂ

(.034)

REF

DETAIL “A”

0.ꢀ8

(.007)

0.ꢂ5

(.0ꢁ5ꢂ)

BSC

0.4ꢁ 0.038

(.0ꢀꢂ5 .00ꢀ5)

TYP

SEATING

PLANE

0.ꢁꢁ – 0.38

0.ꢀ0ꢀꢂ 0.0508

RECOMMENDED SOLDER PAD LAYOUT

NOTE:

ꢀ. DIMENSIONS IN MILLIMETER/(INCH)

ꢁ. DRAWING NOT TO SCALE

(.009 – .0ꢀ5)

(.004 .00ꢁ)

0.ꢂ5

(.0ꢁ5ꢂ)

BSC

TYP

MSOP (MS8) 0307 REV F

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.ꢀ5ꢁmm (.00ꢂ") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.ꢀ5ꢁmm (.00ꢂ") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.ꢀ0ꢁmm (.004") MAX

6350fc

26

For more information www.linear.com/LT6350

LT6350

revision hisTory

REV

DATE

DESCRIPTION

PAGE NUMBER

A

03/10 Updated Units on V in Electrical Characteristics

4

OH

B

05/10 Updated Note 2

5

28

7

Updated Related Parts

C

06/13 Corrected curve labels on Input Bias Current vs Input Voltage graphs

6350fc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

27

For more information www.linear.com/LT6350

LT6350

Typical applicaTion

Low Noise, Low Power 1MΩ Single Supply Photodiode Transimpedance Ampliﬁer

5V

20k

5V

3V

0.1µF

V

OUT2

0.1µF

4.99k

2.5V

V

OUT1

+

500mV/DIV

IN1 SHDN

V

OUT2

24.9k

+

–

V

OUT2

500mV/DIV

–

+

LT6350

LIGHT

ASSERT

I

PD

PHILIPS/NXP

BF862

–

+

–

IN2

V

OUT1

OSRAM

SFH213

IN1

6350 TA04

2.5V

0.1µF

R1

1M

V_OUTDIFF= ~ ±±22mV ꢀ I_PD• 2MΩ

BW = 1.35MHz

V

OUT1

6350 TA03

R2

3.01k

0.1pF

relaTeD parTs

PART NUMBER

DESCRIPTION

COMMENTS

LTC2391-16/

LTC2392-16/

LTC2393-16

16-Bit SAR ADCs

250ksps/500ksps/1Msps

LT6202/LT6203

LT1806/LT1807

LTC6403

Single/Dual 100MHz Rail-to-Rail Input/Output Ultralow

Noise, Low Power Ampliﬁers

1.9nV√Hz, 3mA Maximum, 100MHz Gain Bandwidth

Single/Dual 325MHz Low Noise/Low Distortion Rail-toRail

Input/Output Ampliﬁers

2.5V Operation, 550µV Maximum V , 3.5µV/√Hz

OS

200MHz Low Noise, Low Distortion, Fully Differential

Input/Output Ampliﬁer/Driver

10.8mA Supply Current, –95dBc Distortion at 3MHz, 2V Output

P-P

LT1468/LT1469

Single/Dual 90MHz, 22V/µs 16-Bit Accurate Op Amp

5V to 15V Operation, VOS ꢀ 75µV

LTC6246/LTC6247/ Single/Dual/Quad 180MHz Rail-to-Rail Low Power Op Amps 1mA/Ampliﬁer, 4.2nV/√Hz

LTC6248

LTC1992/LTC1992-X Fully Differential Input/Output Ampliﬁers

Programmable Gain or Fixed Gain (G = 1, 2, 5, 10)

Low Distortion, 2V , 1MHz –94dBc, 13mA, Low Noise 3nV/√Hz

LT1994

Low Noise, Low Distortion Fully Differential Input/Output

Ampliﬁer/Driver

P-P

6350fc

LT 0613 REV C • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

28

For more information www.linear.com/LT6350

●

 LINEAR TECHNOLOGY CORPORATION 2010

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LT6350


型号：	LT6350IMS8#PBF
厂家：	Linear
描述：	LT6350 - Low Noise Single-Ended to Differential Converter/ADC Driver; Package: MSOP; Pins: 8; Temperature Range: -40°C to 85°C 放大器光电二极管
文件：	总28页 (文件大小：870K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT6350IMS8#PBF [Linear]

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