LT6360_技术文档

LTC2370-16

16-Bit, 2Msps, Pseudo-

Differential Unipolar SAR

ADC with 94dB SNR

FEATURES

DESCRIPTION

The LTC^®2370-16 is a low noise, low power, high speed

16-bit successive approximation register (SAR) ADC.

Operating from a 2.5V supply, the LTC2370-16 has a 0V

n

2Msps Throughput Rate

n

±±0.85Sꢀ IN5 ꢁMaꢂx

n

Guaranteed 16-ꢀit No Missing Codes

n

5ow Power: 19mW at 2Msps, 19µW at 2ksps

to V pseudo-differential unipolar input range with V

REF

n

94dꢀ SNR ꢁTypx at f = 2kHz

ranging from 2.5V to 5.1V. The LTC2370-16 consumes

only 19mW and achieves 0.ꢀ5LSꢁ ꢂIL maximum, no

missing codes at 16 bits with 94dꢁ SIR.

IN

n

–112dꢀ THD ꢁTypx at f = 2kHz

IN

n

Guaranteed Operation to 125°C

n

2.5V Supply

The LTC2370-16 has a high speed SPꢂ-compatible serial

interface that supports 1.ꢀV, 2.5V, 3.3V and 5V logic while

alsofeaturingadaisy-chainmode.Thefast2Mspsthrough-

put with no cycle latency makes the LTC2370-16 ideally

suited for a wide variety of high speed applications. An

internaloscillatorsetstheconversiontime,easingexternal

timingconsiderations.TheLTC2370-16automaticallypow-

ers down between conversions, leading to reduced power

dissipation that scales with the sampling rate.

n

Pseudo-Differential Unipolar ꢂnput Range: 0V to V

REF

n

V

ꢂnput Range from 2.5V to 5.1V

REF

n

Io Pipeline Delay, Io Cycle Latency

1.ꢀV to 5V ꢂ/O Voltages

SPꢂ-Compatible Serial ꢂ/O with Daisy-Chain Mode

ꢂnternal Conversion Clock

16-Lead MSOP and 4mm × 3mm DFI Packages

APPLICATIONS

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners. Protected by U.S. Patents, including 7705765.

n

Medical ꢂmaging

n

High Speed Data Acquisition

n

Portable or Compact ꢂnstrumentation

ꢂndustrial Process Control

Low Power ꢁattery-Operated ꢂnstrumentation

ATE

n

TYPICAL APPLICATION

32k Point FFT f_S= 2Msps, f_IN= 2kHz

0

2.5V 1.8V TO 5V

10µF

SNR = 94dB

–20

–40

THD = –112dB

SINAD = 93.9dB

SFDR = 117dB

0.1µF

V

REF

–60

+

–

V

OV

DD

5.1Ω

CHAIN

RDL/SDI

SDO

SCK

BUSY

CNV

0V

–80

+

–

LT^®6202

IN

–100

–120

–140

–160

–180

10nF

LTC2370-16

IN

SAMPLE CLOCK

REF

GND

237016 TA01a

2.5V TO 5.1V

47µF

(X5R, 0805 SIZE)

0

100 200 300 400 500 600 700 800 9001000

FREQUENCY (kHz)

237016 TA01b

237016fa

1

LTC2370-16

ABSOLUTE MAXIMUM RATINGS ^{ꢁNotes 1, 2x}

Supply Voltage (V )...............................................2.ꢀV

Power Dissipation.............................................. 500mW

DD

Supply Voltage (OV )................................................6V

Operating Temperature Range

DD

Reference ꢂnput (REF).................................................6V

LTC2370C ................................................ 0°C to 70°C

LTC2370ꢂ .............................................–40°C to ꢀ5°C

LTC2370H.......................................... –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

Analog ꢂnput Voltage (Iote 3)

+

–

ꢂI , ꢂI .........................(GID – 0.3V) to (REF + 0.3V)

Digital ꢂnput Voltage

(Iote 3).......................... (GID – 0.3V) to (OV + 0.3V)

DD

Digital Output Voltage

(Iote 3).......................... (GID – 0.3V) to (OV + 0.3V)

DD

PIN CONFIGURATION

TOP VIEW

CHAIN

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

GND

OV

TOP VIEW

V

DD

CHAIN 1

16 GND

GND

SDO

V

2

15 OV

DD

+

GND 3

14 SDO

13 SCK

17

GND

IN

SCK

+

–

IN

4

5

–

IN

RDL/SDI

BUSY

GND

12 RDL/SDI

11 BUSY

10 GND

GND

REF

GND 6

REF 7

REF 8

9

CNV

MS PACKAGE

16-LEAD PLASTIC MSOP

DE PACKAGE

T

= 150°C, θ = 110°C/W

16-LEAD (4mm × 3mm) PLASTIC DFN

JMAX

JA

T

= 150°C, θ = 40°C/W

JA

JMAX

EXPOSED PAD (PꢂI 17) ꢂS GID, MUST ꢁE SOLDERED TO PCꢁ

ORDER INFORMATION

5EAD FREE FINISH

LTC2370CMS-16#PꢁF

LTC2370ꢂMS-16#PꢁF

LTC2370HMS-16#PꢁF

LTC2370CDE-16#PꢁF

LTC2370ꢂDE-16#PꢁF

TAPE AND REE5

PART MARKING*

PACKAGE DESCRIPTION

16-Lead Plastic MSOP

TEMPERATURE RANGE

0°C to 70°C

LTC2370CMS-16#TRPꢁF 237016

LTC2370ꢂMS-16#TRPꢁF 237016

LTC2370HMS-16#TRPꢁF 237016

LTC2370CDE-16#TRPꢁF 23706

–40°C to ꢀ5°C

–40°C to 125°C

0°C to 70°C

16-Lead (4mm × 3mm) Plastic DFI

LTC2370ꢂDE-16#TRPꢁF

23706

–40°C to ꢀ5°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

237016fa

2

LTC2370-16

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 28°C0 ꢁNote 4x

SYMꢀO5

V +

PARAMETER

CONDITIONS

(Iote 5)

MIN

–0.1

0

TYP

MAX

+ 0.1

REF

UNITS

+

l

Absolute ꢂnput Range (ꢂI )

V

ꢂI

–

V –

ꢂI

Absolute ꢂnput Range (ꢂI )

(Iote 5)

0.1

V + – V – ꢂnput Differential Voltage Range

V

ꢂI

= V + – V –

V

REF

V

ꢂI

ꢂ

ꢂI

Analog ꢂnput Leakage Current

Analog ꢂnput Capacitance

1

µA

C

Sample Mode

Hold Mode

45

5

pF

ꢂI

CMRR

ꢂnput Common Mode Rejection Ratio

f

ꢂI

= 1MHz

77

dꢁ

CONVERTER CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 28°C0 ꢁNote 4x

SYMꢀO5 PARAMETER

CONDITIONS

MIN

16

TYP

MAX

UNITS

ꢁits

l

Resolution

Io Missing Codes

16

ꢁits

Transition Ioise

0.5

0.25

0.1

0

LSꢁ

RMS

l

ꢂIL

ꢂntegral Linearity Error

Differential Linearity Error

Zero-Scale Error

(Iote 6)

(Iote 7)

–0.ꢀ5

–0.5

–4

0.ꢀ5

0.5

4

LSꢁ

DIL

ZSE

LSꢁ

Zero-Scale Error Drift

Full-Scale Error

0.02

4

LSꢁ/°C

LSꢁ

l

FSE

–20

20

Full-Scale Error Drift

1

ppm/°C

DYNAMIC ACCURACY ^Thel denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 28°C and A_IN= –1dꢀFS0 ꢁNotes 4, .x

SYMꢀO5 PARAMETER

CONDITIONS

MIN

90.6

ꢀ9.6

TYP

93.9

MAX

UNITS

dꢁ

l

SꢂIAD

SIR

Signal-to-(Ioise + Distortion) Ratio

f

ꢂI

f

ꢂI

= 2kHz, V = 5V

REF

= 2kHz, V = 5V, (H-Grade)

dꢁ

REF

l

Signal-to-Ioise Ratio

f

ꢂI

f

ꢂI

= 2kHz, V = 5V

91.1

ꢀ6

94

ꢀ9.5

dꢁ

REF

= 2kHz, V = 2.5V

REF

l

f

ꢂI

f

ꢂI

= 2kHz, V = 5V, (H-Grade)

90

ꢀ5

94

ꢀ9.5

dꢁ

REF

= 2kHz, V = 2.5V, (H-Grade)

REF

l

THD

Total Harmonic Distortion

f

ꢂI

f

ꢂI

= 2kHz, V = 5V

–112

–100

–96

dꢁ

REF

= 2kHz, V = 2.5V

REF

l

SFDR

Spurious Free Dynamic Range

–3dꢁ ꢂnput ꢁandwidth

Aperture Delay

f

= 2kHz, V = 5V

100

113

34

dꢁ

MHz

ps

ꢂI

REF

500

4

Aperture Jitter

ps

Transient Response

Full-Scale Step

165

ns

237016fa

3

LTC2370-16

REFERENCE INPUT ^Thel denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at T_A= 28°C0 ꢁNote 4x

SYMꢀO5

PARAMETER

CONDITIONS

(Iote 5)

MIN

TYP

MAX

5.1

UNITS

V

l

V

Reference Voltage

Reference ꢂnput Current

2.5

REF

ꢂ

(Iote 9)

1.1

1.3

mA

DIGITAL INPUTS AND DIGITAL OUTPUTS ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 28°C0 ꢁNote 4x

SYMꢀO5 PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

l

V

High Level ꢂnput Voltage

Low Level ꢂnput Voltage

Digital ꢂnput Current

0.8 • OV

ꢂH

ꢂL

DD

0.2 • OV

V

DD

ꢂ

V

= 0V to OV

DD

–10

10

µA

pF

ꢂI

C

V

Digital ꢂnput Capacitance

High Level Output Voltage

Low Level Output Voltage

Hi-Z Output Leakage Current

Output Source Current

Output Sink Current

5

ꢂI

l

ꢂ = –500µA

O

OV – 0.2

DD

V

OH

OL

ꢂ = 500µA

O

0.2

10

V

ꢂ

V

= 0V to OV

DD

–10

µA

mA

OZ

OUT

= 0V

= OV

–10

10

SOURCE

SꢂIK

DD

POWER REQUIREMENTS ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 28°C0 ꢁNote 4x

SYMꢀO5

PARAMETER

Supply Voltage

CONDITIONS

MIN

2.375

1.71

TYP

MAX

2.625

5.25

ꢀ.ꢀ

UNITS

l

V

2.5

V

DD

OV

DD

ꢂ

Supply Current

Power Down Mode

2Msps Sample Rate

7.5

0.9

mA

µA

VDD

OVDD

PD

2Msps Sample Rate (C = 20pF)

L

l

Conversion Done (ꢂ

+ ꢂ

+ ꢂ , V > 2V)

REF REF

90

140

VDD

OVDD

REF REF

+ ꢂ , V > 2V, H-Grade)

µA

PD

P

Power Dissipation

Power Down Mode

2Msps Sample Rate

19

2.25

22

225

315

mW

µW

D

Conversion Done (ꢂ

+ ꢂ

OVDD

+ ꢂ

OVDD

+ ꢂ , V > 2V)

REF REF

VDD

REF REF

+ ꢂ , V > 2V, H-Grade)

ADC TIMING CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 28°C0 ꢁNote 4x

SYMꢀO5

PARAMETER

CONDITIONS

MIN

TYP

MAX

2

UNITS

Msps

ns

l

f

t

Maximum Sampling Frequency

Conversion Time

SMPL

COIV

ACQ

27ꢀ

165

500

20

322

Acquisition Time

t

= t

– t

– t (Iote 10)

ꢁUSYLH

ns

ACQ

CYC

COIV

Time ꢁetween Conversions

CIV High Time

ns

CYC

ns

CIVH

ꢁUSYLH

CIVL

QUꢂET

SCK

C = 20pF

L

13

ns

CIV↑ to ꢁUSY Delay

Minimum Low Time for CIV

SCK Quiet Time from CIV↑

SCK Period

(Iote 11)

(Iote 10)

20

10

4

ns

(Iotes 11, 12)

ns

SCK High Time

ns

SCKH

237016fa

4

LTC2370-16

ADC TIMING CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 28°C0 ꢁNote 4x

SYMꢀO5

PARAMETER

CONDITIONS

MIN

4

TYP

MAX

UNITS

ns

l

t

SCK Low Time

SCKL

(Iote 11)

4

ns

SDꢂ Setup Time From SCK↑

SDꢂ Hold Time From SCK↑

SCK Period in Chain Mode

SDO Data Valid Delay from SCK↑

SDO Data Remains Valid Delay from SCK↑

SDO Data Valid Delay from ꢁUSY↓

ꢁus Enable Time After RDL↓

ꢁus Relinquish Time After RDL↑

SSDꢂSCK

HSDꢂSCK

SCKCH

DSDO

1

ns

t

= t

+ t (Iote 11)

DSDO

13.5

ns

SCKCH

SSDꢂSCK

C = 20pF (Iote 11)

L

9.5

ns

C = 20pF (Iote 10)

L

1

ns

HSDO

C = 20pF (Iote 10)

L

5

ns

DSDOꢁUSYL

EI

(Iote 11)

16

13

ns

DꢂS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may effect device

reliability and lifetime.

Note 7: Zero-scale error is the offset voltage measured from 0.5LSꢁ

when the output code flickers between 0000 0000 0000 0000 and

0000 0000 0000 0001. Full-scale error is the deviation of the last code

transition from ideal and includes the effect of offset error.

Note 2: All voltage values are with respect to ground.

Note 3: When these pin voltages are taken below ground or above REFor

Note .: All specifications in dꢁ are referred to a full-scale 5V input with a

5V reference voltage.

OV , they will be clamped by internal diodes. This product can handle

DD

Note 9: f

= 2MHz, ꢂ varies proportionately with sample rate.

SMPL REF

input currents up to 100mA below ground or above REFor OV without

latch-up.

DD

Note 1±: Guaranteed by design, not subject to test.

Note 11: Parameter tested and guaranteed at OV = 1.71V, OV = 2.5V

DD

Note 4: V = 2.5V, OV = 2.5V, REF = 5V, f = 2MHz.

SMPL

DD

and OV = 5.25V.

DD

Note 8: Recommended operating conditions.

Note 12: t

of 10ns maximum allows a shift clock frequency up to

SCK

Note 6: ꢂntegral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

100MHz for rising capture.

0.8*OV

DD

t

WIDTH

0.2*OV

DD

50%

t

DELAY

237016 F01

0.8*OV

0.2*OV

0.8*OV

0.2*OV

DD

Figure 10 Voltage 5evels for Timing Specifications

237016fa

5

LTC2370-16

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 28°C, V}_DD= 208V, OV_DD= 208V, REF = 8V,

f_SMP5= 2Msps, unless otherwise noted0

Integral Nonlinearity

vs Output Code

Differential Nonlinearity

vs Output Code

DC Histogram

1.0

0.8

0.5

0.4

100000

90000

σ = 0.5

0.6

0.3

80000

70000

60000

0.4

0.2

0.1

0.0

50000

40000

–0.2

–0.4

–0.6

–0.8

–1.0

–0.1

–0.2

–0.3

–0.4

–0.5

30000

20000

10000

0

16384

32768

49152

65536

0

16384

32768

49152

65536

32676 32677 32678 32679 32680

CODE

OUTPUT CODE

237016 G01

237016 G02

237016 G03

THD, Harmonics

32k Point FFT f_S= 2Msps,

f_IN= 2kHz

vs Input Frequency

SNR, SINAD vs Input Frequency

–60

–70

0

–20

100

95

90

85

80

75

70

SNR = 94dB

THD = –112dB

SINAD = 93.9dB

SFDR = 117dB

SNR

–80

–40

–90

–60

THD

2ND

–100

–110

–120

–130

–140

–150

–160

SINAD

–80

–100

–120

–140

–160

–180

3RD

125 150

0

25 50 75 100

175 200

0

100 200 300 400 500 600 700 800 9001000

0

175

200

25 50 75 100 125 150

FREQUENCY (kHz)

237016 G04

237016 G05

237016 G06

SNR, SINAD vs Input level,

f_IN= 2kHz

SNR, SINAD vs Reference

Voltage, f_IN= 2kHz

THD, Harmonics vs Reference

Voltage, f_IN= 2kHz

95.0

94.5

94.0

93.5

93.0

–100

–105

–110

–115

–120

–125

–130

–135

–140

–145

–150

95

94

93

92

91

90

89

THD

2ND

SNR

SINAD

SNR

SINAD

3RD

–40

–30

–20

–10

0

3

3.5

4

5

2.5

3

3.5

4

4.5

5

2.5

4.5

INPUT LEVEL (dB)

REFERENCE VOLTAGE (V)

237016 G07

237016 G09

237016 G08

237016fa

6

LTC2370-16

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 28°C, V}_DD= 208V, OV_DD= 208V, REF = 8V,

f_SMP5= 2Msps, unless otherwise noted0

SNR, SINAD vs Temperature,

f_IN= 2kHz

THD, Harmonics vs Temperature,

f_IN= 2kHz

IN5/DN5 vs Temperature

95.0

94.5

94.0

93.5

93.0

92.5

92.0

1.0

0.5

0

–100

–105

–110

–115

–120

–125

–130

–135

–140

THD

2ND

SNR

MAX INL

MAX DNL

SINAD

MIN DNL

MIN INL

3RD

–0.5

–1.0

25 45

TEMPERATURE (°C)

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

65 85 105 125

–55

5

85

125

105

–35 –15

25 45 65

TEMPERATURE (°C)

237016 G10

237016 G12

237016 G11

Full-Scale Error vs Temperature

Offset Error vs Temperature

Supply Current vs Temperature

15

10

5

4

3

8

7

6

5

4

3

2

1

0

I

VDD

2

1

0

–1

–2

–3

–4

–5

–10

–15

I

REF

I

OVDD

25 45

TEMPERATURE (°C)

–55 –35 –15

5

65 85 105 125

–55 –35 –15

5

25 45 65

85 105

125

–55 –35 –15

5

25 45 65 85 105 125

TEMPERATURE (°C)

237016 G15

237016 G13

237016 G14

Reference Current

vs Reference Voltage

Shutdown Current vs Temperature

CMRR vs Input Frequency

45

40

35

30

25

20

15

10

5

100

95

90

85

80

75

70

1.2

1.0

0.8

0.6

0.4

0.2

0

I

+ I

VDD OVDD REF

0

200

400

600

800

1000

–55 –35 –15

5

25 45 65 85 105 125

2.5

4.5

5

3

3.5

4

FREQUENCY (kHz)

TEMPERATURE (°C)

REFERENCE VOLTAGE (V)

237016 G16

237016 G17

237016 G18

237016fa

7

LTC2370-16

PIN FUNCTIONS

CHAIN ꢁPin 1x: Chain Mode Selector Pin. When low, the

LTC2370-16 operates in normal mode and the RDL/SDꢂ

input pin functions to enable or disable SDO. When high,

the LTC2370-16 operates in chain mode and the RDL/SDꢂ

pin functions as SDꢂ, the daisy-chain serial data input.

ꢀUSY ꢁPin 11x: ꢁUSY ꢂndicator. Goes high at the start of

a new conversion and returns low when the conversion

has finished. Logic levels are determined by OV .

DD

RD5/SDI ꢁPin 12x: When CHAꢂI is low, the part is in nor-

mal mode and the pin is treated as a bus enabling input.

When CHAꢂI is high, the part is in chain mode and the

pin is treated as a serial data input pin where data from

another ADC in the daisy chain is input. Logic levels are

Logic levels are determined by OV .

DD

V

ꢁPin 2x: 2.5V Power Supply. The range of V is

DD

2.375Vto2.625V. ꢁypassV toGIDwitha10µFceramic

DD

capacitor.

determined by OV .

DD

GND ꢁPins 3, 6, 1± and 16x: Ground.

SCKꢁPin13x:SerialDataClockꢂnput.WhenSDOisenabled,

the conversion result or daisy-chain data from another

ADC is shifted out on the rising edges of this clock MSꢁ

+

–

IN ꢁPin 4x: Analog ꢂnput. ꢂI operates differential with

–

+

respect to ꢂI with an ꢂI -ꢂI range of 0V to V

.

REF

first. Logic levels are determined by OV .

DD

–

IN ꢁPin 8x: Analog Ground Sense. ꢂI has an input range

of 100mV with respect to GID and must be tied to the

ground plane or a remote ground sense.

SDO ꢁPin 14x: Serial Data Output. The conversion result

or daisy-chain data is output on this pin on each rising

edgeofSCKMSꢁfirst. Theoutputdataisinstraightbinary

REFꢁPins7,.x:Referenceꢂnputs.TherangeofREFis2.5V

to 5.1V. This pin is referred to the GID pin and should be

decoupledcloselytothepinwitha47µFceramiccapacitor

(X5R, 0ꢀ05 size).

format. Logic levels are determined by OV .

DD

OV ꢁPin 18x: ꢂ/O ꢂnterface Digital Power. The range of

DD

OV is 1.71V to 5.25V. This supply is nominally set to

DD

the same supply as the host interface (1.ꢀV, 2.5V, 3.3V,

CNV ꢁPin 9x: Convert ꢂnput. A rising edge on this input

or 5V). ꢁypass OV to GID with a 0.1µF capacitor.

DD

powers up the part and initiates a new conversion. Logic

GND ꢁEꢂposed Pad Pin 17, DFN Package Onlyx: Ground.

Exposedpadmustbesoldereddirectlytothegroundplane.

levels are determined by OV .

DD

237016fa

8

LTC2370-16

FUNCTIONAL BLOCK DIAGRAM

V

= 2.5V

DD

OV = 1.8V to 5V

DD

REF = 5V

CHAIN

SDO

RDL/SDI

SCK

+

IN

+

SPI

PORT

16-BIT SAMPLING ADC

–

IN

–

CNV

CONTROL LOGIC

BUSY

GND

237016 BD

TIMING DIAGRAM

Conversion Timing Using the Serial Interface

CHAIN, RDL/SDI = 0

CNV

CONVERT

POWER-DOWN AND ACQUIRE

BUSY

SCK

SDO

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

237016 TD01

237016fa

9

LTC2370-16

APPLICATIONS INFORMATION

OVERVIEW

1LSB = FS/65536

111...111

111...110

111...101

111...100

TheLTC2370-16isalownoise,lowpower,highspeed16-bit

successive approximation register (SAR) ADC. Operating

from a single 2.5V supply, the LTC2370-16 supports a

0V to V

REF

pseudo-differential unipolar input range with

REF

V

ranging from 2.5V to 5.1V, making it ideal for high

UNIPOLAR

ZERO

performance applications which require a wide dynamic

range. The LTC2370-16 achieves 0.ꢀ5LSꢁ ꢂIL max, no

missing codes at 16 bits and 94dꢁ SIR.

000...011

000...010

000...001

000...000

0V

1

FS – 1LSB

Fast 2Msps throughput with no cycle latency makes the

LTC2370-16 ideally suited for a wide variety of high speed

applications.Aninternaloscillatorsetstheconversiontime,

easing external timing considerations. The LTC2370-16

dissipatesonly19mWat2Msps,whileanautopower-down

feature is provided to further reduce power dissipation

during inactive periods.

LSB

INPUT VOLTAGE (V)

237016 F02

Figure 20 5TC237±-16 Transfer Function

ANA5OG INPUT

TheanaloginputsoftheLTC2370-16arepseudo-differential

in order to reduce any unwanted signal that is common

to both inputs. The analog inputs can be modeled by the

equivalentcircuitshowninFigure3.Thediodesattheinput

provide ESD protection. ꢂn the acquisition phase, each

CONVERTER OPERATION

The LTC2370-16 operates in two phases. During the ac-

quisition phase, the charge redistribution capacitor D/A

input sees approximately 45pF (C ) from the sampling

ꢂI

CDAC in series with 40Ω (R ) from the on-resistance

OI

+

–

+

converter (CDAC) is connected to the ꢂI and ꢂI pins to

sample the pseudo-differential analog input voltage. A ris-

ing edge on the CIV pin initiates a conversion. During the

conversionphase,the16-bitCDACissequencedthrougha

successiveapproximationalgorithm,effectivelycomparing

the sampled input with binary-weighted fractions of the

of the sampling switch. The ꢂI input draws a current

spike while charging the C capacitor during acquisition.

ꢂI

During conversion, the analog inputs draw only a small

leakage current.

REF

C

IN

R

40Ω

ON

45pF

referencevoltage(e.g.V /2,V /4…V /65536)using

REF

+

IN

the differential comparator. At the end of conversion, the

CDAC output approximates the sampled analog input. The

ADC control logic then prepares the 16-bit digital output

code for serial transfer.

BIAS

VOLTAGE

REF

C

IN

R

40Ω

ON

45pF

–

237016 F03

TRANSFER FUNCTION

The LTC2370-16 digitizes the full-scale voltage of REF

16

into 2 levels, resulting in an LSꢁ size of 76µV with

Figure 30 The Equivalent Circuit for the

Differential Analog Input of the 5TC237±-16

REF = 5V. The ideal transfer function is shown in Figure 2.

The output data is in straight binary format.

237016fa

10

LTC2370-16

APPLICATIONS INFORMATION

INPUT DRIVE CIRCUITS

Highqualitycapacitorsandresistorsshouldbeusedinthe

RCfilterssincethesecomponentscanadddistortion.IPO

and silver mica type dielectric capacitors have excellent

linearity. Carbon surface mount resistors can generate

distortion from self heating and from damage that may

occurduringsoldering.Metalfilmsurfacemountresistors

are much less susceptible to both problems.

A low impedance source can directly drive the high im-

pedance input of the LTC2370-16 without gain error. A

high impedance source should be buffered to minimize

settling time during acquisition and to optimize the dis-

tortion performance of the ADC. Minimizing settling time

is important even for DC inputs, because the ADC input

draws a current spike when entering acquisition.

Pseudo-Differential Unipolar Inputs

For best performance, a buffer amplifier should be used

to drive the analog input of the LTC2370-16. The ampli-

fier provides low output impedance, which produces fast

settling of the analog signal during the acquisition phase.

ꢂt also provides isolation between the signal source and

the current spike the ADC input draws.

For most applications, we recommend the low power

LT6202 ADC driver to drive the LTC2370-16. With a low

noise density of 1.9nV/√Hz and a low supply current of

3mA, the LT6202 is flexible and may be configured to

convertsignals of variousamplitudes to the 0V to5V input

range of the LTC2370-16.

To achieve the full distortion performance of the

LTC2370-16, a low distortion single-ended signal source

driven through the LT6202 configured as a unity-gain buf-

fer as shown in Figure 4 can be used to get the full data

sheet THD specification of –112dꢁ.

Input Filtering

The noise and distortion of the buffer amplifier and signal

sourcemustbeconsideredsincetheyaddtotheADCnoise

and distortion. Ioisy input signals should be filtered prior

to the buffer amplifier input with an appropriate filter to

minimizenoise.Thesimple1-poleRClowpassfilter(LPF1)

shown in Figure 4 is sufficient for many applications.

The LT6202 can also be used to buffer and convert large

true bipolar signals which swing below ground to the 0V

to 5V input range of the LTC2370-16. Figure 5a shows the

LT6202 being used to convert a 10V true bipolar signal

for use by the LTC2370-16. ꢂn this case, the LT6202 is

configured as an inverting amplifier stage, which acts to

attenuateandlevelshifttheinputsignaltothe0Vto5Vinput

rangeoftheLTC2370-16.ꢂntheinvertingconfiguration,the

single-ended input signal source no longer directly drives

a high impedance input. The input impedance is instead

LPF1

50Ω

LPF2

V

REF

+

–

5.1Ω

10nF

0V

+

–

66nF

BW = 48kHz

IN

LT6202

LTC2370-16

IN

237016 F04

BW = 3.2MHz

Figure 40 Input Signal Chain

set by resistor R . R must be chosen carefully based on

ꢂI ꢂI

the source impedance of the signal source. Higher values

Another filter network consisting of LPF2 should be used

between the buffer and ADC input to both minimize the

noisecontributionofthebufferandtohelpminimizedistur-

bances reflected into the buffer from sampling transients.

Long RC time constants at the analog inputs will slow

down the settling of the analog inputs. Therefore, LPF2

requires a wider bandwidth than LPF1. A buffer amplifier

with a low noise density must be selected to minimize

degradation of the SIR.

of R tend to degrade both the noise and distortion of

ꢂI

the LT6202 and LTC2370-16 as a system. Table 1 shows

the resulting SIR and THD for several values of R , R1,

ꢂI

R2, R3 and R4 in this configuration. Figure 5b shows the

resultingFFTwhenusingtheLT6202asshowninFigure5a.

237016fa

11

LTC2370-16

APPLICATIONS INFORMATION

V

= V /2

REF

200pF

CM

ADC REFERENCE

The LTC2370-16 requires an external reference to define

its input range. A low noise, low temperature drift refer-

enceiscriticaltoachievingthefulldatasheetperformance

of the ADC. Linear Technology offers a portfolio of high

performance references designed to meet the needs of

many applications. With its small size, low power and

highaccuracy, theLTC6655-5isparticularlywellsuitedfor

use with the LTC2370-16. The LTC6655-5 offers 0.025%

(max) initial accuracy and 2ppm/°C (max) temperature

coefficient for high precision applications. The LTC6655-5

is fully specified over the H-grade temperature range and

complements the extended temperature operation of the

LTC2370-16 up to 125°C. We recommend bypassing the

LTC6655-5witha47µFceramiccapacitor(X5R,0ꢀ05size)

close to the REF pin.

R2

R4

499Ω

402Ω

3

4

+

–

5V

0V

R3

2k

10µF

LT6202

R1

1

R

IN

2k

10V

0V

–10V

499Ω

200pF

237016 F05a

Figure 8a0 5T62±2 Converting a ±1±V ꢀipolar Signal

to a ±V to 8V Input Signal

0

SNR = 93.9dB

–20

THD = –97.8dB

SINAD = 91.4dB

–40

SFDR = 99.6dB

–60

–80

TheREFpinoftheLTC2370-16drawscharge(Q

)from

COIV

–100

–120

–140

–160

the 47µF bypass capacitor during each conversion cycle.

The reference replenishes this charge with a DC current,

ꢂ

= Q

/t . The DC current draw of the REF pin,

, depends on the sampling rate and output code. ꢂf

the LTC2370-16 is used to continuously sample a signal

at a constant rate, the LTC6655-5 will keep the deviation

of the reference voltage over the entire code span to less

than 0.5LSꢁs.

REF

COIV CYC

–180

400 500

0

100 200 300

600 700 800 9001000

FREQUENCY (kHz)

237016 F05b

Figure 8b0 32k Point FFT Plot with f_IN= 2kHz

for Circuit Shown in Figure 8a

When idling, the REF pin on the LTC2370-16 draws only

a small leakage current (< 1µA). ꢂn applications where a

burst of samples is taken after idling for long periods as

Table 10 SNR, THD vs R_INfor ±1±V Input Signal

R

R1

ꢁΩx

R2

ꢁΩx

R3

ꢁΩx

R4

ꢁΩx

SNR

ꢁdꢀx

THD

ꢁdꢀx

IN

shown in Figure 6, ꢂ quickly goes from approximately

REF

ꢁΩx

0µA to a maximum of 1.3mA at 2Msps. This step in DC

current draw triggers a transient response in the reference

that must be considered since any deviation in the refer-

ence output voltage will affect the accuracy of the output

2k

499

2k

402

2k

93.9

94

–97.ꢀ

–92.9

–93.2

10k

100k

2.49k

24.9k

2.49k

24.9k

10k

100k

20k

92.2

CNV

237016 F06

IDLE

PERIOD

IDLE

PERIOD

Figure 60 CNV Waveform Showing ꢀurst Sampling

237016fa

12

LTC2370-16

APPLICATIONS INFORMATION

code. ꢂn applications where the transient response of the

reference is important, the fast settling LTC6655-5 refer-

ence is also recommended.

0

–20

SNR = 94dB

THD = –112dB

SINAD = 93.9dB

SFDR = 117dB

–40

–60

ꢂn applications where power management is critical and

the external reference may be powered down, it is rec-

ommended that REF is kept greater than 2V in order to

guaranteeamaximumshutdowncurrentof140µA.ꢂnsuch

applications, a Schottky diode can be placed between REF

–80

–100

–120

–140

–160

–180

and V , as shown in Figure 7.

DD

0

100 200 300 400 500 600 700 800 9001000

FREQUENCY (kHz)

237016 F08

REF

V

DD

Figure .0 32k Point FFT with f_IN= 2kHz of the 5TC237±-16

LTC2370-16

the RMS amplitude of all other frequency components

except the first five harmonics and DC. Figure ꢀ shows

that the LTC2370-16 achieves a typical SIR of 94dꢁ at a

2MHz sampling rate with a 2kHz input.

237016 F07

Figure 70 A Schottky Diode ꢀetween REF and V_DDMaintains

REF > 2V for Applications Where the Reference May ꢀe

Powered Down

Total Harmonic Distortion ꢁTHDx

TotalHarmonicDistortion(THD)istheratiooftheRMSsum

ofallharmonicsoftheinputsignaltothefundamentalitself.

The out-of-band harmonics alias into the frequency band

DYNAMIC PERFORMANCE

Fast Fourier Transform (FFT) techniques are used to test

the ADC’s frequency response, distortion and noise at the

rated throughput. ꢁy applying a low distortion sine wave

and analyzing the digital output using an FFT algorithm,

the ADC’s spectral content can be examined for frequen-

cies outside the fundamental. The LTC2370-16 provides

guaranteed tested limits for both AC distortion and noise

measurements.

between DC and half the sampling frequency (f

THD is expressed as:

/2).

SMPL

V2²+ V3²+ V4²+…+ V_I²

THD= 20log

V1

where V1 is the RMS amplitude of the fundamental fre-

quencyandV2throughV aretheamplitudesofthesecond

I

Signal-to-Noise and Distortion Ratio ꢁSINADx

through Ith harmonics.

The signal-to-noise and distortion ratio (SꢂIAD) is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency and the RMS amplitude of all other frequency

components at the A/D output. The output is band-limited

tofrequenciesfromaboveDCandbelowhalfthesampling

frequency. Figure ꢀ shows that the LTC2370-16 achieves

a typical SꢂIAD of 93.9dꢁ at a 2MHz sampling rate with

a 2kHz input.

POWER CONSIDERATIONS

The LTC2370-16 provides two power supply pins: the

2.5V power supply (V ), and the digital input/output

DD

interface power supply (OV ). The flexible OV supply

DD

allows the LTC2370-16 to communicate with any digital

logic operating between 1.ꢀV and 5V, including 2.5V and

3.3V systems.

Signal-to-Noise Ratio ꢁSNRx

The signal-to-noise ratio (SIR) is the ratio between the

RMS amplitude of the fundamental input frequency and

237016fa

13

LTC2370-16

APPLICATIONS INFORMATION

Power Supply Sequencing

power down, disable SDO and turn off SCK. The auto

power-down feature will reduce the power dissipation of

the LTC2370-16 as the sampling frequency is reduced.

Since power is consumed only during a conversion, the

LTC2370-16remainspowereddownforalargerfractionof

The LTC2370-16 does not have any specific power supply

sequencing requirements. Care should be taken to adhere

to the maximum voltage relationships described in the

Absolute Maximum Ratings section. The LTC2370-16

has a power-on-reset (POR) circuit that will reset the

LTC2370-16 at initial power-up or whenever the power

supply voltage drops below 1V. Once the supply voltage

re-enters the nominal supply voltage range, the POR will

reinitialize the ADC. Io conversions should be initiated

until 20µs after a POR event to ensure the reinitialization

period has ended. Any conversions initiated before this

time will produce invalid results.

the conversion cycle (t ) at lower sample rates, thereby

CYC

reducing the average power dissipation which scales with

the sampling rate as shown in Figure 9.

DIGITA5 INTERFACE

The LTC2370-16 has a serial digital interface. The flexible

OV supply allows the LTC2370-16 to communicate with

DD

any digital logic operating between 1.ꢀV and 5V, including

2.5V and 3.3V systems.

TIMING AND CONTRO5

CNV Timing

The serial output data is clocked out on the SDO pin when

anexternalclockisappliedtotheSCKpinifSDOisenabled.

Clocking out the data after the conversion will yield the

best performance. With a shift clock frequency of at least

100MHz, a 2Msps throughput is still achieved. The serial

output data changes state on the rising edge of SCK and

can be captured on the falling edge or next rising edge of

SCK. D15 remains valid till the first rising edge of SCK.

The LTC2370-16 conversion is controlled by CIV. A ris-

ing edge on CIV will start a conversion and power up the

LTC2370-16.Onceaconversionhasbeeninitiated,itcannot

berestarteduntiltheconversioniscomplete.Foroptimum

performance, CIV should be driven by a clean low jitter

signal. Converter status is indicated by the ꢁUSY output

which remains high while the conversion is in progress.

To ensure that no errors occur in the digitized results, any

additional transitions on CIV should occur within 40ns

from the start of the conversion or after the conversion

has been completed. Once the conversion has completed,

the LTC2370-16 powers down and begins acquiring the

input signal.

The serial interface on the LTC2370-16 is simple and

straightforwardtouse.Thefollowingsectionsdescribethe

operation of the LTC2370-16. Several modes are provided

depending on whether a single or multiple ADCs share the

SPꢂ bus or are daisy chained.

8

7

6

5

Internal Conversion Clock

The LTC2370-16 has an internal clock that is trimmed to

achieveamaximumconversiontimeof322ns.Withamin-

imum acquisition time of 165ns, throughput performance

of 2Msps is guaranteed without any external adjustments.

I

VDD

4

3

2

1

0

I

REF

Auto Power-Down

OVDD

800

SAMPLING RATE (kHz)

0

400

1200

1600

2000

The LTC2370-16 automatically powers down after a

conversion has been completed and powers up once a

new conversion is initiated on the rising edge of CIV.

During power down, data from the last conversion can

be clocked out. To minimize power dissipation during

237016 F09

Figure 90 Power Supply Current of the 5TC237±-16

Versus Sampling Rate

237016fa

14

LTC2370-16

TIMING DIAGRAMS

Normal Mode, Single Device

Figure 10 shows a single LTC2370-16 operated in normal

mode with CHAꢂI and RDL/SDꢂ tied to ground. With

RDL/SDꢂ grounded, SDO is enabled and the MSꢁ(D15) of

the new conversion data is available at the falling edge of

ꢁUSY. ThisisthesimplestwaytooperatetheLTC2370-16.

When CHAꢂI = 0, the LTC2370-16 operates in normal

mode. ꢂn normal mode, RDL/SDꢂ enables or disables the

serial data output pin SDO. ꢂf RDL/SDꢂ is high, SDO is in

high impedance. ꢂf RDL/SDꢂ is low, SDO is driven.

CONVERT

DIGITAL HOST

IRQ

CNV

CHAIN

BUSY

LTC2370-16

RDL/SDI

SDO

DATA IN

CLK

SCK

POWER-DOWN

AND ACQUIRE

CONVERT

POWER-DOWN AND ACQUIRE

CONVERT

CHAIN = 0

RDL/SDI = 0

t

CYC

t

CNVH

t

CNVL

CNV

t

= t

– t

ACQ CYC CONV BUSYLH

t

CONV

ACQ

BUSY

t

SCK

t

BUSYLH

t

QUIET

SCKH

1

2

3

14

15

16

SCK

SDO

t

SCKL

HSDO

t

DSDO

DSDOBUSYL

D15

D14

D13

D1

D0

237016 F10

Figure 1±0 Using a Single 5TC237±-16 in Normal Mode

237016fa

15

LTC2370-16

TIMING DIAGRAMS

Normal Mode, Multiple Devices

be used to allow only one LTC2370-16 to drive SDO at a

timeinordertoavoidbusconflicts. AsshowninFigure11,

the RDL/SDꢂ inputs idle high and are individually brought

low to read data out of each device between conversions.

When RDL/SDꢂ is brought low, the MSꢁ of the selected

device is output onto SDO.

Figure 11 shows multiple LTC2370-16 devices operating

in normal mode (CHAꢂI = 0) sharing CIV, SCK and SDO.

ꢁy sharing CIV, SCK and SDO, the number of required

signals to operate multiple ADCs in parallel is reduced.

Since SDO is shared, the RDL/SDꢂ input of each ADC must

RDL

B

A

CONVERT

CNV

CHAIN

BUSY

SDO

IRQ

CHAIN

LTC2370-16

B

LTC2370-16

A

DIGITAL HOST

SDO

RDL/SDI

SCK

DATA IN

CLK

POWER-DOWN

AND ACQUIRE

CONVERT

POWER-DOWN AND ACQUIRE

CHAIN = 0

t

CNVL

CNV

t

CONV

BUSY

t

BUSYLH

RDL/SDI

A

B

RDL/SDI

t

SCK

t

QUIET

SCKH

17

SCK

SDO

1

2

3

14

15

16

18

19

30

31

32

t

HSDO

SCKL

t

DSDO

DIS

t

EN

Hi-Z

D15

D14

D13

D1

D0

A

D15

D14

D13

D1

D0

B

A

B

237016 F11

Figure 110 Normal Mode With Multiple Devices Sharing CNV, SCK and SDO

237016fa

16

LTC2370-16

TIMING DIAGRAMS

Chain Mode, Multiple Devices

number of converters. Figure 12 shows an example with

two daisy-chained devices. The MSꢁ of converter A will

appear at SDO of converter ꢁ after 16 SCK cycles. The

MSꢁ of converter A is clocked in at the SDꢂ/RDL pin of

converter ꢁ on the rising edge of the first SCK.

When CHAꢂI = OV , the LTC2370-16 operates in

DD

chain mode. ꢂn chain mode, SDO is always enabled and

RDL/SDꢂ serves as the serial data input pin (SDꢂ) where

daisy-chain data output from another ADC can be input.

This is useful for applications where hardware constraints

maylimitthenumberoflines neededtointerface to a large

CONVERT

OV

DD

OV

DD

CNV

DIGITAL HOST

CHAIN

LTC2370-16

RDL/SDI

SDO

RDL/SDI

BUSY

SDO

IRQ

A

B

DATA IN

SCK

CLK

POWER-DOWN

AND ACQUIRE

CONVERT

POWER-DOWN AND ACQUIRE

CONVERT

CHAIN = OV

DD

RDL/SDI = 0

A

t

CYC

t

CNVL

CNV

BUSY

t

CONV

t

BUSYLH

t

SCKCH

t

SCKH

QUIET

SCK

1

2

3

14

15

16

17

18

30

31

32

t

SCKL

t

SSDISCK

HSDO

t

DSDO

HSDISCK

SDO = RDL/SDI

A

B

D15

D14

D13

D1

D0

A

t

DSDOBUSYL

D13

D1

B

D0

D15

D14

D1

D0

A

SDO

B

A

B

237016 F12

Figure 120 Chain Mode Timing Diagram

237016fa

17

LTC2370-16

BOARD LAYOUT

To obtain the best performance from the LTC2370-16

a printed circuit board is recommended. Layout for the

printed circuit board (PCꢁ) should ensure the digital and

analog signal lines are separated as much as possible. ꢂn

particular,careshouldbetakennottorunanydigitalclocks

orsignalsalongsideanalogsignalsorunderneaththeADC.

Recommended 5ayout

ThefollowingisanexampleofarecommendedPCꢁlayout.

A single solid ground plane is used. ꢁypass capacitors to

the supplies are placed as close as possible to the supply

pins. Low impedance common returns for these bypass

capacitors are essential to the low noise operation of the

ADC. The analog input traces are screened by ground.

For more details and information refer to DC1ꢀ13A, the

evaluation kit for the LTC2370-16.

Partial Top Silkscreen

237016fa

18

LTC2370-16

BOARD LAYOUT

Partial 5ayer 1 Component Side

Partial 5ayer 2 Ground Plane

237016fa

19

LTC2370-16

BOARD LAYOUT

Partial 5ayer 3 PWR Plane

Partial 5ayer 4 ꢀottom 5ayer

237016fa

20

LTC2370-16

BOARD LAYOUT

Partial Schematic of Demoboard

R E F

8

R E F

1

G N D

7

1 5

2

D D

G N D 1 6

O V

G N D

1 0

V

G N D

6

3

2

1

3

2

1

237016fa

21

LTC2370-16

PACKAGE DESCRIPTION

Please refer to http://www0linear0com/designtools/packaging/ for the most recent package drawings0

DE Package

16-Lead Plastic DFN (4mm × 3mm)

(Reference LTC DWG # 05-08-ꢀ732 Rev Ø)

R = 0.ꢀꢀ5

TYP

0.40 0.ꢀ0

4.00 0.ꢀ0

(2 SIDES)

9

ꢀ6

R = 0.05

0.70 0.05

TYP

3.30 0.ꢀ0

3.30 0.05

ꢀ.70 0.05

3.60 0.05

2.20 0.05

3.00 0.ꢀ0

(2 SIDES)

PACKAGE

OUTLINE

ꢀ.70 0.ꢀ0

PIN ꢀ NOTCH

R = 0.20 OR

PIN ꢀ

TOP MARK

0.35 × 45°

CHAMFER

(DEꢀ6) DFN 0806 REV Ø

(SEE NOTE 6)

8

ꢀ

0.23 0.05

0.45 BSC

0.75 0.05

0.200 REF

0.25 0.05

0.45 BSC

3.ꢀ5 REF

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

NOTE:

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

ꢀ. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC

PACKAGE OUTLINE MO-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

MS Package

16-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1669 Rev Ø)

4.039 ± 0.102

(.159 ± .004)

(NOTE 3)

0.280 ± 0.076

(.011 ± .003)

REF

16151413121110

9

0.889 ± 0.127

(.035 ± .005)

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

DETAIL “A”

0° – 6° TYP

4.90 ± 0.152

(.193 ± .006)

0.254

(.010)

GAUGE PLANE

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

0.53 ± 0.152

(.021 ± .006)

1 2 3 4 5 6 7 8

0.86

(.034)

REF

1.10

(.043)

MAX

DETAIL “A”

0.18

(.007)

0.50

(.0197)

BSC

0.305 ± 0.038

(.0120 ± .0015)

SEATING

PLANE

TYP

0.17 – 0.27

(.007 – .011)

TYP

0.1016 ± 0.0508

(.004 ± .002)

MSOP (MS16) 1107 REV Ø

RECOMMENDED SOLDER PAD LAYOUT

0.50

(.0197)

BSC

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

237016fa

22

LTC2370-16

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMꢀER

A

03/12 Updated conditions for ꢂ and P in Power Requirements section

4

PD

D

Added Figure 7 and associated text

Updated Related Parts

13

24

237016fa

ꢂnformation furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

23

LTC2370-16

TYPICAL APPLICATION

5T62±2 Converting a ±1±V ꢀipolar Signal to a ±V to 8V Input Signal Into the 5TC237±-16

LTC6655-5

V

8V

IN

OUT_F

OUT_S

5V

200pF

47µF

R2

3k

5

R4

402Ω

LT6202

+

2.5V

V

5V

0V

3

4

+

REF

V

DD

5.1Ω

R3

2k

+

–

10µF

1

IN

10nF

LTC2370-16

–

V

2

237016 TA02

R

R1

IN

–3V

10V

2k

499Ω

0V

–10V

220pF

RELATED PARTS

PART NUMꢀER

DESCRIPTION

COMMENTS

ADCs

LTC2379-1ꢀ/LTC237ꢀ-1ꢀ 1ꢀ-ꢁit, 1.6Msps/1Msps/500ksps/250ksps Serial, Low 2.5V Supply, Differential ꢂnput, 101.2dꢁ SIR, 5V ꢂnput Range, DGC,

LTC2377-1ꢀ/LTC2376-1ꢀ Power ADC

Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFI-16 Packages

LTC23ꢀ0-16/LTC237ꢀ-16 16-ꢁit, 2Msps/1Msps/500ksps/250ksps Serial, Low

LTC2377-16/LTC2376-16 Power ADC

2.5V Supply, Differential ꢂnput, 96.2dꢁ SIR, 5V ꢂnput Range, DGC,

Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFI-16 Packages

LTC23ꢀ3-16/LTC23ꢀ2-16/ 16-ꢁit, 1Msps/500ksps/250ksps Serial, Low

2.5V Supply, Differential ꢂnput, 92dꢁ SIR, 2.5V ꢂnput Range, Pin-

Compatible Family in MSOP-16 and 4mm × 3mm DFI-16 Packages

LTC23ꢀ1-16

Power ADC

LTC2393-16/LTC2392-16/ 16-ꢁit, 1Msps/500ksps/250ksps Parallel/Serial ADC

LTC2391-16

5V Supply, Differential ꢂnput, 94dꢁ SIR, 4.096V ꢂnput Range, Pin-

Compatible Family in 7mm × 7mm LQFP-4ꢀ and QFI-4ꢀ Packages

LTC2355-14/LTC2356-14 14-ꢁit, 3.5Msps Serial ADC

3.3V Supply, 1-Channel, Unipolar/ꢁipolar, 1ꢀmW, MSOP-10 Package

DACS

LTC2641

16-ꢁit/14-ꢁit/12-ꢁit Single Serial V

DACs

1LSꢁ ꢂIL/DIL, MSOP-ꢀ Package, 0V to 5V Output

OUT

LTC2630

12-ꢁit/10-ꢁit/ꢀ-ꢁit Single V

DACs

SC70 6-Pin Package, ꢂnternal Reference, 1LSꢁ ꢂIL (12 ꢁits)

OUT

References

LTC6655

Precision Low Drift Low Ioise ꢁuffered Reference

5V/2.5V, 5ppm/°C, 0.25ppm Peak-to-Peak Ioise, MSOP-ꢀ Package

5V/2.5V, 5ppm/°C, 2.1ppm Peak-to-Peak Ioise, MSOP-ꢀ Package

LTC6652

Amplifiers

LT6202/LT6203

Single/Dual 100MHz Rail-to-Rail ꢂnput/Output Ioise 1.9nV√Hz, 3mA Maximum, 100MHz Gain ꢁandwidth

Low Power Amplifiers

LT6200/LT6200-5/

LT6200-10

165MHz/ꢀ00MHz/1.6GHz Op Amp with

Unity Gain/AV = 5/AV = 10

Low Ioise Voltage: 0.95nV/√Hz (100kHz), Low Distortion: –ꢀ0dꢁ at

1MHz, TSOT23-6 Package

LT6360

Low Ioise SAR ADC Driver with True Zero Output

Low Ioise ꢂntegrated Charge Pump

237016fa

LT 0312 REV A • PRINTED IN USA

24 ^{LinearTechnology Corporation}

1630 McCarthy ꢁlvd., Milpitas, CA 95035-7417

●

 LINEAR TECHNOLOGY CORPORATION 2011

(40ꢀ) 432-1900 FAX: (40ꢀ) 434-0507 www.linear.com


型号：	LT6360
厂家：	Linear
描述：	16-Bit, 2Msps, Pseudo-Differential Unipolar SAR 16位， 2MSPS ，伪差分SAR单极
文件：	总24页 (文件大小：528K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT6360 [Linear]

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