LT6402CUD-20#PBF [Linear]
LT6402-20 - 300MHz Low Distortion, Low Noise Differential Amplifier/ADC Driver (AV = 20dB); Package: QFN; Pins: 16; Temperature Range: 0°C to 70°C;型号: | LT6402CUD-20#PBF |
厂家: | Linear |
描述: | LT6402-20 - 300MHz Low Distortion, Low Noise Differential Amplifier/ADC Driver (AV = 20dB); Package: QFN; Pins: 16; Temperature Range: 0°C to 70°C 驱动器 运算放大器 放大器电路 |
文件: | 总16页 (文件大小:322K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LT6402-20
300MHz Low Distortion, Low
Noise Differential Amplifier/
ADC Driver (A = 20dB)
V
U
DESCRIPTIO
FEATURES
■
300 MHz –3dB Bandwidth
The LT®6402-20 is a low distortion, low noise differential
amplifier/ADC driver for use in applications from DC to
300MHz. The LT6402-20 has been designed for ease of
use,withminimalsupportcircuitryrequired.Exceptionally
low input-referred noise and low distortion (with either
single-ended or differential inputs) make the LT6402-20
an excellent solution for driving high speed 12-bit and
14-bit ADCs. In addition to the normal unfiltered outputs
(+OUT and –OUT), the LT6402-20 has a built-in 75MHz
differential low pass filter and an additional pair of filtered
outputs (+OUTFILTERED, –OUTFILTERED) to reduce
external filtering components when driving high speed
ADCs. The output common mode voltage is easily set via
■
Fixed Gain of 20dB
■
Low Distortion:
51dBm OIP3, –81dBc HD3 (20MHz, 2V
)
P-P
■
Low Noise:
12.4dB NF, e = 1.9nV/√Hz (20MHz)
n
■
■
■
■
■
■
Differential Inputs and Outputs
Additional Filtered Outputs
Adjustable Output Common Mode Voltage
DC- or AC-Coupled Operation
Minimal Support Circuitry Required
Small 0.75mm Profile 16-Lead 3mm × 3mm QFN
Package
the V
pin, eliminating an output transformer or AC-
OCM
U
coupling capacitors in many applications.
APPLICATIO S
TheLT6402-20isdesignedtomeetthedemandingrequire-
ments of communications transceiver applications. It can
be used as a differential ADC driver, a general-purpose
differential gain block, or in other applications requiring
differential drive. The LT6402-20 can be used in data
acquisition systems required to function at frequencies
down to DC.
■
Differential ADC Driver for:
Imaging
Communications
■
Differential Driver/Receiver
■
Single Ended to Differential Conversion
■
Differential to Single Ended Conversion
■
Level Shifting
IF Sampling Receivers
SAW Filter Interfacing/Buffering
■
The LT6402-20 operates on a 5V supply and consumes
30mA.Itcomesinacompact16-lead3mm×3mmQFNpack-
ageandoperatesovera–40°Cto85°Ctemperaturerange.
■
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
U
Distortion vs Frequency, Differential
TYPICAL APPLICATIO
Input, No R
LOAD
–40
–50
–60
–70
–80
–90
–100
FILTERED OUTPUTS
= 2V
V
OUT
5V
P-P
0.1µF
0.1µF
–INB
V
CC
V
CM
–INA
V
10Ω
10Ω
OCM
+OUT
+
–
AIN
0.1µF
0.1µF
HD3
LT6402-20
–OUT
LTC®2249
AIN
+INB
+INA
HD2
V
IF IN
EE
6402 TA01a
1
10
FREQUENCY (MHz)
100
64022 G08
640220fa
1
LT6402-20
W W U W
U
W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
Total Supply Voltage (V /V /V
to
CCA CCB CCC
V
/V /V ) ...................................................5.5V
EEA EEB EEC
Input Current (+INA, –INA, +INB, –INB,
16 15 14 13
V
1
2
3
4
12
V
EEC
CCC
V
, ENABLE)................................................ 10mA
OCM
V
11 ENABLE
OCM
17
Output Current (Continuous)
V
V
V
10
9
CCA
CCB
EEB
+OUT, –OUT................................................... 100mA
+OUTFILTERED, –OUTFILTERED...................... 30mA
Output Short Circuit Duration (Note 2) ............ Indefinite
Operating Temperature Range (Note 3) ... –40°C to 85°C
Specified Temperature Range (Note 4) .... –40°C to 85°C
Storage Temperature Range................... –65°C to 125°C
Junction Temperature ........................................... 125°C
Lead Temperature Range (Soldering 10 sec) ........ 300°C
V
EEA
5
6
7
8
UD PACKAGE
16-LEAD (3mm × 3mm) PLASTIC QFN
= 125°C, θ = 68°C/W, θ = 4.2°C/W
T
JMAX
JA
JC
EXPOSED PAD IS V (PIN 17)
EE
MUST BE SOLDERED TO THE PCB
ORDER PART NUMBER
UD PART MARKING*
LT6402CUD-20
LT6402IUD-20
LCBC
LCBC
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
DC ELECTRICAL CHARACTERISTICS
The
CCA
●
denotes the specifications which apply over the full operating
= V = 5V, V = V = V = 0V, ENABLE = 0.8V, +INA
temperature range, otherwise specifications are at T = 25°C. V
= V
A
CCB
CCC
EEA
EEB
EEC
shorted to +INB (+IN), –INA shorted to –INB (–IN), V
= 2.2V, Input common mode voltage = 2.2V, no R
unless otherwise noted.
OCM
CONDITIONS
Input/Output Characteristics (+INA, +INB, –INA, –INB, +OUT, –OUT, +OUTFILTERED, –OUTFILTERED)
LOAD
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
●
GDIFF
Gain
Differential (+OUT, –OUT), V
Differential
=
160mV
18.9
20
0.25
3.6
7
20.9
dB
IN
V
V
V
Single-Ended +OUT, –OUT, +OUTFILTERED,
–OUTFILTERED, V 600mV Differential
0.35
0.5
V
V
SWINGMIN
SWINGMAX
SWINGDIFF
OUT
=
●
●
IN
Single-Ended +OUT, –OUT, +OUTFILTERED,
–OUTFILTERED, V 600mV Differential
3.4
3.3
V
V
=
IN
Output Voltage Swing
Differential (+OUT, –OUT), V
Differential
=
600mV
6.1
5.6
V
V
IN
P-P
P-P
●
●
I
Output Current Drive
Input Offset Voltage
30
35
1
mA
V
–6.5
–10
6.5
10
mV
mV
OS
●
●
TCV
Input Offset Voltage Drift
T
MIN
to T
MAX
2.5
µV/°C
OS
640220fa
2
LT6402-20
DC ELECTRICAL CHARACTERISTICS
The
CCA
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V
= V
= V
= 5V, V = V = V = 0V, ENABLE = 0.8V, +INA
CCC EEA EEB EEC
A
CCB
shorted to +INB (+IN), –INA shorted to –INB (–IN), V
= 2.2V, Input common mode voltage = 2.2V, no R
unless otherwise noted.
OCM
LOAD
SYMBOL
PARAMETER
CONDITIONS
Single-Ended
Single-Ended
MIN
TYP
MAX
UNITS
V
●
●
●
I
I
Input Voltage Range, MIN
Input Voltage Range, MAX
Input Resistance
0.9
VRMIN
VRMAX
3.9
77
V
Ω
R
INDIFF
100
1
122
C
Input Capacitance
pF
dB
Ω
INDIFF
●
CMRR
Common Mode Rejection Ratio
Output Resistance
Input Common Mode 0.9V to 3.9V
45
70
R
0.3
0.8
OUTDIFF
OUTDIFF
C
Output Capacitance
pF
Common Mode Voltage Control (V
Pin)
OCM
GCM
Common Mode Gain
Differential (+OUT, –OUT), V
Differential (+OUT, –OUT), V
= 1.2V to 3.6V
= 1.4V to 3.4V
0.9
0.9
1
1.1
1.1
V/V
V/V
OCM
OCM
●
●
●
V
V
V
Output Common Mode Voltage
Adjustment Range, MIN
1.2
1.4
V
V
OCMMIN
OCMMAX
OSCM
Output Common Mode Voltage
Adjustment Range, MAX
Single-Ended
3.6
3.4
V
V
Output Common Mode Offset
Voltage
Measured from V
to Average of +OUT and –OUT
–30
4
30
15
mV
OCM
●
●
I
V
V
V
Input Bias Current
Input Resistance
Input Capacitance
5
3
1
µA
MΩ
pF
BIASCM
OCM
OCM
OCM
R
0.8
INCM
INCM
C
ENABLE Pin
●
●
●
●
V
V
ENABLE Input Low Voltage
ENABLE Input High Voltage
ENABLE Input Low Current
ENABLE Input High Current
0.8
V
V
IL
2
IH
I
IL
I
IH
ENABLE = 0.8V
ENABLE = 2V
0.5
3
µA
µA
1
Power Supply
●
●
●
●
V
Operating Range
4
5
5.5
37
V
mA
µA
S
I
I
Supply Current
ENABLE = 0.8V
ENABLE = 2V
4V to 5.5V
24
30
S
Supply Current (Disabled)
Power Supply Rejection Ratio
250
90
500
SDISABLED
PSRR
55
dB
640220fa
3
LT6402-20
AC ELECTRICAL CHARACTERISTICS
T = 25°C, V
= V
= V
= 5V, V = V = V = 0V,
CCC EEA EEB EEC
A
CCA
CCB
ENABLE = 0.8V, +INA shorted to +INB (+IN), –INA shorted to –INB (–IN), V
unless otherwise noted.
= 2.2V, Input common mode voltage = 2.2V, no R
OCM
LOAD
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input/Output Characteristics
–3dBBW
0.1dBBW
0.5dBBW
SR
–3dB Bandwidth
20mV Differential (+OUT, –OUT)
200
300
30
MHz
MHz
MHz
V/µs
ns
P-P
Bandwidth for 0.1dB Flatness
Bandwidth for 0.5dB Flatness
Slew Rate
20mV Differential (+OUT, –OUT)
P-P
20mV Differential (+OUT, –OUT)
80
P-P
3.2V Differential (+OUT, –OUT)
400
8
P-P
t
1% Settling
1% Settling for a 1V Differential Step
s1%
P-P
(+OUT, –OUT)
t
t
Turn-On Time
Turn-Off Time
100
1
ns
µs
ON
OFF
Common Mode Voltage Control (V
Pin)
OCM
–3dBBW
Common Mode Small-Signal –3dB
Bandwidth
0.1V at V , Measured Single-Ended at +OUT
OCM
200
250
MHz
V/µs
CM
P-P
and –OUT
SR
Common Mode Slew Rate
1.3V to 3.4V Step at V
OCM
CM
Noise/Harmonic Performance Input/Output Characteristics
10MHz Signal
Second/Third Harmonic Distortion
2V Differential (+OUTFILTERED, –OUTFILTERED)
–85
–85
–93
dBc
dBc
dBc
P-P
2V Differential (+OUT, –OUT)
P-P
Third-Order IMD
2V Differential Composite (+OUTFILTERED,
P-P
–OUTFILTERED), f1 = 9.5MHz, f2 = 10.5MHz
OIP3
NF
Output Third-Order Intercept
Differential (+OUTFILTERED, –OUTFILTERED),
f1 = 9.5MHz, f2 = 10.5MHz (Note 5)
49.5
dBm
10M
Noise Figure
Measured Using DC954A Demo Board
12.3
1.85
19.5
dB
nV/√Hz
dBm
e
Input Referred Noise Voltage Density
1dB Compression Point
n10M
R = 100Ω (Note 5)
L
20MHz Signal
Second/Third Harmonic Distortion
Third-Order IMD
2V Differential (+OUTFILTERED, –OUTFILTERED)
–81
–81
–96
dBc
dBc
dBc
P-P
2V Differential (+OUT, –OUT)
P-P
2V Differential Composite (+OUTFILTERED,
P-P
–OUTFILTERED), f1 = 19.5MHz, f2 = 20.5MHz
2V Differential Composite (+OUT, –OUT),
L
–91
51
dBc
P-P
R = 400Ω, f1 = 19.5MHz, f2 = 20.5MHz
OIP3
NF
Output Third-Order Intercept
Differential (+OUTFILTERED, –OUTFILTERED),
f1 = 19.5MHz, f2 = 20.5MHz (Note 5)
dBm
20M
Noise Figure
Measured Using DC954A Demo Board
12.4
1.9
18
dB
nV/√Hz
dBm
e
Input Referred Noise Voltage Density
1dB Compression Point
n20M
R = 100Ω (Note 5)
L
640220fa
4
LT6402-20
AC ELECTRICAL CHARACTERISTICS
T = 25°C, V
= V
= V
= 5V,V = V = V = 0V,
A
CCA
CCB
CCC EEA EEB EEC
ENABLE = 0.8V, +INA shorted to +INB (+IN), –INA shorted to –INB (–IN), V
unless otherwise noted.
= 2.2V, Input common mode voltage = 2.2V, no R
OCM
LOAD
UNITS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
25MHz Signal
Second/Third Harmonic Distortion
Third-Order IMD
2V Differential (+OUTFILTERED, –OUTFILTERED)
–80
–80
–86
dBc
dBc
dBc
P-P
2V Differential (+OUT, –OUT)
P-P
2V Differential Composite (+OUTFILTERED,
P-P
–OUTFILTERED), f1 = 24.5MHz, f2 = 25.5MHz
2V Differential Composite (+OUT, –OUT),
L
–84
46
dBc
P-P
R = 400Ω, f1 = 24.5MHz, f2 = 25.5MHz
OIP3
NF
Output Third-Order Intercept
Differential (+OUTFILTERED, –OUTFILTERED),
f1 = 24.5MHz, f2 = 25.5MHz (Note 5)
dBm
25M
Noise Figure
Measured Using DC954A Demo Board
12.5
1.9
dB
nV/√Hz
dBm
e
Input Referred Noise Voltage Density
1dB Compression Point
n25M
R = 100Ω (Note 5)
L
16.6
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: The LT6402C is guaranteed to meet specified performance from
0°C to 70°C. It is designed, characterized and expected to meet specified
performance from –40°C and 85°C but is not tested or QA sampled
at these temperatures. The LT6402I is guaranteed to meet specified
performance from –40°C to 85°C.
Note 2: As long as output current and junction temperature are kept below
the Absolute Maximum Ratings, no damage to the part will occur.
Note 3: The LT6402 is guaranteed functional over the operating
temperature range of –40°C to 85°C.
Note 5: Since the LT6402-20 is a feedback amplifier with low output
impedance, a resistive load is not required when driving an ADC.
Therefore, typical output power is very small. In order to compare the
LT6402-20 with typical g amplifiers that require 50Ω output loading, the
m
LT6402-20 output voltage swing driving an ADC is converted to OIP3 and
P1dB as if it were driving a 50Ω load.
TYPICAL PERFORMANCE CHARACTERISTICS
Frequency Response
LOAD
Frequency Response
LOAD
Frequency Response vs
, R = 400Ω
R
= 400Ω
R
= 100Ω
C
LOAD LOAD
30
25
20
15
10
5
30
25
20
15
10
5
35
30
25
20
15
10
5
V
= 20mV
P-P
IN
UNFILTERED OUTPUTS
UNFILTERED
FILTERED
UNFILTERED
FILTERED
0
0
V
= 20mV
P-P
0pF
V
= 20mV
P-P
IN
IN
UNFILTERED: R
FILTERED: R
= 400Ω
1.6pF
5pF
UNFILTERED: R
FILTERED: R
= 100Ω
LOAD
LOAD
–5
–10
–5
–10
= 300Ω (EXTERNAL)
= 100Ω
LOAD
LOAD
+ 100Ω (INTERNAL, FILTERED OUTPUTS)
10 100
FREQUENCY (MHz)
10pF
(INTERNAL, FILTERED OUTPUTS)
10 100
FREQUENCY (MHz)
0
1
1000
1
1000
1
10
100
1000
FREQUENCY (MHz)
64022 G01
64022 G03
34022 G02
640220fa
5
LT6402-20
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Output Third Order Intercept vs
Frequency, Differential Input,
Third Order Intermodulation
Distortion vs Frequency
Differential Input, No R
Third Order Intermodulation
Distortion vs Frequency
No R
Differential Input, R
= 400Ω
LOAD
LOAD
LOAD
60
55
50
45
40
35
30
–60
–65
–60
–65
2 TONES, 2V COMPOSITE
P-P
2 TONES, 2V COMPOSITE
P-P
2 TONES, 2V COMPOSITE
P-P
1MHz TONE SPACING
UNFILTERED OUTPUTS
1MHz TONE SPACING
1MHz TONE SPACING
–70
–70
UNFILTERED OUTPUTS
FILTERED OUTPUTS
–75
–75
–80
–80
–85
–85
UNFILTERED OUTPUTS
–90
–90
–95
–95
FILTERED OUTPUTS
–100
–105
–110
–100
–105
–110
FILTERED OUTPUTS
5
15
20
25
30
35
5
10
20
25
30
35
35
10
5
10
20
25
30
35
10
15
15
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
64022 G06
64022 G04
64022 G05
Output Third Order Intercept vs
Frequency, Differential Input,
Distortion vs Frequency,
Differential Input, No R
(Unfiltered)
Distortion vs Frequency,
Differential Input, No R
(Filtered)
LOAD
LOAD
R
LOAD
= 400Ω
60
55
50
45
40
35
30
–40
–50
–60
–70
–80
–90
–100
–40
–50
–60
–70
–80
–90
–100
FILTERED OUTPUTS
UNFILTERED OUTPUTS
2 TONES, 2V COMPOSITE
P-P
1MHz TONE SPACING
V
= 2V
V
= 2V
OUT P-P
OUT
P-P
FILTERED OUTPUTS
HD3
HD2
HD3
HD2
UNFILTERED OUTPUTS
5
15
20
25
30
1
10
FREQUENCY (MHz)
100
1
10
FREQUENCY (MHz)
100
10
FREQUENCY (MHz)
64022 G08
64022 G10
64022 G07
Distortion vs Output Amplitude
20MHz Differential Input,
Distortion vs Output Amplitude
20MHz Differential Input,
Output 1dB Compression
vs Frequency
No R
(Filtered)
No R
(Unfiltered)
LOAD
LOAD
–70
–75
–80
–70
–72
–74
–76
–78
–80
–82
–84
– 86
25
20
15
10
5
FILTERED OUTPUTS
UNFILTERED OUTPUTS
20MHz DIFFERENTIAL INPUT
20MHz DIFFERENTIAL INPUT
NO R
NO R
LOAD
LOAD
HD2
HD3
400Ω LOAD
100Ω LOAD
HD2
HD3
–85
–90
–95
0
–5
–10
UNFILTERED OUTPUTS
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
10
1
10
100
1000
OUTPUT AMPLITUDE (dBm)
OUTPUT AMPLITUDE (dBm)
FREQUENCY (Hz)
64022 G14
64022 G12
64022 G13
640220fa
6
LT6402-20
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Input Referred Noise Voltage
vs Frequency
Noise Figure vs Frequency
Isolation vs Frequency
30
25
20
15
10
5
8
7
6
5
4
3
2
1
0
–30
–40
UNFILTERED OUTPUTS
–50
–60
–70
–80
–90
–100
–110
MEASURED USING DC954A DEMO BOARD
10
100
1000
10
100
FREQUENCY (MHz)
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
64022 G15
64022 G16
64022 G17
Differential Input Impedance
vs Frequency
Differential Output Impedance
vs Frequency
Input Reflection Coefficient
vs Frequency
1000
100
10
1
0
–5
400
350
300
250
200
150
100
50
UNFILTERED OUTPUTS
MEASURED USING
DC954A DEMO BOARD
–10
–15
–20
–25
–30
–35
IMPEDANCE MAGNITUDE
IMPEDANCE PHASE
0
–50
–100
0
10
100
1000
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
64022 G19
64022 G18
34022 G20
Output Reflection Coefficient
vs Frequency
PSRR, CMRR vs Frequency
Small-Signal Transient Response
0
–5
120
110
100
90
80
70
60
50
40
30
20
10
0
MEASURED USING
DC954A DEMO BOARD
UNFILTERED OUTPUTS
R
= 100Ω PER OUTPUT
LOAD
PSRR
CMRR
2.25
2.20
2.15
–10
–15
–20
–25
–30
–35
–40
64022 G23
TIME (5ns/DIV)
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
64022 G21
64022 G22
640220fa
7
LT6402-20
TYPICAL PERFORMANCE CHARACTERISTICS
Distortion vs Output Common
Mode Voltage LT6402-20 Driving
LTC2249 14-Bit ADC
Large-Signal Transient Response
Overdrive Recovery Time
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
–80
–82
–84
–86
–88
–90
R
= 100Ω PER OUTPUT
FILTERED OUTPUTS, NO R
LOAD
OUT
R
LOAD
= 100Ω PER OUTPUT
LOAD
V
= 20MHz 2V
P-P
+OUT
HD3
HD2
–OUT
TIME (25ns/DIV)
TIME (10ns/DIV)
1
1.2 1.4 1.6 1.8
2.0 2.2 2.4
64022 G25
OUTPUT COMMON MODE VOLTAGE (V)
64022 G24
64022 G26
10MHz 8192 Point FFT,
LT6402-20 Driving
Turn-On Time
Turn-Off Time
LTC2249 14-Bit ADC
0
–10
4.0
3.5
3.0
2.5
4.0
3.5
3.0
2.5
8192 POINT FFT
= 10MHz, –1dBFS
R
= 100
R
= 100
LOAD
LOAD
f
PER OUTPUT
PER OUTPUT
IN
FILTERED OUTPUTS
–20
–30
+OUT
+OUT
–OUT
–40
–50
–60
2.0
1.5
2.0
1.5
–OUT
–70
–80
ENABLE
–90
ENABLE
1.0
0.5
0
1.0
0.5
0
5V
0V
5V
0V
–100
–110
–120
25 30
10 15 20
FREQUENCY (MHz)
0
5
35 40
TIME (125ns/DIV)
TIME (250ns/DIV)
64022 G27
64022 G28
64022 G29
20MHz 8192 Point FFT,
LT6402-20 Driving
LTC2249 14-Bit ADC
25MHz 8192 Point FFT,
LT6402-20 Driving
LTC2249 14-Bit ADC
20MHz 2-Tone 32768 Point FFT,
LT6402-20 Driving
LTC2249 14-Bit ADC
0
–10
0
–10
0
–10
–20
–30
–40
8192 POINT FFT
= 20MHz, –1dBFS
FILTERED OUTPUTS
8192 POINT FFT
32768 POINT FFT
f
f
= 25MHz, –1dBFS
IN
IN
TONE 1 AT 19.5MHz, –7dBFS
TONE 2 AT 20.5MHz, –7dBFS
FILTERED OUTPUTS
FILTERED OUTPUTS
–20
–20
–30
–30
–40
–40
–50
–60
–50
–50
–60
–60
–70
–80
–70
–70
–90
–80
–80
–100
–110
–120
–130
–140
–90
–90
–100
–110
–120
–100
–110
–120
25 30
10 15 20
FREQUENCY (MHz)
25 30
10 15 20
FREQUENCY (MHz)
0
5
35 40
0
5
35 40
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5
FREQUENCY (MHz)
64022 G30
64022 G31
64022 G32
640220fa
8
LT6402-20
U
U
U
PI FU CTIO S
V
(Pin 2): This pin sets the output common mode
+OUTFILTERED, –OUTFILTERED (Pins 6, 7): Filtered
Outputs. These pins add a series 50Ω resistor from the
unfiltered outputs and three 14pF capacitors. Each output
OCM
voltage. Without additional biasing, both inputs bias to
this voltage as well. This input is high impedance.
has 14pF to V , plus an additional 14pF between each pin
EE
V
, V , V
CCA CCB CCC
(Pins 3, 10, 1): Positive Power Supply
(See the Block Diagram). This filter has a –3dB bandwidth
of 75MHz.
(Normally Tied to 5V). All three pins must be tied to the
same voltage. Bypass each pin with 1000pF and 0.1µF
capacitors as close to the package as possible. Split
ENABLE (Pin 11): This pin is a TTL logic input referenced
supplies are possible as long as the voltage between V
and V is 5V.
to the V
pin. If low, the LT6402 is enabled and draws
CC
EEC
typically 30mA of supply current. If high, the LT6402 is
disabled and draws typically 250µA.
EE
V
, V , V (Pins 4, 9, 12): Negative Power Supply
EEA EEB EEC
(Normally Tied to Ground). All three pins must be tied to
+INA, +INB (Pins 15, 16): Positive Inputs. These pins are
normally tied together. These inputs may be DC- or AC-
coupled. If the inputs are AC-coupled, they will self-bias
the same voltage. Split supplies are possible as long as
the voltage between V and V is 5V. If these pins are
CC
EE
nottiedtoground, bypasseachpinwith1000pFand0.1µF
to the voltage applied to the V
pin.
OCM
capacitors as close to the package as possible.
–INA, –INB (Pins 14, 13): Negative Inputs. These pins are
normally tied together. These inputs may be DC- or AC-
coupled. If the inputs are AC-coupled, they will self-bias
+OUT, –OUT (Pins 5, 8): Outputs (Unfiltered). These
pins are high bandwidth, low-impedance outputs. The DC
output voltage at these pins is set to the voltage applied
to the voltage applied to the V
pin.
OCM
at V
.
OCM
Exposed Pad (Pin 17): Tie the pad to V (Pin 12). If split
EEC
supplies are used, DO NOT tie the pad to ground.
W
BLOCK DIAGRA
500Ω
V
EEA
V
CCA
–INA
–INB
14pF
100Ω
100Ω
14
13
–
+
+OUT
5
6
A
+OUTFILTERED
50Ω
V
EEA
V
CCC
500Ω
V
OCM
2
+
–
C
14pF
V
EEC
500Ω
100Ω
50Ω
–OUTFILTERED
–OUT
V
CCB
+INA
+INB
7
8
16
15
+
–
B
100Ω
14pF
V
EEB
V
EEB
500Ω
BIAS
11
6402 BD
3
10
1
4
9
12
V
V
V
ENABLE
V
V
V
EEC
CCA
CCB
CCC
EEA
EEB
640220fa
9
LT6402-20
U
W U U
APPLICATIO S I FOR ATIO
Circuit Description
the outputs, the common mode voltage is set via the V
OCM
pin, allowing the LT6402-20 to drive ADCs directly. No
outputAC-couplingcapacitorsortransformersareneeded.
At the inputs, signals can be differential or single-ended
with virtually no difference in performance. Furthermore,
DC levels at the inputs can be set independently of the
outputcommonmodevoltage.Theseinputcharacteristics
often eliminate the need for an input transformer and/or
AC-coupling capacitors.
The LT6402-20 is a low noise, low distortion differential
amplifier/ADC driver with:
• –3dB bandwidth
DC to 300MHz
• Fixed gain independent of R
10V/V (20dB)
LOAD
• Differential input impedance
100Ω
Input Impedance and Matching Networks
• Low output impedance
Calculation of the input impedance of the LT6402-20 is
notstraightforwardfromexaminationoftheblockdiagram
because of the internal feedback network. In addition, the
inputimpedancewhendrivendifferentiallyisdifferentthan
when driven single-ended.
• Built-in, user adjustable output filtering
• Requires minimal support circuitry
Referring to the block diagram, the LT6402-20 uses a
closed-loop topology which incorporates 3 internal am-
plifiers. Two of the amplifiers (A and B) are identical and
drive the differential outputs. The third amplifier is used
to set the output common mode voltage. Gain and input
impedance are set by the 500Ω and 100Ω resistors in
the internal feedback network. Output impedance is low,
determinedbytheinherentoutputimpedanceofamplifiers
A and B, and further reduced by internal feedback.
Differential
Single-Ended
LT6402-20
100Ω
85.9Ω
Forsingle-ended50Ωapplications,a121Ωshuntmatching
resistor to ground will result in the proper input termina-
tion (Figure 1). For differential inputs there are several
terminationoptions. Iftheinputsourceis50Ωdifferential,
then the input matching can be accomplished by either
a 100Ω shunt resistor across the inputs (Figure 3), or
equivalent 49.9Ω shunt resistors on each of the inputs
to ground (Figure 2). If additional AC gain is desired, an
impedance ratio transformer can also be used to better
match impedances.
The LT6402-20 also includes built-in single-pole output
filtering. The user has the choice of using the unfiltered
outputs, the filtered outputs (75MHz –3dB lowpass), or
modifying the filtered outputs to alter frequency response
by adding additional components. Many lowpass and
bandpass filters are easily implemented with just one or
two additional components.
13
–INB
–INA
8
–OUT
LT6402-20
+OUT
14
The LT6402-20 has been designed to minimize the need
for external support components such as transformers or
AC-coupling capacitors. As an ADC driver, the LT6402-20
requires no external components except for power-supply
bypass capacitors. This allows DC-coupled operation for
applications that have frequency ranges including DC. At
0.1µF
15
16
IF IN
+INB
+INA
5
121Ω
Z
= 50Ω
IN
6402 F01
SINGLE-ENDED
Figure 1. Input Termination for Single-Ended 50Ω
Input Impedance
640220fa
10
LT6402-20
U
W U U
APPLICATIO S I FOR ATIO
Single-Ended to Differential Operation
and filtered outputs of the LT6402-20 can easily drive the
high impedance inputs of these differential ADCs. If the
filtered outputs are used, then cutoff frequency and the
type of filter can be tailored for the specific application if
needed.
The LT6402-20’s performance with single-ended inputs
is comparable to its performance with differential inputs.
This excellent single-ended performance is largely due
to the internal topology of the LT6402-20. Referring to
the block diagram, if the +INA and +INB pins are driven
with a single-ended signal (while –INA and –INB are tied
to AC ground), then the +OUT and –OUT pins are driven
differentially without any voltage swing needed from
amplifier C. Single-ended to differential conversion using
more conventional topologies suffers from performance
limitations due to the common mode amplifier.
Wideband Applications
(Using the +OUT and –OUT Pins)
In applications where the full bandwidth of the LT6402-20
is desired, the unfiltered output pins (+OUT and –OUT)
should be used. They have a low output impedance;
therefore, gain is unaffected by output load. Capacitance
in excess of 5pF placed directly on the unfiltered outputs
results in additional peaking and reduced performance.
When driving an ADC directly, a small series resistance
is recommended between the LT6402-20’s outputs and
the ADC inputs (Figure 4). This resistance helps eliminate
any resonances associated with bond wire inductances of
either the ADC inputs or the LT6402-20’s outputs. A value
between 10Ω and 25Ω gives excellent results.
Driving ADCs
The LT6402-20 has been specifically designed to interface
directly with high speed Analog to Digital Converters
(ADCs).Ingeneral,theseADCshavedifferentialinputs,with
an input impedance of 1kΩ or higher. In addition, there is
generally some form of lowpass or bandpass filtering just
prior to the ADC to limit input noise at the ADC, thereby
improving system signal to noise ratio. Both the unfiltered
13
–INB
–
IF IN
8
5
14
–OUT
LT6402-20
+OUT
–INA
49.9Ω
Z
= 50Ω
IN
DIFFERENTIAL
15
16
+INB
+INA
+
IF IN
49.9Ω
6402 F02
Figure 2. Input Termination for Differential 50Ω Input Impedance
13
14
–INB
–INA
10Ω TO 25Ω
10Ω TO 25Ω
–
IF IN
8
5
8
5
–OUT
LT6402-20
+OUT
–OUT
LT6402-20
+OUT
Z
= 50Ω
DIFFERENTIAL
IN
100Ω
ADC
15
16
+INB
+INA
+
IF IN
6402 F03
6402 F04
Figure 3. Alternate Input Termination for Differential 50Ω
Input Impedance
Figure 4. Adding Small Series R at LT6402 Output
640220fa
11
LT6402-20
U
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APPLICATIO S I FOR ATIO
Filtered Applications
TERED (Figure 6). These resistors are in parallel with the
internal 50Ω resistor, lowering the overall resistance and
increasingfilterbandwidth. Todoublethefilterbandwidth,
for example, add two external 50Ω resistors to lower the
seriesresistanceto25Ω.The42pFofcapacitanceremains
unchanged, so filter bandwidth doubles.
(Using the +OUTFILTERED and –OUTFILTERED Pins)
Filtering at the output of the LT6402-20 is often desired
to provide either anti-aliasing or improved signal to noise
ratio. To simplify this filtering, the LT6402-20 includes an
additional pair of differential outputs (+OUTFILTERED and
–OUTFILTERED) which incorporate an internal lowpass
filter network with a –3dB bandwidth of 75MHz (Figure 5).
These pins each have an output impedance of 50Ω. Inter-
To decrease filter bandwidth, add two external capacitors,
one from +OUTFILTERED to ground, and the other from
–OUTFILTERED to ground. A single differential capacitor
connected between +OUTFILTERED and –OUTFILTERED
can also be used, but since it is being driven differentially
it will appear at each filtered output as a single-ended
capacitance of twice the value. To halve the filter band-
width, for example, two 42pF capacitors could be added
(one from each filtered output to ground). Alternatively
one 21pF capacitor could be added between the filtered
outputs, again halving the filter bandwidth. Combinations
of capacitors could be used as well; a three capacitor
nal capacitances are 14pF to V on each filtered output,
EE
plus an additional 14pF capacitor connected differentially
between the two filtered outputs. This resistor/capaci-
tor combination creates filtered outputs that look like a
series 50Ω resistor with a 42pF capacitor shunting each
filtered output to AC ground, giving a –3dB bandwidth of
75MHz.
The filter cutoff frequency is easily modified with just a
fewexternalcomponents.Toincreasethecutofffrequency,
simplyadd2equalvalueresistors, onebetween+OUTand
+OUTFILTEREDandtheotherbetween–OUTand–OUTFIL-
LT6402-20
8
7
–OUT
V
EE
14pF
50Ω
50Ω
LT6402-20
14pF
8
–OUTFILTERED
–OUT
V
EE
FILTERED OUTPUT
(37.5MHz)
14pF
14pF
14pF
14pF
50Ω
50Ω
7
6
–OUTFILTERED
+OUTFILTERED
+OUTFILTERED
6
5
FILTERED OUTPUT
(75MHz)
14pF
14pF
14pF
V
EE
+OUT
6402 F07
V
EE
5
+OUT
Figure 7. LT6402-20 Internal Filter Topology Modified
for 1/2x Filter Bandwidth (3 External Capacitors)
6402 F05
Figure 5. LT6402-20 Internal Filter Topology –3dB BW ≈75MHz
LT6402-20
8
7
–OUT
V
EE
LT6402-20
8
–OUT
50Ω
14pF
V
EE
50Ω
50Ω
–OUTFILTERED
14pF
14pF
50Ω
50Ω
7
6
–OUTFILTERED
14pF
FILTERED OUTPUT
FILTERED OUTPUT
(150MHz)
14pF
+OUTFILTERED
+OUTFILTERED
6
5
14pF
50Ω
V
EE
V
EE
5
+OUT
+OUT
6402 F06
6402 F08
Figure 6. LT6402-20 Internal Filter Topology Modified
for 2x Filter Bandwidth (2 External Resistors)
Figure 8. LT6402-20 Output Filter Modified for Bandpass
Filtering (1 External Inductor, 1 External Capacitor)
640220fa
12
LT6402-20
U
W U U
APPLICATIO S I FOR ATIO
solution of 14pF from each filtered output to ground plus
a 14pF capacitor between the filtered outputs would also
halve the filter bandwidth (Figure 7).
Input Bias Voltage and Bias Current
The input pins of the LT6402-20 are internally biased to
the voltage applied to the V pin. No external biasing
OCM
Bandpass filtering is also easily implemented with just a
few external components. An additional 560pF and 62nH,
each added differentially between +OUTFILTERED and
–OUTFILTERED creates a bandpass filter with a 26MHz
center frequency, –3dB points of 23MHz and 30MHz, and
1.6dB of insertion loss (Figure 8).
resistors are needed, even for AC-coupled operation. The
input bias current is determined by the voltage difference
between the input common mode voltage and the V
OCM
pin (which sets the output common mode voltage). For
example, if the inputs are tied to 2.5V with the V pin
OCM
at 2.2V, then a total input bias current of 1mA will flow
into the LT6402-20’s +INA and +INB pins. Furthermore,
an additional input bias current totaling 1mA will flow into
the –INA and –INB inputs.
Output Common Mode Adjustment
The LT6402-20’s output common mode voltage is set by
the V
pin. It is a high-impedance input, capable of
OCM
Application (Demo) Boards
setting the output common mode voltage anywhere in
a range from 1.1V to 3.6V. Bandwidth of the V
pin is
pin
TheDC954ADemoBoardhasbeencreatedforstand-alone
evaluation of the LT6402-20 with either single-ended or
differential input and output signals. As shown, it accepts
a single-ended input and produces a single-ended output
so that the LT6402-20 can be evaluated using standard
laboratory test equipment. For more information on this
Demo Board, please refer to the layout and schematic
diagrams found later in this data sheet.
OCM
typically 200MHz, so for applications where the V
OCM
is tied to a DC bias voltage, a 0.1µF capacitor at this pin is
recommended.Forbestdistortionperformance,thevoltage
at the V
pin should be between 1.8V and 2.6V.
OCM
When interfacing with most ADCs, there is generally a
output pin that is at about half of the supply voltage
V
OCM
of the ADC. For 5V ADCs such as the LTC17XX family, this
output pin should be connected directly (with the
V
There are also additional demo boards available that
combine the LT6402-20 with a variety of different Linear
Technology ADCs. Please contact the factory for more
information on these demo boards.
OCM
addition of a 0.1µF capacitor) to the input V
pin of the
OCM
LT6402-20. For 3V ADCs such as the LTC22XX families,
the LT6402-20 will function properly using the 1.65V from
the ADC’s V reference pin, but improved Spurious Free
CM
Dynamic Range (SFDR) and distortion performance can
3V
beachievedbylevel-shiftingtheLTC22XX’sV reference
CM
11k
voltage up to at least 1.8V. This can be accomplished as
1.9V
shown in Figure 9 by using a resistor divider between the
0.1µF
4.02k
LTC22XX’s V output pin and V and then bypassing
CM
CC
2
13
14
31 1.5V
–INB
–INA
the LT6402-20’s V
pin with a 0.1µF capacitor. For a
OCM
V
V
CM
OCM
10Ω
10Ω
commonmodevoltageabove1.9V,ACcouplingcapacitors
are recommended between the LT6402-20 and LTC22XX
ADCs because of the input voltage range constraints of
the ADC.
6
7
1
2
+
–
+OUTFILTERED
LT6402-20
AIN
AIN
0.1µF
LTC22xx
–OUTFILTERED
15
16
+INB
+INA
IF IN
121Ω
6402 F9
Large Output Voltage Swings
The LT6402-20 has been designed to provide the
Figure 9. Level Shifting 3V ADC V Voltage for
CM
3.2V
output swing needed by the LTC1748 family
Improved SFDR
P-P
of 14-bit low-noise ADCs. This additional output swing
improves system SNR by up to 4dB.
640220fa
13
LT6402-20
U
TYPICAL APPLICATIO
Top Silkscreen
640220fa
14
LT6402-20
U
PACKAGE DESCRIPTIO
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691)
0.70 0.05
3.50 0.05
2.10 0.05
1.45 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
R = 0.115
TYP
0.75 0.05
3.00 0.10
(4 SIDES)
15 16
PIN 1
TOP MARK
(NOTE 6)
0.40 0.10
1
2
1.45 0.10
(4-SIDES)
(UD16) QFN 0904
0.200 REF
0.25 0.05
0.50 BSC
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
640220fa
InformationfurnishedbyLinearTechnologyCorporationisbelievedtobeaccurateandreliable.However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LT6402-20
U
TYPICAL APPLICATIO
Demo Circuit DC954A Schematic (AC Test Circuit)
R18
0Ω
R17
0Ω
V
CC
V
CC
GND
V
CC
2
1
2
1
1
SW1
3
TP1
ENABLE
C17
1000pF
C18
0.01µF
R16
0Ω
2
1
1
2
R2
R4
R14
C11
[1]
12
11
10
9
C2
0.1µF
C4
0Ω
49.9Ω
0Ω
R6
R10
R12
0.1µF
V
ENABLE
V
V
EEC
CCB EEB
–OUT
0Ω
24.9Ω
75Ω
13
8
–INB
1
2
1
2
J1
–IN
R8
[1]
J4
–OUT
T1
T2
C21
0.1µF
14
15
16
7
6
5
1:1 Z-RATIO
4:1 Z-RATIO
5
4
1
3
–INA
+INB
+INA
–OUTFILTERED
LT6402-20
+OUTFILTERED
3
1
4
5
2
1
2
2
L1
[1]
C8
[1]
R15
[1]
R7
[1]
0dB
+18.8dB
+14dB
1
2
MINI-
M/A-COM
ETC1-1T
0dB
+8dB
J2
+IN
J5
+OUT
C1
0.1µF
C3
0.1µF
CIRCUITS
TCM 4-19
R9
24.9Ω
R11
75Ω
R5
0Ω
+OUT
1
2
1
2
V
CCC
V
OCM
V
V
4
CCA
EEA
1
2
2
1
R1
[1]
R3
49.9Ω
R13
[1]
C16
[1]
C22
0.1µF
1
2
3
V
CC
V
CC
2
1
2
1
2
1
2
1
C10
0.01µF
C9
1000pF
C12
1000pF
C13
0.01µF
V
CC
R19
14k
J3
V
OCM
2
1
C7
0.01µF
R20
11k
C5
0.1µF
J6
TEST IN
T3
T4
J7
1:4
4:1
TEST OUT
4
5
5
1
3
3
2
1
2
R22
C19, 0.1µF
C20, 0.1µF
2
R21
[1]
C6
[1]
0.1µF
1
2
1
2
MINI-
CIRCUITS
TCM 4-19
MINI-
CIRCUITS
TCM 4-19
4
1
1
2
TP2
CC
V
CC
V
NOTES: UNLESS OTHERWISE SPECIFIED,
[1] DO NOT STUFF.
1
1
2
2
1
C14
4.7µF
C15
1µF
1
TP3
GND
6402 TA02
RELATED PARTS
PART NUMBER
LT1993-2
LT1993-4
LT1993-10
LT5514
DESCRIPTION
COMMENTS
A = 2V/V, NF = 12.3dB, OIP3 = 38dBm at 70MHz
800MHz Differential Amplifier/ADC Driver
900MHz Differential Amplifier/ADC Driver
700MHz Differential Amplifier/ADC Driver
Ultralow Distortion IF Amplifier/ADC Driver
V
A = 4V/V, NF = 14.5dB, OIP3 = 40dBm at 70MHz
V
A = 10V/V, NF = 12.7dB, OIP3 = 40dBm at 70MHz
V
Digitally Controlled Gain Output IP3 47dBm at 100MHz
LT6600-5
LT6600-10
Very Low Noise Differential Amplifier and 5MHz Lowpass Filter 82dB S/N with 3V Supply, SO-8 Package
Very Low Noise Differential Amplifier and 10MHz Lowpass
Filter
82dB S/N with 3V Supply, SO-8 Package
LT6600-20
Very Low Noise Differential Amplifier and 20MHz Lowpass
Filter
76dB S/N with 3V Supply, SO-8 Package
LT6402-6
LT6402-12
LT6411
300MHz Differential Amplifier/ADC Driver
300MHz Differential Amplifier/ADC Driver
A = 6dB, e = 3.8nV/√Hz at 20MHz, 150mV
V n
A = 12dB, e = 2.6nV/√Hz at 20MHz, 150mV
V
n
650MHz Differential ADC Driver/Dual Selectable Gain Amplifier 3300V/µs Slew Rate, 16mA Current Consumption, Selectable Gain:
A = –1, +1, +2
V
640220fa
LT 0706 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
© LINEAR TECHNOLOGY CORPORATION 2005
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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Linear
LT6402CUD-6-TRPBF
300MHz Low Distortion, Low Noise Differential Amplifi er/ ADC Driver (AV = 6dB)
Linear
LT6402IUD-12
300MHz Low Distortion, Low Noise Differential Amplifi er/ ADC Driver (AV = 12dB)
Linear
LT6402IUD-12#TRPBF
LT6402-12 - 300MHz Low Distortion, Low Noise Differential Amplifier/ADC Driver (AV = 12dB); Package: QFN; Pins: 16; Temperature Range: -40°C to 85°C
Linear
LT6402IUD-12-PBF
300MHz Low Distortion, Low Noise Differential Amplifi er/ ADC Driver (AV = 12dB)
Linear
LT6402IUD-12-TR
300MHz Low Distortion, Low Noise Differential Amplifi er/ ADC Driver (AV = 12dB)
Linear
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