LT6402IUD-6#PBF [Linear]
暂无描述;型号: | LT6402IUD-6#PBF |
厂家: | Linear |
描述: | 暂无描述 驱动器 运算放大器 放大器电路 功率放大器 |
文件: | 总16页 (文件大小:233K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LT6402-6
300MHz Low Distortion, Low
Noise Differential Amplifier/
ADC Driver (A = 6dB)
DESCRIPTION
V
FEATURES
The LT®6402-6 is a low distortion, low noise differential
amplifier/ADC driver for use in applications from DC to
300MHz. The LT6402-6 has been designed for ease of
use,withminimalsupportcircuitryrequired.Exceptionally
low input-referred noise and low distortion (with either
single-ended or differential inputs) make the LT6402-6 an
excellent solution for driving high speed 12-bit and 14-bit
ADCs. In addition to the normal unfiltered outputs (+OUT
and –OUT), the LT6402-6 has a built-in 75MHz differential
low pass filter and an additional pair of filtered outputs
(+OUTFILTERED, –OUTFILTERED) to reduce external fil-
tering components when driving high speed ADCs. The
n
300 MHz –3dB Bandwidth
n
Fixed Gain of 6dB
n
Low Distortion:
49dBm OIP3, –85dBc HD3 (20MHz, 2V
)
P-P
n
Low Noise:
18.6dB NF, e = 3.8nV/√Hz (20MHz)
n
n
n
n
n
n
n
Differential Inputs and Outputs
Additional Filtered Outputs
Adjustable Output Common Mode Voltage
DC- or AC-Coupled Operation
Minimal Support Circuitry Required
Small 0.75mm Profile 16-Lead 3mm × 3mm QFN
Package
output common mode voltage is easily set via the V
OCM
pin, eliminating an output transformer or AC-coupling
capacitors in many applications.
APPLICATIONS
n
The LT6402-6 is designed to meet the demanding require-
ments of communications transceiver applications. It can
be used as a differential ADC driver, a general-purpose
differential gain block, or in other applications requir-
ing differential drive. The LT6402-6 can be used in data
acquisition systems required to function at frequencies
down to DC.
Differential ADC Driver for:
Imaging
Communications
n
Differential Driver/Receiver
n
Single Ended to Differential Conversion
Differential to Single Ended Conversion
Level Shifting
IF Sampling Receivers
SAW Filter Interfacing/Buffering
n
n
n
TheLT6402-6operatesona5Vsupplyandconsumes30mA.
It comes in a compact 16-lead 3mm × 3mm QFN package
and operates over a –40°C to 85°C temperature range.
n
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Distortion vs Frequency, Differential Input, No RLOAD
TYPICAL APPLICATION
–40
FILTERED OUTPUTS
V
= 2V
OUT
P-P
5V
–50
–60
0.1μF
0.1μF
–INB
–70
V
CC
V
CM
–INA
V
10Ω
10Ω
OCM
+OUT
+
–
AIN
0.1μF
0.1μF
–80
HD3
HD2
LT6402-6
–OUT
LTC®2249
AIN
–90
+INB
+INA
V
IF IN
EE
64026 TA01a
–100
1
10
FREQUENCY (MHz)
100
64026 TA01b
64026fa
1
LT6402-6
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
Total Supply Voltage (V /V /V
EEA EEB EEC
Input Current (+INA, –INA, +INB, –INB,
to
CCA CCB CCC
/V /V ) ...................................................5.5V
V
16 15 14 13
V
1
2
3
4
12
V
EEC
CCC
V
, ENABLE)................................................ 10mA
OCM
V
11 ENABLE
OCM
17
Output Current (Continuous)
V
V
V
10
9
CCA
CCB
EEB
+OUT, –OUT ................................................... 100mA
+OUTFILTERED, –OUTFILTERED...................... 30mA
Output Short-Circuit Duration (Note 2) ............ Indefinite
Operating Temperature Range (Note 3).... –40°C to 85°C
Specified Temperature Range (Note 4) .... –40°C to 85°C
Storage Temperature Range................... –65°C to 125°C
Junction Temperature ........................................... 125°C
V
EEA
5
6
7
8
UD PACKAGE
16-LEAD (3mm × 3mm) PLASTIC QFN
= 125°C, θ = 68°C/W, θ = 4.2°C/W
T
JMAX
JA
JC
EXPOSED PAD IS V (PIN 17)
EE
MUST BE SOLDERED TO THE PCB
ORDER INFORMATION
LEAD FREE FINISH
LT6402CUD-6#PBF
LT6402IUD-6#PBF
LEAD BASED FINISH
LT6402CUD-6
TAPE AND REEL
PART MARKING*
LBZZ
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 85°C
LT6402CUD-6#TRPBF
LT6402IUD-6#TRPBF
TAPE AND REEL
16-Lead (3mm × 3mm) Plastic QFN
16-Lead (3mm × 3mm) Plastic QFN
PACKAGE DESCRIPTION
LBZZ
–40°C to 85°C
PART MARKING*
LBZZ
TEMPERATURE RANGE
–40°C to 85°C
LT6402CUD-6#TR
LT6402IUD-6#TR
16-Lead (3mm × 3mm) Plastic QFN
16-Lead (3mm × 3mm) Plastic QFN
LT6402IUD-6
LBZZ
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
DC ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCCA = VCCB = VCCC = 5V, VEEA = VEEB = VEEC = 0V, ENABLE = 0.8V, +INA
shorted to +INB (+IN), –INA shorted to –INB (–IN), VOCM = 2.2V, Input common mode voltage = 2.2V, no RLOAD unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input/Output Characteristics (+INA, +INB, –INA, –INB, +OUT, –OUT, +OUTFILTERED, –OUTFILTERED)
l
l
l
GDIFF
Gain
Differential (+OUT, –OUT), V
=
800mV Differential
5.8
6
6.3
dB
IN
V
V
V
Single-Ended +OUT, –OUT, +OUTFILTERED,
0.25
0.35
0.5
V
V
SWINGMIN
SWINGMAX
SWINGDIFF
OUT
–OUTFILTERED, V 2.2V Differential
=
IN
Single-Ended +OUT, –OUT, +OUTFILTERED,
–OUTFILTERED, V 2.2V Differential
3.4
3.3
3.6
7
V
V
=
IN
Output Voltage Swing
Differential (+OUT, –OUT), V 2.2V Differential
=
6.1
5.6
V
V
IN
P-P
P-P
l
l
I
Output Current Drive
Input Offset Voltage
30
35
1
mA
V
OS
–6.5
–10
6.5
10
mV
mV
l
64026fa
2
LT6402-6
DC ELECTRICAL CHARACTERISTICS
shorted to +INB (+IN), –INA shorted to –INB (–IN), VOCM = 2.2V, Input common mode voltage = 2.2V, no RLOAD unless otherwise noted.
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCCA = VCCB = VCCC = 5V, VEEA = VEEB = VEEC = 0V, ENABLE = 0.8V, +INA
SYMBOL
PARAMETER
CONDITIONS
to T
MIN
TYP
MAX
–0.1
240
UNITS
μV/°C
V
l
l
l
l
TCV
Input Offset Voltage Drift
Input Voltage Range, MIN
Input Voltage Range, MAX
Input Resistance
T
2.5
OS
VRMIN
VRMAX
MIN
MAX
I
I
Single-Ended
Single-Ended
5.1
V
Ω
R
170
200
1
INDIFF
INDIFF
C
Input Capacitance
pF
l
CMRR
Common Mode Rejection Ratio Input Common Mode –0.1V to 5.1V
42
65
dB
Ω
R
Output Resistance
Output Capacitance
0.3
0.8
OUTDIFF
OUTDIFF
C
pF
Common Mode Voltage Control (V
Pin)
OCM
GCM
Common Mode Gain
Differential (+OUT, –OUT), V
Differential (+OUT, –OUT), V
= 1.2V to 3.6V
= 1.4V to 3.4V
0.9
0.9
1
1.1
1.1
V/V
V/V
OCM
OCM
l
l
l
V
V
V
Output Common Mode Voltage
Adjustment Range, MIN
1.2
1.4
V
V
OCMMIN
OCMMAX
OSCM
Output Common Mode Voltage Single-Ended
Adjustment Range, MAX
3.6
3.4
V
V
Output Common Mode Offset
Voltage
Measured from V
to Average of +OUT and –OUT
–30
4
30
15
mV
OCM
l
l
I
V
V
V
Input Bias Current
Input Resistance
Input Capacitance
5
3
1
μA
MΩ
pF
BIASCM
OCM
OCM
OCM
R
0.8
INCM
INCM
C
ENABLE Pin
l
l
l
l
V
ENABLE Input Low Voltage
ENABLE Input High Voltage
ENABLE Input Low Current
ENABLE Input High Current
0.8
V
V
IL
V
2
IH
I
I
ENABLE = 0.8V
ENABLE = 2V
0.5
3
μA
μA
IL
IH
1
Power Supply
l
l
l
l
V
Operating Range
4
5
5.5
37
V
mA
μA
S
I
I
Supply Current
ENABLE = 0.8V
ENABLE = 2V
4V to 5.5V
24
30
S
Supply Current (Disabled)
Power Supply Rejection Ratio
250
90
500
SDISABLED
PSRR
55
dB
64026fa
3
LT6402-6
AC ELECTRICAL CHARACTERISTICS
TA = 25°C, VCCA = VCCB = VCCC = 5V, VEEA = VEEB = VEEC = 0V,
ENABLE = 0.8V, +INA shorted to +INB (+IN), –INA shorted to –INB (–IN), VOCM = 2.2V, Input common mode voltage = 2.2V, no RLOAD
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input/Output Characteristics
–3dBBW
0.1dBBW
0.5dBBW
SR
–3dB Bandwidth
100mV Differential (+OUT, –OUT)
200
300
30
MHz
MHz
MHz
V/μs
ns
P-P
Bandwidth for 0.1dB Flatness
Bandwidth for 0.5dB Flatness
Slew Rate
100mV Differential (+OUT, –OUT)
P-P
100mV Differential (+OUT, –OUT)
80
P-P
3.2V Differential (+OUT, –OUT)
400
10
P-P
t
1% Settling
1% Settling for a 1V Differential Step
s1%
P-P
(+OUT, –OUT)
t
t
Turn-On Time
Turn-Off Time
200
1.8
ns
μs
ON
OFF
Common Mode Voltage Control (V
Pin)
OCM
–3dBBW
Common Mode Small-Signal –3dB
Bandwidth
0.1V at V , Measured Single-Ended at +OUT
OCM
200
250
MHz
V/μs
CM
P-P
and –OUT
SR
Common Mode Slew Rate
1.3V to 3.4V Step at V
OCM
CM
Noise/Harmonic Performance Input/Output Characteristics
10MHz Signal
Second/Third Harmonic Distortion
2V Differential (+OUTFILTERED, –OUTFILTERED)
–86
–84
dBc
dBc
dBc
P-P
2V Differential (+OUT, –OUT)
P-P
Third-Order IMD
2V Differential Composite (+OUTFILTERED,
–101
P-P
–OUTFILTERED), f1 = 9.5MHz, f2 = 10.5MHz
OIP3
NF
Output Third-Order Intercept
Differential (+OUTFILTERED, –OUTFILTERED),
f1 = 9.5MHz, f2 = 10.5MHz (Note 5)
53
dBm
10M
Noise Figure
Measured Using DC954A Demo Board
18.6
3.8
dB
nV/√Hz
dBm
e
Input Referred Noise Voltage Density
1dB Compression Point
n10M
R = 100Ω (Note 5)
L
20.7
20MHz Signal
Second/Third Harmonic Distortion
Third-Order IMD
2V Differential (+OUTFILTERED, –OUTFILTERED)
–84
–73
–90
dBc
dBc
dBc
P-P
2V Differential (+OUT, –OUT)
P-P
2V Differential Composite (+OUTFILTERED,
P-P
–OUTFILTERED), f1 = 19.5MHz, f2 = 20.5MHz
2V Differential Composite (+OUT, –OUT),
L
–71
49
dBc
P-P
R = 400Ω, f1 = 19.5MHz, f2 = 20.5MHz
OIP3
NF
Output Third-Order Intercept
Differential (+OUTFILTERED, –OUTFILTERED),
f1 = 19.5MHz, f2 = 20.5MHz
dBm
20M
Noise Figure
Measured Using DC954A Demo Board (Note 5)
18.6
3.8
dB
nV/√Hz
dBm
e
Input Referred Noise Voltage Density
1dB Compression Point
n20M
R = 100Ω (Note 5)
L
17.7
64026fa
4
LT6402-6
AC ELECTRICAL CHARACTERISTICS
TA = 25°C, VCCA = VCCB = VCCC = 5V,VEEA = VEEB = VEEC = 0V,
ENABLE = 0.8V, +INA shorted to +INB (+IN), –INA shorted to –INB (–IN), VOCM = 2.2V, Input common mode voltage = 2.2V, no RLOAD
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
25MHz Signal
Second/Third Harmonic Distortion
Third-Order IMD
2V Differential (+OUTFILTERED, –OUTFILTERED)
–84
–69
–88
dBc
dBc
dBc
P-P
2V Differential (+OUT, –OUT)
P-P
2V Differential Composite (+OUTFILTERED,
P-P
–OUTFILTERED), f1 = 24.5MHz, f2 = 25.5MHz
2V Differential Composite (+OUT, –OUT),
L
–67
47
dBc
P-P
R = 400Ω, f1 = 24.5MHz, f2 = 25.5MHz
OIP3
NF
Output Third-Order Intercept
Differential (+OUTFILTERED, –OUTFILTERED),
f1 = 24.5MHz, f2 = 25.5MHz (Note 5)
dBm
25M
Noise Figure
Measured Using DC954A Demo Board
12.6
3.9
dB
nV/√Hz
dBm
e
Input Referred Noise Voltage Density
1dB Compression Point
n25M
R = 100Ω (Note 5)
L
17.2
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: The LT6402C is guaranteed to meet specified performance from
0°C to 70°C. It is designed, characterized and expected to meet specified
performance from –40°C and 85°C but is not tested or QA sampled
at these temperatures. The LT6402I is guaranteed to meet specified
performance from –40°C to 85°C.
Note 2: As long as output current and junction temperature are kept below
the Absolute Maximum Ratings, no damage to the part will occur.
Note 3: The LT6402 is guaranteed functional over the operating
temperature range of –40°C to 85°C.
Note 5: Since the LT6402-6 is a feedback amplifier with low output
impedance, a resistive load is not required when driving an ADC.
Therefore, typical output power is very small. In order to compare the
LT6402-6 with typical g amplifiers that require 50Ω output loading, the
m
LT6402-6 output voltage swing driving an ADC is converted to OIP3 and
P1dB as if it were driving a 50Ω load.
TYPICAL PERFORMANCE CHARACTERISTICS
Frequency Response,
RLOAD = 400Ω
Frequency Response vs CLOAD
,
Frequency Response,
RLOAD = 100Ω
RLOAD = 400Ω
15
12
9
6
3
0
–3
–6
–9
15
10
30
25
20
15
UNFILTERED OUTPUTS
FILTERED OUTPUTS
UNFILTERED
FILTERED
5
0
10
5
–5
–12
–15
–18
–21
–24
–27
–30
0
–5
–10
–15
–20
–25
V
= 100mV
P-P
IN
V
= 100mV
P-P
UNFILTERED: R
FILTERED: R
= 400Ω
IN
0pF
LOAD
LOAD
–10
–15
–20
UNFILTERED: R
= 100Ω
LOAD
= 300Ω
1.6pF
5pF
FILTERED: R
= 100Ω
LOAD
(EXTERNAL) + 100Ω
(INTERNAL, FILTERED OUTPUTS)
(INTERNAL, FILTERED OUTPUTS)
10 100
FREQUENCY (MHz)
10pF
1
10 100
FREQUENCY (MHz)
1000
1
1000
1
10
100
1000
FREQUENCY (MHz)
64026 G01
64026 G03
64026 G02
64026fa
5
LT6402-6
TYPICAL PERFORMANCE CHARACTERISTICS
Third Order Intermodulation
Third Order Intermodulation
Output Third Order Intercept vs
Frequency, Differential Input,
No RLOAD
Distortion vs Frequency,
Distortion vs Frequency,
Differential Input, No RLOAD
Differential Input, RLOAD = 400Ω
–40
60
55
50
45
40
35
30
25
–45
2 TONES
2 TONES
2V COMPOSITE
2V COMPOSITE
P-P
P-P
–50 1MHz TONE SPACING
–55 1MHz TONE SPACING
FILTERED OUTPUTS
UNFILTERED
–65
–60
OUTPUTS
UNFILTERED
OUTPUTS
–70
–75
UNFILTERED OUTPUTS
FILTERED
OUTPUTS
FILTERED
OUTPUTS
–80
–90
–85
–95
–100
–105
5
15
20
25
30
35
25
FREQUENCY (MHz)
35
5
15
20
25
30
35
10
5
10
15
20
30
10
FREQUENCY (MHz)
FREQUENCY (MHz)
64026 G05
64026 G04
64026 G06
Output Third Order Intercept vs
Frequency, Differential Input,
RLOAD = 400Ω
Distortion vs Frequency,
Distortion vs Frequency,
Differential Input, No RLOAD
Differential Input, No RLOAD
–40
–50
–60
–70
–80
–90
–100
51
47
43
39
35
31
27
–40
–50
–60
–70
–80
–90
–100
UNFILTERED OUTPUTS
FILTERED OUTPUTS
V
= 2V
V
= 2V
OUT
P-P
OUT
P-P
FILTERED
OUTPUTS
UNFILTERED
OUTPUTS
HD3
HD3
HD2
HD2
2 TONES
2V COMPOSITE
P-P
1MHz TONE SPACING
25
FREQUENCY (MHz)
30
5
10
15
20
35
1
10
FREQUENCY (MHz)
100
1
10
FREQUENCY (MHz)
100
64026 G09
64026 G08
64026 G07
Distortion vs Output Amplitude,
20MHz Differential Input, No RLOAD
Output 1dB Compression
vs Frequency
Distortion vs Output Amplitude,
20MHz Differential Input, No RLOAD
–70
–75
–80
–85
–90
–70
–75
25
20
15
10
5
UNFILTERED OUTPUTS
FILTERED OUTPUTS
UNFILTERED OUTPUTS
400Ω LOAD
–80
–85
HD2
100Ω LOAD
HD2
HD3
HD3
0
–90
–95
–5
–10
–15
–20
–100
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
1
10
100
1000
OUTPUT AMPLITUDE (dBm)
OUTPUT AMPLITUDE (dBm)
FREQUENCY (MHz)
64026 G12
64206 G10
64026 G11
64026fa
6
LT6402-6
TYPICAL PERFORMANCE CHARACTERISTICS
Input Referred Noise Voltage
Noise Figure vs Frequency
vs Frequency
Reverse Isolation vs Frequency
0
–20
40
35
30
25
20
15
10
35
30
25
20
15
10
5
UNFILTERED OUTPUTS
MEASURED USING
DC954 DEMO BOARD
–40
–60
–80
–100
–120
0
1
10
100
1000
10
100
1000
10
1000
100
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
64026 G13
64026 G15
64206 G14
Input Reflection Coefficient
vs Frequency
Differential Output Impedance
vs Frequency
Differential Input Impedance
vs Frequency
100
10
1
0
–5
500
400
300
200
100
0
MEASURED USING
DC954 DEMO BOARD
UNFILTERED OUTPUTS
–10
–15
–20
–25
–30
–35
IMPEDANCE MAGNITUDE
IMPEDANCE PHASE
–100
10
100
1000
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
64206 G17
64026 G18
64026 G16
Output Reflection Coefficient
vs Frequency
PSRR, CMRR vs Frequency
Small-Signal Transient Response
120
110
100
90
80
70
60
50
40
30
20
10
0
0
–5
2.280
2.260
2.240
2.220
2.200
2.180
2.160
2.140
2.120
UNFILTERED OUTPUTS
MEASURED USING
DC954 DEMO BOARD
PSRR
CMRR
–10
–15
–20
–25
–30
–35
–40
1
10
100
1000
1
10
100
1000
TIME (5ns/DIV)
FREQUENCY (MHz)
FREQUENCY (MHz)
64026 G20
64026 G19
64026 G21
64026fa
7
LT6402-6
TYPICAL PERFORMANCE CHARACTERISTICS
Distortion vs Output Common
Mode Voltage, LT6402-6 Driving
an LTC2249 14-Bit ADC
Overdrive Recovery Time
Turn-On Time
–60
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
FILTERED OUTPUTS
NO R
LOAD
= 20MHz 2V
–65
–70
V
OUT
P-P
–75
–80
–85
–90
–95
HD2
HD3
TIME (125ns/DIV)
–100
1.2
1.4
1.8 2.0 2.2 2.4
1.0
1.6
TIME (25ns/DIV)
OUTPUT COMMON MODE VOLTAGE (V)
64026 G22
64026 G23
64026 G24
20MHz 8192 Point FFT, LT6402-6
Driving an LTC2249 14-Bit ADC
10MHz 8192 Point FFT, LT6402-6
Driving an LTC2249 14-Bit ADC
Turn-Off Time
0
–10
–20
–30
–40
–50
–60
–70
–80
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–90
–100
–110
–120
–130
–140
–100
–110
–120
–130
–140
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
TIME (250ns/DIV)
FREQUENCY (MHz)
FREQUENCY (MHz)
64026 G27
64026 G25
64026 G26
20MHz 2-Tone 32768 Point FFT,
LT6402-6 Driving an LTC2249
14-Bit ADC
25MHz 8192 Point FFT, LT6402-6
Driving an LTC2249 14-Bit ADC
0
–10
–20
–30
–40
0
–10
–20
–30
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–140
–100
–110
–120
–130
–140
0
2
4
6
8
10 12 14 16 18 20
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5
FREQUENCY (MHz)
FREQUENCY (MHz)
64026 G28
64026 G29
64026fa
8
LT6402-6
PIN FUNCTIONS
V
(Pin 2): This pin sets the output common mode
+OUTFILTERED, –OUTFILTERED (Pins 6, 7): Filtered
Outputs. These pins add a series 50Ω resistor from the
unfiltered outputs and three 14pF capacitors. Each output
OCM
voltage. Without additional biasing, both inputs bias to
this voltage as well. This input is high impedance.
has 14pF to V , plus an additional 14pF between each pin
EE
V
, V , V
CCA CCB CCC
(Pins 3, 10, 1): Positive Power Supply
(See the Block Diagram). This filter has a –3dB bandwidth
of 75MHz.
(Normally Tied to 5V). All three pins must be tied to the
same voltage. Bypass each pin with 1000pF and 0.1μF
capacitors as close to the package as possible. Split
ENABLE (Pin 11): This pin is a TTL logic input referenced
supplies are possible as long as the voltage between V
and V is 5V.
to the V pin. If low, the LT6402-6 is enabled and draws
CC
EEC
typically 30mA of supply current. If high, the LT6402-6 is
EE
disabled and draws typically 250μA.
V
, V , V (Pins 4, 9, 12): Negative Power Supply
EEA EEB EEC
(Normally Tied to Ground). All three pins must be tied to
+INA, +INB (Pins 15, 16): Positive Inputs. These pins are
normally tied together. These inputs may be DC- or AC-
coupled. If the inputs are AC-coupled, they will self-bias
the same voltage. Split supplies are possible as long as
the voltage between V and V is 5V. If these pins are
CC
EE
nottiedtoground, bypasseachpinwith1000pFand0.1μF
to the voltage applied to the V
pin.
OCM
capacitors as close to the package as possible.
–INA, –INB (Pins 14, 13): Negative Inputs. These pins are
normally tied together. These inputs may be DC- or AC-
coupled. If the inputs are AC-coupled, they will self-bias
+OUT, –OUT (Pins 5, 8): Outputs (Unfiltered). These pins
are high bandwidth, low-impedance outputs. The DC
output voltage at these pins is set to the voltage applied
to the voltage applied to the V
pin.
OCM
at V
.
OCM
Exposed Pad (Pin 17): Tie the pad to V (Pin 12). If split
EEC
supplies are used, DO NOT tie the pad to ground.
64026fa
9
LT6402-6
BLOCK DIAGRAM
200Ω
V
EEA
V
CCA
–INA
14
14pF
200Ω
200Ω
–
+
+OUT
5
6
A
–INB
13
+OUTFILTERED
50Ω
V
EEA
V
CCC
200Ω
V
OCM
2
+
–
C
14pF
V
EEC
200Ω
200Ω
50Ω
–OUTFILTERED
–OUT
V
CCB
+INA
16
7
8
+
–
B
+INB
15
200Ω
14pF
V
EEB
V
EEB
200Ω
BIAS
11
64026 BD
3
10
1
4
9
12
V
V
V
ENABLE
V
EEA
V
V
EEC
CCA
CCB
CCC
EEB
APPLICATIONS INFORMATION
Circuit Description
Referring to the block diagram, the LT6402-6 uses a
closed-loop topology which incorporates 3 internal am-
plifiers. Two of the amplifiers (A and B) are identical and
drive the differential outputs. The third amplifier is used
to set the output common mode voltage. Gain and input
impedance are set by the 200Ω resistors in the internal
feedback network. Output impedance is low, determined
by the inherent output impedance of amplifiers A and B,
and further reduced by internal feedback.
The LT6402-6 is a low noise, low distortion differential
amplifier/ADC driver with:
• –3dB bandwidth
DC to 300MHz
• Fixed gain independent of R
2V/V (6dB)
LOAD
• Differential input impedance
The LT6402-6 also includes built-in single-pole output
filtering. The user has the choice of using the unfiltered
outputs, the filtered outputs (75MHz –3dB lowpass), or
modifying the filtered outputs to alter frequency response
by adding additional components. Many lowpass and
bandpass filters are easily implemented with just one or
200Ω
• Low output impedance
• Built-in, user adjustable output filtering
• Requires minimal support circuitry
two additional components.
64026fa
10
LT6402-6
APPLICATIONS INFORMATION
The LT6402-6 has been designed to minimize the need
for external support components such as transformers or
AC-coupling capacitors. As an ADC driver, the LT6402-6
requires no external components except for power-supply
bypass capacitors. This allows DC-coupled operation for
applications that have frequency ranges including DC.
At the outputs, the common mode voltage is set via the
Single-Ended to Differential Operation
The LT6402-6’s performance with single-ended inputs is
comparable to its performance with differential inputs.
This excellent single-ended performance is largely due
to the internal topology of the LT6402-6. Referring to
the block diagram, if the +INA and +INB pins are driven
with a single-ended signal (while –INA and –INB are tied
to AC ground), then the +OUT and –OUT pins are driven
differentially without any voltage swing needed from
amplifier C. Single-ended to differential conversion using
more conventional topologies suffers from performance
limitations due to the common mode amplifier.
V
OCM
pin, allowingtheLT6402-6todriveADCsdirectly. No
outputAC-couplingcapacitorsortransformersareneeded.
At the inputs, signals can be differential or single-ended
with virtually no difference in performance. Furthermore,
DC levels at the inputs can be set independently of the
outputcommonmodevoltage.Theseinputcharacteristics
often eliminate the need for an input transformer and/or
AC-coupling capacitors.
Driving ADCs
The LT6402-6 has been specifically designed to interface
directly with high speed Analog to Digital Converters
(ADCs).Ingeneral,theseADCshavedifferentialinputs,with
an input impedance of 1kΩ or higher. In addition, there is
generally some form of lowpass or bandpass filtering just
prior to the ADC to limit input noise at the ADC, thereby
improving system signal to noise ratio. Both the unfiltered
and filtered outputs of the LT6402-6 can easily drive the
Input Impedance and Matching Networks
Calculation of the input impedance of the LT6402-6 is not
straightforward from examination of the block diagram
because of the internal feedback network. In addition, the
inputimpedancewhendrivendifferentiallyisdifferentthan
when driven single-ended.
DIFFERENTIAL
SINGLE-ENDED
LT6402-6
200Ω
133Ω
13
–INB
–
IF IN
8
5
14
For single-ended 50Ω applications, an 80.6Ω shunt
matching resistor to ground will result in the proper input
termination (Figure 1). For differential inputs there are
several termination options. If the input source is 50Ω
differential, then the input matching can be accomplished
byeithera67Ωshuntresistoracrosstheinputs(Figure 3),
or equivalent 33Ω shunt resistors on each of the inputs
to ground (Figure 2).
–OUT
LT6402-6
+OUT
–INA
33Ω
33Ω
Z
IN
= 50Ω
DIFFERENTIAL
15
16
+INB
+INA
+
64026 F02
IF IN
Figure 2. Input Termination for Differential 50Ω Input Impedance
13
13
–INB
–INB
–INA
–
8
5
IF IN
8
5
14
–OUT
LT6402-6
+OUT
–OUT
LT6402-6
+OUT
14
–INA
0.1μF
Z
= 50Ω
DIFFERENTIAL
IN
67Ω
15
16
IF IN
+INB
+INA
15
16
+INB
+INA
+
64026 F01
64026 F03
IF IN
80.6Ω
Z
= 50Ω
IN
SINGLE-ENDED
Figure 3. Alternate Input Termination for Differential
50Ω Input Impedance
Figure 1. Input Termination for Single-Ended
50Ω Input Impedance
64026fa
11
LT6402-6
APPLICATIONS INFORMATION
resistor/capacitor combination creates filtered outputs
that look like a series 50Ω resistor with a 42pF capacitor
shuntingeachfilteredoutputtoACground,givinga–3dB
bandwidth of 75MHz.
high impedance inputs of these differential ADCs. If the
filtered outputs are used, then cutoff frequency and the
type of filter can be tailored for the specific application if
needed.
The filter cutoff frequency is easily modified with just a
fewexternalcomponents.Toincreasethecutofffrequency,
simplyadd2equalvalueresistors, onebetween+OUTand
+OUTFILTEREDandtheotherbetween–OUTand–OUTFIL-
TERED (Figure 6). These resistors are in parallel with the
internal 50Ω resistor, lowering the overall resistance and
increasingfilterbandwidth. Todoublethefilterbandwidth,
for example, add two external 50Ω resistors to lower the
seriesresistanceto25Ω.The42pFofcapacitanceremains
unchanged, so filter bandwidth doubles.
Wideband Applications
(Using the +OUT and –OUT Pins)
In applications where the full bandwidth of the LT6402-6
is desired, the unfiltered output pins (+OUT and –OUT)
should be used. They have a low output impedance;
therefore, gain is unaffected by output load. Capacitance
in excess of 5pF placed directly on the unfiltered outputs
results in additional peaking and reduced performance.
When driving an ADC directly, a small series resistance
is recommended between the LT6402-6’s outputs and the
ADC inputs (Figure 4). This resistance helps eliminate any
resonances associated with bond wire inductances of
either the ADC inputs or the LT6402-6’s outputs. A value
between 10Ω and 25Ω gives excellent results.
To decrease filter bandwidth, add two external capacitors,
one from +OUTFILTERED to ground, and the other from
–OUTFILTERED to ground. A single differential capacitor
connected between +OUTFILTERED and –OUTFILTERED
LT6402-6
8
–OUT
V
EE
14pF
50Ω
10Ω TO 25Ω
8
–OUT
7
6
–OUTFILTERED
+OUTFILTERED
FILTERED OUTPUT
(75MHz)
14pF
LT6402-6
+OUT
ADC
50Ω
14pF
10Ω TO 25Ω
5
64026 F04
V
EE
5
+OUT
64026 F05
Figure 4. Adding Small Series R at LT6402-6 Output
Figure 5. LT6402-6 Internal Filter Topology –3dB BW ≈75MHz
Filtered Applications
(Using the +OUTFILTERED and –OUTFILTERED Pins)
LT6402-6
8
–OUT
50Ω
V
EE
Filtering at the output of the LT6402-6 is often desired to
14pF
50Ω
provide either anti-aliasing or improved signal to noise
ratio. To simplify this filtering, the LT6402-6 includes an
additional pair of differential outputs (+OUTFILTERED
and –OUTFILTERED) which incorporate an internal
lowpass filter network with a –3dB bandwidth of 75MHz
(Figure 5). These pins each have an output impedance
7
6
–OUTFILTERED
FILTERED OUTPUT
(150MHz)
14pF
50Ω
14pF
+OUTFILTERED
50Ω
V
EE
5
+OUT
64026 F06
of 50Ω. Internal capacitances are 14pF to V on each
EE
filtered output, plus an additional 14pF capacitor con-
necteddifferentiallybetweenthetwofilteredoutputs.This
Figure 6. LT6402-6 Internal Filter Topology Modified
for 2x Filter Bandwidth (2 External Resistors)
64026fa
12
LT6402-6
APPLICATIONS INFORMATION
can also be used, but since it is being driven differentially
it will appear at each filtered output as a single-ended
capacitance of twice the value. To halve the filter band-
width, for example, two 42pF capacitors could be added
(one from each filtered output to ground). Alternatively
one 21pF capacitor could be added between the filtered
outputs, again halving the filter bandwidth. Combinations
of capacitors could be used as well; a three capacitor
solution of 14pF from each filtered output to ground plus
a 14pF capacitor between the filtered outputs would also
halve the filter bandwidth (Figure 7).
Output Common Mode Adjustment
TheLT6402-6’soutputcommonmodevoltageissetbythe
pin. It is a high-impedance input, capable of setting
V
OCM
the output common mode voltage anywhere in a range
from 1.1V to 3.6V. Bandwidth of the V pin is typically
OCM
200MHz, so for applications where the V
pin is tied to
OCM
a DC bias voltage, a 0.1μF capacitor at this pin is recom-
mended. For best distortion performance, the voltage at
the V
pin should be between 1.2V and 2.6V.
OCM
When interfacing with most ADCs, there is generally a
output pin that is at about half of the supply voltage
V
OCM
Bandpass filtering is also easily implemented with just a
few external components. An additional 560pF and 62nH,
each added differentially between +OUTFILTERED and
–OUTFILTERED creates a bandpass filter with a 26MHz
center frequency, –3dB points of 23MHz and 30MHz, and
1.6dB of insertion loss (Figure 8).
of the ADC. For 5V ADCs such as the LTC17XX family, this
output pin should be connected directly (with the
V
OCM
addition of a 0.1μF capacitor) to the input V
pin of the
OCM
LT6402-6. For 3V ADCs such as the LTC22XX families,
the LT6402-6 will function properly using the 1.65V from
the ADC’s V reference pin, but improved Spurious Free
CM
Dynamic Range (SFDR) and distortion performance can
LT6402-6
8
be achieved by level-shifting the LTC22XX’s V reference
–OUT
CM
V
EE
voltage up to at least 1.8V. This can be accomplished as
14pF
50Ω
shown in Figure 9 by using a resistor divider between the
14pF
7
–OUTFILTERED
LTC22XX’sV outputpinandV andthenbypassingthe
CM
CC
FILTERED OUTPUT
(37.5MHz)
LT6402-6’s V
pin with a 0.1μF capacitor. For a com-
14pF
14pF
OCM
mon mode voltage above 1.9V, AC coupling capacitors
are recommended between the LT6402-6 and LTC22XX
ADCs because of the input voltage range constraints of
the ADC.
50Ω
14pF
+OUTFILTERED
+OUT
6
5
14pF
V
EE
64026 F07
3V
Figure 7. LT6402-6 Internal Filter Topology Modified
for 1/2x Filter Bandwidth (3 External Capacitors)
11k
1.9V
0.1μF
LT6402-6
4.02k
8
–OUT
2
V
13
EE
31 1.5V
–INB
–INA
14
14pF
50Ω
V
OCM
V
CM
10Ω
10Ω
6
7
1
2
+
–
+OUTFILTERED
LT6402-6
AIN
7
–OUTFILTERED
0.1μF
LTC22xx
–OUTFILTERED
AIN
15
16
14pF
FILTERED OUTPUT
+INB
+INA
IF IN
64026 F09
50Ω
14pF
+OUTFILTERED
+OUT
80.6Ω
6
5
V
EE
Figure 9. Level Shifting 3V ADC VCM Voltage for
Improved SFDR
64026 F08
Figure 8. LT6402-6 Output Filter Modified for Bandpass
Filtering (1 External Inductor, 1 External Capacitor)
64026fa
13
LT6402-6
APPLICATIONS INFORMATION
Large Output Voltage Swings
additional input bias current totaling 1.5mA will flow into
the –INA and –INB inputs.
The LT6402-6 has been designed to provide the 3.2V
P-P
output swing needed by the LTC1748 family of 14-bit
low-noise ADCs. This additional output swing improves
system SNR by up to 4dB.
Application (Demo) Boards
TheDC954ADemoBoardhasbeencreatedforstand-alone
evaluation of the LT6402-6 with either single-ended or
differential input and output signals. As shown, it accepts
a single-ended input and produces a single-ended output
so that the LT6402-6 can be evaluated using standard
laboratory test equipment. For more information on this
Demo Board, please refer to the layout and schematic
diagrams found later in this data sheet.
Input Bias Voltage and Bias Current
The input pins of the LT6402-6 are internally biased to
the voltage applied to the V
pin. No external biasing
OCM
resistors are needed, even for AC-coupled operation. The
input bias current is determined by the voltage difference
between the input common mode voltage and the V
OCM
pin (which sets the output common mode voltage). For
There are also additional demo boards available that
combine the LT6402-6 with a variety of different Linear
Technology ADCs. Please contact the factory for more
information on these demo boards.
example, if the inputs are tied to 2.5V with the V pin
OCM
at 2.2V, then a total input bias current of 1.5mA will flow
into the LT6402-6’s +INA and +INB pins. Furthermore, an
TYPICAL APPLICATION
Top Silkscreen
64026fa
14
LT6402-6
PACKAGE DESCRIPTION
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691)
0.70 ±0.05
3.50 ± 0.05
2.10 ± 0.05
1.45 ± 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
R = 0.115
TYP
0.75 ± 0.05
3.00 ± 0.10
(4 SIDES)
15 16
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
1
2
1.45 ± 0.10
(4-SIDES)
(UD16) QFN 0904
0.200 REF
0.25 ± 0.05
0.00 – 0.05
0.50 BSC
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
64026fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LT6402-6
TYPICAL APPLICATION
Demo Circuit DC954A Schematic (AC Test Circuit)
R18
0Ω
R17
0Ω
V
CC
V
CC
GND
V
CC
2
1
2
1
1
SW1
3
TP1
ENABLE
C17
1000pF
C18
0.01μF
R16
0Ω
2
1
1
2
R2
R4
R14
C11
[1]
12
11
10
9
C2
0.1μF
C4
0Ω
33Ω
0Ω
R6
0Ω
R10
R12
75Ω
0.1μF
V
ENABLE
V
V
EEC
CCB EEB
–OUT
24.9Ω
13
14
15
16
8
–INB
1
2
1
2
J1
–IN
R8
[1]
J4
–OUT
T1
T2
C21
0.1μF
7
6
5
1:1 Z-RATIO
4:1 Z-RATIO
5
4
1
3
–INA
+INB
+INA
–OUTFILTERED
+OUTFILTERED
+OUT
3
1
4
5
2
1
2
2
L1
[1]
C8
[1]
R15
[1]
R7
[1]
0dB
LT6402-6
4.8dB
0dB
1
2
MINI-
M/A-COM
ETC1-1T
0dB
–6dB
J2
+IN
J5
+OUT
C1
0.1μF
C3
0.1μF
CIRCUITS
TCM 4-19
R9
24.9Ω
R11
75Ω
R5
0Ω
1
2
1
2
V
V
V
V
CCC
OCM
CCA
EEA
1
2
2
R1
[1]
R3
33Ω
R13
[1]
C16
[1]
C22
0.1μF
1
2
3
4
V
CC
V
CC
1
2
1
2
1
2
1
2
1
C10
0.01μF
C9
1000pF
C12
1000pF
C13
0.01μF
V
CC
R19
14k
J3
V
OCM
2
1
C7
0.01μF
R20
11k
C5
0.1μF
J6
TEST IN
T3
T4
J7
1:4
4:1
TEST OUT
4
5
5
1
3
3
1
1
2
R22
C19, 0.1μF
C20, 0.1μF
2
2
R21
[1]
C6
[1]
0.1μF
1
2
1
2
MINI-
CIRCUITS
TCM 4-19
MINI-
CIRCUITS
TCM 4-19
4
1
2
64026 TA02
TP2
CC
V
CC
V
NOTES: UNLESS OTHERWISE SPECIFIED,
[1] DO NOT STUFF.
1
1
2
2
1
C14
4.7μF
C15
1μF
1
TP3
GND
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
A = 2V/V, NF = 12.3dB, OIP3 = 38dBm at 70MHz
LT1993-2
LT1993-4
LT1993-10
LT5514
800MHz Differential Amplifier/ADC Driver
900MHz Differential Amplifier/ADC Driver
700MHz Differential Amplifier/ADC Driver
Ultralow Distortion IF Amplifier/ADC Driver
300MHz Differential Amplifier/ADC Driver
300MHz Differential Amplifier/ADC Driver
V
A = 4V/V, NF = 14.5dB, OIP3 = 40dBm at 70MHz
V
A = 10V/V, NF = 12.7dB, OIP3 = 40dBm at 70MHz
V
Digitally Controlled Gain Output IP3 47dBm at 100MHz
A = 12dB, e = 2.6nV/√Hz at 20MHz, 150mW
LT6402-12
LT6402-20
LT6411
V
n
A = 20dB, e = 1.9nV/√Hz at 20MHz, 150mW
V
n
650MHz Differential ADC Driver/Dual Selectable Gain Amplifier
3300V/μs Slew Rate, 16mA Current Consumption, Selectable Gain:
A = –1, +1, +2
V
LT6600-5
LT6600-10
LT6600-20
Very Low Noise Differential Amplifier and 5MHz Lowpass Filter
Very Low Noise Differential Amplifier and 10MHz Lowpass Filter
Very Low Noise Differential Amplifier and 20MHz Lowpass Filter
82dB S/N with 3V Supply, SO-8 Package
82dB S/N with 3V Supply, SO-8 Package
76dB S/N with 3V Supply, SO-8 Package
64026fa
LT 1007 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
© LINEAR TECHNOLOGY CORPORATION 2006
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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