LT6555IUF#TR [Linear]
LT6555 - 650MHz Gain of 2 Triple 2:1Video Multiplexer; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C;
| 型号： | LT6555IUF#TR |
| 厂家： | 
Linear |
| 描述： | LT6555 - 650MHz Gain of 2 Triple 2:1Video Multiplexer; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C |
| 文件： | 总16页 (文件大小：357K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT6555
650MHz Gain of 2 Triple
2:1Video Multiplexer
U
DESCRIPTIO
FEATURES
The LT®6555 is a high speed triple 2:1 video multiplexer
with an internally fixed gain of 2. The individual amplifiers
are optimized for performance with a double terminated
75Ω video load and feature a –3dB 2VP-P bandwidth of
450MHz, making them ideal for driving very high resolu-
tion video signals. Separate power supply pins for each
amplifier boost channel separation to 72dB, allowing the
LT6555 to excel in many high speed applications.
■
650MHz –3dB Small Signal Bandwidth
■
450MHz –3dB 2VP-P Large-Signal Bandwidth
■
120MHz ±0.1dB Bandwidth
■
High Slew Rate: 2200V/µs
■
Fixed Gain of 2; No External Resistors Required
■
72dB Channel Separation at 10MHz
50dB Channel Separation at 100MHz
■
■
–80dBc 2nd Harmonic Distortion at 10MHz, 2VP-P
■
–70dBc 3rd Harmonic Distortion at 10MHz, 2VP-P
While the performance of the LT6555 is optimized for dual
supply operation, it can also be operated with a single
supply as low as 4.5V. Using dual 5V supplies, each
amplifier draws only 9mA. When disabled, the amplifiers
draw less than 500µA and the outputs become high
impedance.
■
Low Supply Current: 9mA per Amplifier
■
6.5ns 0.1% Settling Time for 2V Step
■
ISS ≤ 500µA per Amplifier when Disabled
■
Differential Gain of 0.033%, Differential
Phase of 0.022°
■
Wide Supply Range: ±2.25V (4.5V) to ±6V (12V)
■
The LT6555 is manufactured on Linear Technology’s
proprietary low voltage complementary bipolar process
and is available in 24-lead SSOP and ultra-compact
24-lead QFN packages.
Available in 24-Lead SSOP and 24-Lead QFN
Packages
U
APPLICATIO S
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
■
RGB Amplifiers
■
UXGA Video Multiplexing
■
LCD Projectors
U
TYPICAL APPLICATIO
RGB Multiplexer and Line Driver
+
V
R
G
B
LT6555
INA
INA
INA
75Ω
75Ω
×2
Video Amplitude Transient Response
R
G
OUT
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
75Ω
75Ω
75Ω
75Ω
AGND
75Ω
75Ω
×2
OUT
R
G
B
INB
INB
INB
75Ω
V
V
= 0V TO 700mV
= ±5V
IN
S
L
0
–0.2
–0.4
75Ω
R
= 150Ω
×2
B
OUT
75Ω
T
A
= 25°C
0
2
4
6
8
10 12 14 16 18 20
SELECT A/B
TIME (ns)
75Ω
ENABLE
DGND
6555 G21
–
6555 TA01a
V
6555f
1
LT6555
W W U W
ABSOLUTE AXI U RATI GS (Note 1)
Total Supply Voltage (V+ to V–) ............................ 12.6V
Input Current (Note 2) ........................................ ±10mA
Output Current (Continuous) ............................. ±70mA
EN to DGND Voltage (Note 2) ................................. 5.5V
SEL to DGND Voltage (Note 2) .................................. 8V
Output Short-Circuit Duration (Note 3)............ Indefinite
Operating Temperature Range (Note 4) ... –40°C to 85°C
Specified Temperature Range (Note 5).... –40°C to 85°C
Junction Temperature
SSOP ................................................................ 150°C
QFN .................................................................. 125°C
Storage Temperature Range
SSOP ................................................. –65°C to 150°C
QFN ................................................... –65°C to 125°C
Lead Temperature (Soldering, 10 sec)
SSOP ................................................................ 300°C
U
W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
TOP VIEW
ORDER PART
NUMBER
ORDER PART
+
NUMBER
1
2
V
24
23
22
21
20
19
18
17
16
15
14
13
IN1A
DGND
IN2A
EN
24 23 22 21 20 19
LT6555CGN
LT6555IGN
LT6555CUF
LT6555IUF
3
SEL A/B
+
V
1
2
3
4
5
6
18
17
16
V
REF
+
4
V
V
REF
IN3A
OUT1
–
G=+2
G=+2
G=+2
5
OUT1
IN3A
AGND1
IN1B
AGND1
V
25
–
–
6
V
V
15 OUT2
+
7
OUT2
IN1B
14
V
+
8
V
AGND2
IN2B
AGND2
13 OUT3
UF PART*
MARKING
9
OUT3
7
8
9 10 11 12
–
10
11
12
V
AGND3
IN3B
+
6555
V
+
–
V
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
V
GN PACKAGE
TJMAX = 125°C, θJA = 37°C/W, θJC = 2.6°C/W
24-LEAD PLASTIC SSOP
EXPOSED PAD (PIN 25) IS V–
MUST BE SOLDERED TO PCB
TJMAX = 150°C, θJA = 90°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VS = ±5V, RL = 150Ω, CL = 1.5pF, VEN = 0.4V, VAGND, VDGND, VVREF = 0V.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Input Referred Offset Voltage
V
= 0V, V = V /2
5
±16
±24
mV
mV
OS
IN
OS
OUT
●
●
●
I
Input Current
–17
400
1
±45
µA
kΩ
pF
IN
R
Input Resistance
V
= ±1V
100
56
IN
IN
IN
C
Input Capacitance
f = 100kHz
V = ±2.25V to ±6V (Note 6)
PSRR
Power Supply Rejection Ratio
Input Current Power Supply Rejection
Gain Error
●
●
●
62
1
dB
S
I
V = ±2.25V to ±6V (Note 6)
±4
µA/V
%
PSRR
S
A ERR
V
= ±2V, Nominal Gain 2V/V
OUT
±2.5
V
A MATCH
Gain Matching
Any One Channel to Another
(Note 7)
±0.33
±3.4
%
V
V
Output Voltage Swing
±3.15
±3.0
V
V
OUT
●
6555f
2
LT6555
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VS = ±5V, RL = 150Ω, CL = 1.5pF, VEN = 0.4V, VAGND, VDGND, VVREF = 0V.
SYMBOL
PARAMETER
CONDITIONS
R = ∞
MIN
TYP
MAX
UNITS
I
Supply Current, Per Amplifier
9
12
14
mA
mA
S
L
●
Supply Current, Disabled, Per Amplifier
Enable Pin Current
V
V
= 4V, R = ∞
●
●
47
42
500
500
µA
µA
EN
EN
L
= Open, R = ∞
L
I
I
I
V
V
= 0.4V
= 4V
●
●
–200
–75
–95
–21
µA
µA
EN
EN
EN
Select Pin Current
V
V
= 0.4V
= 4V
●
●
–50
–50
–5
–1
µA
µA
SEL
SC
SEL
SEL
Output Short-Circuit Current
Slew Rate
R = 0Ω, V = ±1V
●
±50
±105
2200
650
mA
V/µs
MHz
MHz
MHz
MHz
L
IN
SR
±1V on ±2.5V Output Step (Note 8)
1600
–3dB BW
0.1dB BW
FPBW
Small-Signal –3dB Bandwidth
Gain Flatness ±0.1dB Bandwidth
Full Power Bandwidth 2V
Full Power Bandwidth 4V
All-Hostile Crosstalk
V
V
V
V
= 200mV
= 200mV
OUT
OUT
OUT
OUT
P-P
120
P-P
= 2V (Note 9)
250
350
P-P
= 4V (Note 9)
175
P-P
f = 10MHz, V = 1V
f = 100MHz, V = 1V
–72
–50
dB
dB
IN
P-P
IN
P-P
Selected Channel to Unselected
Channel Crosstalk
f = 10MHz, V = 1V
–80
–55
dB
dB
IN
P-P
f = 100MHz, V = 1V
IN
P-P
Channel Select Output Transient
Channel-to-Channel Select Time
INA = INB = 0V
200
8
mV
P-P
INA = –1V, INB = 1V
from 50% SEL to V
ns
= 0V
OUT
t
Settling Time
0.1% of V
, V = 2V
6.5
520
ns
ps
%
S
FINAL STEP
t , t
Small-Signal Rise and Fall Time
Differential Gain
10% to 90%, V
(Note 10)
= 400mV
P-P
R
F
OUT
dG
dP
0.033
0.022
–80
Differential Phase
(Note 10)
Deg
dBc
dBc
HD2
HD3
2nd Harmonic Distortion
3rd Harmonic Distortion
f = 10MHz, V
f = 10MHz, V
= 2V
OUT
P-P
= 2V
–70
OUT
P-P
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: This parameter is guaranteed to meet specified performance
through design and characterization. It is not production tested.
Note 3: As long as output current and junction temperature are kept below
the Absolute Maximum Ratings, no damage to the part will occur.
Depending on the supply voltage, a heat sink may be required.
Note 4: The LT6555C is guaranteed functional over the operating
temperature range of –40°C to 85°C.
Note 5: The LT6555C is guaranteed to meet specified performance from
0°C to 70°C. The LT6555C is designed, characterized and expected to
meet specified performance from –40°C and 85°C but is not tested or QA
sampled at these temperatures. The LT6555I is guaranteed to meet
specified performance from –40°C to 85°C.
Note 6: In order to follow the constraints for 4.5V operation for PSRR
–
and I
testing at ±2.25V, the DGND pin is set to V , the EN pin is set
PSRR
–
–
–
to V + 0.4V, and the SEL pin is set to either V + 0.4V or V + 4V. At ±6V
and all other cases, DGND is set to ground and the EN and SEL pins are
referenced from it.
Note 7: The V pin is set to 1V when testing positive swing and –1V
REF
when testing negative swing to ensure that the internal input clamps do
not limit the output swing.
Note 8: Slew rate is 100% production tested using both inputs of
channel 2. Slew rates of channels 1 and 3 are guaranteed through
design and characterization.
Note 9: Full power bandwidth is calculated from the slew rate:
FPBW = SR/(π • V
)
P-P
Note 10: Differential gain and phase are measured using a Tektronix
TSG120YC/NTSC signal generator and a Tektronix 1780R video
measurement set. The resolution of this equipment is better than 0.05%
and 0.05°. Nine identical amplifier stages were cascaded giving an
effective resolution of better than 0.0056% and 0.0056%.
6555f
3
LT6555
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current per Amplifier
Supply Current per Amplifier
Supply Current per Amplifier
vs EN Pin Voltage
vs Temperature
vs Supply Voltage
12
10
8
12
10
8
12
10
8
V
R
V
= ±5V
= ∞
IN
V
A
, V , V
, V
= 0V
V
S
= ±5V
= ∞
S
L
EN IN DGND SEL
T
= 25°C
R
L
= 0V
V
= 0V
IN
V
= 0V
EN
T
= –55°C
V
= 0.4V
A
T
EN
= 25°C
A
6
6
6
T
= 125°C
A
4
4
4
2
2
2
V
= 4V
EN
0
0
0
0
1
2
3
4
5
6
7
8
9
10 11 12
–55 –35 –15
5
25 45 65 85 105 125
0
2.0
3.0 3.5
0.5 1.0 1.5
2.5
4.0
TEMPERATURE (°C)
TOTAL SUPPLY VOLTAGE (V)
EN PIN VOLTAGE (V)
6555 G02
6555 G01
6555 G03
Input Bias Current
vs Temperature
Input Referred Offset Voltage
vs Temperature
EN Pin Current vs EN Pin Voltage
0
–5
15
10
0
–20
V
V
= ±5V
IN
V
S
= ±5V
V
V
= ±5V
DGND
S
S
= 0V
= 0V
V
= 0V
IN
–10
–15
–20
–25
–30
–35
–40
–40
V
= 1.5V
IN
5
T
A
= 125°C
–60
0
T
A
= –55°C
V
= –1.5V
IN
–80
T
A
= 25°C
–5
–100
–120
–140
–10
–15
25 45
5
–55 –35 –15
5
65 85 105 125
0
1
2
3
4
–55 –35 –15
5
25 45 65 85 105 125
EN PIN VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
6555 G05
6555 G06
6555 G04
Maximum Output Voltage Swing
vs VREF Pin Voltage
Output Voltage Swing
vs ILOAD (Output High)
Output Voltage Swing
vs ILOAD (Output Low)
4
3
5
4
3
0
–1
–2
V
V
V
= ±5V
V
V
V
= ±5V
T
= –55°C
S
S
A
= 2V
= –2V
IN
IN
V
INPUT
T
= 125°C
A
REF
HIGH SWING
= 0V
= 0V
VREF
VREF
CLAMPING
T
= 25°C
A
T
= 25°C
A
2
T
= –55°C
A
T
= 125°C
A
1
0
T
= 125°C
A
V
= ±5V
S
L
2
1
0
–3
–4
–5
–1
–2
–3
–4
R
= 150Ω
T
= 125°C
T
= 25°C
A
A
T
= 25°C
A
V
INPUT
REF
T
= –55°C
A
LOW SWING
CLAMPING
T
1
= –55°C
A
0
0.5
–2 –1.5 –1 –0.5
1.5
2
0
10 20 30 40 50 60 70 80 90 100
SOURCE CURRENT (mA)
6555 G08
0
10 20 30 40 50 60 70 80 90 100
V
PIN VOLTAGE (V)
SINK CURRENT (mA)
REF
6555 G07
6555 G09
6555f
4
LT6555
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Input Referred PSRR
vs Frequency
Input Noise Spectral Density
Input Impedance vs Frequency
70
60
50
40
30
20
10
0
1000
100
10
1000
100
10
V
V
A
= ±5V
V
T
= ±5V
= 25°C
V
T
= ±5V
= 25°C
S
S
A
S
A
±PSRR
= 0V
IN
= 25°C
T
+PSRR
–PSRR
e
n
i
n
1
1
0.1
0.001
0.01
0.1
1
10
100
0.001
0.01
0.1
1
10
100
0.01
0.1
1
10
100
1000
FREQUENCY (kHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
6555 G12
6555 G11
6555 G10
Frequency Response
vs Output Amplitude
Frequency Response with
Capacitive Loads
Gain Flatness vs Frequency
6.20
18
16
14
12
10
8
9
8
7
6
5
4
3
2
1
0
V
V
= ±5V
V
= ±5V
= 150Ω
= 25°C
S
S
L
= 2V
R
T
OUT
P-P
R
= 150Ω
6.15
6.10
6.05
6.00
L
A
T
= 25°C
A
IN1A
C
= 10pF
L
IN3B
IN3A
C
= 4.7pF
L
6
V
OUT
= 200mV
P-P
C
= 0pF
L
IN1B
IN2A
4
V
= 2V
OUT
P-P
2
IN2B
V
OUT
= 4V
P-P
0
V
V
= ±5V
S
= 200mV
P-P
–2
–4
–6
OUT
5.95
5.90
R
= 150Ω
L
T
= 25°C
A
0.1
1
10
FREQUENCY (MHz)
100
1000
0.1
1
10
100
1000
0.1
1
10
FREQUENCY (MHz)
100
1000
FREQUENCY (MHz)
6555 G14
6555 G15
6555 G13
Harmonic Distortion vs Frequency
Crosstalk vs Frequency
Crosstalk vs Frequency
0
0
0
V
V
R
T
= ±5V
V
V
= ±5V
V
V
R
T
= ±5V
S
S
S
–10
–20
= 2V
= 1V
P-P
= 2V
OUT
P-P
IN
OUT
P-P
= 150Ω
R
T
= 150Ω
= 25°C
–20
–40
–20
–40
= 150Ω
L
L
A
L
= 25°C
= 25°C
A
A
–30
–40
–50
–60
–60
–80
–60
–80
WORST
ADJACENT
HD3
DRIVE IN A,
SELECT IN B
–70
ALL
CHANNELS
DRIVEN
–80
HD2
DRIVE IN B,
SELECT IN A
–90
–100
–110
–120
–100
–120
–100
–120
0.1
1
10
FREQUENCY (MHz)
100
1000
0.1
1
10
100
1000
0.01
0.1
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
6555 G16
6555 G17
6555 G18
6555f
5
LT6555
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Video Amplitude Transient
Response
Output Impedance vs Frequency
Small-Signal Transient Response
1000
100
10
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.4
0.3
V
V
= 200mV
= ±5V
IN
S
L
P-P
DISABLED
R
= 150Ω
= 25°C
V
EN
= 4V
T
A
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
ENABLED
1
V
V
= 0V TO 700mV
= ±5V
IN
S
L
V
EN
= O.4V
V
= ±5V
= 150Ω
= 25°C
S
L
R
T
R
T
= 150Ω
–0.2
–0.4
= 25°C
A
A
0.1
0.01
0.1
1
10
100
1000
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
FREQUENCY (MHz)
TIME (ns)
TIME (ns)
6555 G19
6555 G21
6555 G20
Gain Error Distribution
Large-Signal Transient Response
Large-Signal Transient Response
1.5
1.0
4
3
40
35
30
25
20
15
10
5
V
V
= 1V
P-P
V
V
= ±5V
V
V
= 2.5V
IN
S
L
S
IN
S
L
P-P
= ±5V
= ±2V
= 150Ω
= 25°C
= ±5V
OUT
R
T
= 150Ω
= 25°C
R
T
R
T
= 150Ω
= 25°C
L
A
A
A
2
0.5
0
1
0
–1
–2
–3
–4
–0.5
–1.0
–1.5
0
0
2
4
6
8
10 12 14 16 18 20
–1.5
0
1.5
–1.0 –0.5
0.5
1.0
0
2
4
6
8
10 12 14 16 18 20
TIME (ns)
GAIN ERROR—INDIVIDUAL CHANNEL (%)
TIME (ns)
6555 G22
6555 G24
6555 G23
Gain Matching Distribution
Channel Switching Transient
Channel Switching Transient
0.2
0.1
40
35
30
25
20
15
10
5
1.5
1.0
0.5
0
V
= ±5V
INA = 0V
T = 25°C
A
V
V
= ±5V
S
L
S
R
= 150Ω INB = 0V
= ±2V
= 150Ω
= 25°C
OUT
R
L
T
A
0
–0.5
–1.0
–1.5
V
= ±5V
INB = 300MHz, 1V SINE
P-P
S
L
–0.1
R
= 150Ω T = 25°C INA = 0V
A
5
4
5
4
3
2
1
0
2
0
0
0
–1.5 –1.0 –0.5
0.5
1.0
1.5
0
10 20 30 40 50 60 70 80 90 100
TIME (ns)
0
10 20 30 40 50 60 70 80 90 100
GAIN MATCHING–BETWEEN CHANNELS (%)
TIME (ns)
6555 G25
6555 G26
6555 G27
6555f
6
LT6555
U
U
U
PI FU CTIO S (GN24 Package)
IN1A (Pin 1): Channel 1 Input A. This pin has a nominal
impedance of 400kΩ and does not have any internal
termination resistor.
V– (Pin15):NegativeSupplyVoltageforChannel3Output
Stage. V– pins are not internally connected to each other
andmustallbeconnectedexternally.Propersupplybypass-
ingisnecessaryforbestperformance.SeetheApplications
Information section.
DGND (Pin 2): Digital Ground Reference for Enable Pin.
This pin is normally connected to ground.
OUT3 (Pin 16): Channel 3 Output. It is twice the selected
channel 3 input and performs optimally with a 150Ω load
(a double terminated 75Ω cable).
V+ (Pin 17): Positive Supply Voltage for Channels 2 and 3
OutputStages.V+ pinsarenotinternallyconnectedtoeach
other and must all be connected externally. Proper supply
bypassing is necessary for best performance. See the
Applications Information section.
IN2A (Pin 3): Channel 2 Input A. This pin has a nominal
impedance of 400kΩ and does not have any internal
termination resistor.
V
REF (Pin 4): Voltage Reference for Input Clamping. This
is the tap to an internal voltage divider that defines mid-
supply. It is normally connected to ground in dual supply,
DC coupled applications.
IN3A (Pin 5): Channel 3 Input A. This pin has a nominal
impedance of 400kΩ and does not have any internal
termination resistor.
OUT2 (Pin 18): Channel 2 Output. It is twice the selected
channel 2 input and performs optimally with a 150Ω load
(a double terminated 75Ω cable).
V– (Pin 19): Negative Supply Voltage for Channels 1 and
2OutputStages.V–pinsarenotinternallyconnectedtoeach
other and must all be connected externally. Proper supply
bypassing is necessary for best performance. See the Ap-
plications Information section.
AGND1 (Pin 6): Analog Ground for the 360Ω Gain Resis-
tor of Channel 1.
IN1B (Pin 7): Channel 1 Input B. This pin has a nominal
impedance of 400kΩ and does not have any internal
termination resistor.
AGND2 (Pin 8): Analog Ground for the 360Ω Gain Resis-
OUT1 (Pin 20): Channel 1 Output. It is twice the selected
channel 1 input and performs optimally with a 150Ω load
(a double terminated 75Ω cable).
V+ (Pin 21): Positive Supply Voltage for Channel 1 Output
Stage. V+ pins are not internally connected to each other
and must all be connected externally. Proper supply
bypassing is necessary for best performance. See the
Applications Information section.
tor of Channel 2.
IN2B (Pin 9): Channel 2 Input B. This pin has a nominal
impedance of 400kΩ and does not have any internal
termination resistor.
AGND3 (Pin 10): Analog Ground for the 360Ω Gain
Resistor of Channel 3.
IN3B (Pin 11): Channel 3 Input B. This pin has a nominal
impedance of 400kΩ and does not have any internal
termination resistor.
V– (Pin 12): Negative Supply Voltage. V– pins are not in-
ternallyconnectedtoeachotherandmustallbeconnected
externally. Proper supply bypassing is necessary for best
performance. See the Applications Information section.
V+ (Pins 13, 14, 24): Positive Supply Voltage. V+ pins are
not internally connected to each other and must all be
connected externally. Proper supply bypassing is neces-
sary for best performance. See the Applications Informa-
tion section.
SEL (Pin 22): Select Pin. This high impedance pin selects
which set of inputs are sent to the output pins. When the
pin is pulled low, the A inputs are selected. When the pin
is pulled high, the B inputs are selected.
EN (Pin 23): Enable Control Pin. An internal pull-up
resistor of 46k defines the pin’s impedance and will turn
thepartoffifthepinisunconnected.Whenthepinispulled
low, the amplifiers are enabled.
Exposed Pad (Pin 25, QFN Only): The Exposed Pad is V–
and must be soldered to the PCB. It is internally connected
to the QFN Pin 4, V–.
6555f
7
LT6555
U
W U U
APPLICATIO S I FOR ATIO
Power Supplies
The DGND pin should not be pulled above the EN pin since
doing so will turn on an ESD protection diode. If the EN pin
voltageisforcedadiodedropbelowtheDGNDpin,current
should be limited to 10mA or less.
The LT6555 is optimized for ±5V supplies but can be
operated on as little as ±2.25V or a single 4.5V supply and
as much as ±6V or a single 12V supply. Internally, each
supply is independent to improve channel isolation. Do
not leave any supply pins disconnected or the part may
not function correctly!
The enable/disable times of the LT6555 are fast when
driven with a logic input. Turn on (from 50% EN input to
50% output) typically occurs in less than 50ns. Turn off is
slower, but is typically below 500ns.
Enable/Shutdown
The LT6555 has a shutdown mode controlled by the EN
pin and referenced to the DGND pin. If the amplifier will
be enabled at all times, the EN pin can be connected
directly to DGND. If the enable function is desired, either
driving the pin above 2V or allowing the internal 46k pull-
up resistor to pull the EN pin to the top rail will disable the
amplifier. When disabled, the DC output impedance will
rise to approximately 360Ω through the internal feedback
and gain resistors. Supply current into the amplifier in the
disabled state will be:
Channel Select
TheSELpinusesthesameinternalthresholdastheENpin
and is also referenced to DGND. When the pin is logic low,
the channel A inputs are passed to the output. When the
pin is logic high, the channel B inputs are passed to the
output. The pin should not be floated but can be tied to
DGND to force the outputs to always be channel A or to V+
(when less than 8V) to force the outputs to always be
channel B.
Truth Table
V+ – VEN
46k
V+ – V–
80k
SEL A/B
EN
0
OUT
2 × IN A
2 × IN B
OFF
IS =
+
0
1
X
0
It is important that the following constraints on the DGND,
EN and SEL pins are always followed:
1
V+ – VDGND ≥ 4.5V
VEN – VDGND ≤ 5.5V
VSEL – VDGND ≤ 8V
Input Considerations
The LT6555 uses input clamps referenced to the VREF pin
to prevent damage to the input stage on the unselected
channel. Three transistors in series limit the input voltage
to within three diode drops (±) from VREF. VREF is nomi-
nally set to half of the sum of the supplies by the 40k
resistors. A simplified schematic is shown in Figure 1.
In dual supply cases where V+ is less than 4.5V, DGND
should be connected to a potential below ground, such as
V–. Since the EN and SEL pins are referenced to DGND,
they may need to be pulled below ground in those cases.
In single supply applications above 5.5V, an additional
resistor may be needed from the EN pin to DGND if the pin
is ever allowed to float. For example, on a 12V single
supply, a 33k resistor would protect the pin from floating
too high while still allowing the internal pull-up resistor to
disable the part.
To improve clamping, the pin’s DC impedance should be
minimizedbyconnectingtheVREF pindirectlytogroundin
the symmetric dual supply case with a common mode
voltage of 0V. While loaded output swing limits the useful
input voltage range in that case, if the common mode
voltage is not centered at ground or the input voltage
exceeds plus or minus three diodes from ground, an
external resistor to either supply can be added to shift the
On dual ±2.25V supplies, connecting the DGND pin to V–
is the only way of ensuring that V+ – VDGND ≥ 4.5V.
6555f
8
LT6555
W U U
APPLICATIO S I FOR ATIO
U
+
V
40k
IN
V
REF
40k
–
6555 F01
V
Figure 1. Simplified Schematic of VREF Pin and Input Clamping
VREF voltage to the desired level. The only way to cover the
full common mode voltage range of V– + 1V to V+ – 1V is
to shift VREF up or down. Note that on a single supply, the
unclamped input range limits the output low swing to 2V
(1V multiplied by the internal gain of 2).
Series termination resistors should be placed as close to
the output pins as possible to minimize output capaci-
tance. See the Typical Performance Characteristics sec-
tion for a plot of frequency response with various output
capacitors—only 10pF of parasitic output capacitance
before the series termination resistor causes 6dB of
peaking in the frequency response!
The VREF pin can also be directly driven with a DC source.
Bypassing the VREF pin is not necessary.
Low ESL/ESR bypass capacitors should be placed as
close to the positive and negative supply pins as possible.
One 4700pF ceramic capacitor is recommended for both
V+ and V– supply busses. Additional 470pF ceramic ca-
pacitors with minimal trace length on each supply pin will
further improve AC and transient response as well as
channel isolation. For high current drive and large-signal
transient applications, additional 1µF to 10µF tantalums
should be added on each supply. The smallest value
capacitors should be placed closest to the package.
The inputs can be driven beyond the point at which the
output clips so long as input currents are limited to less
than ±10mA. Continuing to drive the input beyond the
output limit can result in increased current drive and
slightly increased swing, but will also increase supply
current and may result in delays in transient response at
larger levels of overdrive.
Layout and Grounding
It is imperative that care is taken in PCB layout in order to
benefit from the very high speed and very low crosstalk of
the LT6555. Separate power and ground planes are highly
recommended and trace lengths should be kept as short
as possible. If input or output traces must be run over a
distance of several centimeters, they should use a con-
trolled impedance with matching series and shunt resis-
tances (nominally 75Ω) to maintain signal fidelity.
If the AGND pins are not connected to ground, they must
be carefully bypassed to maintain minimal impedance
over frequency. Although crosstalk will vary depending
upon board layout, a recommended starting point for
bypass capacitors would be 470pF as close as possible to
each AGND pin with a single 4700pF capacitor in parallel.
6555f
9
LT6555
W U U
U
APPLICATIO S I FOR ATIO
To maintain the LT6555’s channel isolation, it is beneficial
to shield parallel input and parallel output traces using a
groundplaneorpowersupplytraces.Viasbetweentopside
and backside metal may be required to maintain a low
inductance ground near the part where numerous traces
converge. See Figures 6 and 7 for photos of an optimized
layout.
Figure 3 illustrates the loading effect of expanding the
number of inputs. The resultant gain error can be calcu-
lated by the following formula using n as the number of
LT6555s:
435Ω
n – 1
⎛
⎞
75Ω
⎜
⎟
Gain Error (dB)= 6dB+20log
dB
⎜
⎟
435Ω
n – 1
⎜
⎝
⎟
⎠
75 +
75Ω
Input Expansion
In applications with more than two inputs per channel,
multiple LT6555s can be connected by several different
methods. The simplest method is to connect the outputs
afterthe75Ωseriestermination,asshowninFigure2. The
compromise of this approach is that the internal gain
settingresistorscausea435Ωshuntacrossthe75Ωcable
termination, resulting in increased gain error.
For example, two LT6555s would result in a gain error of
–0.74dB per channel. Three LT6555s (i.e., six red inputs,
six green inputs and six blue inputs), would have a gain
error of –1.4dB.
1/3 LT6555 #1
75Ω
IN1A
IN1B
360Ω
OFF
360Ω
75Ω
IN1A
A
= 2
V
⇒
75Ω
R2
75Ω
435
n – 1
360Ω
OFF
IN1B
360Ω
EN
n = NUMBER OF LT6555s
IN PARALLEL
LT6555 #1
1/3 LT6555 #2
CABLE
75Ω
IN1C
IN1D
360Ω
OFF
75Ω
IN1C
IN1D
360Ω
A
= +2
V
75Ω
OUT
75Ω
360Ω
ON
360Ω
EN
6555 F03
LT6555 #2
74HC04
.
.
.
CHIP
SELECT
6555 F02
n
Figure 3. Disabled Amplifiers Load the Cable
Termination with 435Ω Each
Figure 2. Two LT6555s Build a 4-Input Router
6555f
10
LT6555
W U U
APPLICATIO S I FOR ATIO
U
1.5
This systematic gain error can be significantly reduced by
loweringthevalueofthe75Ωseriesterminationresistors.
The compromise of this approach is an increased depen-
dence on the accuracy of the 75Ωshunt termination at the
receiving end of the line. A table of values for 1% series
termination resistors from n = 2 to n = 4 is shown below.
V
V
V
= ±5V
S
1.0
0.5
= –0.5V
= 0.5V
IN(AMP1)
IN(AMP2)
= 150Ω
R
L
0
SERIES 63.9Ω
–0.5
–1.0
AT EACH OUTPUT
OUTPUTS
DIRECTLY
CONNECTED
150
100
50
NUMBER OF DEVICES (n)
SERIES R
63.9
T
–
I
+
2
3
4
S
I
S
56.2
0
2
2.5
0
0.5
1
1.5
TIME (µs)
3
3.5
4
49.9
6555 F04
Another approach that does not compromise gain accu-
racy is to connect the outputs directly together before the
series termination. In this case, there will be slightly
increased output glitching and supply current spiking
during the EN pin switching, but the additional output
loading will not increase the gain error, and the series
termination resistors remain at their ideal value for AC
response. See Figure 4 for a scope photo showing the
result of the outputs connected both before and after the
series terminations, and Figure 8 for a full schematic of a
4:1 RGB multiplexer with the output pins directly con-
nected together. It is imperative that the output traces be
as short as possible before the series termination in order
to reduce capacitance and minimize AC peaking.
Figure 4. 4-Input Router Switching with Outputs Directly
Connected and with Outputs Connected After 63.9Ω
Series Termination
ESD Protection
The LT6555 has reverse-biased ESD protection diodes on
all pins. If any pins are forced a diode drop above the
positive supply or a diode drop below the negative supply,
large currents may flow through these diodes. If the
current is kept below 10mA, no damage to the devices will
occur.
U
TYPICAL APPLICATIO
RGB Multiplexer Demo Board
possible. The board is fabricated with four layers with
internal ground and power planes. For ideal operation, a
75Ω load termination should be connected at the output.
The LT6555’s gain of 2 will compensate for the resulting
divider between the series and load termination resistors.
Figures 6 and 7 show the topside and bottom side board
layout and placement.
The DC858A Demo Board illustrates optimal routing,
bypassing and termination using the LT6555 as an
RGB video multiplexer. The schematic is shown in Fig-
ure 5. All inputs and outputs are routed to have a charac-
teristicimpedanceof75Ωand75Ωinputshuntandoutput
series terminations are connected as close to the part as
6555f
11
LT6555
U
TYPICAL APPLICATIO
E1
EN
E4
SEL A/B
J8
J1
50Ω BNC
1
50Ω BNC
Z = 50
Z = 50
1
R7
20k
2
JP1
EN
SEL A/B
E2
DGND
R8
50Ω
OPT
R9
50Ω
OPT
CONTROL
A
B
1
3
1
3
V
CC
2
JP4
SEL
EXT ENABLE
5
4 3 2
DGND
5
4
3
2
DGND
JP2
DGND
3
1
2
FLOAT AGND
E5
REF
V
J2
BANANA JACK
JP5
REF
V
3
1
V
CC
3.3V TO 5V
2
C1
4700pF
C2
470pF
C3
470pF
C10
4700pF
C4
C11
0.33µF
16V
BNC × 6
EXT GND
10µF
16V
1206
5
JP12
U1 LT6555CGN
IN1A
V
1
L1 Z = 75
L1 Z = 75
L1 Z = 75
L1 Z = 75
L1 Z = 75
L1 Z = 75
CC
1
2
24
4
3
2
+
IN1A
V
DGND
23 EN
DGND
IN2A
EN
5
4
3
2
5
4
3
2
5
4
3
2
5
4
3
2
JP13
JP14
JP5
1
1
1
1
1
SEL
3
22
21
20
19
18
17
16
15
IN2A
IN3A
IN1B
IN2B
IN3B
SEL
V
BNC × 3
4
REF
+
V
V
R1
75Ω
REF
5
4
3
2
5
4
3
2
5
4
3
2
J9
Z = 75
Z = 75
Z = 75
L2
1
1
1
5
IN3A
OUT1
OUT1
OUT2
OUT3
6
–
AGND1
IN1B
V
R2
75Ω
J10
J11
L2
L2
7
OUT2
8
+
AGND2
IN2B
V
R3
75Ω
JP6
9
OUT3
10
–
AGND3
IN3B
V
5
4
3
2
JP7
11
12
14
13
+
V
R10
75Ω
R11
75Ω
R12
75Ω
R4
75Ω
R5
75Ω
R6
–
+
J4
V
V
75Ω
BANANA JACK
V
EE
E3
AGND
–3.3V TO –5V
C5
4700pF
C6
470pF
C7
470pF
C9
C8
0.33µF
6555 F05
10µF
16V
1206
J3
BANANA JACK
SINGLE DUAL
2
V
EE
AGND
NOTE:
1
3
JP3
SUPPLY
470pF BYPASS CAPACITORS LOCATED
AS CLOSE TO PINS AS POSSIBLE
Figure 5. Demo Board Schematic
Figure 6. Demo Board Topside
(IC Removed for Clarity)
Figure 7. Demo Board Bottom Side
6555f
12
LT6555
W
W
SI PLIFIED SCHE ATIC (One channel shown)
6555f
13
LT6555
U
PACKAGE DESCRIPTIO
GN Package
24-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.337 – .344*
(8.560 – 8.738)
.033
(0.838)
REF
24 23 22 21 20 19 18 17 16 15 14 13
.045 ±.005
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.254 MIN
.150 – .165
1
2
3
4
5
6
7
8
9 10 11 12
.0165 ± .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
.015 ± .004
(0.38 ± 0.10)
.0532 – .0688
(1.35 – 1.75)
× 45°
.004 – .0098
(0.102 – 0.249)
.0075 – .0098
(0.19 – 0.25)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.008 – .012
.0250
(0.635)
BSC
GN24 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
6555f
14
LT6555
U
PACKAGE DESCRIPTIO
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
0.70 ±0.05
4.50 ± 0.05
3.10 ± 0.05
2.45 ± 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
R = 0.115
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
0.75 ± 0.05
4.00 ± 0.10
(4 SIDES)
TYP
23 24
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
1
2
2.45 ± 0.10
(4-SIDES)
(UF24) QFN 0105
0.200 REF
0.25 ± 0.05
0.00 – 0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
6555f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LT6555
U
TYPICAL APPLICATIO
RED 1
GREEN 1
BLUE 1
+
V
LT6555 #1
×2
5V
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
IN1A
IN1B
OUT1
OUT2
OUT3
IN2A
IN2B
×2
×2
RED 2
GREEN 2
BLUE 2
IN3A
IN3B
AGND
DGND
SEL
EN
75Ω
V
R
G
REF
OUT
75Ω
–
V
75Ω
75Ω
–2V
5V
OUT
75Ω
75Ω
RED 3
GREEN 3
BLUE 3
+
V
LT6555 #2
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
IN1A
IN1B
OUT1
OUT2
OUT3
B
OUT
×2
×2
×2
IN2A
IN2B
RED 4
GREEN 4
BLUE 4
IN3A
IN3B
AGND
DGND
SEL1 SEL0 OUTPUT
SEL
EN
0
0
1
1
0
1
0
1
1
2
3
4
V
REF
–
SEL0
V
NC75Z14
SEL1
6555 F08
–2V
Figure 8. 4:1 RGB Multiplexer
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
Single SPDT Video Switch
0.1dB Gain Flatness to 150MHz, Shutdown
LT1203
150MHz Single 2:1 Multiplexer
LT1399
300MHz Triple Current Feedback Amplifier
250MHz Triple RGB Multiplexer
LT1675
100MHz Pixel Switching, 1100V/µs Slew Rate, 16-Lead SSOP
110MHz Gain of 2 Buffers in MS Package
LT6550/LT6551 3.3V Triple and Quad Video Buffers
LT6553
LT6554
650MHz Gain of 2 Triple Video Amplifier
650MHz Gain of 1 Triple Video Amplifier
Performance Similar to the LT6555 with One Set of Inputs, 16-Lead SSOP
Same Pinout as the LT6553 but Optimized for High Impedance Loads
6555f
LT/TP 0405 500 • PRINTED IN USA
16 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005
相关型号：
LT6556CGN#TR
LT6556 - 750MHz Gain of 1 Triple 2:1Video Multiplexer; Package: SSOP; Pins: 24; Temperature Range: 0°C to 70°C
ADI
LT6556CUF#PBF
LT6556 - 750MHz Gain of 1 Triple 2:1Video Multiplexer; Package: QFN; Pins: 24; Temperature Range: 0°C to 70°C
ADI
LT6556CUF#TRPBF
LT6556 - 750MHz Gain of 1 Triple 2:1Video Multiplexer; Package: QFN; Pins: 24; Temperature Range: 0°C to 70°C
ADI
LT6556IUF#TR
LT6556 - 750MHz Gain of 1 Triple 2:1Video Multiplexer; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C
ADI
©2020 ICPDF网 联系我们和版权申明