LT8500ITJ#PBF
更新时间:2024-09-18 19:15:23
品牌:Linear
描述:LT8500 - 48-Channel LED PWM Generator with 12-Bit Resolution and 50MHz Cascadable Serial Interface; Package: QFN; Pins: 56; Temperature Range: -40°C to 85°C
LT8500ITJ#PBF 概述
LT8500 - 48-Channel LED PWM Generator with 12-Bit Resolution and 50MHz Cascadable Serial Interface; Package: QFN; Pins: 56; Temperature Range: -40°C to 85°C 其他接口集成电路
LT8500ITJ#PBF 规格参数
是否Rohs认证: | 符合 | 生命周期: | Active |
零件包装代码: | QFN | 针数: | 56 |
Reach Compliance Code: | compliant | 风险等级: | 2.13 |
Base Number Matches: | 1 |
LT8500ITJ#PBF 数据手册
通过下载LT8500ITJ#PBF数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载LT8500
48-Channel LED PWM Generator
with 12-Bit Resolution and 50MHz
Cascadable Serial Interface
FeaTures
DescripTion
The LT®8500 is a pulse width modulation (PWM) genera-
tor with 48 independent channels. Each channel has an
individually adjustable 12-bit (4096-step) PWM register
anda6-bit(64-step) 50ꢀcorrectionregister.Allcontrols
are programmable via a simple serial data interface. Three
banks of 16-channels each can be configured such that
n
3V to 5.5V Input Voltage
n
48 Independent PWM Outputs
n
TTL/CMOS Logic 50MHz Serial Data Interface
n
12-Bit (4096 Steps) PWM Width Resolution
6-Bit (64 Steps) PWM Correction
( 50ꢀ of Prograꢁꢁed PWM Width)
Up to 6.1kHz PWM Frequency (PWMCK = 25MHz)
Phase-Shift Option Reduces Switching Noise
Directly Controls Three LT3595A 16-Channel
LED Drivers
Diagnostic Information: Sync Error/Open LED Flags
56-Pin (6mm × 6mm × 0.78mm) TLA QFN Package
n
n
they operate 120° out-of-phase with each other.
n
n
The LT8500 features two diagnostic information flags:
synchronization error and open LED. The flags are sent,
withadditionalstateinformation,ontheserialdatainterface
duringstatusreadback.The50MHzcascadableserialdata
interface includes buffering and skew-balancing, making
the chip suitable for PWM intensive applications such
as large screen LCD dynamic backlighting and mono-,
multi- and full-color LED displays. The LT8500 is also
ideally suited to control three LT3595A LED drivers.
n
n
applicaTions
n
Large Screen Display LED Backlighting
n
Mono-, Multi-, Full-Color LED Displays
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
n
LED Billboards and Signboards
Motor Control
Industrial Control
Automated Test Equipment
Robotics
n
n
n
n
Typical applicaTion
48 PWM OUTPUTS
48 PWM OUTPUTS
48 PWM OUTPUTS
• • • • •
• • • • •
• • • • •
PWM[48:1]
PWM[48:1]
PWM[48:1]
5-WIRE
SERIAL
• • • •
• • • •
SDI
SCKI
SDO
SCK0
SDI
SCKI
SDO
SCK0
SDI
SCKI
SDO
SCK0
DATA
INTERFACE
LDIBLANK
LT8500 (1)
LDIBLANK
LDIBLANK
LT8500 (2)
LT8500 (N)
OSC
PWMCK
PWMCK
PWMCK
OPENLED
OPENLED
OPENLED
DIAGNOSTIC
CIRCUIT
• • • •
• • • •
• • • •
8500 TA01a
8500fb
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For more information www.linear.com/LT8500
LT8500
absoluTe MaxiMuM raTings (Note 1)
V ............................................................... –0.3V to 6V
Operating Junction Temperature Range
CC
SDI, SCKI, PWMCK, OPENLED,
(Note 2).................................................. –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
LDIBLANK......... –0.3V to Lesser of 6V and (V + 0.3V)
CC
pin conFiguraTion
TOP VIEW
TOP VIEW
56 55 54 53 52 51 50 49 48 47
PWM1
PWM24
PWM23
PWM22
PWM21
PWM28
PWM27
PWM26
PWM25
1
2
3
4
5
6
7
8
9
46 PWM12
45 PWM5
PWM6
PWM7
44
43
PWM2
PWM24
PWM22
PWM23
PWM26
PWM25
A1 A40 A39 A38 A37 A36 A35 A34 A33 A32 A31
PWM12
PWM7
42 PWM8
A2
A3
A4
A5
A6
A7
A8
A9
A10
A30
A29
A28
A27
A26
A25
A24
A23
A22
PWM1
PWM21
PWM27
PWM28
PWM32
PWM30
PWM19
PWM18
B1
B2
B3
B4
B5
B6
B7
B8
B16
B15
B14
B13
B12
B11
B10
B9
PWM5
PWM8
SDI
41
LDIBLANK
PWM6
40 SDI
LDIBLANK
PWMCK
39 PWMCK
38 SCKO
37 VCC
57
GND
SDKO
57
GND
PWM32 10
PWM31 11
PWM30 12
PWM29 13
PWM20 14
PWM19 15
PWM18 16
PWM17 17
PWM40 18
V
CC
SCKI
36 SCKI
PWM31
PWM20
PWM29
PWM17
PWM40
SDO
OPENLED
PWM35
PWM45
35 SDO
PWM33
PWM34
PWM36
PWM46
34 OPENLED
33 PWM33
32 PWM34
31 PWM35
30 PWM36
29 PWM45
A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
19 20 21 22 23 24 25 26 27 28
TJ PACKAGE
56-LEAD PLASTIC TLA QFN (6mm × 6mm)
T
= 125°C, θ = 35°C/W, θ = 5°C/W
JA JC
JMAX
UHH PACKAGE
56-LEAD (5mm × 9mm) PLASTIC QFN
EXPOSED PAD (PIN 57) IS GND, MUST BE SOLDERED TO PCB
T
= 125°C, θ = 35°C/W, θ = 5°C/W
JA JC
JMAX
EXPOSED PAD (PIN 57) IS GND, MUST BE SOLDERED TO PCB
(NOT RECOMMENDED FOR NEW DESIGNS)
http://www.linear.coꢁ/product/LT8500#orderinfo
orDer inForMaTion
LEAD FREE FINISH
LT8500EUHH#PBF
LT8500IUHH#PBF
LT8500ETJ#PBF
LT8500ITJ#PBF
TAPE AND REEL
PART MARKING*
8500
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
LT8500EUHH#TRPBF
LT8500IUHH#TRPBF
LT8500ETJ#TRPBF
LT8500ITJ#TRPBF
56-Lead (5mm × 9mm) Plastic QFN
56-Lead (5mm × 9mm) Plastic QFN
56-Lead (6mm × 6mm) Plastic TLAQFN
56-Lead (6mm × 6mm) Plastic TLAQFN
8500
LT8500TJ
LT8500TJ
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
8500fb
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For more information www.linear.com/LT8500
LT8500
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
teꢁperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, unless otherwise noted.
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
l
V
CC
V
CC
Operating Voltage
3.0
5.5
V
Digital Inputs: SCKI, SDI, LDIBLANK, OPENLED, PWMCK
Input Logic Levels
l
l
l
l
V
V
High Level Voltage
V
V
V
V
= 5V
4.0
2.7
V
V
V
V
IH
CC
CC
CC
CC
= 3.3V
= 5V
Low Level Voltage
1.0
0.6
IL
= 3.3V
I
Input Current
Pin Voltage = V or GND Excluding OPENLED
–1
70
1
µA
kΩ
pF
IN
CC
R
OPENLED Pull-Up Resistor
V
= 5.5V
CC
100
3
130
PU
IN
C
Input Capacitance (Note 4)
Pin to GND
Digital Outputs: SCKO, SDO, PWM[48:1]
SDO, SCKO Output Voltages
l
l
l
l
V
V
High Level Voltage
I
I
I
I
= –6mA, V = 5V
4.0
2.7
V
V
V
V
OH
OUT
OUT
OUT
OUT
CC
= –3mA, V = 3.3V
CC
Low Level Voltage
= 6mA, V = 5V
1.0
0.6
OL
CC
= 3mA, V = 3.3V
CC
PWM [48:1] Output Voltages
High Level Voltage
l
l
l
l
V
V
I
I
I
I
= –3mA, V = 5V
4.0
2.7
V
V
V
V
OH
OUT
OUT
OUT
OUT
CC
= –1.5mA, V = 3.3V
CC
Low Level Voltage
= 3mA, V = 5V
1.0
0.6
OL
CC
= 1.5mA, V = 3.3V
CC
TiMing characTerisTics The l denotes the specifications which apply over the full operating teꢁperature
range, otherwise specifications are at TA = 25°C. VCC = 3.3V, and all inputs are rail-to-rail unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
50
UNIT
MHz
MHz
ns
l
l
f
Data Shift Clock Frequency
PWMCK Clock Frequency
Minimum SCKI High Time (Note 3)
Minimum SCKI Low Time (Note 3)
SCKI ↑ – SCKI ↑ (Figure 4)
PWMCK ↑ – PWMCK ↑ (Figure 5)
SCKI = High
SCKI
f
25
PWMCK
t
t
t
2
2
WH-SCKI
WL-SCKI
WH-LDI
SCKI = Low
ns
l
l
LDIBLANK Pulse Duration
(LDI Function)
LDIBLANK = High (Figure 4)
8
5,000
ns
t
LDIBLANK Pulse Duration
(BLANK Function)
LDIBLANK = High (Figure 4)
50,000
ns
WH-BLANK
l
l
l
t
t
t
SDI-SCKI Setup Time (Note 3)
SCKI-SDI Hold Time (Note 3)
3
ns
ns
ns
SDI ↑↓ – SCKI ↑ (Figure 4)
SCKI ↑ – SDI ↑↓ (Figure 4)
SU-SDI
HD-SDI
SU-LDI
1.75
10
SCKI-LDIBLANK Setup Time (Note 3)
SCKI ↑ – LDIBLANK ↑ (Figure 4)
SCKI 50ꢀ Duty Cycle
l
l
l
l
t
t
t
t
t
LDIBLANK-SCKI Hold Time (Note 3)
SCKI-SDO Propagation Delay (Note 3)
SCKI-SCKO Propagation Delay (Note 3)
SCKO-SDO Hold Time (Note 3)
5
ns
ns
ns
ns
ns
LDIBLANK ↓ – SCKI ↑ (Figure 4)
SCKI ↑ – SDO ↑↓ (Figure 4)
HD-LDI
PD-SDO
PD-SCK
HD-SDO
DC-SCK
15
10
25
20
SCKI ↑ – SCKO ↑ (Figure 4)
2.75
SCKO ↑ – SDO ↑↓ (Figure 4)
Difference Between SCKI = High Time
SCKI-SCKO Duty Cycle Change (Note 4)
–0.2
and SCKO = High Time, C
= 25pF
LOAD
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For more information www.linear.com/LT8500
LT8500
TiMing characTerisTics The l denotes the specifications which apply over the full operating teꢁperature
range, otherwise specifications are at TA = 25°C. VCC = 3.3V, and all inputs are rail-to-rail unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
l
t
PWMCK-PWM[48:1] Propagation Delay
(Note 3)
32
50
ns
PWMCK ↑ – PWM ↑↓ (Figure 5)
PD-PWM
t
t
t
t
SDO, SCKO Rise Time (Note 4)
SDO, SCKO Fall Time (Note 4)
PWM[48:1] Rise Time (Note 4)
PWM[48:1] Fall Time (Note 4)
C
LOAD
C
LOAD
C
LOAD
C
LOAD
= 25pF, 30ꢀ to 70ꢀ
= 25pF, 70ꢀ to 30ꢀ
= 25pF, 30ꢀ to 70ꢀ
= 25pF, 70ꢀ to 30ꢀ
2
2
ns
ns
ns
ns
R-SDO
F-SDO
12
12
R-PWM
F-PWM
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
characterization and correlation with statistical process controls. The
LT8500I is guaranteed over the full –40°C to 125°C operating junction
temperature range.
Note 3: Propagation delays, setup/hold times and hi times are measured
Note 2: The LT8500E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
from 50ꢀ to 50ꢀ.
Note 4: This parameter is correlated to lab measurements and is not
subject to production testing.
TiMing DiagraM
t
t
WH-SCKI
WH-LDI
t
1/f
SCKI
HD-SDI
t
t
t
SU-LDI
HD-LDI
WL-SCKI
t
SU-SDI
SCKI
SDI
LDIBLANK
SCKO
SDO
8500 TD01
t
t
t
PD-SDO
PD-SCK
HD-SDO
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For more information www.linear.com/LT8500
LT8500
Typical perForMance characTerisTics
For the ICC vs VCC Graphs, the Following Conditions
Apply: 23pF Load on SCKO. PWM Outputs Enabled: Duty Cycle = 1365/4096, 10pF Average Load on PWMs.
ICC vs VCC, SCKI = 0MHz,
SDI = 0MHz, PWMCK = 0MHz
ICC vs VCC, SCKI = 0MHz,
SDI = 0MHz, PWMCK = 10MHz
ICC vs VCC, SCKI = 0MHz,
SDI = 0MHz, PWMCK = 25MHz
3.0
2.5
2.0
1.5
1.0
0.5
0
3.0
2.5
2.0
1.5
1.0
0.5
0
3.0
2.5
2.0
1.5
1.0
0.5
0
3
3.5
4
4.5
(V)
5
5.5
3
3.5
4
4.5
(V)
5
5.5
3
3.5
4
4.5
(V)
5
5.5
V
CC
V
CC
V
CC
8500 G01
8500 G02
8500 G03
ICC vs VCC, SCKI = 12MHz,
SDI = 6MHz, PWMCK = 0MHz
I
CC vs VCC, SCKI = 20MHz,
ICC vs VCC, SCKI = 50MHz,
SDI = 25MHz, PWMCK = 25MHz
SDI = 10MHz, PWMCK = 10MHz
30
25
20
15
10
5
30
25
20
15
10
5
30
25
20
15
10
5
0
0
0
3
3.5
4
4.5
(V)
5
5.5
3
3.5
4
4.5
(V)
5
5.5
3
3.5
4
4.5
(V)
5
5.5
V
CC
V
CC
V
CC
8500 G06
8500 G04
8500 G05
VOL vs VCC
VOH vs VCC
0.6
0.5
0.4
0.3
0.2
0.1
0
0.6
0.5
0.4
0.3
0.2
0.1
0
PWMs AT 3mA
SCKO, SDO AT 6mA
PWMs AT 1.8mA
PWMs AT 3mA
SCKO, SDO AT 6mA
PWMs AT 1.8mA
0
1
2
3
4
5
6
0
1
2
3
4
5
6
V
CC
(V)
V
(V)
CC
8500 G07
8500 G08
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For more information www.linear.com/LT8500
LT8500
pin FuncTions (TLAQFN/QFN)
PWM[48:1] (Pins A1 to A24, A29 to A40, B1 to B10, B15
to B16/Pins 1 to 33, 42 to 56): Pulse Width Modulated
(PWM) Output Pins. Pulse width is determined by com-
paring the value in the PWMRSYNC latches to an internal
PWMCK counter. Outputs are high when the value in the
PWMCK counter is less than the value in PWMRSYNC[n].
The PWM frequency is determined by the signal applied
to the PWMCK pin.
PWMCK (Pin A27/Pin 39): PWM Clock Input Pin. This pin
provides PWM timing for the outputs. Each PWM signal
is generated by counting the pulses on this clock from
zero to the calculated value in the PWM synchronization
register(PWMRSYNC). ThisclockisindependentofSCKI.
SDI (Pin B14/Pin 40): Serial Data Input Pin. This pin
provides serial interface data to issue commands and set
up the individual PWM channels.
OPENLED (Pin B11/Pin 34): Not Open LED Input Pin.
This input passes diagnostic information to the host via
the status frame. When used with LT3595A LED drivers,
it connects to the wired-OR (open collector) OPENLED
outputs which indicate an open in one or more of the
LED strings. The user can run a self test on the LT8500
to detect which PWM output is associated with an open
LED string, or other fault. This pin has an internal 100kΩ
LDIBLANK (Pin A28/Pin 41): Latch Data In/Blank Input
Pin. This is a dual function pin.
LDI Function: The internal LDI signal is directly con-
nected to the LDIBLANK pin. A logic high on the pin
always asserts the LDI function. The rising edge of
LDIBLANKcapturesthedecodedcommandfield(CMD,
CR[7:0]) of the shift register (SR[7:0]). The high level
ofLDIBLANKlatchesdatafromthecorrectionmultiplier
into the PWM Registers (PWMR). When LDIBLANK is
high, status information is loaded into the shift register
(SR) to shift out on SDO when the next frame shifts in
on SDI. See more details in the Operation section.
pull-up to the V supply rail.
CC
SDO (Pin A25/Pin 35): Serial Data Output Pin. This pin is
the output of the shift register (SR), and cascades data to
downstream chips or returns data to the host.
SCKI (Pin B12/Pin 36): Serial Clock Input Pin. This clock
pin provides timing for the serial interface and the calcula-
tion of PWM values in the correction multiplier. This clock
is independent of PWMCK.
BLANK Function: Asserting LDIBLANK high for more
than 50µs turns off all PWM[48:1] outputs and resets
the chip. To avoid inadvertently resetting the chip, do
not assert LDIBLANK high for more than 5µs.
V
(Pin A26/Pin 37): Supply Pin. 3.0V to 5.5V. Must be
CC
GND (Exposed Pad Pin 57): This is the ground reference
for the chip.
locally bypassed with a capacitor to ground.
SCKO (Pin B13/Pin 38): Serial Clock Output Pin. Buffered
pass through of SCKI. This pin cascades the clock to the
next chip or to the host.
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For more information www.linear.com/LT8500
LT8500
block DiagraM
V
CC
37
34
100k
OPENLED
CRD, PHS, SYC,
OLT, CR[4:7]*
STATUS (COR’s, OLED’s)
PD
SDI
40
36
SDO
SD
35
LD
SHIFT REGISTER (SR[0:583])*
POR
SCKI
CR[0:7]* FRAME DATA (SR[8:583])*
8
288 = {SR[14:19], SR[26, 31],..., SR[578:583]}*
6
LD
LDIBLANK
PWMCK
COR[n]
41
39
CTRL
×48
6
288
CORRECTION
MULTIPLIER
SEL
LD
576
SCKO
38
PWM CHANNEL
12
PWMR[n]
12
EN
EN
PWMxx
×48
12
PWMRSYNC[n]
12-BIT PWM
GENERATION
GND
57
PWMCK
COUNTER
8500 BD
*REVERSE INDEXING IS USED TO INDICATE PHYSICAL BIT ORDER.
Figure 1. Block Diagraꢁ
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For more information www.linear.com/LT8500
LT8500
operaTion
OVERVIEW
Update frames are used to serially load the 12-bit values
for each of the 48 PWM channels. The LT8500 contains
a correction multiplier that can automatically scale the
12-bit PWM channel data before it’s stored. By default,
the correction multiplier is enabled and scales incoming
channel data according to:
The LT8500 controls 48 pulse width modulated
(PWM[48:1]) outputs, suitable for control applications
such as driving three LT3595A LED drivers. The chip’s
operation is best understood by referring to the Block
Diagram in Figure 1.
3
CORn + 32
64
2
The major blocks inside the LT8500 are: a 584-bit
shift register (SR[0:583]), 48 6-bit correction registers
(COR[1:48]), a correction multiplier, 48 PWM channels
and a PWMCK clock counter. Each PWM channel stores
data for the associated PWMx output pin and includes a
PWM register (PWMR) and a PWM synchronization reg-
ister (PWMRSYNC). The lower 8 bits of the 584-bit shift
register are the command register (CR[0:7]) and the rest
of the shift register contains the frame data.
PWMOUTn = CHANn(NOM)
•
•
where PWM
is the number of PWMCK cycles that
OUTn
PWMn is high, CHAN
is the nth channel field in
n(NOM)
the frame, and CORn is the nth programmed correction
setting (CORn = 0 to 63). See Table 1 for examples.
Otherwise, when the correction multiplier is disabled, the
incoming data is stored unchanged:
PWM
= CHAN
n(NOM)
A comparison of a channel’s PWMRSYNC register to the
PWMCK counter generates the respective PWM output
signal. The input of the 584-bit shift register (SR[0]) is
connected to the SDI signal. SDI is also an input to the
correctionmultiplier.Theoutputofthe584-bitshiftregister
(SR[583]) is connected to SDO.
OUTn
The correction multiplier is disabled by the correction
register disable bit (CRD), which is toggled by the cor-
rection toggle command (CMD = 0x7X). By default, the
correction multiplier is enabled after power-up and the
CRD bit is low.
The user communicates with the part by controlling the
serialinterfacepinsSDI,SCKIandLDIBLANK.Aserialdata
frame, called a command frame, is shifted into the part
on SDI using SCKI as the clock signal. At the same time,
the status frame is shifted out on SDO. A rising edge on
the LDIBLANK pin terminates a frame. A frame consists
of a 12-bit data field for each PWM channel, followed
by an 8-bit command field, totaling (12 × 48) + 8 = 584
bits. The data is transꢁitted with the ꢁost significant
channel first, and each field is transꢁitted MSB first.
The frame formats and timing are illustrated in Figures 3
and 4, respectively. There are eight commands, two of
whichupdatethePWM[48:1]outputs. Thecommandsare
summarized in Table 2. Within this document, command
frames will be referred to by the commands they issue,
such as “update frame” or “correction frame.”
The result generated by the correction multiplier moves
to the respective PWMRSYNC register after an update
frame. An update frame does this either synchronously or
asynchronously. A synchronous update frame will copy
the data to the PWMR on the subsequent rising edge of
LDI which marks the end of the frame, and then from the
PWMR to the PWMRSYNC register at the beginning of a
PWM period. A PWM period starts when the free-running
PWMCK counter is zero. Otherwise, the asynchronous
update frame will copy the data from the correction mul-
tiplier, through the PWMR to the PWMRSYNC at the same
time, on the subsequent rising edge of LDI which marks
the end of the frame.
As soon as the PWMRSYNC registers are updated with
their new values, the PWM outputs will reflect the update.
As mentioned earlier, the PWMR outputs are generated
by comparing the respective PWMRSYNC values to the
PWMCK counter.
With a 50MHz SCKI, a single frame can be transmitted in
11.7µs (584 SCKIs + LDI), for a frame rate of 85.5kHz.
A 25MHz PWMCK creates a PWM period (4096 PWMCKs)
of 164µs, or a PWM output frequency of 6.1kHz.
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START-UP
SERIAL DATA INTERFACE
The LT8500 is ready to communicate after power-up, if
the LDIBLANK pin is low. The PWM[48:1] outputs remain
disabled (logic 0) until an output enable frame is sent. The
recommended sequence of events for start-up is:
The LT8500 has a 50MHz cascadable serial data interface
with full buffering and skew balancing on clock and data.
The interface uses a novel 5-wire (LDIBLANK, SCKI, SDI,
SCKO, and SDO) topology and can be connected to a
variety of digital controllers, such as microcontrollers,
digital signal processors (DSPs), or field programmable
gate arrays (FPGAs).
1. Apply power and drive LDIBLANK low. SDO will go low
when the on-chip power-on-reset (POR) de-asserts.
2. Send a correction register frame (CMD = 0x20) on the
serial interface. This sets the correction factor on each
channel.
Topology
TwotopologiesshowninFigure2aresupportedforcascad-
ing the LT8500. For higher speeds and a large number of
LT8500s, consider the novel 5-wire topology. For lower
speedsandfewLT8500s,considertheconventional4-wire
topology. Whichever topology is used, signal integrity
should be carefully evaluated, especially for the clocks.
3. Send an update frame (CMD = 0x00 or CMD = 0x10)
on the serial interface. This sets the pulse width of each
channel.
4. Send an output enable frame (CMD = 0x30) on the
serial interface. This enables the modulated pulses on
the PWM[48:1] outputs.
The 5-wire topology eliminates the need for global SCKI
routing and reduces the need for buffer insertion for the
SCKI signal. Instead, it provides the SCKO signal along
with the SDO signal to drive the next chip. The skew inside
the chip between the SCKI and SDI signals is balanced
internally. The skew outside the chip between the SCKO
and SDO signals can be easily balanced by parallel routing
The PWM clock (PWMCK) should be turned on before
step 4. The start of a PWM period, when all PWM[48:1]
channels turn on, is synchronized to the output enable
frame when the outputs are disabled prior to the frame.
Novel 5-Wire Topology
LDI
SCKI
SDI
LDI
SCKI
SDI
LDI
SCKI
SDI
LDI
SCKI
SDI
SCK0
SDO
LT8500 (1)
SCK0
SDO
LT8500 (2)
SCK0
SDO
LT8500 (N)
HOST
CONTROLLER
SDO
SCKO
Conventional 4-Wire Topology
LDI
SCKI
SDI
LDI
SCKI
SDI
LDI
SCKI
SDI
LDI
SCKI
SDI
SDO
SDO
SDO
LT8500 (1)
LT8500 (2)
LT8500 (N)
HOST
CONTROLLER
SDO
8500 F02
Figure 2. Serial Interface Topologies
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these two signals between chips. When properly balanced
in this way, the SCKO/SDO timing will meet the timing
requirements of SCKI/SDI on the next cascaded chip,
enabling faster clock speeds and more chips in cascade.
The host controller sends the SDI signal with the SCKI
signal, and receives the SDO signal with the SCKO signal.
The controller will see skew between SCKI and SCKO,
and will need to operate on two clock planes depending
on the number of cascaded LT8500s and system timing
significant channel first, and each field is transmitted with
MSB first. The command frames are sent with the SCKI
signal and the status frame is received with the SCKO
signal. The command field determines the function of a
frame, according to Table 2. The status frame consists of
the four MSB’s of the last command (CR[7:4]), the open
LED self test bit (OLT), the synchronization error status
bit (SYC), the phase-shift status bit (PHS), the correction
register disable status bit (CRD), and individual OPENLED
fault bits (NOL[48:1]), as well as each 6-bit correction
register (COR[48:1]). Logic zeros fill in the unused bits
of the status frame. Refer to Figure 3.
constraints. A duty cycle change (t
) will also occur
DC-SCK
between SCKI and SCKO, limiting the number of LT8500s
in a chain, depending on SCKI speed. This change results
from a slight difference in propagation delays of the posi-
tive and negative edges of SCKI. LDIBLANK skew between
chips may require balancing in timing critical systems,
otherwise the host should increase the delay between
SCKI and LDI to avoid violating LDI to SCKI setup and
Figure 4 illustrates the timing relationship among serial
input and serial output signals in more detail. One correc-
tion register frame followed by an update frame is sent
through the SDI, SCKI, and LDIBLANK pins. At the same
time, two status frames are received through the SDO,
SCKO, and LDIBLANK pins. The rising edges of SCKI shift
a frame of data into shift register SR[0:583]. After 584
clock cycles, all bits of data sit in the shift register waiting
for the LDI signal. An asynchronous LDIBLANK “high”
signal captures the decoded 8-bit CMD field (CR[7:0]),
executing commands and routing data accordingly. At
the same time, a frame of status information, including
the 4 MSB’s of the CMD field (CR[7:4]), status bits, COR
registers, and individual open LED fault flags, is parallel
loaded into the 584-bit shift register and will be shifted
out as the next frame shifts in.
hold times (t
and t
). In summary, the 5-wire
HD-LDI
SU-LDI
topology extends the maximum number of cascadable
chips, boosts the series data interface clock frequency,
eliminates global SCKI routing, reduces the need of buf-
fer insertion for SCKI signals, and offers an easier PCB
layout. In a low-speed application with a small number of
cascaded chips, the 5-wire topology can be simplified to
the 4-wire topology by ignoring the SCKO output.
In a 4-wire topology, the LDIBLANK and SCKI signals
need global routing while the SDI signal only needs local
routing between chips. SCKO is ignored. When a large
number of chips are in cascade, or long board traces
are used, external clock-tree buffers with corresponding
driving capability might be needed for the LDIBLANK and
SCKI signals to minimize signal skews. The propagation
delay caused by the buffer insertion on the SCKI signal
yields the skew between the SCKI and SDI signals, which
usually requires balancing. Since both the SDI and SDO
signals require the same SCKI signal to send and receive,
the propagation delay between the SDI and SDO signals
limits the number of chips in cascade and the series data
interface clock frequency.
LDIBLANK = LDI + BLANK
The LDIBLANK pin is a dual function input, determined by
the duration of a logic high on the pin. LDI is the latch data
input, which signals the end of a frame and executes the
command in the CMD field (CR[7:0]). The BLANK signal
turns off the PWM[48:1] outputs and performs a global
reset of the part, including the shift register in the serial
interface. A logic high on LDIBLANK always asserts LDI,
while a logic high greater than the minimum LDIBLANK
pulsedurationforBLANK(t
)alsoassertsBLANK.
WH-BLANK
BLANKwillneverbeassertedifthepinisheldhighlessthan
Coꢁꢁunication
the maximum LDIBLANK pulse duration for LDI (t
).
WH-LDI
Figure 3 shows two command frames sent on SDI, and
one status frame received on SDO. All the frames have
the same 584-bit length and are transmitted with the most
Between maximum t
and minimum t
,
WH-LDI
WH-BLANK
BLANK becomes asserted at an undetermined time.
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A rising edge on the LDI signal is always interpreted as
the end of a frame. The next rising edge of SCKI after the
falling edge of LDIBLANK is always interpreted as the start
of a new frame. An out-of-sync error bit (SYC) is provided
in the status frame to alert the system if the part saw an
LDI unexpectedly. This occurs when LDI and SCKI are
both hi, or when LDI is hi on other than a frame boundary
(n • 584 SCKI’s). The SYC bit is for information only, it has
no other effect on the part. If the SYC bit is set, none of
the other data in the status frame is reliable and the effect
of the prior frame is unknown; the LT8500 assumes the
system’s timing of the LDI is correct and considers the
next SCKI as the start of the next frame.
counter is free-running from the PWMCK clock when
outputs are enabled. When an output enable frame is sent,
the PWMCK counter increments to one on the second ris-
ing edge of PWMCK after the rising edge of LDIBLANK, as
shown in Figure 5. By default, all outputs with non-zero
values in PWMRSYNC will turn on when the PWMCK
counter is one. Alternatively, if the phase-shift bit (PHS)
is set, the PWM[48:1] outputs will turn on as illustrated in
the phase-shift synchronous updates in Figure 6, case A.
Further discussion of the phase-shift function follows.
Each subsequent rising edge of PWMCK increases the
PWMCK counter by one. Any PWM channel will be turned
off when its PWMRSYNC value is equal to the value in
the PWMCK counter. An output disable frame resets the
PWMCK counter immediately after LDI, and turns off all
thePWMchannelsonthenextrisingedgeofPWMCKafter
LDI. Figure 5 shows the PWM output enable timing chart.
OPENLED
The OPENLED pin provides status information to the
host by reporting its state in the status frame. The state
of the pin is captured by each rising edge of PWMCK and
is reported in two ways. In typical use, the status frame
receives the captured state of the pin on the rising edge
of the first SCKI after LDIBLANK goes low. This state is
duplicated 48 times and reported in the LSB of each PWM
channel in the status frame. The state will normally be a
logic “1” due to the on-chip pull-up resistor.
1
t
PD-PWM
f
PWMCK
0
1
2
3
PWMCK
LDI, CMD = 0x30
8500 F05
PWM
Alternatively, the LT8500 supports a diagnostic self test
frame (CMD = 0x5X) that reports the OPENLED state
differently. In this case, the LT8500 sequentially pulses
PWM[1] through PWM[48] high for 64 PWMCK cycles
each. The state of the OPENLED pin is captured for each
channel while the corresponding PWM pin is high. This
by-channel data is shifted out in the status frame as the
nextframeisshiftedin.Inaddition,thestatusframewillset
the open LED test bit (OLT), indicating that the OPENLED
data in the current status frame is from the self test. The
statusframewillreturntotypicalreportingonthefollowing
frame. When the LT8500 is used with the LT3595A, the
OPENLEDpinandtheselftestprovideadiagnosticroutine
to identify the location of open LED faults. See “Diagnostic
InformationFlags”intheApplicationsInformationsection.
Figure 5. PWM Output Enable Tiꢁing Chart
Assuꢁes Outputs Were Previously Disabled
PHASE DIFFERENCE BETWEEN 16-CHANNEL BANKS
By default, the rising edges of all PWM[48:1] channels
occur on the same rising edge of PWMCK. This event
begins a PWM period of 4096 PWMCK cycles. The
LT8500 provides a phase-shift toggle command (CMD =
0x6X) to reduce system noise and current spikes result-
ing from 48 pins switching at once. The function of this
command is illustrated in Figure 6, case A. In phase-shift
mode, the PWM[48:1] outputs are divided into three
16-channel banks that are 120 degrees out-of-phase
with each other within a PWM period. This means that
channels PWM[48:33] will turn on with the rising edge of
PWMCK(1), then channels PWM[32:17] will turn on with
the rising edge of PWMCK(1365), 1/3 of the PWM period,
and channels PWM[16:1] will turn on with the rising edge
of PWMCK(2730), 2/3 of the PWM period.
OUTPUTS
After power-up or reset, no PWM[48:1] output will turn on
until an output enable frame is sent. The 12-bit PWMCK
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Table 1. Exaꢁple PWM Width Calculations (Base 10) with Correction Enabled (CRD = 0)
A
B
C
D
E
PWM UPDATE VALUE
SENT ON SDI
PRESCALED PWM
(A • 2/3)
CORRECTION REGISTER
(COR) VALUE
MULTIPLIER
(C + 32)/64
PWM WIDTH (B•D)
(IN UNITS OF t
)
PWMCK
3
2
63
63
32
0
1.484375
1.484375
1.0
3
120
80
119
80
120
80
120
80
0.5
40
1200
1200
1200
4095
4095
4095
800
800
800
2730
2730
2730
63
32
0
1.484375
1.0
1188
800
400
4052
2730
1365
0.5
63
32
0
1.484375
1.0
0.5
PWM CALCULATION BY DIGITAL MULTIPLICATION OF
CORRECTION REGISTER AND PWM UPDATE VALUES
So, a correction multiplier of ~1.5 (CORn = 63) yields a
corrected PWM width of 4052 = 4095 • (2/3) • 1.484375.
ThePWM
widthisalwaysroundedtothenearestwhole
OUTn
The correction multiplier is used to automatically scale
the 12-bit PWM channel data before storing the PWM
update value for the respective channel. The correction
multiplier is disabled by the correction register disable bit
(CRD),whichistoggledbythecorrectiontogglecommand
(CMD=0x7X). When the correction multiplier is disabled,
the incoming data is stored unchanged:
number. Table 1 shows examples of PWM calculations for
selected register values. This means the maximum PWM
duty cycle with CRD=0 is 4052/4096, and with CRD=1 it
is 4095/4096.
COMMAND DESCRIPTIONS
The LT8500 implements eight commands, outlined in
Table 2. The commands (CMD) are encoded in the eight
LSB’s of a command frame, and so reside in the eight
LSB’s of the shift register when a frame has been com-
pletely shifted in. The command field is executed by the
rising edge of LDI. Only the four MSB’s of the command
field are decoded for commands.
PWM
= CHAN
n(NOM)
OUTn
The correction multiplier is enabled by default (CRD=0)
and scales incoming channel data according to:
2
3
DCR + 32
n
GSRn(CALC) = GSRn (NOM)
•
•
64
where PWM
is the number of PWMCK cycles that
OUTn
PWMn is high, CHAN
is the nth channel field in
Synchronous Update Fraꢁe: CMD = 0x0X
n(NOM)
the frame, and CORn is the nth programmed correction
setting (CORn = 0 to 63). See Table 1 for examples.
AsynchronousupdateframeupdatesPWM[48:1]withthe
data in the frame, after processing through the Correction
Multiplier. The PWMR is updated when LDIBLANK goes
high. The PWMRSYNC register will be written from the
PWMR synchronously to the start of the PWM period (on
PWMCK 1). This command eliminates shortened PWM
“runt” pulses. The value in the PWMRSYNC registers
will update the PWM outputs on the next rising edge of
PWMCK. Examples are shown in Figure 6, cases B and E.
The 6-bit COR value sets a multiplier of 0.5X to ~1.5X
(exactly 1.484375, or ((63 + 32)/64)) with 64 values and
a midrange, signifying a multiple of 1.0, at 32 (0x20). In
order to avoid overflow in the PWM registers when the
multiplier is greater than 1.0, the nominal PWM update
value (CHANn) is first prescaled on chip by 2/3. This
means that the full-scale width for a channel with a mul-
tiplier of 1.0 (CHANn = 4095, CORn = 32) will result in a
PWM
width of 4095 • (2/3) • 1.0 = 2730, not 4095.
OUTn
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Table 2. Coꢁꢁand Register Decoding
CMD (CR[7:0])
0000_xxxx
0001_xxxx
0010_xxxx
0011_xxxx
0100_xxxx
0101_xxxx
0110_xxxx
0111_xxxx
1xxx_xxxx
NAME
SUMMARY
FRAME DATA
Synchronous Update Frame
Asynchronous Update Frame
Correction Frame
Update PWM’s Synchronously to PWM Period
Update PWM’s Asynchronously to PWM Period
Set PWM Correction Factor
PWM Update by Channel
PWM Update by Channel
Correction by Channel
Don’t Care
Output Enable Frame
Output Disable Frame
Self Test Frame
Enable PWM Outputs
Disable (Drive Low) PWM Outputs
Initiates Self Test
Don’t Care
Don’t Care
Phase-Shift Toggle Frame
Correction Toggle Frame
Reserved
Toggle 16-Channel Bank 120° Phase-Shift (PHS)
Toggle Correction Disable Bit in Multiplier (CRD)
Do Not Use
Don’t Care
Don’t Care
–
Asynchronous Update Fraꢁe: CMD = 0x1X
Output Disable Fraꢁe: CMD = 0x4X
An asynchronous update frame updates PWM[48:1] with
the data in the frame, after processing through the correc-
tionmultiplier.ThePWMRisupdatedwhenLDIBLANKgoes
high.ThePWMRSYNCregisterwillbewrittenimmediately
(asynchronously), through the PWMR, when LDI is high.
ThevalueinthePWMRSYNCregisterswillupdatethePWM
outputs on the next rising edge of PWMCK. Examples are
shown in Figure 6, cases C and F.
An output disable frame immediately resets the PWMCK
counterwhenLDIgoeshigh,anddisablesthePWMoutputs
on the next rising edge of PWMCK. There is no effect on
either SDO or SCKO. The data in the output disable frame
is irrelevant to the command, but allows a daisy chain of
LT8500’s to function properly.
Self Test Fraꢁe: CMD = 0x5X
The self test frame can be used for diagnostics on each
PWM[48:1], including identifying open LED strings on
an LT3595A. After LDIBLANK goes hi, the LT8500 pulses
PWM[1] through PWM[48] sequentially for 64 PWMCK
cycles each. The state of the OPENLED pin is captured
for each channel while the corresponding PWM pin is
high. This by-channel data is subsequently shifted out in
the status frame. In addition, the status frame will set the
open LED test bit (OLT) to confirm that the OPENLED data
in the current status frame is from the self test. For all
othercommands,thestateoftheOPENLEDpiniscaptured
once on the first SCKI of the frame. The same value is
then reported in the status frame on all 48 channels. The
data in the self test frame is irrelevant to the command,
but allows a daisy chain of LT8500’s to function properly.
Correction Fraꢁe: CMD = 0x2X
A correction frame updates the correction registers (COR)
with the six MSB’s of each channel’s data field in the
frame. The CORs are used by the correction multiplier to
adjust the PWM width, prescaled by 2/3, by a multiplier of
between 0.5 and ~1.5. Example PWM width calculations
are shown in Table 1. In typical applications, this com-
mand will only be run once after power-up to initialize the
system. Therefore, a correction frame will not update the
PWM outputs. The update frame that follows a correction
frame will reflect the COR update.
Output Enable Fraꢁe: CMD = 0x3X
An output enable frame starts a PWM period, and enables
the PWM outputs, on the second PWMCK edge after
LDIBLANK goes high. There is no effect on either SDO or
SCKO. The data in the output enable frame is irrelevant
to the command, but allows a daisy chain of LT8500’s to
function properly.
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Phase-Shift Toggle Fraꢁe: CMD = 0x6X
Case B illustrates a synchronous update frame (CMD =
0x0X) while in phase-shift mode, as in case A. The LDI
signal goes active 512 PWMCK cycles into the PWM
period, after PWM[48] has turned off. The update frame
programs a PWM width of 1024, but the synchronous
update command prevents a channel from updating
except at the beginning of its PWM period. As a result,
PWM[48] remains low until the next PWM period, when
the updated width drives it high for 1024 PWMCK cycles.
PWM[32] begins its PWM period at PWMCK 1365, and
PWM[16] starts at PWMCK 2730, both updated to 1024
PWMCK cycles.
Thephase-shifttoggleframetogglesthephase-shift(PHS)
bit, which is off by default. When PHS is set, it sets the
rising edges of the PWM outputs, by banks of 16 chan-
nels, out-of-phase with each other by 120 degrees. This
meansthatchannelsPWM[48:33]willstartthePWMcycle
with a rising edge at the beginning of a PWM period, then
channels PWM[32:17] will start their PWM cycle 1/3 of
the time into a PWM period, and channels PWM[16:1] will
start 2/3 of the time into a PWM period. The state of the
PHS bit is returned in every status frame. The data in the
phase-shift toggle frame is irrelevant to the command,
but allows a daisy chain of LT8500’s to function properly.
Case C illustrates an asynchronous update frame (CMD
= 0x1X) while in phase-shift mode, as in case A. The LDI
signalgoesactive512PWMCKcyclesintothePWMperiod,
afterPWM[48]hasturnedoff. Theupdateframeprograms
a PWM width of 1024, and because it is an asynchronous
update, PWM[48] immediately rises and stays high until
PWMCK 1024. PWM[32] and PWM[16] (and all PWM’s)
are also updated, but no rising edge occurs until their
PWM period begins due to the phase-shifting.
Correction Toggle Fraꢁe: CMD = 0x7X
Thecorrectiontoggleframetogglesthecorrectionregister
disable(CRD)bit, whichisoffbydefault. WhenCRDisset,
it disables use of the correction registers (CORs) in the
correctionmultiplier,insteadmultiplyingtheincomingdata
from SDI by “1.” This causes the data in an update frame
to reach the PWMRSYNC registers unchanged. The state
oftheCRDbitisreturnedineverystatusframe. Thedatain
the correction toggle frame is irrelevant to the command,
but allows a daisy chain of LT8500’s to function properly.
Case D illustrates the default (not phase-shifted) mode in
steady-state. All PWM outputs rise on the same PWMCK
edge at the beginning of the PWM period.
Case E illustrates a synchronous update frame (CMD =
0x0X) without phase-shifting, as in case D. The LDI signal
goes active 512 PWMCK cycles into the PWM period, after
the PWMs have turned off. The update programs a PWM
width of 1024, but the synchronous update command
prevents a channel from updating except at the beginning
of it’s PWM period. As a result, all PWM’s remain low until
thenextPWMperiod, whentheupdatedwidthdrivesthem
high for 1024 PWMCK cycles.
Exaꢁples of PWM Updates for Selected Cases
Figure6showsexamplesoftheeffectofvariouscommands
onthePWMoutputwaveforms.Theseexamplewaveforms
assume all three channels shown are always programmed
for the same PWM width. For each case, a representative
channelisshownfromeachofthethree16channelbanks,
PWM[48:33], PWM[32:17], and PWM[16:1].
CaseAillustratesthephase-shiftmodeinsteady-state,with
PWM’s programmed for a width of 256 PWMCK cycles.
PWM[48], from bank 2, rises at the beginning of the PWM
period. PWM[32], from bank 1, rises 1/3 of the way into
the PWM period of bank 2, or 1365 PWMCK cycles later.
PWM[16], from bank 0, rises 2/3 of the way into the PWM
period of bank 2, or 2730 PWMCK cycles later.
Case F illustrates an asynchronous update frame (CMD =
0x1X) without phase-shifting, as in case D. The LDI signal
goes active 512. PWMCK cycles into the PWM period,
after the PWMs have turned off. The update programs a
PWM width of 1024, and because it is an asynchronous
update, all PWM’s immediately rise and stay high until
PWMCK 1024.
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4096 • t
PWMCK
2730 • t
PWMCK
1365 • t
PWMCK
256 • t
PWMCK
PWM [48]
PWM [32]
PWM [16]
LDI
CASE A: STEADY STATE WITH PHASE-SHIFT
512 • t
PWMCK
PWM [48]
PWM [32]
PWM [16]
CASE B: SYNCHRONOUS UPDATE WITH PHASE-SHIFT
CASE C: ASYNCHRONOUS UPDATE WITH PHASE-SHIFT
1024 • t
PWMCK
PWM [48]
PWM [32]
PWM [16]
PWM [48]
PWM [32]
PWM [16]
CASE D: DEFAULT STEADY STATE (NO PHASE-SHIFT)
LDI
PWM [48]
PWM [32]
PWM [16]
CASE E: SYNCHRONOUS UPDATE (NO PHASE-SHIFT)
PWM [48]
PWM [32]
PWM [16]
8500 F06
CASE F: ASYNCHRONOUS UPDATE (NO PHASE-SHIFT)
Figure 6. Exaꢁples of PWM Outputs For Selected Coꢁꢁand Cases
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applicaTions inForMaTion
This section is illustrated with an LED dimming applica-
tion, but is relevant to other applications as well. The
LT8500 provides 48 PWM outputs, such as for driving
three LT3595A LED drivers. The LT8500 provides an LED
dot correction function using digital multiplication of the
correction register (COR) and the PWM update value,
which is prescaled by 2/3. This results in a dot corrected
PWM duty cycle. Optionally, the PWM update can be
written directly (unchanged) by setting the correction
register disable bit (CMD = 0x7X). When this bit is set,
the multiplication is bypassed and dot correction, if any,
must be calculated off-chip. The PWM duty cycle in this
case will be the nominal value sent in the update frame,
divided by 4096. The part provides a status frame with
OPENLEDandCORdataforeachchannel, andglobalstate
data indicating self testing (such as for open LED’s), out-
of-sync error, phase-shift status, and direct data status.
The status frame is shifted out of the part whenever a new
frame is shifted in. An on-chip self test is available (CMD
= 0x5X) to determine which channel is responsible for a
fault, such as open LEDs. The OPENLED pin and self test
are especially suited for use with the LT3595A. In this
application, the self test will identify which channels have
opens in their LED strings. This Applications Information
section serves as a guideline for avoiding common pitfalls
for the typical application.
where GSR
(same as PWMR) setting (GSR
dot correction enabled).
is the nth calculated grayscale register
n(CALC)
= 0 to 4052 with
n(CALC)
Setting Dot Correction
The LT8500 can adjust the PWM duty cycle for each chan-
nel independently. The duty cycle adjustment, also called
dot correction, is mainly used to calibrate the brightness
deviationbetweenLED channels. The 6-bit(64 values) dot
correction registers (DCR) adjust each PWM duty cycle
from 0.5X to ~1.5X of the duty cycle, prescaled by 2/3,
sent to the grayscale register (GSR) according to
2
3
DCR + 32
n
GSRn(CALC) = GSRn (NOM)
•
•
64
whereGSR
isthenthcalculatedgrayscaleregister,
n(CALC)
GSR
isthenominalgrayscalevaluesenttothenthchan-
n(NOM)
nelandDCR isthenthprogrammeddotcorrectionsetting
n
(DCR = 0 to 63).
n
Cascading Devices and Deterꢁining Serial Data
Interface Clock
In a large LCD backlighting or LED display system, mul-
tiple LT8500 chips can be easily cascaded to drive all LED
drivers, such as the LT3595A, and their associated LED
strings.TheLT8500adoptsanovel5-wiretopology,which
balances clock skew and eases PCB layout.
Setting Grayscale by PWM Updates
Although adjusting the LED current changes its luminous
intensity, or brightness, it will also affect the color match-
ing between LED channels by shifting the chromaticity
coordinate. The best way to adjust the brightness is to
control the amount of LED on/off time by pulse width
modulation (PWM).
The time required to send a set of cascaded frames is 584
SCKI cycles per LT8500, plus another cycle time for LDI.
Assuming LDI is externally balanced, the minimum serial
data interface clock frequency ƒ
system can be calculated as:
for a large display
SCK
ƒ
SCK
= [(n • 584) + 1] • ƒ
CHIPS REFRESH
The LT8500 can adjust the brightness for each channel
independently. The 12-bit PWM registers (PWMR), used
for grayscale (GS) dimming, results in 4095 different
brightness steps from 0ꢀ to 99.98ꢀ. The brightness
level, or PWM duty cycle, GSnꢀ for channel n can be
calculated as:
where n
REFRESH
is the number of cascaded LT8500s and
CHIPS
ƒ
is the refresh rate of the whole system.
Status Fraꢁe Inforꢁation
The status frame is captured and shifted out of SDO as a
new data frame shifts in on SDI. The format of a status
frame is shown in Figure 3. With the exception of the
diagnostic flags (SYC and NOL[48:1]), the data in the
status frame does not change without a command from
8500fb
GSR
GSnꢀ=
n(CALC) •100ꢀ
4096
18
For more information www.linear.com/LT8500
LT8500
applicaTions inForMaTion
the user interface. It can therefore be monitored to con-
firm proper communication with the chip. The following
non-diagnostic status information is continually provided
in the status frame: dot correct registers for each channel
(COR[48:1]), Open LED Testing bit (OLT), phase-shift bit
(PHS), correction register disable (CRD) bit. There are
five unused bits, [5:1], in the field associated with each
channel, all of which are always set to logic zero.
open, each of the 48 OPENLED (NOL[48:1]) status flags
will be cleared. Upon detecting this condition in the status
frame, or as a polling strategy, the host may request an
LED self test (CMD = 0x5X), where the LT8500 will test
each channel to determine which, if any, is open. The test
drives each PWM pin high, one at a time, in order, for 64
PWMCKcycleseach,andcapturesthecorrespondingvalue
on the OPENLED pin for the associated PWM channel.
These results will overwrite the NOL flags in the status
frame and the open LED test bit (OLT) will be set in the
status frame to indicate that the NOL data in this status
frame is given by channel. In the next frame, the OLT bit
will be cleared and all 48 NOL bits will again reflect the
state of the OPENLED pin.
Diagnostic Inforꢁation Flags
The LT8500 features two kinds of diagnostic information
flags: global out-of-sync error (SYC) and 48 individual
open LED flags (NOL[48:1]).
An out-of-sync error occurs when the part sees an LDI
signal unexpectedly, whether before 584 SCKI clocks,
or coinciding with SCKI high. Either of these events can
corrupt the data and the state of the chip. The SYC bit is
available in every status frame to notify the system if an
erroneous LDI was seen since the first rising edge of SCKI
ofthelastframe.AseriesofmultipleLDI’sbetweenframes,
with no SCKI, is not an out-of-sync error. Recovery from
an out-of-sync error may require the user to completely
rewrite the data and state of the chip. The LDI signal resets
the serial interface.
PCB Layout Guidelines
The following guidelines should be considered when de-
signing printed circuit boards (PCBs) using the LT8500.
These guidelines are more important as clock speeds and
daisy chain sizes increase.
1. Match the line lengths and delays between SDI and
SCKI to each LT8500.
2. Ensure the timing of LDI to each chip meets SCKI to LDI
setup and hold requirements. In a 5-pin topology, SCKI
is delayed by each chip in the daisy chain, so LDI may
need extra delay to match the delayed SCKI down the
chain. See the discussion on topology in the Operation
section.
The OPENLED bits, NOL[48:1], are well suited for use
with the LT3595A, and indicate an open circuit has been
detected on at least one of the 48 LED strings driven
by the three LT3595A’s. The part monitors the three
LT3595A wired-OR OPENLED pins that detect open LED
strings for each LT3595A. When one of the LT3595A’s
detects an open LED string, it will pull OPENLED low dur-
ing the PWM high time for that LED string. The state of
OPENLED is captured by the LT8500 on the rising edge
of the first SCKI of a new frame (after LDI). Since SCKI
and PWMCK are asynchronous, the detection of an
open LED string by this method is a probability function
dependent on the frame rate and PWM duty cycle. If a new
frame begins when the PWM pin associated with an open
LED string is high, the OPENLED pin will be driven low and
captured in the status register, but if a new frame begins
whentheassociatedPWMpinislow,theOPENLEDpinwill
be pulled high and the status register will capture a default
high. When a low OPENLED pin is captured, signaling an
3. Avoid cross talk between the communication signals
(SDI, SCKI, LDI, SDO, SCKO) and the PWMs. Even
though the PWM’s signals toggle at a slow rate, all of
their rising edges can occur within a few nanoseconds
of each other.
4. Buffer the signals returning to the host if their paths
are long.
5. Highspeedtechniques:standardhighspeedPCBdesign
techniquesshouldbeusedonhighfrequencyclockand
datalines.Theseincludeshortpathlengths,shieldingof
high speed data cables and traces, minimized parasitic
capacitance, and reducing antennas and reflections.
6. A ceramic bypass capacitor should be placed close to
the V pin.
CC
8500fb
19
For more information www.linear.com/LT8500
LT8500
Typical applicaTions
Four typical applications are shown in Figures 7 to 10.
Figures 7 and 8 illustrate the 5-pin and 4-pin topologies
for daisy chains as discussed earlier in this data sheet.
Figure 9 illustrates a single LT8500 controlling 48 resistor
ballasted LED strings. Figure 10 illustrates a novel use of
the LT8500 as a 48-channel digital-to-analog converter
(DAC). Using a simple RC filter on each PWM output, the
resulting converter has very good error characteristics
as shown in the accompanying differential linearity error
(DLE) and integrated linearity error (ILE) charts (Figures
11 and 12). The DLE measurements were taken from an
all codes test, and were compensated for power supply
variation on V of less than 0.01ꢀ over the course of
CC
the test. The ILE is simply the sum of all previous com-
pensated DLE measurements. The units of the DLE and
ILE measurements are in PWM LSB’s.
8500fb
20
For more information www.linear.com/LT8500
LT8500
Typical applicaTions
8500fb
21
For more information www.linear.com/LT8500
LT8500
Typical applicaTions
V
DD
12V
HOST
V
DD
3.0V TO 5.5V
SCKI
SDI
LDIBLANK
PWM1
M1
V
CC
•
•
•
•
•
•
•
•
•
•
LT8500
PWMCK
OK TO FLOAT
PWMCK
OPENLED
CMLDM7003
M48
PWM48
SCKO
SDO
GND
8500 TA04
OK TO
FLOAT
Figure 9. Single LT8500 Driving 48 Resistor Ballasted LED Strings Froꢁ a VDD Rail
HOST
3.0V TO 5.5V
SCKI
SDI
LDIBLANK
PWM1
100k
100k
ANALOG OUT1
ANALOG OUT48
V
CC
•
•
•
•
•
•
•
•
•
•
1µF
1µF
LT8500
PWMCK
OK TO FLOAT
PWMCK
OPENLED
PWM48
SCKO
SDO
GND
8500 TA05
OK TO
FLOAT
Figure 10. Single LT8500 Iꢁpleꢁenting 48 Digital-to-Analog Converter (DAC) Channels
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
512 1024 1536 2048 2560 3072 3584 4096
0
512 1024 1536 2048 2560 3072 3584 4096
PWM WIDTH CODE
PWM WIDTH CODE
8500 TA06
8500 TA07
Figure 11. DAC Differential Linearity Error (DLE)
Figure 12. DAC Integrated Linearity Error (ILE)
8500fb
22
For more information www.linear.com/LT8500
LT8500
package DescripTion
Please refer to http://www.linear.coꢁ/product/LT8500#packaging for the ꢁost recent package drawings.
TJ Package
56-Lead Plastic TLA QFN (6mm × 6mm)
(Reference LTC DWG # 05-08-1968 Rev C)
0.15 0.05
0.50 0.05
3.60 0.05
0.75
6.30 0.05
5.30 0.05
4.70 0.05
4.00 0.05
0.55 0.05
3.10
0.05
0.6
0.125
PACKAGE OUTLINE
0.125
0.30 0.05
0.30 0.05
0.80 0.05
0.15 0.05
0.15 0.05
0.55 0.05
5.20 0.05
6.30 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.78 0.05
6.00 0.10
(4 SIDES)
0.30 0.05
A31
A40 A1
PIN 1 TOP MARK
(SEE NOTE 6)
0.45 REF
B16
B1
PIN 1 NOTCH
R = 0.45 OR
0.35 × 45°
CHAMFER
3.60 0.10
0.30 0.05
0.55
BSC
3.20 0.10
B8
B9
0.8 REF
0.10 REF
A11
A21
0.25 REF
0.03–0.09
0.55 BSC
0.30 0.05
NOTE:
0.10 REF
1. DRAWING NOT TO SCALE
(TL56) QFN REV C 0815
2. ALL DIMENSIONS ARE IN MILLIMETERS
BOTTOM VIEW—EXPOSED PAD
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6. 4 MIL THICK LASER CUT STENCIL IS RECOMMENDED. STENCIL OPENING 1:1 TO PCB LAND PATTERN.
8500fb
23
For more information www.linear.com/LT8500
LT8500
package DescripTion
Please refer to http://www.linear.coꢁ/product/LT8500#packaging for the ꢁost recent package drawings.
Not Recoꢁꢁended for New Designs
UHH Package
56-Lead Plastic QFN (5mm × 9mm)
(Reference LTC DWG # 05-08-1727 Rev B)
0.70 ±0.05
5.50 ±0.05
(2 SIDES)
4.10 ±0.05
(2 SIDES)
3.60 REF
3.45 ±0.05
(2 SIDES)
7.13 ±0.05
PACKAGE
OUTLINE
0.20 ±0.05
0.40 BSC
6.80 REF (2 SIDES)
8.10 ±0.05 (2 SIDES)
9.50 ±0.05 (2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
0.75 ±0.05
5.00 ±0.10
3.60 REF
(2 SIDES)
55 56
0.00 – 0.05
0.40 ±0.10
PIN 1
TOP MARK
1
2
(SEE NOTE 6)
9.00 ±0.10
(2 SIDES)
6.80 REF
7.13 ±0.10
3.45 ±0.10
(UHH) QFN 0515 REV B
0.200 REF
0.20 ±0.05
0.40 BSC
BOTTOM VIEW—EXPOSED PAD
R = 0.10
TYP
0.200 REF
0.00 – 0.05
0.75 ±0.05
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
3. ALL DIMENSIONS ARE IN MILLIMETERS
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
8500fb
24
For more information www.linear.com/LT8500
LT8500
revision hisTory
REV
DATE
12/15 Added TJ Package.
Clarified Pin Functions to include TJ Package.
DESCRIPTION
PAGE NUMBER
A
2, 23
6
Added UHH Package Not Recommended for New Designs.
06/16 Clarified Setting Dot Correction section
24
18
18
B
Clarified Status Frame Information section pin functions to include TJ package
8500fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
25
LT8500
Typical applicaTion
Single LT8500 Driving 48 Resistor Ballasted LED Strings Froꢁ a VDD Rail
V
DD
12V
HOST
V
DD
3.0V TO 5.5V
SCKI
SDI
LDIBLANK
PWM1
M1
V
CC
•
•
•
•
•
•
•
•
•
•
LT8500
PWMCK
OK TO FLOAT
PWMCK
OPENLED
CMLDM7003
M48
PWM48
SCKO
SDO
GND
8500 TA08
OK TO
FLOAT
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
= 6V, V
LT3746
55V, 1MHz 32-Channel Full Featured 30mA Step-Down LED Driver V
= 55V, V
= 13V, Dimming = 5,000:1
IN(MIN)
IN(MAX)
SD
OUT(MAX)
True Color PWM, I < 1µA, Package 5mm × 9mm QFN-56
LT3595/
LT3595A
45V, 2.5MHz 16-Channel, 50mA Full Featured Boost LED Driver
V
= 4.5V, V
= 45V, V
SD
= 45V, Dimming =
IN(MIN)
IN(MAX)
OUT(MAX)
5,000:1 True Color PWM, I < 1µA, Package 5mm × 9mm QFN-56
LT3754
LT3598
LT3599
60V, 1MHz Boost 16-Channel, 50mA LED Driver with True Color
3,000:1 PWM Dimming and 2ꢀ Current Matching
V
= 4.5V, V
= 40V, V
SD
= 60V, Dimming =
IN(MIN)
IN(MAX)
OUT(MAX)
3,000:1 True Color PWM, I < 1µA, Package 5mm × 5mm QFN-32
44V, 1.5A, 2.5MHz Boost 6-Channel, 30mA LED Driver
V
= 3V, V
= 30V(40V
SD
), V
= 44V, Dimming =
IN(MIN)
IN(MAX)
MAX
OUT(MAX)
1,000:1 True Color PWM, I < 1µA, Package 4mm × 4mm QFN-24
44V, 2A, 2.5MHz Boost 4-Channel, 120mA LED Driver
V
= 3V, V
= 30V(40V
SD
), V
MAX
= 44V, Dimming =
IN(MIN)
IN(MAX)
OUT(MAX)
1,000:1 True Color PWM, I < 1µA, Package 4mm × 4mm QFN-24
8500fb
LT 0616 REV B • PRINTED IN USA
26 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2011
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LT8500
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