LT8570_技术文档

LT8570/LT8570-1

Boost/SEPIC/Inverting

DC/DC Converter with 65V

Switch, Soft-Start and Synchronization

FeaTures

DescripTion

The LT^®8570 and LT8570-1 are PWM DC/DC converters.

n

65V Power Switch

n

Current Limit Options of 0.5A (LT8570) or 0.25A

(LT8570-1)

The LT8570 contains a 0.5A, 65V power switch, while

the LT8570-1 contains a 0.25A, 65V power switch. The

LT8570andLT8570-1canbeconfiguredaseitheraboost,

SEPIC or inverting converter.

n

Adjustable Switching Frequency

Single Feedback Resistor Sets V

OUT

Synchronizable to External Clock

High Gain SHDN Pin Accepts Slowly Varying

Input Signals

The LT8570/LT8570-1 have an adjustable oscillator, set

by a resistor from the RT pin to ground. Additionally, the

LT8570/LT8570-1 can be synchronized to an external

clock. The switching frequency of the part may be free

running or synchronized, and can be set between 200kHz

and 1.5MHz.

n

Wide Input Voltage Range: 2.55V to 40V

Low V

Switch

CESAT

Integrated Soft-Start Function

Easily Configurable as a Boost, SEPIC, or Inverting

Converter

The LT8570/LT8570-1 also feature innovative SHDN pin

circuitry that allows for slowly varying input signals and

an adjustable undervoltage lockout function.

n

User Configurable Undervoltage Lockout (UVLO)

Pin Compatible with LT3580 and LT8580

Tiny Thermally Enhanced 8-Lead 3mm × 3mm DFN

and 8-Lead MSOP Packages

Additional features such as frequency foldback and soft-

start are integrated. The LT8570/LT8570-1 are available

in tiny thermally enhanced 3mm × 3mm 8-lead DFN and

8-lead MSOP packages.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners. Protected by U.S. Patents, including 7579816.

applicaTions

n

VFD Bias Supplies

n

TFT-LCD Bias Supplies

n

GPS Receivers

DSL Modems

Local Power Supply

n

Typical applicaTion

Efficiency and Power Loss

1.5MHz, 5V to 12V Boost Converter

100

90

80

70

60

50

40

30

20

320

280

240

200

160

120

80

22µH

V

OUT

V

IN

12V

5V

125mA

10k

V

IN

SW

FBX

VC

130k

SHDN

2.2µF

LT8570

1µF

SYNC

RT

6.19k

2.2nF

GND SS

47pF

EFFICIENCY

40

POWER LOSS

56.2k

0.1µF

0

125

8570 TA01a

0

25

50

LOAD CURRENT (mA)

75

100

8570 TA01b

85701f

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LT8570/LT8570-1

absoluTe MaxiMuM raTings ^{(Note 1)}

V Voltage.................................................–0.3V to 40V

SYNC Voltage............................................–0.3V to 5.5V

Operating Junction Temperature Range

IN

SW Voltage ................................................–0.4V to 65V

RT Voltage ...................................................–0.3V to 5V

SS Voltage ................................................–0.3V to 2.5V

FBX Voltage.................................................................5V

FBX Current............................................................–1mA

VC Voltage ...................................................–0.3V to 2V

SHDN Voltage ............................................–0.3V to 40V

LT8570E, LT8570-1E (Notes 2, 5) ......–40°C to 125°C

LT8570I, LT8570-1I (Notes 2, 5) ........–40°C to 125°C

Storage Temperature Range ..............–65°C to 150°C

Lead Temperature (Soldering, 10 sec)

MS8E Package Only..........................................300°C

pin conFiguraTion

TOP VIEW

FBX

VC

1

2

3

4

8

7

6

5

SYNC

SS

FBX

VC

1

2

3

4

8 SYNC

7 SS

9

GND

9

GND

6

5

V

IN

RT

SHDN

V

IN

RT

SW

SHDN

MS8E PACKAGE

8-LEAD PLASTIC MSOP

DD PACKAGE

8-LEAD (3mm × 3mm) PLASTIC DFN

θ

= 35°C/W TO 40°C/W

JA

EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB

θ

= 43°C/W

JA

EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB

orDer inForMaTion

LEAD FREE FINISH

TAPE AND REEL

PART MARKING*

LGRY

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LT8570EDD#PBF

LT8570EDD#TRPBF

LT8570IDD#TRPBF

LT8570EMS8E#TRPBF

LT8570IMS8E#TRPBF

LT8570EDD-1#TRPBF

LT8570IDD-1#TRPBF

8-Lead (3mm × 3mm) Plastic DFN

8-Lead Plastic MSOP

–40°C to 125°C

LT8570IDD#PBF

LGRY

LT8570EMS8E#PBF

LT8570IMS8E#PBF

LT8570EDD-1#PBF

LT8570IDD-1#PBF

LT8570EMS8E-1#PBF

LT8570IMS8E-1#PBF

LTGRZ

8-Lead Plastic MSOP

LGSB

8-Lead (3mm × 3mm) Plastic DFN

8-Lead Plastic MSOP

LGSB

LT8570EMS8E-1#TRPBF LTGSC

LT8570IMS8E-1#TRPBF LTGSC

8-Lead Plastic MSOP

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

85701f

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LT8570/LT8570-1

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 5V, V_SHDN= V_INunless otherwise noted. (Note 2)

PARAMETER

CONDITIONS

MIN

2.55

1.185

–3

81

TYP

MAX

40

1.220

12

85

86

UNITS

V

l

Operating Voltage Range

Positive Feedback Voltage

Negative Feedback Voltage

Positive FBX Pin Bias Current

Negative FBX Pin Bias Current

Error Amplifier Transconductance

Error Amplifier Voltage Gain

Quiescent Current

1.204

3

83.3

200

60

1.2

0

0.01

V

mV

µA

V

= Positive Feedback Voltage, Current Into Pin

= Negative Feedback Voltage, Current Out of Pin

FBX

µA

FBX

µmhos

V/V

mA

µA

V

= 2.5V, Not Switching

= 0V

1.7

1

0.05

SHDN

Quiescent Current in Shutdown

Reference Line Regulation

SHDN

2.55V ≤ V ≤ 40V

%/V

IN

l

Switching Frequency, f

R = 56.2k

T

1.23

165

1.5

200

1.77

235

MHz

kHz

OSC

T

R = 422k

Switching Frequency in Foldback

Switching Frequency Set Range

SYNC High Level for Synchronization

SYNC Low Level for Synchronization

SYNC Clock Pulse Duty Cycle

Compared to Normal f

SYNCing or Free Running

1/6

Ratio

kHz

V

OSC

l

200

1.3

1500

0.4

65

V

%

V

SYNC

= 0V to 2V

35

Recommended Minimum SYNC Ratio

SYNC OSC

3/4

f

/f

Minimum Off-Time

Minimum On-Time

Switch Current Limit

100

0.75

0.5

0.4

ns

A

l

Minimum Duty Cycle (Note 3), LT8570

Maximum Duty Cycle (Notes 3, 4), LT8570, f

0.6

0.27

0.15

1

0.85

0.8

= 1.5MHz

= 200kHz

OSC

l

Minimum Duty Cycle (Note 3), LT8570-1

Maximum Duty Cycle (Notes 3, 4), LT8570-1, f

0.3

0.15

0.075

0.375

0.25

0.2

0.5

0.43

0.4

A

= 1.5MHz

= 200kHz

OSC

Switch V

I

V

= 0.4A (LT8570)

= 0.2A (LT8570-1)

250

0.01

6

mV

µA

CESAT

SW

Switch Leakage Current

Soft-Start Charging Current

= 5V

= 0.5V

1

8

SW

SS

l

4

µA

l

SHDN Minimum Input

Voltage High

Active Mode, SHDN Rising

Active Mode, SHDN Falling

1.23

1.21

1.31

1.27

1.4

1.33

V

SHDN Minimum Input Voltage Hysteresis

SHDN Input Voltage Low

40

mV

V

l

Shutdown Mode

0.3

SHDN Pin Bias Current

V

SHDN

V

SHDN

V

SHDN

= 3V

= 1.3V

= 0V

44

12

0

56

15

0.1

µA

9

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

junction temperature range. Operating lifetime is derated at junction

temperatures greater than 125°C.

Note 3: Current limit guaranteed by design and/or correlation to static test.

Note 4: Current limit measured at equivalent of listed switching frequency.

Note 2: The LT8570E/LT8570-1E are guaranteed to meet performance

specifications from 0°C to 125°C junction temperature. Specifications over

the –40°C to 125°C operating junction temperature range are assured by

design, characterization and correlation with statistical process controls. The

LT8570I/LT8570-1I are guaranteed over the full –40°C to 125°C operating

Note 5: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

85701f

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LT8570/LT8570-1

Typical perForMance characTerisTics ^T_A^{= 25°C, unless otherwise specified}

Maximum Switch Current vs SS

Switch Current Limit vs Duty Cycle

Switch Saturation Voltage

1.0

0.8

0.6

0.4

0.2

0.0

1.00

0.75

0.50

0.25

0

700

600

500

400

300

200

100

0

LT8570

LT8570-1

LT8570, 1.5MHz

LT8570, 200kHz

LT8570

LT8570-1

LT8570-1, 1.5MHz

LT8570-1, 200kHz

0

0.4

0.6

0.8

1

1.2

0.2

60 70

10 20 30 40 50

DUTY CYCLE (%)

80 90

0

0.2

0.4

0.6

0.8

SS VOLTAGE (V)

SWITCH CURRENT (A)

8570 G03

8570 G01

8570 G02

Switch Current Limit

vs Temperature

Positive and Negative Output

Voltage Regulation

1.0

0.8

1.220

1.215

1.210

1.205

1.200

1.195

1.190

1.185

1.180

1.175

1.170

30

25

20

15

10

5

0.6

0.4

0.2

0

–5

–10

–15

–20

LT8570

LT8570-1

0.0

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

8570 G04

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

8570 G05

Positive and Negative FBX Current

at Output Voltage Regulation

Oscillator Frequency

86

85

84

83

82

81

80

86

85

84

83

82

81

80

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

R

= 56.2k

T

R

T

= 422k

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

–50 –25

25 50 75

125

100 150

0

TEMPERATURE (°C)

8570 G06

8570 G07

85701f

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LT8570/LT8570-1

Typical perForMance characTerisTics ^T_A^{= 25°C, unless otherwise specified}

Oscillator Frequency During

Soft-Start

Internal UVLO

SHDN Pin Current

2.7

2.6

2.5

2.4

2.3

2.2

2.1

30

25

1

125°C

25°C

–40°C

20

15

1/2

1/3

1/4

1/5

1/6

10

5

INVERTING

NONINVERTING

CONFIGURATIONS CONFIGURATIONS

0

0.2 0.4 0.6 0.8

FBX VOLTAGE (V)

1

1.2

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

0

0.25 0.5 0.75

1

1.25 1.5 1.75

2

SHDN VOLTAGE (V)

8570 G08

8570 G09

8570 G10

SHDN Pin Current

Active/Lockout Threshold

Minimum On-Time vs Temperature

280

240

200

160

120

80

400

350

300

250

200

150

100

50

1.40

1.38

1.36

1.34

1.32

1.30

1.28

1.26

1.24

1.22

1.20

125°C

25°C

–40°C

RECOMMENDED MINIMUM ON-TIME

SHDN RISING

SHDN FALLING

MEASURED MINIMUM ON-TIME

40

0

5

10 15 20 25 30 35 40

SHDN VOLTAGE (V)

8570 G11

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

8570 G13

8570 G12

85701f

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LT8570/LT8570-1

pin FuncTions

FBX (Pin 1): Positive and Negative Feedback Pin. For a

RT (Pin 6): Timing Resistor Pin. Adjusts the switching

frequency. Place a resistor from this pin to ground to set

the frequency to a fixed free running level. Do not float

this pin.

noninverting or inverting converter, tie a resistor from

the FBX pin to V

according to the following equations:

OUT

V

−1.204V

(

)

OUT

R_FBX

=

; Noninverting Converter

SS(Pin7):Soft-StartPin.Placeasoft-startcapacitorhere.

Upon start-up, the SS pin will be charged by a (nominally)

280k resistor to about 2.1V.

83.3µA

+ 3mV

V

(

)

; InvertingConverter

OUT

R_FBX

83.3µA

SYNC (Pin 8): To synchronize the switching frequency to

an outside clock, simply drive this pin with a clock. The

high voltage level of the clock needs to exceed 1.3V, and

the low level should be less 0.4V. Drive this pin to less

than 0.4V to revert to the internal free-running clock. See

theApplicationsInformationsectionformoreinformation.

VC (Pin 2): Error Amplifier Output Pin. Tie external com-

pensation network to this pin.

V (Pin 3): Input Supply Pin. Must be locally bypassed.

IN

SW (Pin 4): Switch Pin. This is the collector of the internal

NPN Power switch. Minimize the metal trace area connec-

ted to this pin to minimize EMI.

GND (Exposed Pad Pin 9): Ground. Exposed pad must

be soldered directly to local ground plane.

SHDN (Pin 5): Shutdown Pin. In conjunction with the

UVLO (undervoltage lockout) circuit, this pin is used

to enable/disable the chip and restart the soft-start

sequence. Drive below 1.21V to disable the chip. Drive

above 1.40V to activate the chip and restart the soft-start

sequence. Do not float this pin.

85701f

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LT8570/LT8570-1

block DiagraM

R

C

V

IN

C

SS

C

IN

7

2

50k

SS

VC

SHDN

5

–

+

DISCHARGE

DETECT

L1

1.3V

280k

D1

SW

UVLO

SR2

VC

I

SOFT-

START

4

V

OUT

R

COMPARATOR

LIMIT

SR1

S

Q2

Q

–

+

DRIVER

C1

V

IN

S

A3

R

Q

Q1

1.204V

REFERENCE

3

+

–

+

R

FBX

0.04Ω (LT8570)

14.5k

A4

∑

A1

A2

0.08Ω (LT8570-1)

–

SLOPE

COMPENSATION

GND

FBX

9

1

+

–

÷N

FREQUENCY

FOLDBACK

ADJUSTABLE

OSCILLATOR

14.5k

SYNC

BLOCK

SYNC

RT

8

6

R

T

8570 BD

85701f

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LT8570/LT8570-1

operaTion

The LT8570/LT8570-1 use a constant-frequency, current

mode control scheme to provide excellent line and load

regulation. Refer to the Block Diagram for the following

description of the part’s operation. At the start of each

oscillator cycle, the SR latch (SR1) is set, which turns on

the power switch, Q1. The switch current flows through

the internal current sense resistor, generating a voltage

proportional to the switch current. This voltage (amplified

by A4) is added to a stabilizing ramp and the resulting sum

isfedintothepositiveterminalofthePWM comparatorA3.

Whenthisvoltageexceedsthelevelatthenegativeinputof

A3, the SR latch is reset, turning off the power switch. The

level at the negative input of A3 (VC pin) is set by the error

amplifier A1 (or A2) and is simply an amplified version of

the difference between the feedback voltage (FBX pin) and

the reference voltage (1.204V or 3mV, depending on the

configuration). In this manner, the error amplifier sets the

correct peak current level to keep the output in regulation.

down to 3mV by the R

to FBX. Amplifier A1 becomes inactive and amplifier A2

performs the noninverting amplification from FBX to VC.

resistor connected from V

FBX OUT

SEPIC Topology

As shown in Figure 1, the LT8570/LT8570-1 can be

configured as a SEPIC (single-ended primary inductance

converter). This topology allows for the input to be higher,

equal, or lower than the desired output voltage. Output

disconnect is inherently built into the SEPIC topology,

meaning no DC path exists between the input and output.

This is useful for applications requiring the output to be

disconnected from the input source when the circuit is

in shutdown.

Inverting Topology

The LT8570/LT8570-1 can also work in a dual induc-

tor inverting topology, as shown in Figure 2. The part’s

unique feedback pin allows for the inverting topology to

be built by simply changing the connection of external

components. This solution results in very low output

voltage ripple due to the inductor L2 in series with the

output. Abrupt changes in output capacitor current are

eliminated because the output inductor delivers current

to the output during both the off-time and the on-time of

the LT8570/LT8570-1 switch.

TheLT8570/LT8570-1haveanFBXpinarchitecturethatcan

beusedforeithernoninvertingorinvertingconfigurations.

When configured as a noninverting converter, the FBX pin

is pulled up to the internal bias voltage of 1.204V by the

R

FBX

resistor connected from V

to FBX. Amplifier A2

OUT

becomes inactive and amplifier A1 performs the inverting

amplificationfromFBXtoVC.WhentheLT8570/LT8570-1

are in an inverting configuration, the FBX pin is pulled

C2

L1

D1

L1

L2

V

> V

= V

< V

IN

OUT

OR

OUT

OR

•

V

IN

V

OUT

IN

V

SW

V

SW

IN

L2

D1

+

OUT

C1

LT8570/LT8570-1

C1

LT8570/LT8570-1

•

R1

SHDN

RT

SYNC

FBX

SHUTDOWN

SHDN

RT

FBX

SHUTDOWN

+

GND

VC

SS

GND

VC

SS

C3

+

SYNC

R

C

R

C

R

T

R

T

C

SS

C

SS

C

8570 F01

8570 F02

Figure 1. SEPIC Topology Allows for the Input to Span

the Output Voltage. Coupled or Uncoupled Inductors

Can Be Used. Follow Noted Phasing if Coupled

Figure 2. Dual Inductor Inverting Topology Results in

Low Output Ripple. Coupled or Uncoupled Inductors

Can Be Used. Follow Noted Phasing if Coupled

85701f

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LT8570/LT8570-1

operaTion

Start-Up Operation

duty cycle that the part can achieve thus allowing better

control of the switch current during start-up. When the

FBXvoltageispulledoutsideofthisrange,theswitching

frequency returns to normal.

Several functions are provided to enable a very clean

start-up for the LT8570/LT8570-1.

•ꢀ First, the SHDN pin voltage is monitored by an internal

voltage reference to give a precise turn-on voltage level.

Anexternalresistor(orresistordivider)canbeconnected

from the input power supply to the SHDN pin to provide

a user-programmable undervoltage lockout function.

Current Limit and Thermal Shutdown Operation

The LT8570/LT8570-1 have a current limit circuit not

shown in the Block Diagram. The switch current is con-

stantlymonitoredandnotallowedtoexceedthemaximum

switch current at a given duty cycle (see the Electrical

Characteristics table). If the switch current reaches this

value, the SR latch (SR1) is reset regardless of the state

of the comparator (A1/A2). Also, not shown in the Block

Diagramisthethermalshutdowncircuit.Ifthetemperature

of the part exceeds approximately 165°C, the SR2 latch is

set regardless of the state of the amplifier (A1/A2). When

the part temperature falls below approximately 160°C, a

full soft-start cycle will then be initiated. The current limit

and thermal shutdown circuits protect the power switch

as well as the external components connected to the

LT8570/LT8570-1.

•ꢀ Second, the soft-start circuitry provides for a gradual

ramp-up of the switch current. When the part is brought

out of shutdown, the external SS capacitor is first

discharged (providing protection against SHDN pin

glitches and slow ramping), then an integrated 280k

resistor pulls the SS pin up to ~2.1V. By connecting an

external capacitor to the SS pin, the voltage ramp rate

on the pin can be set. Typical values for the soft-start

capacitor range from 100nF to 1µF.

•ꢀ Finally,thefrequencyfoldbackcircuitreducestheswitch-

ing frequency when the FBX pin is in a nominal range

of 300mV to 920mV. This feature reduces the minimum

85701f

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LT8570/LT8570-1

applicaTions inForMaTion

Setting Output Voltage

For the SEPIC or dual inductor inverting topology (see

Figure 1 and Figure 2):

The output voltage is set by connecting a resistor (R

)

FBX

V_D+ |V_OUT

|

from V

to the FBX pin. R

is determined from the

OUT

FBX

DC ≅

following equation:

V + |V | + V_D− V

IN

OUT

CESAT

|V_OUT− V

|

FBX

R_FBX

=

The LT8570/LT8570-1 can be used in configurations

where the duty cycle is higher than DC , but it must be

83.3µA

MAX

operated in the discontinuous conduction mode so that

where V is 1.204V (typical)for noninverting topologies

FBX

the effective duty cycle is reduced.

(i.e., boost and SEPIC regulators) and 3mV (typical) for

inverting topologies (see the Electrical Characteristics).

Inductor Selection

Power Switch Duty Cycle

General Guidelines: The high frequency operation of the

LT8570/LT8570-1allowsfortheuseofsmallsurfacemount

inductors. For high efficiency, choose inductors with high

frequency core material, such as ferrite, to reduce core

losses. To improveefficiency, chooseinductorswithmore

volume for a given inductance. The inductor should have

In order to maintain loop stability and deliver adequate

current to the load, the power NPN (Q1 in the Block Dia-

gram) cannot remain “on” for 100% of each clock cycle.

The maximum allowable duty cycle is given by:

2

(T_P− MinOffTime)

lowDCR(copperwireresistance)toreduceI Rlosses,and

DC_MAX

=

• 100%

must be able to handle the peak inductor current without

saturating. Note that in some applications, the current

handling requirements of the inductor can be lower, such

asintheSEPICtopology, whereeachinductoronlycarries

a fraction of the total switch current. Multilayer or chip

inductors usually do not have enough core area to sup-

port peak inductor currents in the 0.25A to 1A range. To

minimize radiated noise, use a toroidal or shielded induc-

tor. Note that the inductance of shielded types will drop

more as current increases, and will saturate more easily.

See Table 1 for a list of inductor manufacturers. Thorough

lab evaluation is recommended to verify that the following

guidelines properly suit the final application.

T_P

where T is the clock period and Min Off Time (found in

P

the Electrical Characteristics) is typically 100ns.

The application should be designed so that the operating

duty cycle does not exceed DC

.

MAX

The minimum allowable duty cycle is given by:

MinOn Time

DC_MIN

=

•100%

T_P

where T is the clock period and Min On-Time is as shown

P

in the Typical Performance Characteristics.

The application should be designed so that the operating

Table 1. Inductor Manufacturers

duty cycle is at least DC

.

MIN

Coilcraft

LPS5030, MSS7341, LPS4018,

LPD6235 and LPD5030 Series

www.coilcraft.com

Duty cycle equations for several common topologies are

given below, where V is the diode forward voltage drop

Coiltronics DR, DRQ, SD and SDQ Series

www.coiltronics.com

www.sumida.com

D

Sumida

CDRH8D58/LD, CDRH64B, and

CDRH70D430MN Series

and V

is typically 250mV at 0.4A for the LT8570 and

250mV at 0.2A for the LT8570-1.

CESAT

Würth

WE-PD, WE-DD, WE-TPC,

WE-LHMI and WE-LQS Series

www.we-online.com

For the boost topology:

V_OUT− V + V_D

V_OUT+ V_D− V_CESAT

Minimum Inductance: Although there can be a trade-off

with efficiency, it is often desirable to minimize board

space by choosing smaller inductors. When choosing

an inductor, there are two conditions that limit the mini-

IN

DC ≅

mum inductance: (1) providing adequate load current,

85701f

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LT8570/LT8570-1

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and (2) avoiding subharmonic oscillation. Choose an

inductance that is high enough to meet both of these

requirements.

is greater than 50%, provided that the inductance exceeds

a minimum value. In applications that operate with duty

cycles greater than 50%, the inductance must be at least:

V

2i DC −1

Adequate Load Current : Small value inductors result in

increased ripple currents and thus, due to the limited peak

switch current, decrease the average current that can be

IN

L_MIN

>

i

k_SC•(DC− 300ns • f) • f 1− DC

for boost topologies (see Figure 15)

L

MIN

= L1

provided to a load (I ). In order to provide adequate

OUT

load current, L should be at least:

L

= L1 = L2 for coupled dual inductor topologies

(see Figure 16 and Figure 17)

MIN

DC • V

IN

L_BOOST

>

⎛

⎜

⎝

⎞

|V_OUT| •I_OUT

||

L

= L1 L2 for uncoupled dual inductor topologies

(see Figure 16 and Figure 17)

MIN

2 • f • I_LIM

−

⎟

V • η

⎠

IN

k

SC

= 0.6 for LT8570 and 0.3 for LT8570-1

for boost, topologies, or:

Maximum Inductance: Excessive inductance can reduce

currentrippletolevelsthataredifficultforthecurrentcom-

parator (A3 in the Block Diagram) to cleanly discriminate,

thus causing duty cycle jitter and/or poor regulation. The

maximum inductance can be calculated by:

DC • V

IN

L_DUAL

>

⎛

⎞

V_OUT•I_OUT

2 • f • I_LIM

−

− I_OUT

⎜

⎟

V • η

⎝

⎠

IN

for the SEPIC and inverting topologies.

where:

V − V

I_MIN-RIPPLE

DC

f

IN

CESAT

L_MAX

=

•

L

= L1 for boost topologies (see Figure 15)

BOOST

where

= L1 = L2 for coupled dual inductor topologies

(see Figure 16 and Figure 17)

DUAL

for boost topologies (see Figure 15)

L

= L1

MIN

= L1 = L2 for coupled dual inductor topologies

(see Figure 16 and Figure 17)

L

DUAL

= L1||L2 for uncoupled dual inductor topologies

(see Figure 16 and Figure 17)

MIN

||

L

= L1 L2 for uncoupled dual inductor topologies

DC = switch duty cycle (see previous section)

MIN

(see Figure 16 and Figure 17)

I

= switch current limit, typically about 0.6A for

LIM

I

= typically 40mA for LT8570 and 20mA for

LT8570 and 0.3A for LT8570-1 at 50% duty cycle (see

MIN-RIPPLE

LT8570-1

the Typical Performance Characteristics section).

Current Rating: Finally, the inductor(s) must have a rating

greater than its peak operating current to prevent inductor

saturation resulting in efficiency loss. In steady state, the

peakinputinductorcurrent(continuousconductionmode

only) is given by:

h =powerconversionefficiency(typically85%forboost

and 83% for dual inductor topologies at high currents).

f = switching frequency

I

= maximum load current

OUT

Negative values of L indicate that the output load current

OUT

LT8570/LT8570-1.

|V_OUT•I_OUT

|

V • DC

2 • L1• f

IN

I_L1-PEAK

=

+

I

exceeds the switch current limit capability of the

V • η

IN

fortheboost,SEPICanddualinductorinvertingtopologies.

Avoiding Subharmonic Oscillations: The LT8570/

LT8570-1’sinternalslopecompensationcircuitcanprevent

subharmonicoscillationsthatcanoccurwhenthedutycycle

85701f

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For uncoupled dual inductor topologies, the peak output

inductor current is given by:

Table 2. Ceramic Capacitor Manufacturers

Kemet

www.kemet.com

Murata

Taiyo Yuden

TDK

www.murata.com

www.t-yuden.com

www.tdk.com

V_OUT• 1− DC

(

)

I_L2-PEAK=I_OUT

+

2 • L2 • f

For the coupled inductor topologies:

Compensation—Adjustment

⎡

⎤

⎢V_OUT

⎪

V • DC

2 • L • f

IN

To compensatethefeedbackloopoftheLT8570/LT8570-1,

a series resistor-capacitor network in parallel with a single

capacitor should be connected from the VC pin to GND.

For most applications, the series capacitor should be in

the range of 470pF to 2.2nF with 1nF being a good start-

ing value. The parallel capacitor should range in value

from 10pF to 100pF with 47pF a good starting value. The

I_L2-PEAK= I_OUT1+

+

⎢

⎥

η • V

IN

⎣

⎦

Note:Inductorcurrentcanbehigherduringloadtransients.

Itcanalsobehigherduringstart-upifinadequatesoft-start

capacitance is used.

Capacitor Selection

compensation resistor, R , is usually in the range of 5k to

C

Low ESR (equivalent series resistance) capacitors should

beusedattheoutputtominimizetheoutputripplevoltage.

Multilayer ceramic capacitors are an excellent choice, as

they have an extremely low ESR and are available in very

small packages. X5R or X7R dielectrics are preferred, as

these materials retain their capacitance over wider voltage

and temperature ranges. For LT8570, a 0.22µF to 4.7µF

and for LT8570-1, a 0.1µF to 2.2µF output capacitor is

sufficient for most applications. Always use a capacitor

with a sufficient voltage rating. Although many ceramic

capacitorshavegreatlyreducedcapacitanceatthedesired

output voltage, ceramic capacitors with larger case sizes

are less sensitive to applied voltage. Solid tantalum or

OS-CON capacitors can be used, but they will occupy

more board area than a ceramic and will have a higher

ESR with greater output ripple.

50k. A good technique to compensate a new application

is to use a 100kΩ potentiometer in place of series resis-

tor R . With the series capacitor and parallel capacitor at

C

1nF and 47pF respectively, adjust the potentiometer while

observing the transient response and the optimum value

for R can be found. Figure 3 (3a to 3c) illustrates this pro-

C

cess for the circuit of Figure 4 with a load current stepped

between 30mA and 90mA. Figure 3a shows the transient

response with R equal to 1.04k. The phase margin is

C

poor, as evidenced by the excessive ringing in the output

voltage and inductor current. In Figure 3b, the value of

R is increased to 2.09k, which results in a more damped

C

response.Figure3cshowstheresultswhenR isincreased

C

further to 6.19k. The transient response is nicely damped

and the compensation procedure is complete.

Ceramic capacitors also make a good choice for the input

decoupling capacitor, which should be placed as closely

Compensation—Theory

Like all other current mode switching regulators, the

LT8570/LT8570-1 need to be compesated for stable and

efficient operation. Two feedback loops are used in the

LT8570/LT8570-1 — a fast current loop which does not

require compensation, and a slower voltage loop which

does. Standard bode plot analysis can be used to under-

stand and adjust the voltage feedback loop.

as possible to the V pin of the LT8570/LT8570-1 as well

IN

as to the inductor connected to the input of the power

path. If it is not possible to optimally place a single input

capacitor, thenuseone attheV pinofthechip (C )and

IN

VIN

one at the V side of the inductor (C

). See equations

IN

PWR

in Table 4, Table 5 and Table 6 for sizing information. For

LT8570, a 0.47µF to 1µF and for LT8570-1, a 0.22µF to

0.47µF input capacitor is sufficient for most applications.

Table 2 shows a list of several ceramic capacitor manu-

facturers. Consultthemanufacturersfordetailedinforma-

tion on their entire selection of ceramic parts.

85701f

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LT8570/LT8570-1

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V

OUT

500mV/DIV

AC-COUPLED

I

STEP

50mA/DIV

I

L1

100mA/DIV

8570 F03a

8570 F03b

R

= 1.04k

50µs/DIV

R

C

= 2.09k

50µs/DIV

C

(3a) Transient Response Shows Excessive Ringing

(3b) Transient Response Is Better

V

OUT

500mV/DIV

AC-COUPLED

I

STEP

50mA/DIV

I

L1

100mA/DIV

8570 F03c

R

C

= 6.19k

50µs/DIV

(3c) Transient Response Is Well Damped

Figure 3. Transient Response

D1

22µH

V

OUT

V

IN

12V

5V

125mA

10k

V

SW

FBX

R

IN

FBX

130k

C

OUT

SHDN

2.2µF

C

IN

LT8570

1µF

SYNC

RT

VC

R

C

6.19k

GND SS

C

F

47pF

C

2.2nF

R

56.2k

SS

T

0.1µF

8570 F04

Figure 4. 1.5MHz, 5V to 12V Boost Converter

85701f

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LT8570/LT8570-1

applicaTions inForMaTion

As with any feedback loop, identifying the gain and phase

contribution of the various elements in the loop is critical.

Figure5showsthekeyequivalentelementsofaboostcon-

verter. Because of the fast current control loop, the power

stage of the IC, inductor and diode have been replaced by

a combination of the equivalent transconductance ampli-

From Figure 5, the DC gain, poles and zeros can be cal-

culated as follows:

DCGain:

(Breaking Loop at FBX Pin)

∂V_C∂I_VIN∂V_OUT∂V

FBX

fier g and the current controlled current source which

A_DC= A_OL(0) =

•

=

mp

∂V

∂V_C∂I_VIN∂V_OUT

FBX

converts I to (hV /V ) •ꢀI . g acts as a current

VIN

IN OUT

VIN mp

source where the peak input current, I , is proportional

VIN

⎛

⎞

V

V_OUT

R_L

2

0.5R2

R1+ 0.5R2

IN

g

• R • g_mp• η •

•

to the VC voltage. h is the efficiency of the switching

(

)

ma

0

⎜

⎟

⎝

⎠

regulator, and is typically about 85%.

2

Notethatthemaximumoutputcurrentsofg andg are

Output Pole: P1=

mp

ma

2 • π • R_L• C_OUT

finite.Thelimitsforg areintheElectricalCharacteristics

mp

section(switchcurrentlimit), andg isnominallylimited

ma

1

Error AmpPole: P2 =

Error Amp Zero: Z1=

ESR Zero: Z2 =

to about +15µA and –17µA.

2 • π • R +R • C

C

⎡

⎤

C ⎦

⎣ O

–

1

V

OUT

I

VIN

g

mp

2 • π • R_C• C_C

+

R

ESR

R

L

η• V

V_OUT

IN

1

•I_VIN

C

OUT

PL

2 • π • R_ESR• C_OUT

1.204V

REFERENCE

R1

+

–

V

²• R_L

C

IN

g

ma

RHP Zero: Z3 =

R2

2 • π • V_OUT²• L

FBX

R

O

C

8570 F05

F

C

f_S

HighFrequency Pole: P3 >

3

C : COMPENSATION CAPACITOR

C

: OUTPUT CAPACITOR

: PHASE LEAD CAPACITOR

OUT

1

PhaseLead Zero: Z4 =

PL

C : HIGH FREQUENCY FILTER CAPACITOR

2 • π • R1• C_PL

F

g

ma

g

mp

: TRANSCONDUCTANCE AMPLIFIER INSIDE IC

: POWER STAGE TRANSCONDUCTANCE AMPLIFIER

1

R : COMPENSATION RESISTOR

R : OUTPUT RESISTANCE DEFINED AS V

R : OUTPUT RESISTANCE OF g

R1, R2: FEEDBACK RESISTOR DIVIDER NETWORK

C

PhaseLeadPole: P4 =

Error Amp Filter Pole:

R2

2

DIVIDED BY I

LOAD(MAX)

L

OUT

R1•

O

ma

2 • π •

• C_PL

R

: OUTPUT CAPACITOR ESR

R2

R1+

2

ESR

η: CONVERTER EFFICIENCY (~85% AT HIGHER CURRENTS)

Figure 5. Boost Converter Equivalent Model

1

C_C

,C_F<

10

P5 =

R_C• R_O

R_C+R_O

2 • π •

• C_F

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The current mode zero (Z3) is a right-half plane zero

which can be an issue in feedback control design, but is

manageable with proper external component selection.

In Figure 6, the phase is –135° when the gain reaches 0dB

giving a phase margin of 45°. The crossover frequency is

17kHz, which is more than three times lower than the fre-

quencyoftheRHPzerotoachieveadequatephasemargin.

Using the circuit in Figure 4 as an example, Table 3 shows

the parameters used to generate the bode plot shown in

Figure 6.

Diode Selection

Schottkydiodes, withtheirlowforward-voltagedropsand

fast switching speeds, are recommended for use with the

140

120

100

80

0

–45

LT8570/LT8570-1. For applications where V (see Tables

R

PHASE

4, 5 and 6) < 40V, the Diodes, Inc. PD3S140 is a good

–90

choice. Where V > 40V, the Diodes Inc. DFLS1100 works

R

–135

–180

–225

–270

–315

–360

well. These diodes are rated to handle an average forward

60

45° AT

17kHz

current of 1A.

40

GAIN

100

20

Oscillator

0

TheoperatingfrequencyoftheLT8570/LT8570-1canbeset

by the internal free-running oscillator. When the SYNC pin

is driven low (< 0.4V), the frequency of operation is set by

aresistorfromRT toground. Aninternallytrimmedtiming

capacitor resides inside the IC. The oscillator frequency

is calculated using the following formula:

–20

10

1k

10k

100k

1M

FREQUENCY (Hz)

8570 F06

Figure 6. Bode Plot for Example Boost Converter

Table 3. Bode Plot Parameters

85.5

(R_T+ 1)

f_OSC

=

PARAMETER

VALUE

96

UNITS

W

COMMENT

Application Specific

Not Adjustable

Adjustable

R

C

L

2.2

10

µF

where f

is in MHz and R is in kΩ. Conversely, R

T

OUT

OSC

T

(in kΩ) can be calculated from the desired frequency

(in MHz) using:

R

mW

kW

pF

ESR

O

R

300

2200

47

C

85.5

f_OSC

R_T=

−1

pF

Optional/Adjustable

Adjustable

F

0

pF

PL

R

C

6.19

130

14.5

12

kW

V

Clock Synchronization

R1

R2

Adjustable

Not Adjustable

Application Specific

Not Adjustable

Application Specific

Adjustable

The operating frequency of the LT8570/LT8570-1 can be

synchronized to an external clock source. To synchronize

totheexternalsource, simplyprovideadigitalclocksignal

into the SYNC pin. The LT8570/LT8570-1 will operate at

the SYNC clock frequency. The LT8570/LT8570-1 will

revert to the internal free-running oscillator clock after

SYNC is driven low for a few free-running clock periods.

V

OUT

V

IN

5

V

g

ma

g

mp

L

200

7

µmho

mho

µH

22

f

S

1.5

MHz

85701f

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LT8570/LT8570-1

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Driving SYNC high for an extended period of time effec-

tively stops the operating clock and prevents latch SR1

from becoming set (see the Block Diagram). As a result,

theswitchingoperationoftheLT8570/LT8570-1willstop.

This capacitor is slowly charged to ~2.1V by an internal

280k resistor once the part is activated. SS pin voltages

below ~1.1V reduce the internal current limit. Thus, the

gradualrampingoftheSSvoltagealsograduallyincreases

the current limit as the capacitor charges. This, in turn,

allows the output capacitor to charge gradually toward its

final value while limiting the start-up current.

The duty cycle of the SYNC signal must be between 35%

and 65% for proper operation. Also, the frequency of the

SYNC signal must meet the following two criteria:

In the event of a commanded shutdown or lockout (SHDN

pin), internal undervoltage lockout (UVLO) or a thermal

lockout,thesoft-startcapacitorisautomaticallydischarged

to ~200mV before charging resumes, thus assuring that

the soft-start occurs after every reactivation of the chip.

(1) SYNC may not toggle outside the frequency range of

200kHz to 1.5MHz unless it is stopped low to enable

the free-running oscillator.

(2) The SYNC frequency can always be higher than the

free-runningoscillatorfrequency, f , butshouldnot

OSC

be less than 25% below f

.

Shutdown

OSC

The SHDN pin is used to enable or disable the chip. For

most applications, SHDN can be driven by a digital logic

source. Voltages above 1.4V enable normal active op-

eration. Voltages below 300mV will shutdown the chip,

resulting in extremely low quiescent current.

Operating Frequency Selection

There are several considerations in selecting the operat-

ing frequency of the converter. The first is staying clear

of sensitive frequency bands, which cannot tolerate any

spectral noise. For example, in products incorporating RF

communications, the 455kHz IF frequency is sensitive to

any noise, therefore switching above 600kHz is desired.

Some communications have sensitivity to 1.1MHz, and in

thatcase, a1.5MHzswitchingconverterfrequencymaybe

employed. The second consideration is the physical size

of the converter. As the operating frequency goes up, the

inductor and filter capacitors go down in value and size.

The trade-off is efficiency, since the switching losses due

to NPN base charge (see Thermal Calculations), Schottky

diode charge, and other capacitive loss terms increase

proportionally with frequency.

While the SHDN voltage transitions through the lockout

voltagerange(0.3Vto1.21V)thepowerswitchisdisabled

and the SR2 latch is set (see the Block Diagram). This

causesthesoft-startcapacitortobegindischarging,which

continues until the capacitor is discharged and active op-

eration is enabled. Although the power switch is disabled,

SHDN voltages in the lockout range do not necessarily

reduce quiescent current until the SHDN voltage is near

or below the shutdown threshold.

Also note that SHDN can be driven above V or V

as

OUT

IN

long as the SHDN voltage is limited to less than 40V.

Soft-Start

ACTIVE

(NORMAL OPERATION)

The LT8570/LT8570-1 contain a soft-start circuit to limit

peak switch currents during start-up. High start-up cur-

rent is inherent in switching regulators in general since

1.40V

(HYSTERESIS AND TOLERANCE)

1.21V

LOCKOUT

the feedback loop is saturated due to V

being far from

OUT

(POWER SWITCH OFF,

its final value. The regulator tries to charge the output

capacitor as quickly as possible, which results in large

peak currents.

SS CAPACITOR DISCHARGED)

0.3V

SHUTDOWN

(LOW QUIESCENT CURRENT)

0.0V

8570 F07

The start-up current can be limited by connecting an

external capacitor (typically 100nF to 1µF) to the SS pin.

Figure 7. Chip States vs SHDN Voltage

85701f

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Configurable Undervoltage Lockout

For example, to disable the LT8570/LT8570-1 for V

IN

voltages below 3.5V using the single resistor configura-

Figure 8 shows how to configure an undervoltage lockout

(UVLO)fortheLT8570/LT8570-1. Typically, UVLOisused

in situations where the input supply is current-limited,

has a relatively high source resistance, or ramps up/down

slowly. A switching regulator draws constant power from

the source, so source current increases as source voltage

drops. This looks like a negative resistance load to the

source and can cause the source to current-limit or latch

low under low source voltage conditions. UVLO prevents

the regulator from operating at source voltages where

these problems might occur.

tion, choose:

3.5V −1.27V

R_UVLO1

=

= 187k

1.27V

⎛

⎞

+ 12µA

⎜

⎝

⎟

⎠

∞

To activate the LT8570/LT8570-1 for V voltages greater

IN

than 4.5V using the double resistor configuration, choose

R

= 10k and:

UVLO2

4.5V − 1.31V

R_UVLO1

=

= 22.1k

1.31V

⎛

⎞

+ 12µA

⎜

⎝

⎟

⎠

The shutdown pin comparator has voltage hysteresis with

typicalthresholdsof1.31V(rising)and1.27V(falling). Re-

10k

sistorR

isoptional.R

canbeincludedtoreduce

UVLO2

Internal Undervoltage Lockout

The LT8570/LT8570-1 monitor the V supply voltage in

the overall UVLO voltage variation caused by variations

IN

in SHDN pin current (see the Electrical Characteristics).

A good choice for R

value for R

of the following:

caseV dropsbelowaminimumoperatinglevel(typically

IN

is ≤10k 1%. After choosing a

can be determined from either

UVLO2

UVLO2 UVLO1

about 2.35V). When V is detected low, the power switch

IN

, R

is deactivated, and while sufficient V voltage persists,

IN

the soft-start capacitor is discharged. After V is detected

IN

V

⁺− 1.31V

high,thepowerswitchwillbereactivatedandthesoft-start

IN

R_UVLO1

=

capacitor will begin charging.

⎛

⎞

1.31V

+12µA

⎜

⎟

R

⎝

⎠

UVLO2

Thermal Considerations

or

FortheLT8570/LT8570-1todelivertheirfulloutputpower,

it is imperative that a good thermal path be provided to

dissipate the heat generated within the package. This is

accomplished by taking advantage of the thermal pad on

the underside of the IC. It is recommended that multiple

vias in the printed circuit board be used to conduct heat

away from the IC and into a copper plane with as much

area as possible.

−

V

− 1.27V

IN

R_UVLO1

⎛

⎞

1.27V

+12µA

⎜

⎟

R

⎝

⎠

UVLO2

+

–

where V and V are the V voltages when rising or

IN

falling, respectively.

V

IN

V

IN

ACTIVE/

LOCKOUT

1.3V

–

+

R

UVLO1

SHDN

12µA

AT 1.3V

R

UVLO2

(OPTIONAL)

GND

8570 F08

Figure 8. Configurable UVLO

85701f

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LT8570/LT8570-1

applicaTions inForMaTion

Thermal Lockout

P

= 32mW

= 85mW

= 22mW

= 23mW

SW

If the die temperature reaches approximately 165°C, the

part will go into thermal lockout, the power switch will be

turned off and the soft-start capacitor will be discharged.

The part will be enabled again when the die temperature

has dropped by ~5°C (nominal).

BAC

BDC

INP

Total LT8570 power dissipation (P ) = 161mW

TOT

ThermalresistancefortheLT8570/LT8570-1isinfluenced

by the presence of internal, topside or backside planes.

To calculate die temperature, use the appropriate ther-

mal resistance number and add in worst-case ambient

temperature:

Thermal Calculations

Power dissipation in the LT8570/LT8570-1 chip comes

fromfourprimarysources:switchI Rloss,NPNbasedrive

(AC), NPN base drive (DC), and additional input current.

The following formulas can be used to approximate the

power losses. These formulas assume continuous mode

operation, so they should not be used for calculating ef-

ficiency in discontinuous mode or at light load currents.

2

T = T + θ ꢀ•ꢀP

TOT

J

A

JA

whereT =junctiontemperature,T =ambienttemperature,

J

A

and θ is the thermal resistance from the silicon junction

JA

to the ambient air.

V_OUT•I_OUT

AverageInput Current: I =

IN

V • η

The published θ value is 43°C/W for the 3mm × 3mm

IN

JA

DFN package and 35°C/W to 40°C/W for the MSOP ex-

Switch Conduction Loss: P_SW=(DC)(I )(V

)

IN

SW

posed pad package. In practice, lower θ values can be

JA

obtained if the board layout uses ground as a heat sink.

For instance, thermal resistances of 34.7°C/W for the

DFN package and 22.5°C/W for the MSOP package were

obtained on a board designed with large ground planes.

BaseDriveLoss(AC): P = 20ns(I )(V_OUT)(f)

IN

BAC

(V )(I )(DC)

IN IN

BaseDriveLoss(DC): P

=

BDC

40

Input Power Loss: P_INP= 4.5mA (V )

IN

V Ramp Rate

IN

where:

While initially powering a switching converter application,

theV ramprateshouldbelimited.HighV rampratescan

V

SW

= switch on voltage (see Typical Performance

IN

causeexcessiveinrushcurrentsinthepassivecomponents

of the converter. This can lead to current and/or voltage

overstress and may damage the passive components or

the chip. Ramp rates less than 500mV/µs, depending on

componentparameters,willgenerallypreventtheseissues.

Also,becarefultoavoidhot-plugging.Hot-pluggingoccurs

when an active voltage supply is “instantly” connected or

switchedtotheinputoftheconverter.Hot-pluggingresults

in very fast input ramp rates and is not recommended.

Finally, for more information, refer to Linear application

note AN88, which discusses voltage overstress that can

occurwhenaninductivesourceimpedanceishot-plugged

to an input pin bypassed by ceramic capacitors.

Characteristics for Switch Saturation Voltage)

DC = duty cycle (see the Power Switch Duty Cycle sec-

tion for formulas)

h = power conversion efficiency (typically 85% at high

currents)

Example: LT8570 in boost configuration, V = 5V,

IN

V

OUT

= 12V, I

= 0.1A, f = 1.25MHz, V = 0.5V:

OUT D

I = 0.28A

IN

DC = 62.0%

85701f

18

For more information www.linear.com/LT8570

LT8570/LT8570-1

applicaTions inForMaTion

Layout Hints

a good thermal path for heat out of the package. Solder-

ing the pad onto the board reduces die temperature and

increases the power capability of the LT8570/LT8570-1.

Provide as much copper area as possible around this

pad. Adding multiple feedthroughs around the pad to the

ground plane will also help. Figure 10 and Figure 11 show

the recommended component placement for the boost

and SEPIC configurations, respectively.

As with all high frequency switchers, when considering

layout, care must be taken to achieve optimal electrical,

thermal and noise performance. One will not get adver-

tised performance with a careless layout. For maximum

efficiency, switch rise and fall times are typically in the

10ns to 20ns range. To prevent noise, both radiated and

conducted,thehighspeedswitchingcurrentpath,shownin

Figure 9, must be kept as short as possible. This is imple-

mented in the suggested layout of a boost configuration in

Figure10.Shorteningthispathwillalsoreducetheparasitic

trace inductance. At switch-off, this parasitic inductance

produces a flyback spike across the LT8570/LT8570-1

switch. When operating at higher currents and output

voltages, with poor layout, this spike can generate volt-

ages across the LT8570/LT8570-1 that may exceed the

absolute maximum rating. A ground plane should also

be used under the switcher circuitry to prevent interplane

coupling and overall noise.

Layout Hints for Inverting Topology

Figure12showsrecommendedcomponentplacementfor

thedualinductorinvertingtopology.Inputbypasscapacitor,

C1,shouldbeplacedclosetotheLT8570/LT8570-1,asshown.

The load should connect directly to the output capacitor,

C2, for best load regulation. The local ground may be tied

into the system ground plane at the C3 ground terminal.

The cut ground copper at D1’s cathode is essential to

obtain low noise. This important layout issue arises due

to the chopped nature of the currents flowing in Q1 and

D1. If they are both tied directly to the ground plane before

being combined, switching noise will be introduced into

the ground plane. It is almost impossible to get rid of this

noise, once present in the ground plane. The solution is to

tieD1’scathodetothegroundpinoftheLT8570/LT8570-1

before the combined currents are dumped in the ground

plane as drawn in Figure 12, Figure 13 and Figure 14. This

single layout technique can virtually eliminate high

frequency “spike” noise, so often present on switching

regulator outputs.

The VC and FBX components should be kept as far away

as practical from the switch node, while still remaining

closetothechip.Thegroundforthesecomponentsshould

be separated from the switch current path. Failure to do

so can result in poor stability or subharmonic oscillation.

Board layout also has a significant effect on thermal re-

sistance. The exposed package ground pad is the copper

plate that runs under the LT8570/LT8570-1 die. This is

L1

Differences from LT3580

D1

C1

LT8570/LT8570-1 are very similar to LT3580. However,

LT8570/LT8570-1 do deviate from LT3580 in a few areas:

V

OUT

SW

•ꢀ 65V, 0.5A switch for LT8570

HIGH

FREQUENCY

SWITCHING

PATH

V

IN

C2 LOAD

LT8570/

LT8570-1

•ꢀ 65V, 0.25A switch for LT8570-1

GND

•ꢀ 40V V and SHDN absolute maximum rating

IN

•ꢀ FB renamed to FBX

8570 F09

•ꢀ 5V FBX absolute maximum rating

Figure 9. High Speed “Chopped” Switching

Path for Boost Topology

85701f

19

For more information www.linear.com/LT8570

LT8570/LT8570-1

applicaTions inForMaTion

GND

SYNC

1

2

3

4

8

7

6

5

SYNC

1

2

3

4

8

7

6

5

9

C1

9

C1

V

IN

V

IN

SHDN

L1

L2

SW

C2

VIAS TO GROUND

PLANE REQUIRED

TO IMPROVE

D1

C2

VIAS TO GROUND

PLANE REQUIRED

TO IMPROVE

THERMAL

D1

C3

PERFORMANCE

8570 F10

V

OUT

THERMAL

PERFORMANCE

8570 F11

V

OUT

Figure 10. Suggested Component Placement for Boost Topology

(Both DFN and MSOP Packages. Not to Scale). Pin 9 (Exposed

Pad) Must Be Soldered Directly to the Local Ground Plane for

Adequate Thermal Performance. Multiple Vias to Additional

Ground Planes Will Improve Thermal Performance

Figure 11. Suggested Component Placement for SEPIC Topology

(Both DFN And MSOP Packages. Not to Scale). Pin 9 (Exposed

Pad) Must Be Soldered Directly to the Local Ground Plane for

Adequate Thermal Performance. Multiple Vias to Additional

Ground Planes Will Improve Thermal Performance

GND

SYNC

1

8

9

C1

2

3

4

7

V

IN

6

SHDN

5

L1

L2

SW

C2

D1

VIAS TO GROUND

PLANE REQUIRED

TO IMPROVE

C3

THERMAL

PERFORMANCE

8570 F12

V

OUT

Figure 12. Suggested Component Placement for Inverting Topology (Both DFN and MSOP Packages. Not to Scale).

Note Cut in Ground Copper at Diode’s Cathode. Pin 9 (Exposed Pad) Must be Soldered Directly to Local Ground Plane

for Adequate Thermal Performance. Multiple Vias to Additional Ground Planes Will Improve Thermal Performance

85701f

20

For more information www.linear.com/LT8570

LT8570/LT8570-1

applicaTions inForMaTion

V

–(V + V )

IN OUT

CESAT

C2

L1

L2

SW

SWX

V

–V

OUT

IN

D1

Q1

+

C1

C3

R

LOAD

+

8570 F13

Figure 13. Switch-On Phase of an Inverting Converter. L1 and L2 Have Positive dI/dt

V

+ V + V

V

D

IN

OUT

D

C2

L1

L2

SW

SWX

V

–V

OUT

IN

D1

Q1

+

C1

C3

R

LOAD

+

8570 F14

Figure 14. Switch-Off Phase of an Inverting Converter. L1 and L2 Currents Have Negative dI/dt

85701f

21

For more information www.linear.com/LT8570

LT8570/LT8570-1

applicaTions inForMaTion

BOOST CONVERTER COMPONENT SELECTION

Table 4. Boost Design Equations

PARAMETERS/EQUATIONS

D1

22µH

V

OUT

V

IN

Pick V , V , and f

to calculate equations below

Step 1:

Inputs

IN OUT

OSC

12V

5V

125mA

10k

Step 2:

DC

V

_OUT– V_IN(MIN)+ 0.5V

DC_MAX

DC_MIN

=

V

SW

FBX

R

IN

FBX

V_OUT+ 0.5V– 0.4V

130k

C

2.2µF

OUT

SHDN

V_OUT– V_IN(MAX)+ 0.5V

C

IN

=

LT8570

V

_OUT+ 0.5V– 0.4V

1µF

SYNC

RT

VC

Step 3:

L1

R

C

(V_IN(MIN)– 0.4V)•DC_MAX

f_OSC•I_RTYP

(1)

(2)

(3)

(4)

6.19k

L_TYP

=

GND SS

C

F

47pF

C

2.2nF

R

56.2k

SS

T

(V_IN(MIN)– 0.4V)•(2 •DC_MAX– 1)

0.1µF

L_MIN

=

8570 F15

k_SC•(DC_MAX− 300ns • f_OSC)• f_OSC•(1–DC_MAX

(V_IN(MIN)– 0.4V)•DC_MAX

)

L_MAX1

=

f_OSC•I_RMIN

Figure 15. Boost Converter: The Component Values Given Are

Typical Values for a 1.5MHz, 5V to 12V Boost

(V_IN(MAX)– 0.4V)•DC_MIN

f_OSC•I_RMIN

L_MAX2

=

The LT8570/LT8570-1 can be configured as a boost con-

verter as in Figure 15. This topology allows for positive

output voltages that are higher than the input voltage.

A single feedback resistor sets the output voltage. For

output voltages higher than 60V, see the Charge Pump

Aided Regulators section.

•ꢀ Solve equations 1 to 4 for a range of L values

•ꢀ The minimum of the L value range is the higher of L and L

TYP

MIN

•ꢀ The maximum of the L value range is the lower of L

and L

MAX1

MAX2

Step 4:

RIPPLE

(V_IN(MIN)– 0.4V)•DC_MAX

I_RIPPLE(MIN)

=

I

f_OSC•L₁

(V_IN(MAX)– 0.4V)•DC_MIN

f_OSC•L₁

I_RIPPLE(MAX)

=

For a desired output voltage over a given input voltage

range, Table 4 is a step-by-step set of equations to cal-

culate component values for the LT8570/LT8570-1 when

operating as a boost converter. Refer to the Applications

Information section for further information on the design

equations presented in Table 4.

Step 5:

OUT

I_RIPPLE(MIN)

⎛

⎞

I

_OUT(MIN)= I_LIM

−

•(1−DC_MAX)

I

⎜

⎟

2

⎝

⎠

I_RIPPLE(MAX)

⎛

⎞

I

_OUT(MAX)= I_LIM

−

•(1−DC_MIN)

⎟

⎜

2

⎝

⎠

V

> V ; I

> I

Step 6:

D1

R

OUT AVG OUT

Step 7:

OUT

I_OUT•DC_MAX

f_OSC• 0.005 • V_OUT

C_OUT

≥

Variable Definitions:

C

V = Input Voltage

IN

Step 8:

IN

C

_IN≥ C_VIN+C_PWR

≥

C

V

OUT

= Output Voltage

I_RIPPLE(MAX)

8 • f_OSC• 0.005 • V

I_LIM•DC_MAX

+

40 • f_OSC• 0.005 • V

IN(MIN)

IN(MAX)

DC = Power Switch Duty Cycle

•ꢀRefer to the Capacitor Selection Section for definition of C and C

VIN

PWR

f

I

= Switching Frequency

OSC

Step 9:

V_OUT−1.204V

R_FBX

=

R

FBX

= Maximum Average Output Current

83.3µA

OUT

Step 10:

85.5

f_OSC

= Inductor Ripple Current

RIPPLE

R_T

=

–1; f_OSCin MHz and R_Tin kΩ

R

T

= 150mA for LT8570 and 75mA for LT8570-1

= 0.6A for LT8570 and 0.3A for LT8570-1

RTYP

Note 1: This table uses 0.5A and 0.25A for the peak switch current.

Refer to the Electrical Characteristics Table and Typical Performance

Characteristics plots for the peak switch current at an operating duty cycle.

Note 2: The final values for C and C may deviate from the previous

k

SC

I

= 0.04A for LT8570 and 0.02A for LT8570-1

RMIN

OUT

IN

equations in order to obtain desired load transient performance.

= 0.5A for LT8570 and 0.25A for LT8570-1

LIM

85701f

22

For more information www.linear.com/LT8570

LT8570/LT8570-1

applicaTions inForMaTion

SEPIC CONVERTER COMPONENT SELECTION

(COUPLED OR UNCOUPLED INDUCTORS)

Table 5. SEPIC Design Equations

PARAMETERS/EQUATIONS

Pick V , V and f to calculate equations below

Step 1:

Inputs

IN OUT

OSC

C1

0.47µF

L1

47µH

D1

Step 2:

DC

V

_OUT+ 0.5V

V

OUT

V

•

IN

DC_MAX

=

12V

9V TO 16V

V_IN(MIN)+ V_OUT+ 0.5V– 0.4V

160mA

L2

47µH

487k

V

_OUT+ 0.5V

DC_MIN

=

V

_IN(MAX)+ V_OUT+ 0.5V– 0.4V

V

SW

FBX

R

IN

•

FBX

130k

C

OUT

2.2µF

IN

SHDN

Step 3:

L

1µF

(V_IN(MIN)– 0.4V)•DC_MAX

f_OSC•I_RTYP

LT8570

(1)

(2)

(3)

L_TYP

=

SYNC

VC

R

C

26.7k

(V_IN(MIN)– 0.4V)•(2 •DC_MAX– 1)

RT

GND SS

C

F

L_MIN

47pF

k_SC•(DC_MAX− 300ns • f_OSC)• f_OSC•(1–DC_MAX

)

C

2.2nF

R

SS

T

0.22µF

84.5k

8570 F16

(V_IN(MIN)– 0.4V)•DC_MAX

f_OSC•I_RMIN

L_MAX

•ꢀ Solve equations 1, 2 and 3 for a range of L values

•ꢀ The minimum of the L value range is the higher of L and L

Figure 16. SEPIC Converter: The Component Values and Voltages

Given Are Typical Values for a 1MHz, 9V-16V to 12V SEPIC

Converter Using Coupled Inductors

TYP

MIN

•ꢀ The maximum of the L value range is L

•ꢀ L = L1 = L2 for coupled inductors

•ꢀ L = L1 || L2 for uncoupled inductors

MAX

Figure 16 shows the LT8570 configured as a SEPIC. This

topologyallowsforpositiveoutputvoltagesthatarelower,

equal or higher than the input voltage. Output disconnect

is inherent to the SEPIC topology, meaning no DC path

exists between the input and output due to capacitor C1.

Step 4:

RIPPLE

(V_IN(MIN)– 0.4V)•DC_MAX

f_OSC•L

I_RIPPLE(MIN)

=

I

(V_IN(MAX)– 0.4V)•DC_MIN

f_OSC•L

I_RIPPLE(MAX)

=

Step 5:

I_RIPPLE(MIN)

⎛

⎞

For a desired output voltage over a given input voltage

range, Table 5 is a step-by-step set of equations to calculate

componentvaluesfortheLT8570/LT8570-1whenoperating

as a SEPIC converter. Refer to the Applications Information

section for further information on the design equations

presented in Table 5.

I

_OUT(MIN)= I_LIM

−

• 1−DC

(

MAX

I

)

OUT

⎜

⎟

2

⎝

⎠

I_RIPPLE(MAX)

⎛

⎞

I

_OUT(MAX)= I_LIM

−

• 1−DC

MIN

⎟

(

)

⎜

2

⎝

⎠

V

> V + V ; I

> I

Step 6:

D1

Step 7:

C1

R

IN

OUT AVG

OUT

V

≥ V

RATING

IN

C1 ≥ 0.47µF for LT8570, C1 ≥ 0.22µF for LT8570-1

Variable Definitions:

Step 8:

I_OUT(MIN)•DC_MAX

C_OUT

≥

C

OUT

f_OSC• 0.005 • V_OUT

V = Input Voltage

IN

Step 9:

IN

C

_IN≥ C_VIN+C_PWR

≥

V

= Output Voltage

OUT

C

I_RIPPLE(MAX)

I_LIM•DC_MAX

DC = Power Switch Duty Cycle

+

40 • f_OSC• 0.005 • V

8 • f_OSC• 0.005 • V_IN(MAX)

IN(MIN)

f

I

= Switching Frequency

OSC

•ꢀRefer to the Capacitor Selection Section for definition of C and C

VIN

PWR

Step 10:

FBX

V_OUT−1.204V

= Maximum Average Output Current

OUT

R_FBX

=

R

83.3µA

= Inductor Ripple Current

RIPPLE

Step 11:

85.5

f_OSC

R_T

=

–1; f_OSCin MHz and R_Tin kΩ

R

T

= 150mA for LT8570 and 75mA for LT8570-1

= 0.6A for LT8570 and 0.3A for LT8570-1

RTYP

Note 1: This table uses 0.5A and 0.25A for the peak switch current.

k

SC

Refer to the Electrical Characteristics Table and Typical Performance

Characteristics plots for the peak switch current at an operating duty cycle.

I

= 0.04A for LT8570 and 0.02A for LT8570-1

RMIN

Note 2: The final values for C , C and C1 may deviate from the

OUT IN

= 0.5A for LT8570 and 0.25A for LT8570-1

previous equations in order to obtain desired load transient performance.

LIM

85701f

23

For more information www.linear.com/LT8570

LT8570/LT8570-1

applicaTions inForMaTion

DUAL INDUCTOR INVERTING CONVERTER COMPONENT

Table 6. Dual Inductor Inverting Design Equations

PARAMETERS/EQUATIONS

SELECTION (COUPLED OR UNCOUPLED INDUCTORS)

Pick V , V

and f

to calculate equations below

Step 1:

Inputs

IN OUT

OSC

C1

0.47µF

L1

47µH

L2

47µH

Step 2:

DC

V

V_OUT+ 0.5V

_IN(MIN)+ V_OUT+ 0.5V– 0.4V

OUT

–15V

65mA (V = 5V)

V

•

IN

5V TO 35V

DC_MAX

DC_MIN

=

V

IN

232k

D1

150mA (V = 12V)

IN

210mA (V = 24V)

IN

V_OUT+ 0.5V

_IN(MAX)+ V_OUT+ 0.5V– 0.4V

V

SW

FBX

R

=

IN

FBX

182k

V

SHDN

C

2.2µF

IN

2.2µF

OUT

Step 3:

L

LT8570

(V_IN(MIN)– 0.4V)•DC_MAX

f_OSC•I_RTYP

(1)

(2)

(3)

L_TYP

=

SYNC

RT

VC

R

C

20.5k

GND SS

C

F

(V_IN(MIN)– 0.4V)•(2 •DC_MAX– 1)

47pF

C

2.2nF

R

121k

L_MIN

SS

T

k_SC•(DC_MAX− 300ns • f_OSC)• f_OSC•(1–DC_MAX

)

0.1µF

8570 F17

(V_IN(MIN)– 0.4V)•DC_MAX

f_OSC•I_RMIN

L_MAX

Figure 17. Dual Inductor Inverting Converter: The Component

Values Given Are Typical Values for a 700kHz 5V-35V to –15V

Inverting Topology Using Coupled Inductors

•ꢀSolve equations 1, 2 and 3 for a range of L values

•ꢀThe minimum of the L value range is the higher of L and L

TYP

MIN

•ꢀThe maximum of the L value range is L

•ꢀL = L1 = L2 for coupled inductors

•ꢀL = L1||L2 for uncoupled inductors

MAX

Due to its unique FBX pin, the LT8570/LT8570-1 can work

in an inverting configuration as in Figure 17. Changing the

connectionsofL2andtheSchottkydiodeintheSEPICtopol-

ogy results in negative output voltages. Output disconnect

isinherentlybuiltintothistopologyduetothecapacitorC1.

Step 4:

RIPPLE

(V_IN(MIN)– 0.4V)•DC_MAX

I_RIPPLE(MIN)

=

I

f_OSC•L

(V_IN(MAX)– 0.4V)•DC_MIN

f_OSC•L

I_RIPPLE(MAX)

=

Step 5:

OUT

I_RIPPLE(MIN)

⎛

⎞

For a desired output voltage over a given input voltage

range, Table 6 is a step-by-step set of equations to

calculate component values for the LT8570/LT8570-1

when operating as a dual inductor inverting converter.

Refer to the Applications Information section for further

information on the design equations presented in Table 6.

I

_OUT(MIN)= I_LIM

−

• 1−DC

MAX

I

(

)

⎜

⎟

2

⎝

⎠

I_RIPPLE(MAX)

⎛

⎞

I

_OUT(MAX)= I_LIM

−

• 1−DC

(

MIN

)

⎜

⎟

2

⎝

⎠

V

> V + |V |; I

> I

Step 6:

D1

R

IN

OUT AVG

OUT

V

≥ V

+ |V

|

Step 7:

C1

RATING

IN(MAX)

OUT

C1 ≥ 0.47µF for LT8570, C1 ≥ 0.22µF for LT8570-1

Step 8:

I_RIPPLE(MAX)

Variable Definitions:

C_OUT

≥

C

OUT

8 • f_OSC(0.005 • V_OUT

)

V = Input Voltage

IN

Step 9:

C

_IN≥ C_VIN+C_PWR

≥

V

OUT

= Output Voltage

C

IN

I_RIPPLE(MAX)

8 • f_OSC• 0.005 • V_IN(MAX)

I_LIM•DC_MAX

40 • f_OSC• 0.005 • V

+

DC = Power Switch Duty Cycle

IN(MIN)

•ꢀRefer to the Capacitor Selection Section for definition of C and C

VIN

PWR

f

I

= Switching Frequency

OSC

OUT

Step 10:

FBX

V_OUT+ 3mV

R_FBX

=

= Maximum Average Output Current

= Inductor Ripple Current

R

83.3µA

Step 11:

85.5

f_OSC

RIPPLE

R_T

=

–1; f_OSCin MHz and R_Tin kΩ

R

T

= 150mA for LT8570 and 75mA for LT8570-1

RTYP

Note 1: This table uses 0.5A and 0.25A for the peak switch current.

Refer to the Electrical Characteristics Table and Typical Performance

k

= 0.6A for LT8570 and 0.3A for LT8570-1

SC

Characteristics plots for the peak switch current at an operating duty cycle.

I

= 0.04A for LT8570 and 0.02A for LT8570-1

RMIN

Note 2: The final values for C , C and C1 may deviate from the

OUT IN

previous equations in order to obtain desired load transient performance.

= 0.5A for LT8570 and 0.25A for LT8570-1

LIM

85701f

24

For more information www.linear.com/LT8570

LT8570/LT8570-1

Typical applicaTions

1.5MHz, 5V to 12V Output Boost Converter

L1

22µH

L1

47µH

D1

V

OUT

V

IN

5V

IN

12V

5V

125mA

60mA

10k

V

SW

FBX

VC

V

SW

FBX

IN

130k

C

OUT

1µF

OUT

SHDN

2.2µF

C

IN

0.47µF

IN

LT8570

LT8570-1

1µF

SYNC

RT

SYNC

RT

VC

6.19k

2.2nF

6.19k

2.2nF

GND SS

47pF

56.2k

0.1µF

56.2k

0.1µF

8570 TA02a

8570 TA02b

L1: WÜRTH 22µH WE-LQS 74404042220

D1: DIODES INC. PD3S140

L1: WÜRTH 47µH WE-LQS 74404032470

D1: DIODES INC. PD3S140

C

: 1µF, 16V, 0805, X7R

C

: 0.47µF, 16V, 0805, X7R

IN

OUT

IN

OUT

: 2.2µF, 16V, 0805, X7R

: 1µF, 16V, 0805, X7R

Efficiency and Power Loss (LT8570)

Efficiency and Power Loss (LT8570-1)

100

90

80

70

60

50

40

30

20

360

320

280

240

200

160

120

80

100

180

90

80

70

60

50

40

30

20

160

140

120

100

80

60

EFFICIENCY

40

POWER LOSS

40

125

20

0

25

0

60

50

75

100

15

30

45

LOAD CURRENT (mA)

8570 TA02c

8570 TA02d

30mA to 90mA to 30mA Output Load Step (LT8570)

15mA to 45mA to 15mA Output Load Step (LT8570-1)

V

OUT

500mV/DIV

AC-COUPLED

OUT

500mV/DIV

AC-COUPLED

I

STEP

20mA/DIV

STEP

50mA/DIV

I

L1

50mA/DIV

L1

100mA/DIV

8570 TA02e

8570 TA02f

50µs/DIV

85701f

25

For more information www.linear.com/LT8570

LT8570/LT8570-1

Typical applicaTions

700kHz, –15V Output Inverting Converter Accepts 5V to 35V Input

C1

0.47µF

L1

47µH

L2

47µH

V

OUT

V

•

IN

–15V

65mA (V = 5V)

5V TO 35V

IN

232k

D1

150mA (V = 12V)

IN

210mA (V = 24V)

IN

V

SW

FBX

VC

IN

182k

SHDN

C

2.2µF

IN

OUT

LT8570

2.2µF

SYNC

RT

20.5k

2.2nF

GND SS

47pF

0.1µF

121k

8570 TA03a

L1: COILCRAFT 47µH LPD6235-473

D1: DIODES INC SBR160S23

C

, C

: 2.2µF, 50V, 0805, X7R

IN OUT

C1: 0.47µF, 100V, 0805, X7S

C1

0.22µF

L1

100µH

L2

100µH

V

OUT

V

•

IN

–15V

35mA (V = 5V)

5V TO 35V

IN

232k

D1

75mA (V = 12V)

IN

105mA (V = 24V)

IN

V

SW

FBX

IN

182k

SHDN

C

1µF

IN

OUT

LT8570-1

1µF

SYNC

RT

VC

20.5k

2.2nF

GND SS

47pF

0.1µF

121k

8570 TA03b

L1: COILCRAFT 100µH LPD5030-104

D1: DIODES INC SBR160S23

C

, C

: 1µF, 50V, 0805, X7R

IN OUT

C1: 0.22µF, 100V, 0805, X7S

Efficiency and Power Loss

(LT8570, V_IN= 12V)

Efficiency and Power Loss

(LT8570-1, V_IN= 12V)

90

80

70

60

50

40

30

20

10

560

490

420

350

280

210

140

70

90

80

70

60

50

40

30

20

10

280

245

210

175

140

105

70

EFFICIENCY

35

POWER LOSS

80

60

0

160

0

40

0

20

80

120

40

LOAD CURRENT (mA)

8570 TA03c

85701f

26

For more information www.linear.com/LT8570

LT8570/LT8570-1

Typical applicaTions

1MHz Inverting Converter Generates –48V Output From 12V Input

C1

0.47µF

L1

120µH

L2

120µH

V

OUT

V

•

IN

–48V

12V

50mA

576k

D1

V

SW

FBX

VC

IN

576k

SHDN

C

IN

OUT

LT8570

0.47µF

SYNC

RT

16.2k

GND SS

47pF

0.1µF

2.2nF

84.5k

8570 TA04a

L1, L2: COILCRAFT 120µH MSD7342-124

D1: DIODES, INC. DFLS1100

C

, C

: 0.47µF, 50V, 0805, X7R

IN OUT

C1: 0.47µF, 100V, 0805, X7S

Efficiency and Power Loss

90

80

70

60

50

40

30

20

10

640

560

480

400

320

240

160

80

EFFICIENCY

POWER LOSS

0

10

20

30

40

50

LOAD CURRENT (mA)

8570 TA04b

Switching Waveforms

Start-Up Waveforms

V

SW

V

50V/DIV

SW

20V/DIV

V

OUT

V

OUT

20V/DIV

200mV/DIV

AC-COUPLED

I

+ I

L1 L2

I

+ I

100mA/DIV

L1 L2

100mA/DIV

8570 TA04c

8570 TA04d

500µs/DIV

85701f

27

For more information www.linear.com/LT8570

LT8570/LT8570-1

Typical applicaTions

VFD (Vacuum Fluorescent Display) Power Supply Switches at 1MHz

Danger High Voltage! Operation by High Voltage Trained Personnel Only

D5

V

OUT3

180V

C5

0.22µF

D4

D2

13mA*

30.1Ω

C4

0.22µF

D3

D1

V

OUT2

120V

C3

0.22µF

20mA*

30.1Ω

L1

C2

0.22µF

150µH

V

OUT1

V

IN

60V

9V TO 16V

40mA*

487k

V

SW

FBX

VC

IN

698k

SHDN

C

C1

0.22µF

IN

LT8570

0.47µF

SYNC

RT

27.4k

6.8nF

GND SS

330pF

0.47µF

84.5k

8570 TA05a

*MAX TOTAL OUTPUT POWER 2.5W

L1: WÜRTH 150µH WE-PD2SR 744787151

D1-D5: CENTRAL SEMI CMOD6263

C

: 0.47µF, 25V, 0805, X7R

IN

C1-C5: 0.22µF, 100V, 0805, X7S

Efficiency and Power Loss

(V_IN= 12V with Load on V_OUT3

Start-Up Waveforms

)

V

OUT3

90

80

70

60

50

40

30

20

900

800

700

600

500

400

300

200

50V/DIV

V

OUT2

50V/DIV

V

OUT1

50V/DIV

I

L1

100mA/DIV

8570 TA05c

1ms/DIV

EFFICIENCY

POWER LOSS

0

0.5

1

1.5

2 2.5

OUTPUT POWER (W)

8570 TA05b

85701f

28

For more information www.linear.com/LT8570

LT8570/LT8570-1

Typical applicaTions

1.2MHz Charge Pump Creates 12V From a Single Lithium Ion Battery

C2

V

OUT2

0.22µF

D4

–12V

20mA* (V = 2.6V)

10Ω

D3

IN

30mA* (V = 3.8V)

40mA* (V = 5V)

R1

C

OUT2

**32.4k

C1

0.22µF

1µF

L1

D2

68µH

V

12V

OUT1

V

IN

2.6V TO 5.5V

20mA* (V = 2.6V)

IN

10Ω

D1

10k

30mA* (V = 3.8V)

IN

40mA* (V = 5V)

IN

V

IN

SW

FBX

130k

SHDN

C

1µF

IN

OUT1

LT8570-1

0.47µF

SYNC

RT

VC

26.1k

2.2nF

*MAX TOTAL OUTPUT POWER FOR V = 2.6V: 240mW

GND SS

47pF

0.1µF

69.8k

8570 TA06a

IN

V

IN

V

IN

= 3.8V: 350mW

= 5V: 480mW

L1: WÜRTH 68µH WE-LQS 74404054680

D1-D4: DIODES INC SDM10K45

C

: 0.47µF, 25V, 0805, X7R

IN

OUT1 OUT2

**IF DRIVING ASYMETRICAL LOADS, PLACE A 32.4k RESISTOR

FROM THE 12V OUTPUT TO THE –12V OUTPUT FOR IMPROVED

LOAD REGULATION OF THE –12V OUTPUT

, C

: 1µF, 16V, 0805, X7R

C1-C2: 0.22µF, 25V, 0805, X7R

Efficiency and Power Loss

(Load Between V_OUT1AND V_OUT2

Transient Response with 5mA to 15mA to

5mA Output Load Step (V_IN= 5V)

)

90

80

70

60

50

40

30

20

10

140

125

110

95

V

OUT1

EFFICIENCY

200mV/DIV

AC-COUPLED

V

OUT2

200mV/DIV

AC-COUPLED

POWER LOSS

80

I

STEP

10mA/DIV

65

I

L1

50mA/DIV

50

8570 TA06c

V

= 5V

35

IN

100µs/DIV

= 3.8V

20

0

4

8

12

16

20

LOAD CURRENT (mA)

8570 TA06b

85701f

29

For more information www.linear.com/LT8570

LT8570/LT8570-1

Typical applicaTions

1MHz Boost Converter Generates 24V from 5V-12V Input

L1

47µH

D1

V

OUT

V

IN

24V

60mA (V = 5V)

5V-12V

IN

232k

200mA (V = 12V)

V

SW

FBX

VC

IN

274k

C

OUT

SHDN

1µF

C

IN

LT8570

1µF

SYNC

RT

15k

2.2nF

GND SS

47pF

84.5k

0.1µF

8570 TA07a

L1: WÜRTH 47µH WE-LQS 74404042470

D1: MBR0540

C

: 1µF, 16V, 0603, X7R

OUT

IN

: 1µF, 50V, 0805, X7R

L1

100µH

D1

V

OUT

V

IN

24V

30mA (V = 5V)

5V-12V

IN

232k

100mA (V = 12V)

V

SW

FBX

IN

274k

C

OUT

SHDN

0.47µF

C

IN

LT8570-1

0.47µF

SYNC

RT

VC

11.3k

2.2nF

GND SS

47pF

84.5k

0.1µF

8570 TA07b

L1: WÜRTH 100µH WE-LQS 74404054101

D1: FAIFCHILD BAT42XV2

C

: 0.47µF, 16V, 0603, X7R

OUT

IN

: 0.47µF, 50V, 0805, X7R

Efficiency and Power Loss

(LT8570, V_IN= 12V)

Efficiency and Power Loss

(LT8570-1, V_IN= 12V)

100

90

80

70

60

50

40

30

630

540

450

360

270

180

90

100

90

80

70

60

50

40

30

350

300

250

200

150

100

50

EFFICIENCY

POWER LOSS

0

200

0

100

0

40

80

120

160

0

20

40

60

80

LOAD CURRENT (mA)

8570 TA07c

8570 TA07d

85701f

30

For more information www.linear.com/LT8570

LT8570/LT8570-1

Typical applicaTions

12V Battery Stabilizer Survives 40V Transients

C1

L1

0.47µF

D1

V

IN

47µH

V

OUT

•

9V-16V

UP TO 40V

TRANSIENT

12V

160mA

L2

47µH

10k

V

IN

SW

•

130k

C

OUT

SHDN

FBX

VC

2.2µF

C

IN

LT8570

1µF

L1, L2: COILCRAFT 47µH LPD6235-473

D1: DIODES INC. DFLS1100

SYNC

RT

26.7k

2.2nF

C

: 1µF, 50V, 0805, X7R

: 2.2µF, 25V, 0805, X7R

IN

OUT

GND SS

47pF

C1: 0.47µF, 100V, 0805, X7S

84.5k

0.22µF

8570 TA08a

C1

0.22µF

L1

68µH

D1

V

IN

V

OUT

9V-16V

UP TO 40V

TRANSIENT

•

12V

70mA

L2

68µH

10k

V

IN

SW

•

130k

C

OUT

SHDN

FBX

VC

1µF

C

IN

LT8570-1

0.47µF

SYNC

RT

L1, L2: COILCRAFT 68µH LPD5030-683

D1: DIODES INC. DFLS1100

16.5k

2.2nF

C

: 0.47µF, 50V, 0805, X7R

: 1µF, 25V, 0805, X7R

IN

OUT

GND SS

47pF

C1: 0.22µF, 100V, 0805, X7S

84.5k

0.22µF

8570 TA08b

Efficiency and Power Loss

(LT8570, V_IN= 12V)

Efficiency and Power Loss

(LT8570-1, V_IN= 12V)

90

80

70

60

50

40

30

540

90

240

200

160

120

80

450

360

270

180

90

80

70

60

50

40

30

40

EFFICIENCY

POWER LOSS

0

160

0

40

80

120

0

20

40

60

80

LOAD CURRENT (mA)

8570 TA08c

8570 TA08d

85701f

31

For more information www.linear.com/LT8570

LT8570/LT8570-1

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

DD Package

8-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1698 Rev C)

0.70 ±0.05

3.5 ±0.05

2.10 ±0.05 (2 SIDES)

1.65 ±0.05

PACKAGE

OUTLINE

0.25 ±0.05

0.50

BSC

2.38 ±0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

R = 0.125

0.40 ±0.10

TYP

5

8

3.00 ±0.10

(4 SIDES)

1.65 ±0.10

(2 SIDES)

PIN 1

TOP MARK

(NOTE 6)

(DD8) DFN 0509 REV C

4

1

0.25 ±0.05

0.75 ±0.05

0.200 REF

0.50 BSC

2.38 ±0.10

BOTTOM VIEW—EXPOSED PAD

0.00 – 0.05

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON TOP AND BOTTOM OF PACKAGE

85701f

32

For more information www.linear.com/LT8570

LT8570/LT8570-1

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

MS8E Package

8-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1662 Rev K)

BOTTOM VIEW OF

EXPOSED PAD OPTION

1.88

(.074)

1

0.29

REF

1.88 ±0.102

(.074 ±.004)

1.68

(.066)

0.889 ±0.127

(.035 ±.005)

0.05 REF

DETAIL “B”

5.10

(.201)

MIN

3.20 – 3.45

(.126 – .136)

1.68 ±0.102

(.066 ±.004)

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

DETAIL “B”

8

NO MEASUREMENT PURPOSE

3.00 ±0.102

(.118 ±.004)

(NOTE 3)

0.65

(.0256)

BSC

0.52

(.0205)

REF

0.42 ±0.038

(.0165 ±.0015)

8

7 6 5

TYP

RECOMMENDED SOLDER PAD LAYOUT

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

4.90 ±0.152

(.193 ±.006)

DETAIL “A”

0.254

(.010)

0° – 6° TYP

GAUGE PLANE

1

2

3

4

0.53 ±0.152

(.021 ±.006)

1.10

(.043)

MAX

0.86

(.034)

REF

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.22 – 0.38

(.009 – .015)

TYP

0.1016 ±0.0508

(.004 ±.002)

0.65

(.0256)

BSC

MSOP (MS8E) 0213 REV K

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD

SHALL NOT EXCEED 0.254mm (.010") PER SIDE.

85701f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

33

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/LT8570

LT8570/LT8570-1

Typical applicaTion

1.2MHz Boost Converter Creates 48V from 9V-16V Input

Efficiency and Power Loss

(V_IN= 12V)

L1

D1

V

OUT

48V

220µH

90

80

70

60

50

40

30

540

450

360

270

180

90

V

IN

35mA (V = 9V)

50mA (V = 12V)

IN

9V TO 16V

IN

576k

V

SW

FBX

IN

562k

SHDN

C

IN

OUT

LT8570-1

0.22µF

SYNC

RT

VC

8.87k

3.3nF

GND SS

47pF

EFFICIENCY

POWER LOSS

0.1µF

69.8k

8570 TA09a

0

10

20

30

40

50

LOAD CURRENT (mA)

L1: COILCRAFT 220µH LPS6235-224

D1: DIODES INC. ZHCS506

8570 TA09b

C

: 0.22µF, 25V, 0603, X7R

IN

OUT

: 0.22µF, 50V, 0805, X7R

relaTeD parTs

PART NUMBER

DESCRIPTION

COMMENTS

LT1613

550mA (I ), 1.4MHz High Efficiency Step-Up DC/DC Converter V : 0.9V to 10V, V

= 34V, I = 3mA, I < 1µA,

Q SD

SW

IN

OUT(MAX)

ThinSOT Package

LT1618

1.5A (I ), 1.4MHz High Efficiency Step-Up DC/DC Converter

V : 1.6V to 18V, V

= 35V, I = 1.8mA, I < 1µA,

Q SD

SW

IN

OUT(MAX)

MS10, 3mm × 3mm DFN Packages

LT1930/LT1930A 1A (I ), 1.2MHz/2.2MHz High Efficiency Step-Up DC/DC

V : 2.6V to 16V, V

= 34V, I = 4.2mA/5.5mA, I < 1µA,

Q SD

SW

Converter

IN

OUT(MAX)

ThinSOT Package

LT1935

2A (I ), 40V, 1.2MHz High Efficiency Step-Up DC/DC Converter V : 2.3V to 16V, V

= 38V, I = 3mA, I < 1µA,

Q SD

SW

IN

ThinSOT Package

LT1944/LT1944-1 Dual Output 350mA (I ), Constant Off-Time, High Efficiency

V : 1.2V to 15V, V

= 34V, I = 20µA, I < 1µA,

Q SD

SW

IN

Step-Up DC/DC Converter

MS10 Package

LT1946/LT1946A 1.5A (I ), 1.2MHz/2.7MHz High Efficiency Step-Up DC/DC

V : 2.6V to 16V, V

= 34V, I = 3.2mA, I < 1µA,

Q SD

SW

IN

Converter

MS8E Package

LT3467

LT3479

LT3580

LT3581

LT3579

LT8582

LT8580

1.1A (I ), 1.3MHz High Efficiency Step-Up DC/DC Converter

V : 2.4V to 16V, V

= 40V, I = 1.2mA, I < 1µA,

Q SD

SW

IN

ThinSOT, 2mm × 3mm DFN Packages

3A Full-Featured DC/DC Converter with Soft-Start and Inrush

Current Protection

V : 2.5V to 24V, V = 40V, I = 5mA, I < 1µA,

IN

OUT(MAX)

Q

SD

DFN, TSSOP Packages

2A (I ), 42V, 2.5MHz, High Efficiency Step-Up DC/DC

V : 2.5V to 32V, V

= 42V, I = 1mA, I = <1µA,

Q SD

SW

IN

OUT(MAX)

Converter

3mm × 3mm DFN-8, MSOP-8E

3.3A (I ), 42V, 2.5MHz, High Efficiency Step-Up DC/DC

V : 2.5V to 22V, V = 42V, I = 1.9mA, I = <1µA,

SW

IN

OUT(MAX)

Q

SD

Converter

4mm × 3mm DFN-14, MSOP-16E

6A (I ), 42V, 2.5MHz, High Efficiency, Step-Up DC/DC

V : 2.5V to 16V, V = 42V, I = 1.9mA, I = <1µA,

SW

IN

OUT(MAX)

Q

SD

Converter

4mm × 5mm DFN-20, TSSOP-20

Dual Channel, 3A (I ), 42V, 2.5MHz, High Efficiency Step-Up

V : 2.5V to 22V, V = 42V, I = 2.1mA, I = <1µA,

SW

IN

OUT(MAX)

Q

SD

DC/DC Converter

4mm × 7mm DFN-24

1A (I ), 65V 1.5MHz, High Efficiency Step-Up DC/DC Converter V : 2.55V to 40V, V

= 65V, I = 1.2mA, I = <1µA,

Q SD

SW

IN

OUT(MAX)

3mm × 3mm DFN-8, MSOP-8E

85701f

LT 0215 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

34

For more information www.linear.com/LT8570

●

 LINEAR TECHNOLOGY CORPORATION 2015

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LT8570


型号：	LT8570
厂家：	Linear
描述：	Boost/SEPIC/Inverting DC/DC Converter with 65V Switch, Soft-Start and Synchronization
文件：	总34页 (文件大小：663K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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