LT8580EDD#TRPBF_技术文档

LT8580

Boost/SEPIC/Inverting

DC/DC Converter with 1A, 65V

Switch, Soft-Start and Synchronization

FeaTures

DescripTion

The LT^®8580 is a PWM DC/DC converter containing an

internal 1A, 65V switch. The LT8580 can be configured

n

1A, 65V Power Switch

n

Adjustable Switching Frequency

n

Single Feedback Resistor Sets V

as either a boost, SEPIC or inverting converter.

OUT

n

Synchronizable to External Clock

High Gain SHDN Pin Accepts Slowly Varying

Input Signals

The LT8580 has an adjustable oscillator, set by a resistor

fromtheRTpintoground. Additionally, theLT8580canbe

synchronizedtoanexternalclock.Theswitchingfrequency

of the part may be free running or synchronized, and can

be set between 200kHz and 1.5MHz.

n

Wide Input Voltage Range: 2.55V to 40V

Low V

Switch: 400mV at 0.75A (Typical)

CESAT

Integrated Soft-Start Function

The LT8580 also features innovative SHDN pin circuitry

that allows for slowly varying input signals and an adjust-

able undervoltage lockout function.

Easily Configurable as a Boost, SEPIC, or Inverting

Converter

User Configurable Undervoltage Lockout (UVLO)

Pin Compatible with LT3580

Tiny Thermally Enhanced 8-Lead 3mm × 3mm DFN

and 8-Lead MSOP Packages

n

Additional features such as frequency foldback and

soft-start are integrated. The LT8580 is available in tiny

thermally enhanced 3mm × 3mm 8-lead DFN and 8-lead

MSOP packages.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners. Protected by U.S. Patents, including 7579816.

applicaTions

n

VFD Bias Supplies

n

TFT-LCD Bias Supplies

n

GPS Receivers

DSL Modems

Local Power Supply

n

Typical applicaTion

1.5MHz, 5V to 12V Boost Converter

Efficiency and Power Loss

100

90

80

70

60

50

40

30

20

480

420

360

300

240

180

120

60

15µH

V

OUT

V

IN

12V

5V

200mA

10k

V

IN

SW

FBX

VC

130k

SHDN

4.7µF

LT8580

2.2µF

SYNC

RT

6.04k

3.3nF

GND SS

47pF

EFFICIENCY

56.2k

0.22µF

POWER LOSS

8580 TA01a

0

200

0

50

LOAD CURRENT (mA)

100

150

8580 TA01b

8580fa

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For more information www.linear.com/LT8580

LT8580

absoluTe MaxiMuM raTings ^{(Note 1)}

V Voltage.................................................–0.3V to 40V

SHDN Voltage ............................................–0.3V to 40V

SYNC Voltage............................................–0.3V to 5.5V

Operating Junction Temperature Range

IN

SW Voltage ................................................–0.4V to 65V

RT Voltage ...................................................–0.3V to 5V

SS Voltage ................................................–0.3V to 2.5V

FBX Voltage.................................................................5V

FBX Current............................................................–1mA

VC Voltage ...................................................–0.3V to 2V

LT8580E (Notes 2, 5).........................–40°C to 125°C

LT8580I (Notes 2, 5)..........................–40°C to 125°C

LT8580H (Notes 2, 5) ........................ –40°C to 150°C

Storage Temperature Range ..................–65°C to 150°C

pin conFiguraTion

TOP VIEW

FBX

VC

1

2

3

4

8

7

6

5

SYNC

SS

FBX

VC

1

2

3

4

8 SYNC

7 SS

9

GND

9

GND

6

5

V

IN

RT

SHDN

V

IN

RT

SW

SHDN

MS8E PACKAGE

8-LEAD PLASTIC MSOP

DD PACKAGE

8-LEAD (3mm × 3mm) PLASTIC DFN

θ

= 35°C/W TO 40°C/W

JA

EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB

θ

= 43°C/W

JA

EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB

http://www.linear.com/product/LT8580#orderinfo

orDer inForMaTion

LEAD FREE FINISH

LT8580EDD#PBF

LT8580IDD#PBF

TAPE AND REEL

PART MARKING*

LGKH

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 125°C

–40°C to 150°C

–40°C to 125°C

–40°C to 150°C

LT8580EDD#TRPBF

LT8580IDD#TRPBF

LT8580HDD#TRPBF

LT8580EMS8E#TRPBF

LT8580IMS8E#TRPBF

LT8580HMS8E#TRPBF

8-Lead (3mm × 3mm) Plastic DFN

8-Lead Plastic MSOP

LGKH

LT8580HDD#PBF

LT8580EMS8E#PBF

LT8580IMS8E#PBF

LT8580HMS8E#PBF

LGKH

LTGKJ

8-Lead Plastic MSOP

LTGKJ

8-Lead Plastic MSOP

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

8580fa

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LT8580

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 5V, V_SHDN= V_INunless otherwise noted. (Note 2)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

Operating Voltage Range

LT8580E, LT8580I

LT8580H

2.55

2.9

40

V

l

Positive Feedback Voltage

Negative Feedback Voltage

Positive FBX Pin Bias Current

Negative FBX Pin Bias Current

Error Amplifier Transconductance

Error Amplifier Voltage Gain

Quiescent Current

1.185

–3

81

1.204

3

83.3

200

60

1.2

0

0.01

1.220

12

85

V

mV

µA

V

= Positive Feedback Voltage, Current Into Pin

= Negative Feedback Voltage, Current Out of Pin

FBX

81

86

µA

FBX

µmhos

V/V

mA

µA

%/V

V

= 2.5V, Not Switching

= 0V

1.7

1

0.05

SHDN

Quiescent Current in Shutdown

Reference Line Regulation

SHDN

2.5V ≤ V ≤ 40V

IN

l

Switching Frequency, f

R = 56.2k

T

1.23

165

1.5

200

1.77

235

MHz

kHz

OSC

T

R = 422k

Switching Frequency in Foldback

Switching Frequency Set Range

SYNC High Level for Synchronization

SYNC Low Level for Synchronization

SYNC Clock Pulse Duty Cycle

Recommended Minimum SYNC Ratio f

Minimum Off-Time

Compared to Normal f

SYNCing or Free Running

1/6

Ratio

kHz

V

OSC

l

200

1.3

1500

0.4

65

V

%

V

= 0V to 2V

35

SYNC

/f

3/4

100

120

SYNC OSC

ns

Minimum On-Time

l

Switch Current Limit

Minimum Duty Cycle (Note 3)

Maximum Duty Cycle (Notes 3, 4), f

1.2

0.6

0.4

1.5

1

0.8

1.8

1.5

1.4

A

= 1.5MHz

= 200kHz

OSC

Switch V

Switch Leakage Current

Soft-Start Charging Current

I

V

= 0.75A

400

0.01

6

mV

µA

CESAT

SW

= 5V

1

8

SW

l

= 0.5V

4

SS

l

SHDN Minimum Input

Voltage High

Active Mode, SHDN Rising

Active Mode, SHDN Falling

1.23

1.21

1.31

1.27

1.4

1.33

V

l

SHDN Input Voltage Low

SHDN Pin Bias Current

Shutdown Mode

0.3

V

SHDN

V

SHDN

V

SHDN

= 3V

= 1.3V

= 0V

44

12

0

56

15

0.1

µA

9

SHDN Hysteresis

40

mV

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LT8580E is guaranteed to meet performance specifications

from 0°C to 125°C junction temperature. Specifications over the –40°C

to 125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LT8580I is guaranteed over the full –40°C to 125°C operating junction

temperature range. The LT8580H is guaranteed over the full –40°C to

150°C operating junction temperature range. Operating lifetime is derated

at junction temperatures greater than 125°C.

Note 3: Current limit guaranteed by design and/or correlation to static test.

Note 4: Current limit measured at equivalent of listed switching frequency.

Note 5: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 150°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

8580fa

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LT8580

Typical perForMance characTerisTics ^T_A^{= 25°C, unless otherwise specified}

Commanded Switch Current vs SS

Switch Current Limit vs Duty Cycle

Switch Saturation Voltage

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

2.0

1.5

1.0

0.5

0

700

600

500

400

300

200

100

0

0.4

0.6

0.8

1

1.2

60 70

DUTY CYCLE (%)

1

0.2

10 20 30 40 50

80 90

0

0.25

0.5

0.75

1.25

1.5

SS VOLTAGE (V)

SWITCH CURRENT (A)

8580 G03

8580 G01

8580 G02

Switch Current Limit

vs Temperature

Positive and Negative Output

Voltage Regulation

2.0

1.5

1.0

0.5

0

1.220

1.215

1.210

1.205

1.200

1.195

1.190

1.185

1.180

1.175

1.170

30

25

20

15

10

5

0

–5

–10

–15

–20

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

8580 G04

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

8580 G05

Positive and Negative FBX Current

at Output Voltage Regulation

Oscillator Frequency

86

85

84

83

82

81

80

86

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

R

= 56.2k

T

85

84

83

82

81

80

R

T

= 422k

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

–50 –25

25 50 75

125

100 150

0

TEMPERATURE (°C)

8580 G06

8580 G07

8580fa

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For more information www.linear.com/LT8580

LT8580

Typical perForMance characTerisTics ^T_A^{= 25°C, unless otherwise specified}

Oscillator Frequency During

Soft-Start

Internal UVLO

SHDN Pin Current

2.7

2.6

2.5

2.4

2.3

2.2

2.1

30

25

1

125°C

25°C

–40°C

20

15

1/2

1/3

1/4

1/5

1/6

10

5

INVERTING

NONINVERTING

CONFIGURATIONS CONFIGURATIONS

0

0.2 0.4 0.6 0.8

FBX VOLTAGE (V)

1

1.2

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

0

0.25 0.5 0.75

1

1.25 1.5 1.75

2

SHDN VOLTAGE (V)

8580 G08

8580 G09

8580 G10

Minimum On Time

vs Temperature

SHDN Pin Current

Active/Lockout Threshold

1.40

1.38

1.36

1.34

1.32

1.30

1.28

1.26

1.24

1.22

1.20

400

350

300

250

200

150

100

50

400

350

300

250

200

150

100

50

125°C

25°C

–40°C

RECOMMENDED MINIMUM ON TIME

SHDN RISING

SHDN FALLING

MEASURED MINIMUM ON TIME

0

5

10 15 20 25 30 35 40

SHDN VOLTAGE (V)

8580 G11

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

8580 G12

8580 G13

8580fa

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For more information www.linear.com/LT8580

LT8580

pin FuncTions

FBX (Pin 1): Positive and Negative Feedback Pin. For a

sequence. Drive below 1.21V to disable the chip. Drive

above 1.40V to activate the chip and restart the soft-start

sequence. Do not float this pin.

noninverting or inverting converter, tie a resistor from the

FBX pin to V

according to the following equations:

OUT

V

−1.204V

RT (Pin 6): Timing Resistor Pin. Adjusts the switching

frequency. Place a resistor from this pin to ground to set

the frequency to a fixed free running level. Do not float

this pin.

(

)

OUT

R_FBX

=

; Noninverting Converter

83.3µA

+ 3mV

V

(

)

OUT

; InvertingConverter

83.3µA

SS(Pin7):Soft-StartPin.Placeasoft-startcapacitorhere.

Upon start-up, the SS pin will be charged by a (nominally)

280k resistor to about 2.1V.

VC (Pin 2): Error Amplifier Output Pin. Tie external com-

pensation network to this pin.

SYNC (Pin 8): To synchronize the switching frequency to

an outside clock, simply drive this pin with a clock. The

high voltage level of the clock needs to exceed 1.3V, and

the low level should be less 0.4V. Drive this pin to less

than 0.4V to revert to the internal free-running clock. See

theApplicationsInformationsectionformoreinformation.

V (Pin 3): Input Supply Pin. Must be locally bypassed.

IN

SW (Pin 4): Switch Pin. This is the collector of the internal

NPN Power switch. Minimize the metal trace area connec-

ted to this pin to minimize EMI.

SHDN (Pin 5): Shutdown Pin. In conjunction with the

UVLO (undervoltage lockout) circuit, this pin is used

to enable/disable the chip and restart the soft-start

GND (Exposed Pad Pin 9): Ground. Exposed pad must

be soldered directly to local ground plane.

block DiagraM

R

C

V

IN

C

IN

SS

C

7

2

50k

SS

VC

SHDN

5

–

+

DISCHARGE

DETECT

L1

1.3V

280k

D1

SW

UVLO

VC

I

SR2

R

SOFT-

START

4

V

OUT

COMPARATOR

LIMIT

SR1

S

Q2

Q

S

–

+

DRIVER

C1

V

IN

A3

R

Q

Q1

1.204V

REFERENCE

3

+

R

FBX

14.5k

A4

∑

0.02Ω

GND

A1

A2

–

SLOPE

COMPENSATION

FBX

9

1

+

–

÷N

FREQUENCY

FOLDBACK

ADJUSTABLE

OSCILLATOR

14.5k

SYNC

BLOCK

SYNC

RT

8

6

R

T

8580 BD

8580fa

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For more information www.linear.com/LT8580

LT8580

operaTion

TheLT8580usesaconstant-frequency,currentmodecon-

trol scheme to provide excellent line and load regulation.

Refer to the Block Diagram for the following description

of the part’s operation. At the start of each oscillator cycle,

theSRlatch(SR1)isset, whichturnsonthepowerswitch,

Q1. The switch current flows through the internal current

sense resistor, generating a voltage proportional to the

switch current. This voltage (amplified by A4) is added

to a stabilizing ramp and the resulting sum is fed into the

positive terminal of the PWM comparator A3. When this

voltage exceeds the level at the negative input of A3, the

SR latch is reset, turning off the power switch. The level

at the negative input of A3 (VC pin) is set by the error

amplifier A1 (or A2) and is simply an amplified version of

the difference between the feedback voltage (FBX pin) and

the reference voltage (1.204V or 3mV, depending on the

configuration). In this manner, the error amplifier sets the

correct peak current level to keep the output in regulation.

an inverting configuration, the FBX pin is pulled down to

3mV by the R

resistor connected from V

to FBX.

FBX

OUT

Amplifier A1 becomes inactive and amplifier A2 performs

the noninverting amplification from FBX to VC.

SEPIC Topology

As shown in Figure 1, the LT8580 can be configured as

a SEPIC (single-ended primary inductance converter).

This topology allows for the input to be higher, equal, or

lower than the desired output voltage. Output disconnect

is inherently built into the SEPIC topology, meaning no DC

path exists between the input and output. This is useful

for applications requiring the output to be disconnected

from the input source when the circuit is in shutdown.

Inverting Topology

The LT8580 can also work in a dual inductor inverting

topology,asshowninFigure2.Thepart’suniquefeedback

pin allows for the inverting topology to be built by simply

changing the connection of external components. This

solution results in very low output voltage ripple due to

the inductor L2 in series with the output. Abrupt changes

in output capacitor current are eliminated because the

output inductor delivers current to the output during both

the off-time and the on-time of the LT8580 switch.

The LT8580 has an FBX pin architecture that can be used

for either noninverting or inverting configurations. When

configured as a noninverting converter, the FBX pin is

pulled up to the internal bias voltage of 1.204V by the

R

FBX

resistor connected from V

to FBX. Amplifier A2

OUT

becomes inactive and amplifier A1 performs the invert-

ing amplification from FBX to VC. When the LT8580 is in

C2

L1

D1

L1

L2

V

> V

= V

< V

IN

OUT

OR

OUT

OR

•

V

IN

V

OUT

IN

V

SW

V

SW

IN

L2

D1

+

OUT

C1

LT8580

C1

LT8580

•

R1

SHDN

FBX

SHUTDOWN

SHDN

FBX

SHUTDOWN

+

RT

GND

VC

SS

GND

VC

SS

C3

+

SYNC

R

C

R

C

R

T

R

T

C

SS

C

SS

C

8580 F01

8580 F02

Figure 1. SEPIC Topology Allows for the Input to Span

the Output Voltage. Coupled or Uncoupled Inductors

Can Be Used. Follow Noted Phasing if Coupled

Figure 2. Dual Inductor Inverting Topology Results in

Low Output Ripple. Coupled or Uncoupled Inductors

Can Be Used. Follow Noted Phasing if Coupled

8580fa

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LT8580

operaTion

Start-Up Operation

of 300mV to 920mV. This feature reduces the minimum

duty cycle that the part can achieve thus allowing better

control of the switch current during start-up. When the

FBXvoltageispulledoutsideofthisrange,theswitching

frequency returns to normal.

Several functions are provided to enable a very clean

start-up for the LT8580.

• First, the SHDN pin voltage is monitored by an internal

voltage reference to give a precise turn-on voltage level.

Anexternalresistor(orresistordivider)canbeconnected

from the input power supply to the SHDN pin to provide

a user-programmable undervoltage lockout function.

Current Limit and Thermal Shutdown Operation

The LT8580 has a current limit circuit not shown in the

BlockDiagram.Theswitchcurrentisconstantlymonitored

and not allowed to exceed the maximum switch current at

agivendutycycle(seetheElectricalCharacteristicstable).

If the switch current reaches this value, the SR latch (SR1)

is reset regardless of the state of the comparator (A1/

A2). Also, not shown in the Block Diagram is the thermal

shutdown circuit. If the temperature of the part exceeds

approximately165°C,theSR2latchissetregardlessofthe

state of the amplifier (A1/A2). When the part temperature

falls below approximately 160°C, a full soft-start cycle will

then be initiated. The current limit and thermal shutdown

circuits protect the power switch as well as the external

components connected to the LT8580.

• Second, the soft-start circuitry provides for a gradual

ramp-up of the switch current. When the part is brought

out of shutdown, the external SS capacitor is first

discharged (providing protection against SHDN pin

glitches and slow ramping), then an integrated 280k

resistor pulls the SS pin up to ~2.1V. By connecting an

external capacitor to the SS pin, the voltage ramp rate

on the pin can be set. Typical values for the soft-start

capacitor range from 100nF to 1µF.

• Finally,thefrequencyfoldbackcircuitreducestheswitch-

ing frequency when the FBX pin is in a nominal range

8580fa

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For more information www.linear.com/LT8580

LT8580

applicaTions inForMaTion

Setting Output Voltage

For the SEPIC or dual inductor inverting topology (see

Figure 1 and Figure 2):

The output voltage is set by connecting a resistor (R

)

FBX

V_D+ |V_OUT

|

from V

to the FBX pin. R

is determined from the

OUT

FBX

DC ≅

following equation:

V +|V |+ V_D− V

IN

OUT

CESAT

|V_OUT− V

|

FBX

R_FBX

=

The LT8580 can be used in configurations where the duty

cycle is higher than DC , but it must be operated in the

83.3µA

MAX

discontinuous conduction mode so that the effective duty

where V is 1.204V (typical) for noninverting topologies

FBX

cycle is reduced.

(i.e., boost and SEPIC regulators) and 3mV (typical) for

inverting topologies (see the Electrical Characteristics).

Inductor Selection

Power Switch Duty Cycle

General Guidelines: The high frequency operation of the

LT8580allowsfortheuseofsmallsurfacemountinductors.

For high efficiency, choose inductors with high frequency

core material, such as ferrite, to reduce core losses. To

improve efficiency, choose inductors with more volume

for a given inductance. The inductor should have low

In order to maintain loop stability and deliver adequate

current to the load, the power NPN (Q1 in the Block Dia-

gram) cannot remain “on” for 100% of each clock cycle.

The maximum allowable duty cycle is given by:

2

DCR (copper wire resistance) to reduce I R losses, and

(T −MinOffTime)

P

DC_MAX

=

• 100%

must be able to handle the peak inductor current without

saturating. Note that in some applications, the current

handling requirements of the inductor can be lower, such

as in the SEPIC topology, where each inductor only carries

a fraction of the total switch current. Multilayer or chip

inductors usually do not have enough core area to sup-

port peak inductor currents in the 1A to 2A range. To

minimize radiated noise, use a toroidal or shielded induc-

tor. Note that the inductance of shielded types will drop

more as current increases, and will saturate more easily.

See Table 1 for a list of inductor manufacturers. Thorough

lab evaluation is recommended to verify that the following

guidelines properly suit the final application.

T

P

where T is the clock period and Min Off Time (found in

P

the Electrical Characteristics) is typically 100ns.

The application should be designed so that the operating

duty cycle does not exceed DC

.

MAX

The minimum allowable duty cycle is given by:

Min On Time

DC_MIN

=

•100%

T

P

where T is the clock period and Minimum On Time is as

P

shown in the Typical Performance Characteristics.

Table 1. Inductor Manufacturers

The application should be designed so that the operating

Coilcraft

XAL5050, MSD7342, MSS7341 and www.coilcraft.com

LPS4018 Series

duty cycle is at least DC

.

MIN

Duty cycle equations for several common topologies are

Coiltronics DR, DRQ, LD and CD Series

www.coiltronics.com

www.sumida.com

given below, where V is the diode forward voltage drop

Sumida

CDRH8D58/LD, CDRH64B, and

CDRH70D430MN Series

D

and V

is typically 400mV at 0.75A.

CESAT

Würth

WE-PD, WE-DD, WE-TPC,

WE-LHMI and WE-LQS Series

www.we-online.com

For the boost topology:

V_OUT− V + V_D

V_OUT+ V_D− V_CESAT

IN

DC ≅

Minimum Inductance: Although there can be a trade-off

with efficiency, it is often desirable to minimize board

space by choosing smaller inductors. When choosing

8580fa

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LT8580

applicaTions inForMaTion

an inductor, there are two conditions that limit the mini-

mum inductance: (1) providing adequate load current,

and (2) avoiding subharmonic oscillation. Choose an

inductance that is high enough to meet both of these

requirements.

AvoidingSubharmonicOscillations:TheLT8580’sinternal

slopecompensationcircuitcanpreventsubharmonicoscil-

lations that can occur when the duty cycle is greater than

50%, provided that the inductance exceeds a minimum

value. In applications that operate with duty cycles greater

than 50%, the inductance must be at least:

Adequate Load Current : Small value inductors result in

increased ripple currents and thus, due to the limited peak

switch current, decrease the average current that can be

V

2 DC −1

IN

L_MIN



>



1.25 •(DC−300ns • f) • f 1−DC

provided to a load (I ). In order to provide adequate

OUT

for boost topologies (see Figure 15)

load current, L should be at least:

L

= L1

MIN

DC • V

= L1 = L2 for coupled dual inductor topologies

MIN

IN

L_BOOST

>

(see Figure 16 and Figure 17)

||

= L1 L2 for uncoupled dual inductor topologies

MIN

⎛

⎞

⎟

⎠

|V_OUT| •I_OUT

2(f) I

−

⎜

LIM

V • h

L

⎝

IN

(see Figure 16 and Figure 17)

for boost, topologies, or:

DC • V

Maximum Inductance: Excessive inductance can reduce

currentrippletolevelsthataredifficultforthecurrentcom-

parator (A3 in the Block Diagram) to cleanly discriminate,

thus causing duty cycle jitter and/or poor regulation. The

maximum inductance can be calculated by:

IN

L_DUAL

>

⎛

⎞

⎟

⎠

V_OUT•I_OUT

2(f) I

−

−I_OUT

⎜

LIM

V • h

⎝

IN

for the SEPIC and inverting topologies.

where:

V − V

I_MIN-RIPPLE

DC

f

IN

CESAT

L_MAX

=

•

L

= L1 for boost topologies (see Figure 15)

BOOST

where

= L1 = L2 for coupled dual inductor topologies

(see Figure 16 and Figure 17)

DUAL

for boost topologies (see Figure 15)

L

= L1

MIN

= L1 = L2 for coupled dual inductor topologies

(see Figure 16 and Figure 17)

MIN

L

= L1||L2 for uncoupled dual inductor topologies

DUAL

(see Figure 16 and Figure 17)

||

L

= L1 L2 for uncoupled dual inductor topologies

MIN

DC = switch duty cycle (see previous section)

(see Figure 16 and Figure 17)

I

= switch current limit, typically about 1.2A at 50%

LIM

I

= typically 80mA

MIN(RIPPLE)

dutycycle(seetheTypicalPerformanceCharacteristics

Current Rating: Finally, the inductor(s) must have a rating

greater than its peak operating current to prevent inductor

saturation resulting in efficiency loss. In steady state, the

peakinputinductorcurrent(continuousconductionmode

only) is given by:

section).

h=powerconversionefficiency(typically85%forboost

and 83% for dual inductor topologies at high currents).

f = switching frequency

I

= maximum load current

OUT

|V_OUT•I_OUT| V • DC

IN

I_L1-PEAK

=

+

Negative values of L indicate that the output load current

OUT

LT8580.

V • h

2 • L1• f

IN

I

exceeds the switch current limit capability of the

fortheboost,SEPICanddualinductorinvertingtopologies.

8580fa

10

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LT8580

applicaTions inForMaTion

Fordualdualinductortopologies,thepeakoutputinductor

current is given by:

Table 2 shows a list of several ceramic capacitor manufac-

turers. Consultthemanufacturersfordetailedinformation

on their entire selection of ceramic parts.

V_OUT• 1−DC

(

)

I_L2-PEAK=I_OUT

+

Table 2. Ceramic Capacitor Manufacturers

2 • L2 • f

Kemet

www.kemet.com

www.murata.com

www.t-yuden.com

www.tdk.com

For the dual inductor topologies, the total peak current is:

Murata

Taiyo Yuden

TDK

⎡

⎤

V_OUT

V • DC

2 • L • f

IN

I_L-PEAK=I_OUT1+

+

⎢

⎥

h • V

⎣

⎦

IN

Compensation—Adjustment

Note:Peakinductorcurrentislimitedbytheswitchcurrent

limit. Refer to the Electrical Characteristics table and to

the Switch Current Limit vs Duty Cycle plot in the Typical

Performance Characteristics.

To compensate the feedback loop of the LT8580, a series

resistor-capacitornetworkinparallelwithasinglecapacitor

should be connected from the VC pin to GND. For most

applications, the series capacitor should be in the range

of 470pF to 2.2nF with 1nF being a good starting value.

The parallel capacitor should range in value from 10pF to

100pF with 47pF a good starting value. The compensation

Capacitor Selection

Low ESR (equivalent series resistance) capacitors should

beusedattheoutputtominimizetheoutputripplevoltage.

Multilayer ceramic capacitors are an excellent choice, as

they have an extremely low ESR and are available in very

small packages. X5R or X7R dielectrics are preferred, as

these materials retain their capacitance over wider voltage

andtemperatureranges.A0.47µFto10µFoutputcapacitor

is sufficient for most applications. Always use a capacitor

with a sufficient voltage rating. Many ceramic capacitors,

particularly 0805 or 0603 case sizes, have greatly reduced

capacitance at the desired output voltage. Solid tantalum

or OS-CON capacitors can be used, but they will occupy

more board area than a ceramic and will have a higher

ESR with greater output ripple.

resistor, R , is usually in the range of 5k to 50k. A good

C

technique to compensate a new application is to use a

100kΩ potentiometer in place of series resistor R . With

C

the series capacitor and parallel capacitor at 1nF and 47pF

respectively, adjust the potentiometer while observing

the transient response and the optimum value for R can

C

be found. Figure 3 (3a to 3c) illustrates this process for

the circuit of Figure 4 with a load current stepped be-

tween 60mA and 160mA. Figure 3a shows the transient

response with R equal to 2k. The phase margin is poor,

C

as evidenced by the excessive ringing in the output

voltage and inductor current. In Figure 3b, the value of

R is increased to 3k, which results in a more damped

C

Ceramic capacitors also make a good choice for the input

decoupling capacitor, which should be placed as closely

response.Figure3cshowstheresultswhenR isincreased

C

further to 6.04k. The transient response is nicely damped

as possible to the V pin of the LT8580 as well as to the

IN

and the compensation procedure is complete.

inductor connected to the input of the power path. If it is

not possible to optimally place a single input capacitor,

Compensation—Theory

then use one at the V pin of the chip (C ) and one at

IN

VIN

Like all other current mode switching regulators, the

LT8580 needs to be compensated for stable and efficient

operation. Two feedback loops are used in the LT8580—

a fast current loop which does not require compensation,

and a slower voltage loop which does. Standard bode plot

analysis can be used to understand and adjust the voltage

feedback loop.

the input of the power path (C

). See equations in

PWR

Table 4, Table 5 and Table 6 for sizing information. A 1µF

to2.2µFinputcapacitorissufficientformostapplications.

8580fa

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LT8580

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I

STEP

100mA/DIV

STEP

100mA/DIV

V

OUT

500mV/DIV

AC-COUPLED

I

L1

200mA/DIV

8580 F03a

8580 F03b

100µs/DIV

(3a) Transient Response Shows Excessive Ringing

(3b) Transient Response Is Better

I

STEP

100mA/DIV

V

OUT

500mV/DIV

AC-COUPLED

I

L1

200mA/DIV

8580 F03c

100µs/DIV

(3c) Transient Response Is Well Damped

Figure 3. Transient Response

L1

15µH

D1

R

V

OUT

V

IN

12V

5V

200mA

10k

V

IN

SW

FBX

130k

C

OUT

SHDN

4.7µF

C

IN

LT8580

2.2µF

SYNC

RT

VC

R

C

6.04k

GND SS

C

F

47pF

C

3.3nF

R

56.2k

SS

T

0.22µF

8580 F04

Figure 4. 1.5MHz, 5V to 12V Boost Converter

8580fa

12

For more information www.linear.com/LT8580

LT8580

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As with any feedback loop, identifying the gain and phase

contribution of the various elements in the loop is critical.

Figure5showsthekeyequivalentelementsofaboostcon-

verter. Because of the fast current control loop, the power

stage of the IC, inductor and diode have been replaced by

a combination of the equivalent transconductance ampli-

From Figure 5, the DC gain, poles and zeros can be cal-

culated as follows:

2

Output Pole: P1=

2 • π • R_L• C_OUT

1

Error AmpPole: P2 =

2 • π • R +R • C

[

]

O

C

fier g and the current controlled current source which

mp

converts I to (hV /V ) • I . g acts as a current

1

VIN

IN OUT

VIN mp

Error Amp Zero: Z1=

DCGain:

source where the peak input current, I , is proportional

VIN

2 • π • R_C• C_C

to the VC voltage. h is the efficiency of the switching

regulator, and is typically about 85%.

(Breaking Loop at FBX Pin)

Notethatthemaximumoutputcurrentsofg andg are

mp

ma

∂V_C∂I_VIN∂V_OUT∂V

finite.Thelimitsforg areintheElectricalCharacteristics

FBX

mp

A_DC= A_OL(0) =

•

=

∂V

∂V_C∂I_VIN∂V_OUT

section(switchcurrentlimit), andg isnominallylimited

FBX

ma

to about +15µA and –17µA.

⎛

⎞

⎟

⎠

V

V_OUT

R_L

2

0.5R2

R1+ 0.5R2

IN

g

_ma• R₀• g • h •

•

⎜

(

)

mp

⎝

–

1

V

OUT

I

ESR Zero: Z2 =

RHP Zero: Z3 =

VIN

g

mp

2 • π • R_ESR• C_OUT

+

R

ESR

η• V

V_OUT

R

L

IN

•I_VIN

V²• R_L

4 • π • V_O²_UT• L

C

OUT

PL

IN

1.204V

REFERENCE

R1

+

–

f_S

3

V

C

HighFrequency Pole: P3 >

g

ma

R2

FBX

R

O

C

8580 F05

F

1

C

PhaseLead Zero: Z4 =

2 • π • R1• C_PL

1

C : COMPENSATION CAPACITOR

C

PhaseLeadPole: P4 =

Error Amp Filter Pole:

R2

C

: OUTPUT CAPACITOR

: PHASE LEAD CAPACITOR

OUT

R1•

PL

2

2 • π •

• C_PL

C : HIGH FREQUENCY FILTER CAPACITOR

F

R2

g

: TRANSCONDUCTANCE AMPLIFIER INSIDE IC

ma

R1+

: POWER STAGE TRANSCONDUCTANCE AMPLIFIER

mp

2

R : COMPENSATION RESISTOR

C

R : OUTPUT RESISTANCE DEFINED AS V

L

DIVIDED BY I

LOAD(MAX)

OUT

R : OUTPUT RESISTANCE OF g

O

ma

R1, R2: FEEDBACK RESISTOR DIVIDER NETWORK

1

C_C

10

P5 =

,C_F<

R

ESR

: OUTPUT CAPACITOR ESR

R_C• R_O

R_C+R_O

η: CONVERTER EFFICIENCY (~85% AT HIGHER CURRENTS)

2 • π •

• C_F

Figure 5. Boost Converter Equivalent Model

The current mode zero (Z3) is a right-half plane zero

which can be an issue in feedback control design, but is

manageable with proper external component selection.

8580fa

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Using the circuit in Figure 4 as an example, Table 3 shows

the parameters used to generate the bode plot shown in

Figure 6.

In Figure 6, the phase is –126° when the gain reaches 0dB

giving a phase margin of 54°. The crossover frequency is

14kHz, which is more than three times lower than the fre-

quencyoftheRHPzerotoachieveadequatephasemargin.

140

120

100

80

0

–45

Diode Selection

PHASE

–90

Schottkydiodes, withtheirlowforward-voltagedropsand

fast switching speeds, are recommended for use with the

–135

–180

–225

–270

–315

–360

LT8580. For applications where V (see Tables 4, 5 and

60

R

6) < 40V, the Diodes, Inc. SBR1V40LP is a good choice.

54° AT

40

GAIN

100

14kHz

Where V > 40V, the Diodes Inc. DFLS1100 works well.

R

20

These diodes are rated to handle an average forward

0

current of 1A.

–20

10

1k

10k

100k

1M

Oscillator

FREQUENCY (Hz)

8580 F06

The operating frequency of the LT8580 can be set by the

internal free-running oscillator. When the SYNC pin is

driven low (< 0.4V), the frequency of operation is set by a

Figure 6. Bode Plot for Example Boost Converter

resistor from R to ground. An internally trimmed timing

T

Table 3. Bode Plot Parameters

capacitor resides inside the IC. The oscillator frequency

is calculated using the following formula:

PARAMETER

VALUE

60

UNITS

W

COMMENT

Application Specific

Not Adjustable

Adjustable

R

L

C

4.7

10

µF

OUT

85.5

f_OSC

=

R

mW

kW

pF

ESR

O

(R_T+ 1)

is in MHz and R is in kΩ. Conversely, R

T

300

3300

47

where f

OSC

T

C

(in kΩ) can be calculated from the desired frequency

(in MHz) using:

pF

Optional/Adjustable

Adjustable

F

0

pF

PL

R

C

6.04

130

14.6

12

kW

V

85.5

f_OSC

R_T=

−1

R1

R2

Adjustable

Not Adjustable

Application Specific

Not Adjustable

Application Specific

Adjustable

V

OUT

V

IN

Clock Synchronization

5

V

TheoperatingfrequencyoftheLT8580canbesynchronized

to an external clock source. To synchronize to the external

source, simply provide a digital clock signal into the SYNC

pin. The LT8580 will operate at the SYNC clock frequency.

The LT8580 will revert to the internal free-running oscilla-

tor clock after SYNC is driven low for a few free-running

clock periods.

g

ma

g

mp

L

200

7

µmho

mho

µH

15

f

S

1.5

MHz

8580fa

14

For more information www.linear.com/LT8580

LT8580

applicaTions inForMaTion

Driving SYNC high for an extended period of time effec-

tively stops the operating clock and prevents latch SR1

from becoming set (see the Block Diagram). As a result,

the switching operation of the LT8580 will stop.

This capacitor is slowly charged to ~2.1V by an internal

280k resistor once the part is activated. SS pin voltages

below ~1.1V reduce the internal current limit. Thus, the

gradualrampingoftheSSvoltagealsograduallyincreases

the current limit as the capacitor charges. This, in turn,

allows the output capacitor to charge gradually toward its

final value while limiting the start-up current.

The duty cycle of the SYNC signal must be between 35%

and 65% for proper operation. Also, the frequency of the

SYNC signal must meet the following two criteria:

In the event of a commanded shutdown or lockout (SHDN

pin), internal undervoltage lockout (UVLO) or a thermal

lockout,thesoft-startcapacitorisautomaticallydischarged

to ~200mV before charging resumes, thus assuring that

the soft-start occurs after every reactivation of the chip.

(1) SYNC may not toggle outside the frequency range of

200kHz to 1.5MHz unless it is stopped low to enable

the free-running oscillator.

(2) The SYNC frequency can always be higher than the

free-running oscillator frequency, f , but should not

OSC

be less than 25% below f

.

Shutdown

OSC

The SHDN pin is used to enable or disable the chip. For

most applications, SHDN can be driven by a digital logic

source. Voltages above 1.4V enable normal active op-

eration. Voltages below 300mV will shutdown the chip,

resulting in extremely low quiescent current.

Operating Frequency Selection

There are several considerations in selecting the operat-

ing frequency of the converter. The first is staying clear

of sensitive frequency bands, which cannot tolerate any

spectral noise. For example, in products incorporating RF

communications, the 455kHz IF frequency is sensitive to

any noise, therefore switching above 600kHz is desired.

Some communications have sensitivity to 1.1MHz, and in

thatcase, a1.5MHzswitchingconverterfrequencymaybe

employed. The second consideration is the physical size

of the converter. As the operating frequency goes up, the

inductor and filter capacitors go down in value and size.

The trade-off is efficiency, since the switching losses due

to NPN base charge (see Thermal Calculations), Schottky

diode charge, and other capacitive loss terms increase

proportionally with frequency.

While the SHDN voltage transitions through the lockout

voltagerange(0.3Vto1.21V)thepowerswitchisdisabled

and the SR2 latch is set (see the Block Diagram). This

causesthesoft-startcapacitortobegindischarging,which

continues until the capacitor is discharged and active op-

eration is enabled. Although the power switch is disabled,

SHDN voltages in the lockout range do not necessarily

reduce quiescent current until the SHDN voltage is near

or below the shutdown threshold.

Also note that SHDN can be driven above V or V

as

OUT

IN

long as the SHDN voltage is limited to less than 40V.

Soft-Start

ACTIVE

(NORMAL OPERATION)

TheLT8580containsasoft-startcircuittolimitpeakswitch

currents during start-up. High start-up current is inherent

in switching regulators in general since the feedback loop

is saturated due to V

regulator tries to charge the output capacitor as quickly as

possible, which results in large peak currents.

1.40V

(HYSTERESIS AND TOLERANCE)

1.21V

LOCKOUT

being far from its final value. The

OUT

(POWER SWITCH OFF,

SS CAPACITOR DISCHARGED)

0.3V

SHUTDOWN

(LOW QUIESCENT CURRENT)

The start-up current can be limited by connecting an

external capacitor (typically 100nF to 1µF) to the SS pin.

0.0V

8580 F07

Figure 7. Chip States vs SHDN Voltage

8580fa

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LT8580

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Configurable Undervoltage Lockout

For example, to disable the LT8580 for V voltages below

IN

3.5V using the single resistor configuration, choose:

Figure 8 shows how to configure an undervoltage lock-

out (UVLO) for the LT8580. Typically, UVLO is used in

situations where the input supply is current-limited, has

a relatively high source resistance, or ramps up/down

slowly. A switching regulator draws constant power from

the source, so source current increases as source voltage

drops. This looks like a negative resistance load to the

source and can cause the source to current-limit or latch

low under low source voltage conditions. UVLO prevents

the regulator from operating at source voltages where

these problems might occur.

3.5V −1.27V

R_UVLO1

=

= 187k

⎛

⎜

⎝

⎞

⎟

⎠

1.27V

∞

+ 12µA

To activate the LT8580 for V voltages greater than

IN

4.5V using the double resistor configuration, choose

R

= 10k and:

UVLO2

4.5V − 1.31V

R_UVLO1

=

= 22.1k

⎛

⎜

⎝

⎞

⎟

⎠

1.31V

10k

+ 12µA

The shutdown pin comparator has voltage hysteresis with

typicalthresholdsof1.31V(rising)and1.27V(falling). Re-

Internal Undervoltage Lockout

The LT8580 monitors the V supply voltage in case V

sistorR

isoptional.R

canbeincludedtoreduce

UVLO2

IN

the overall UVLO voltage variation caused by variations

drops below a minimum operating level (typically about

2.35V). When V is detected low, the power switch is

in SHDN pin current (see the Electrical Characteristics).

A good choice for R

value for R

of the following:

IN

is ≤10k 1%. After choosing a

can be determined from either

UVLO2

UVLO2 UVLO1

deactivated, and while sufficient V voltage persists, the

IN

, R

soft-start capacitor is discharged. After V is detected

IN

high, the power switch will be reactivated and the soft-

V

⁺− 1.31V

start capacitor will begin charging.

IN

R_UVLO1

=

⎛

⎜

⎝

⎞

⎟

⎠

1.31V

+12µA

Thermal Considerations

R

UVLO2

For the LT8580 to deliver its full output power, it is impera-

tive that a good thermal path be provided to dissipate the

heat generated within the package. This is accomplished

bytakingadvantageofthethermalpadontheundersideof

the IC. It is recommended that multiple vias in the printed

circuit board be used to conduct heat away from the IC

and into a copper plane with as much area as possible.

or

V

⁻− 1.27V

IN

R_UVLO1

⎛

⎜

⎝

⎞

1.27V

+12µA

⎟

R

⎠

UVLO2

+

–

where V and V are the V voltages when rising or

IN

falling, respectively.

V

IN

V

IN

ACTIVE/

LOCKOUT

1.3V

–

+

R

UVLO1

SHDN

12µA

AT 1.3V

R

UVLO2

(OPTIONAL)

GND

8580 F08

Figure 8. Configurable UVLO

8580fa

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LT8580

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Thermal Lockout

P

= 117mW

= 169mW

= 44mW

= 30mW

SW

If the die temperature reaches approximately 165°C, the

part will go into thermal lockout, the power switch will be

turned off and the soft-start capacitor will be discharged.

The part will be enabled again when the die temperature

has dropped by ~5°C (nominal).

BAC

BDC

INP

Total LT8580 power dissipation (P ) = 361mW

TOT

ThermalresistancefortheLT8580isinfluencedbythepres-

ence of internal, topside or backside planes. To calculate

die temperature, use the appropriate thermal resistance

number and add in worst-case ambient temperature:

Thermal Calculations

Power dissipation in the LT8580 chip comes from four

primary sources: switch I R loss, NPN base drive (AC),

NPN base drive (DC), and additional input current. The

following formulas can be used to approximate the power

losses. These formulas assume continuous mode opera-

tion, so they should not be used for calculating efficiency

in discontinuous mode or at light load currents.

2

T = T + θ • P

TOT

J

A

JA

whereT =junctiontemperature,T =ambienttemperature,

J

A

and θ is the thermal resistance from the silicon junction

JA

to the ambient air.

V_OUT•I_OUT

The published θ value is 43°C/W for the 3mm × 3mm

AverageInput Current: I =

JA

IN

V • h

DFN package and 35°C/W to 40°C/W for the MSOP ex-

IN

posed pad package. In practice, lower θ values can be

JA

Switch Conduction Loss: P =(DC)(I )(V )

IN

SW

obtained if the board layout uses ground as a heat sink.

For instance, thermal resistances of 34.7°C/W for the

DFN package and 22.5°C/W for the MSOP package were

obtained on a board designed with large ground planes.

BaseDriveLoss(AC): P = 20ns(I )(V_OUT)(f)

IN

BAC

(V )(I )(DC)

IN IN

BaseDriveLoss(DC): P

=

BDC

40

V Ramp Rate

IN

Input Power Loss: P = 6mA (V )

INP

IN

While initially powering a switching converter application,

theV ramprateshouldbelimited.HighV rampratescan

where:

IN

causeexcessiveinrushcurrentsinthepassivecomponents

of the converter. This can lead to current and/or voltage

overstress and may damage the passive components or

the chip. Ramp rates less than 500mV/µs, depending on

componentparameters,willgenerallypreventtheseissues.

Also,becarefultoavoidhot-plugging.Hot-pluggingoccurs

when an active voltage supply is “instantly” connected or

switchedtotheinputoftheconverter.Hot-pluggingresults

in very fast input ramp rates and is not recommended.

Finally, for more information, refer to Linear application

note AN88, which discusses voltage overstress that can

occurwhenaninductivesourceimpedanceishot-plugged

to an input pin bypassed by ceramic capacitors.

V

= switch on voltage (see Typical Performance

SW

Characteristics for Switch Saturation Voltage)

DC = duty cycle (see the Power Switch Duty Cycle sec-

tion for formulas)

h = power conversion efficiency (typically 85% at high

currents)

Example: boost configuration, V = 5V, V

OUT

= 12V,

IN

OUT

I

= 0.2A, f = 1.25MHz, V = 0.5V:

D

I = 0.56A

IN

DC = 62.0%

8580fa

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For more information www.linear.com/LT8580

LT8580

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Layout Hints

theboardreducesdietemperatureandincreasesthepower

capability of the LT8580. Provide as much copper area as

possible around this pad. Adding multiple feedthroughs

aroundthepadtothegroundplanewillalsohelp.Figure10

and Figure 11 show the recommended component place-

mentfortheboostandSEPICconfigurations,respectively.

As with all high frequency switchers, when considering

layout, care must be taken to achieve optimal electrical,

thermal and noise performance. One will not get adver-

tised performance with a careless layout. For maximum

efficiency, switch rise and fall times are typically in the

10ns to 20ns range. To prevent noise, both radiated and

conducted,thehighspeedswitchingcurrentpath,shownin

Figure 9, must be kept as short as possible. This is imple-

mented in the suggested layout of a boost configuration in

Figure10.Shorteningthispathwillalsoreducetheparasitic

trace inductance. At switch-off, this parasitic inductance

produces a flyback spike across the LT8580 switch. When

operatingathighercurrentsandoutputvoltages,withpoor

layout,thisspikecangeneratevoltagesacrosstheLT8580

that may exceed its absolute maximum rating. A ground

plane should also be used under the switcher circuitry to

prevent interplane coupling and overall noise.

Layout Hints for Inverting Topology

Figure12showsrecommendedcomponentplacementfor

the dual inductor inverting topology. Input bypass capaci-

tor, C1, should be placed close to the LT8580, as shown.

The load should connect directly to the output capacitor,

C2, for best load regulation. The local ground may be tied

into the system ground plane at the C3 ground terminal.

The cut ground copper at D1’s cathode is essential to

obtain low noise. This important layout issue arises due

to the chopped nature of the currents flowing in Q1 and

D1. If they are both tied directly to the ground plane before

being combined, switching noise will be introduced into

the ground plane. It is almost impossible to get rid of this

noise, once present in the ground plane. The solution

is to tie D1’s cathode to the ground pin of the LT8580

before the combined currents are dumped in the ground

plane as drawn in Figure 2, Figure 13 and Figure 14. This

single layout technique can virtually eliminate high

frequency “spike” noise, so often present on switching

regulator outputs.

The VC and FBX components should be kept as far away

as practical from the switch node. The ground for these

components should be separated from the switch cur-

rent path. Failure to do so can result in poor stability or

subharmonic oscillation.

Board layout also has a significant effect on thermal re-

sistance. The exposed package ground pad is the copper

platethatrunsundertheLT8580die.Thisisagoodthermal

path for heat out of the package. Soldering the pad onto

DIFFERENCES FROM LT3580

L1

LT8580 is very similar to LT3580. However, LT8580 does

deviate from LT3580 in a few areas:

D1

C1

V

OUT

•ꢀ 65V, 1A switch

SW

LT8580

•ꢀ 40V V and SHDN absolute maximum rating

IN

HIGH

FREQUENCY

SWITCHING

PATH

V

IN

C2 LOAD

•ꢀ FB renamed to FBX

•ꢀ 5V FBX absolute maximum rating

GND

8580 F09

Figure 9. High Speed “Chopped” Switching

Path for Boost Topology

8580fa

18

For more information www.linear.com/LT8580

LT8580

applicaTions inForMaTion

GND

SYNC

1

2

3

4

8

7

6

5

9

C1

SYNC

1

2

3

4

8

7

6

5

9

V

IN

C1

SHDN

V

IN

L1

L2

SHDN

SW

L1

SW

C2

VIAS TO GROUND

PLANE REQUIRED

TO IMPROVE

D1

C2

VIAS TO GROUND

PLANE REQUIRED

TO IMPROVE

D1

C3

THERMAL

PERFORMANCE

8580 F10

THERMAL

V

OUT

PERFORMANCE

8580 F11

V

OUT

Figure 10. Suggested Component Placement for Boost Topology

(Both DFN and MSOP Packages. Not to Scale). Pin 9 (Exposed

Pad) Must Be Soldered Directly to the Local Ground Plane for

Adequate Thermal Performance. Multiple Vias to Additional

Ground Planes Will Improve Thermal Performance

Figure 11. Suggested Component Placement for SEPIC Topology

(Both DFN And MSOP Packages. Not to Scale). Pin 9 (Exposed

Pad) Must Be Soldered Directly to the Local Ground Plane for

Adequate Thermal Performance. Multiple Vias to Additional

Ground Planes Will Improve Thermal Performance

GND

SYNC

1

2

3

4

8

9

C1

7

V

IN

6

SHDN

5

L1

SW

C2

D1

L2

VIAS TO GROUND

PLANE REQUIRED

TO IMPROVE

C3

THERMAL

PERFORMANCE

8580 F12

V

OUT

Figure 12. Suggested Component Placement for Inverting Topology (Both DFN and MSOP Packages. Not to Scale).

Note Cut in Ground Copper at Diode’s Cathode. Pin 9 (Exposed Pad) Must be Soldered Directly to Local Ground Plane

for Adequate Thermal Performance. Multiple Vias to Additional Ground Planes Will Improve Thermal Performance

8580fa

19

For more information www.linear.com/LT8580

LT8580

applicaTions inForMaTion

V

–(V + V )

IN OUT

CESAT

C2

L1

L2

SW

SWX

V

IN

–V

OUT

D1

Q1

+

C1

C3

R

LOAD

+

8580 F13

Figure 13. Switch-On Phase of an Inverting Converter. L1 and L2 Have Positive dI/dt

V

+ V + V

V

D

IN

OUT

D

C2

L1

L2

SW

SWX

V

IN

–V

OUT

D1

Q1

+

C1

C3

R

LOAD

+

8580 F14

Figure 14. Switch-Off Phase of an Inverting Converter. L1 and L2 Currents Have Negative dI/dt

8580fa

20

For more information www.linear.com/LT8580

LT8580

applicaTions inForMaTion

BOOST CONVERTER COMPONENT SELECTION

Table 4. Boost Design Equations

PARAMETERS/EQUATIONS

L1

15µH

D1

Pick V , V , and f

to calculate equations below

Step 1:

Inputs

IN OUT

OSC

V

OUT

V

IN

12V

5V

200mA

Step 2:

DC

V_OUT– V_IN(MIN)+0.5V

10k

DC_MAX

DC_MIN

=

V_OUT+0.5V– 0.4V

V

SW

FBX

R

IN

FBX

130k

V_OUT– V_IN(MAX)+0.5V

C

4.7µF

OUT

=

SHDN

V_OUT+0.5V– 0.4V

C

IN

LT8580

2.2µF

Step 3:

L1

SYNC

RT

VC

(V_IN(MIN)– 0.4V)•DC_MAX

f_OSC• 0.3A

(1)

(2)

L_TYP

=

R

C

6.04k

GND SS

C

F

47pF

C

3.3nF

R

56.2k

SS

T

(V_IN(MIN)– 0.4V)•(2 •DC_MAX– 1)

L_MIN

0.22µF

1.25 •(DC_MAX−300ns • f_OSC)• f_OSC•(1–DC_MAX

(V_IN(MIN)– 0.4V)•DC_MAX

=

)

8580 F15

(3)

(4)

L_MAX1

Figure 15. Boost Converter: The Component Values and Voltages

Given Are Typical Values for a 1.5MHz, 5V to 12V Boost

f_OSC• 0.08A

(V_IN(MAX)– 0.4V)•DC_MIN

f_OSC• 0.08A

L_MAX2

=

The LT8580 can be configured as a boost converter as in

Figure15.Thistopologyallowsforpositiveoutputvoltages

that are higher than the input voltage. A single feedback

resistorsetstheoutputvoltage.Foroutputvoltageshigher

than 60V, see the Charge Pump Aided Regulators section.

•ꢀSolve equations 1 to 4 for a range of L values

•ꢀThe minimum of the L value range is the higher of L and L

TYP

MIN

•ꢀThe maximum of the L value range is the lower of L

and L

.

MAX1

MAX2

Step 4:

RIPPLE

(V_IN(MIN)– 0.4V)•DC_MAX

I_RIPPLE(MIN)

=

I

f_OSC•L₁

Table4isastep-by-stepsetofequationstocalculatecom-

ponent values for the LT8580 when operating as a boost

converter. Input parameters are input and output voltage,

(V_IN(MAX)– 0.4V)•DC_MIN

f_OSC•L₁

I_RIPPLE(MAX)

=

Step 5:

OUT

andf

respectively).

⎛

⎞

andswitchingfrequency(V ,V

I_RIPPLE(MIN)

IN OUT

OSC

I

_OUT(MIN)= ⎜1A −

⎟•(1−DC_MAX

)

I

2

Refer to the Applications Information section for further

information on the design equations presented in Table 4.

⎝

⎠

⎛

⎞

I_RIPPLE(MAX)

I

_OUT(MAX)= ⎜1A −

⎟•(1−DC_MIN

)

2

⎝

⎠

Variable Definitions:

V

> V ; I

> I

Step 6:

D1

R

OUT AVG OUT

V = Input Voltage

IN

Step 7:

I_OUT•DC_MAX

C_OUT

≥

C

V

OUT

= Output Voltage

OUT

f_OSC• 0.005 • V_OUT

Step 8:

IN

DC = Power Switch Duty Cycle

C

_IN≥ C_VIN+C_PWR

≥

C

I_RIPPLE(MAX)

1A •DC_MAX

f

I

= Switching Frequency

OSC

OUT

+

40 • f_OSC• 0.005 • V

8 • f_OSC• 0.005 • V

IN(MIN)

IN(MAX)

= Maximum Average Output Current

= Inductor Ripple Current

•ꢀRefer to the Capacitor Selection Section for definition of C and C

VIN

PWR

Step 9:

RIPPLE

V_OUT−1.204V

R_FBX

=

R

FBX

83.3µA

Step

10:

T

85.5

f_OSC

R_T

=

–1; f_OSCin MHz and R_Tin kΩ

R

Note 1: This table uses 1A for the peak switch current. Refer to the

Electrical Characteristics Table and Typical Performance Characteristics

plots for the peak switch current at an operating duty cycle.

Note 2: The final values for C

and C may deviate from the previous

IN

OUT

equations in order to obtain desired load transient performance.

8580fa

21

For more information www.linear.com/LT8580

LT8580

applicaTions inForMaTion

Table 5. SEPIC Design Equations

PARAMETERS/EQUATIONS

SEPIC CONVERTER COMPONENT SELECTION

(COUPLED OR UNCOUPLED INDUCTORS)

Pick V , V

and f

to calculate equations below

Step 1:

Inputs

IN OUT

OSC

C1

1µF

L1

22µH

D1

V

OUT

V

•

IN

Step 2:

DC

V

_OUT+0.5V

12V

9V TO 16V

DC_MAX

DC_MIN

=

240mA

V

_IN(MIN)+ V_OUT+0.5V– 0.4V

L2

22µH

487k

V_OUT+0.5V

V

SW

FBX

=

R

IN

•

FBX

V

_IN(MAX)+ V_OUT+0.5V– 0.4V

130k

C

4.7µF

OUT

SHDN

C

Step 3:

L

IN

LT8580

(V_IN(MIN)– 0.4V)•DC_MAX

f_OSC• 0.3A

4.7µF

(1)

(2)

(3)

L_TYP

=

SYNC

RT

VC

R

C

16.2k

GND SS

(V_IN(MIN)– 0.4V)•(2 •DC_MAX– 1)

C

F

L_MIN

22pF

C

SS

C

1nF

R

84.5k

1.25 •(DC_MAX−300ns • f_OSC)• f_OSC•(1–DC_MAX

)

T

0.22µF

8580 F16

(V_IN(MIN)– 0.4V)•DC_MAX

f_OSC• 0.08A

L_MAX

Figure 16. SEPIC Converter: The Component Values and Voltages

Given Are Typical Values for a 1MHz, 9V to 16V Input to 12V

Output SEPIC Converter

•ꢀSolve equations 1, 2 and 3 for a range of L values

•ꢀThe minimum of the L value range is the higher of L and L

TYP

MIN

•ꢀThe maximum of the L value range is L

•ꢀL = L1 = L2 for coupled inductors

•ꢀL = L1||L2 for uncoupled inductors

MAX

Step 4:

RIPPLE

(V_IN(MIN)– 0.4V)•DC_MAX

=

The LT8580 can also be configured as a SEPIC, as shown

in Figure 16. This topology allows for positive output

voltages that are lower, equal or higher than the input volt-

age. Output disconnect is inherently built into the SEPIC

topology, meaning no DC path exists between the input

and output due to capacitor C1.

I_RIPPLE(MIN)

I

f_OSC•L

(V_IN(MAX)– 0.4V)•DC_MIN

f_OSC•L

I_RIPPLE(MAX)

=

Step 5:

⎛

⎞

I_RIPPLE(MIN)

I

_OUT(MIN)= ⎜1A −

⎟• 1−DC

I

(

)

MAX

OUT

2

⎝

⎠

⎛

⎞

I_RIPPLE(MAX)

Table 5 is a step-by-step set of equations to calculate com-

ponent values for the LT8580 when operating as a SEPIC

converter. Input parameters are input and output voltage,

I

_OUT(MAX)= ⎜1A −

⎟• 1−DC

(

)

MIN

2

⎝

⎠

V

> V + V ; I

> I

Step 6:

D1

Step 7:

C1

R

IN

OUT AVG

OUT

and switching frequency (V , V

and f , respectively).

IN OUT

OSC

C1 ≥ 1µF; V

≥ V

IN

RATING

Refer to the Applications Information section for further

information on the design equations presented in Table 5.

Step 8:

I_OUT(MIN)•DC_MAX

f_OSC• 0.005 • V_OUT

C_OUT

≥

C

OUT

Variable Definitions:

Step 9:

C

_IN≥ C_VIN+C_PWR≥

C

V = Input Voltage

IN

I_RIPPLE(MAX)

1A •DC_MAX

40 • f_OSC• 0.005 • V

+

8 • f_OSC• 0.005 • V_IN(MAX)

V

OUT

= Output Voltage

IN(MIN)

•ꢀRefer to the Capacitor Selection Section for definition of C and C

DC = Power Switch Duty Cycle

VIN

PWR

Step 10:

FBX

V

_OUT−1.204V

83.3µA

R_FBX

=

f

I

= Switching Frequency

R

OSC

= Maximum Average Output Current

OUT

Step 11:

85.5

f_OSC

R_T

=

–1; f_OSCin MHz and R_Tin kΩ

R

T

= Inductor Ripple Current

RIPPLE

Note 1: This table uses 1A for the peak switch current. Refer to the

Electrical Characteristics Table and Typical Performance Characteristics

plots for the peak switch current at an operating duty cycle.

Note 2: The final values for C , C and C1 may deviate from the

OUT IN

previous equations in order to obtain desired load transient performance.

8580fa

22

For more information www.linear.com/LT8580

LT8580

applicaTions inForMaTion

DUAL INDUCTOR INVERTING CONVERTER COMPONENT

SELECTION (COUPLED OR UNCOUPLED INDUCTORS)

Table 6. Dual Inductor Inverting Design Equations

PARAMETERS/EQUATIONS

Pick V , V

and f

to calculate equations below

Step 1:

Inputs

IN OUT

OSC

C1

1µF

L1

22µH

L2

22µH

Step 2:

DC

V_OUT+0.5V

_IN(MIN)+ V_OUT+0.5V– 0.4V

V

OUT

–15V

90mA (V = 5V)

DC_MAX

=

V

•

IN

5V TO 40V

V

IN

10k

D1

210mA (V = 12V)

IN

420mA (V = 40V)

IN

V_OUT+0.5V

_IN(MAX)+ V_OUT+0.5V– 0.4V

DC_MIN

=

V

SW

FBX

R

IN

FBX

182k

V

SHDN

Step 3:

L

C

4.7µF

(V_IN(MIN)– 0.4V)•DC_MAX

f_OSC• 0.3A

IN

4.7µF

OUT

LT8580

(1)

L_TYP

=

SYNC

RT

VC

R

C

13.7k

GND SS

(V_IN(MIN)– 0.4V)•(2 •DC_MAX– 1)

C

F

L_MIN

(2)

(3)

47pF

C

10nF

R

113k

SS

T

1.25 •(DC_MAX−300ns • f_OSC)• f_OSC•(1–DC_MAX

)

0.22µF

8580 F17

(V_IN(MIN)– 0.4V)•DC_MAX

f_OSC• 0.08A

L_MAX

Figure 17. Dual Inductor Inverting Converter: The Component

Values and Voltages Given Are Typical Values for a 750kHz

Wide Input (5V to 40V) to –15V Inverting Topology Using

Coupled Inductors

•ꢀSolve equations 1, 2 and 3 for a range of L values

•ꢀThe minimum of the L value range is the higher of L and L

TYP

MIN

•ꢀThe maximum of the L value range is L

•ꢀL = L1 = L2 for coupled inductors

•ꢀL = L1||L2 for uncoupled inductors

MAX

Due to its unique FBX pin, the LT8580 can work in a dual

inductor inverting configuration as in Figure 17. Chang-

ing the connections of L2 and the Schottky diode in the

SEPIC topology results in generating negative output

voltages. This solution results in very low output voltage

ripple due to inductor L2 being in series with the output.

Output disconnect is inherently built into this topology

due to the capacitor C1.

Step 4:

RIPPLE

(V_IN(MIN)– 0.4V)•DC_MAX

I_RIPPLE(MIN)

=

I

f_OSC•L

(V_IN(MAX)– 0.4V)•DC_MIN

f_OSC•L

I_RIPPLE(MAX)

=

Step 5:

⎛

⎞

I_RIPPLE(MIN)

I

_OUT(MIN)= ⎜1A −

⎟• 1−DC

I

(

)

MAX

OUT

2

⎝

⎠

⎞

⎛

I_RIPPLE(MAX)

I

_OUT(MAX)= ⎜1A −

⎟• 1−DC

(

)

MIN

2

⎝

⎠

Table 6 is a step-by-step set of equations to calculate

component values for the LT8580 when operating as a

dual inductor inverting converter. Input parameters are

V

> V + |V |; I

IN OUT AVG

> I

Step 6:

D1

R

OUT

C1 ≥ 1µF; V

≥ V

+ |V

|

OUT

Step 7:

C1

RATING

IN(MAX)

input and output voltage, and switching frequency (V ,

Step 8:

IN

I_RIPPLE(MAX)

C_OUT

≥

C

V

and f

respectively). Refer to the Applications

Information section for further information on the design

OUT

OSC

8 • f_OSC(0.005 • V_OUT

)

Step 9:

C

_IN≥ C_VIN+C_PWR≥

equations presented in Table 6.

C

IN

I_RIPPLE(MAX)

8 • f_OSC• 0.005 • V_IN(MAX)

1A •DC_MAX

+

40 • f_OSC• 0.005 • V

Variable Definitions:

IN(MIN)

•ꢀRefer to the Capacitor Selection Section for definition of C and C

VIN

PWR

V = Input Voltage

IN

Step 10:

FBX

V_OUT+ 3mV

R_FBX

=

R

V

OUT

= Output Voltage

83.3µA

DC = Power Switch Duty Cycle

Step 11:

T

85.5

f_OSC

R_T=

–1; f_OSCin MHz and R_Tin kΩ

R

f

I

= Switching Frequency

OSC

OUT

Note 1: This table uses 1A for the peak switch current. Refer to the

Electrical Characteristics Table and Typical Performance Characteristics

plots for the peak switch current at an operating duty cycle.

= Maximum Average Output Current

= Inductor Ripple Current

Note 2: The final values for C , C and C1 may deviate from the

previous equations in order to obtain desired load transient performance.

RIPPLE

OUT IN

8580fa

23

For more information www.linear.com/LT8580

LT8580

Typical applicaTions

1.5MHz, 5V to 12V Output Boost Converter

L1

15µH

D1

V

OUT

V

IN

12V

5V

200mA

10k

V

SW

FBX

VC

IN

130k

C

OUT

SHDN

4.7µF

C

IN

LT8580

2.2µF

SYNC

RT

6.04k

3.3nF

GND SS

47pF

56.2k

0.22µF

8580 TA02a

L1: WÜRTH 15µH WE-LQS 74404054150

D1: DIODES INC. SBR1U40LP

C

: 2.2µF, 35V, 0805, X7R

OUT

IN

: 4.7µF, 16V, 0805, X7R

Efficiency and Power Loss

100

480

420

380

300

240

180

120

60

90

80

70

60

50

40

30

20

EFFICIENCY

POWER LOSS

0

200

0

50

LOAD CURRENT (mA)

100

150

8580 TA02b

50mA to 150mA to 50mA Output Load Step

I

STEP

100mA/DIV

V

OUT

500mV/DIV

AC-COUPLED

I

L1

500mA/DIV

8580 TA02c

100µs/DIV

8580fa

24

For more information www.linear.com/LT8580

LT8580

Typical applicaTions

750kHz, –15V Output Inverting Converter Accepts 5V to 40V Input

C1

1µF

L1

22µH

L2

22µH

V

OUT

V

•

IN

–15V

90mA (V = 5V)

5V TO 40V

IN

10k

D1

210mA (V = 12V)

IN

420mA (V = 40V)

IN

V

SW

FBX

VC

IN

182k

SHDN

C

4.7µF

IN

OUT

LT8580

4.7µF

SYNC

RT

13.7k

10nF

GND SS

47pF

0.22µF

113k

8580 TA03a

L1, L2: COILCRAFT 22µH MSD7342-223

D1: CENTRAL SEMI CMMSH1-60

C

: 4.7µF, 50V, 1206, X5R

IN

: 4.7µF, 25V, 1206, X7R

OUT

C1: 1µF, 100V, 0805, X7S

Efficiency and Power Loss (V_IN= 12V)

90

640

80

70

60

50

40

30

20

10

560

480

400

320

240

160

80

EFFICIENCY

POWER LOSS

0

50

200

100

150

LOAD CURRENT (mA)

8580 TA03b

60mA to 160mA to 60mA Output Load Step (V_IN= 12V)

I

STEP

100mA/DIV

V

OUT

200mV/DIV

AC-COUPLED

I

+ I

L1 L2

200mA/DIV

8580 TA03c

200µs/DIV

8580fa

25

For more information www.linear.com/LT8580

LT8580

Typical applicaTions

1.2MHz Inverting Converter Generates –48V Output From 12V Input

C2

2.2µF

49.9Ω

C1

1µF

L1

150µH

L2

330µH

V

OUT

V

IN

–48V

12V

70mA

619k

D1

V

SW

FBX

VC

IN

576k

SHDN

C

IN

OUT

LT8580

1µF

2.2µF

SYNC

RT

20.5k

4.7nF

GND SS

47pF

0.33µF

69.8k

8580 TA04a

L1: COOPER 150µH DR74-151

L2: COOPER 330µH DR74-331

D1: DIODES, INC. DFLS1100

C

: 1µF, 50V, 0805, X7R

OUT

IN

: 2.2µF, 100V, 1206, X7R

C1: 1µF, 100V, 0805, X7S

C2: 2.2µF, 100V, 1206, X7S

Efficiency and Power Loss

90

1040

920

800

680

560

440

320

200

80

70

60

50

40

30

20

EFFICIENCY

POWER LOSS

0

10

20

30

40

50

60

70

LOAD CURRENT (mA)

8580 TA04b

Switching Waveforms

Start-Up Waveforms

V

SW

20V/DIV

SW

20V/DIV

V

OUT

V

20mV/DIV

OUT

10V/DIV

AC-COUPLED

I

+ I

L1 L2

200mA/DIV

I

+ I

L1 L2

200mA/DIV

8580 TA04c

8580 TA04d

200µs/DIV

8580fa

26

For more information www.linear.com/LT8580

LT8580

Typical applicaTions

VFD (Vacuum Fluorescent Display) Power Supply Switches at 1MHz

Danger High Voltage! Operation by High Voltage Trained Personnel Only

D5

V

OUT3

180V

C5

1µF

D4

D2

20mA*

22Ω

C4

1µF

D3

D1

V

OUT2

120V

C3

1µF

30mA*

22Ω

L1

C2

1µF

68µH

V

OUT1

V

IN

60V

9V TO 16V

60mA*

487k

V

SW

FBX

VC

IN

698k

SHDN

C

C1

1µF

IN

LT8580

1µF

SYNC

RT

22.1k

4.7nF

GND SS

330pF

0.47µF

84.5k

8580 TA05a

*MAX TOTAL OUTPUT POWER 3.5W

L1: WÜRTH 68µH WE-LQS 74404084680

D1-D5: DIODES, INC. DFLS1100

C

: 1µF, 100V, 1206, X7R

IN

C1-C5: 1µF, 100V, 1206, X7S

Efficiency and Power Loss

(V_IN= 12V with Load on V_OUT3

)

Start-Up Waveforms

90

80

70

60

50

40

30

20

960

880

800

720

640

560

480

400

V

OUT3

50V/DIV

V

OUT2

50V/DIV

V

OUT1

50V/DIV

I

L1

200mA/DIV

EFFICIENCY

POWER LOSS

8580 TA05c

2ms/DIV

0

0.5

1

1.5

2

2.5

3

3.5

OUTPUT POWER (W)

8580 TA05b

8580fa

27

For more information www.linear.com/LT8580

LT8580

Typical applicaTions

550kHz SEPIC Converter Generates 24V from 15V to 30V Input

C1

1µF

L1

47µH

D1

V

OUT

V

•

IN

24V

15V TO 30V

195mA (V = 15V)

300mA (V = 24V)

IN

L2

47µH

1M

V

SW

FBX

VC

IN

274k

SHDN

C

IN

OUT

LT8580

2.2µF

4.7µF

SYNC

RT

12.7k

3.3nF

GND SS

22pF

0.1µF

154k

8580 TA06a

L1, L2: COILCRAFT 47µH MSD7342-473

D1: DIODES INC. DFLS1100

C

: 2.2µF, 35V, 0805, X7R

IN

: 4.7µF, 35V, 1206, X7R

OUT

C1: 1µF, 100V, 0805, X7S

Efficiency and Power Loss

(V_IN= 24V)

90

80

70

60

50

40

30

20

10

1400

1250

1100

950

800

650

500

350

200

EFFICIENCY

POWER LOSS

0

50

100

150

200

250

300

LOAD CURRENT (mA)

8580 TA06b

Transient Response with 100mA to 225mA

to 100mA Output Load Step (V_IN= 24V)

I

STEP

100mA/DIV

V

OUT

500mV/DIV

AC-COUPLED

I

+ I

L1 L2

500mA/DIV

8580 TA06c

100µs/DIV

8580fa

28

For more information www.linear.com/LT8580

LT8580

package DescripTion

Please refer to http://www.linear.com/product/LT8580#packaging for the most recent package drawings.

DD Package

8-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1698 Rev C)

0.70 ±0.05

3.5 ±0.05

2.10 ±0.05 (2 SIDES)

1.65 ±0.05

PACKAGE

OUTLINE

0.25 ±0.05

0.50

BSC

2.38 ±0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

R = 0.125

0.40 ±0.10

TYP

5

8

3.00 ±0.10

(4 SIDES)

1.65 ±0.10

(2 SIDES)

PIN 1

TOP MARK

(NOTE 6)

(DD8) DFN 0509 REV C

4

1

0.25 ±0.05

0.75 ±0.05

0.200 REF

0.50 BSC

2.38 ±0.10

BOTTOM VIEW—EXPOSED PAD

0.00 – 0.05

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON TOP AND BOTTOM OF PACKAGE

8580fa

29

For more information www.linear.com/LT8580

LT8580

package DescripTion

Please refer to http://www.linear.com/product/LT8580#packaging for the most recent package drawings.

MS8E Package

8-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1662 Rev K)

BOTTOM VIEW OF

EXPOSED PAD OPTION

1.88

(.074)

1

0.29

REF

1.88 ±0.102

(.074 ±.004)

1.68

(.066)

0.889 ±0.127

(.035 ±.005)

0.05 REF

DETAIL “B”

5.10

(.201)

MIN

3.20 – 3.45

(.126 – .136)

1.68 ±0.102

(.066 ±.004)

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

DETAIL “B”

8

NO MEASUREMENT PURPOSE

3.00 ±0.102

(.118 ±.004)

(NOTE 3)

0.65

(.0256)

BSC

0.52

(.0205)

REF

0.42 ±0.038

(.0165 ±.0015)

8

7 6 5

TYP

RECOMMENDED SOLDER PAD LAYOUT

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

4.90 ±0.152

(.193 ±.006)

DETAIL “A”

0.254

(.010)

0° – 6° TYP

GAUGE PLANE

1

2

3

4

0.53 ±0.152

(.021 ±.006)

1.10

(.043)

MAX

0.86

(.034)

REF

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.22 – 0.38

(.009 – .015)

TYP

0.1016 ±0.0508

(.004 ±.002)

0.65

(.0256)

BSC

MSOP (MS8E) 0213 REV K

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD

SHALL NOT EXCEED 0.254mm (.010") PER SIDE.

8580fa

30

For more information www.linear.com/LT8580

LT8580

revision hisTory

REV

DATE

DESCRIPTION

PAGE NUMBER

A

09/16 Changed Minimum On-Time in the Electrical Characteristics table to typical room value instead of worst case.

Added Minimum On-Time vs Temperature graph.

3

5

Added text and equations explaining minimum on-time.

9

Clarified inductor paragraph in the Applications Information section.

10, 11

11, 14

Adjusted R , R , R , g and resultant gain and phase margin numbers and plot to better reflect applications and the

C

L

O

ma

Electrical Characteristics table.

Clarified Thermal Calculations section.

17

21, 22, 23

32

Corrected L

equation.

MIN

Clarified the Related Parts table.

8580fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

31

For more information www.linear.com/LT8580

LT8580

Typical applicaTion

12V Battery Stabilizer Survives 40V Transients

Efficiency and Power Loss

(V_IN= 12V)

C1

1µF

L1

22µH

D1

90

80

70

60

50

40

30

20

10

800

700

600

500

400

300

200

100

0

V

OUT

V

•

IN

12V

9V TO 16V

UP TO 40V

TRANSIENT

240mA

L2

22µH

487k

V

SW

FBX

VC

IN

130k

SHDN

C

4.7µF

IN

OUT

LT8580

4.7µF

SYNC

RT

16.2k

1nF

GND SS

22pF

EFFICIENCY

POWER LOSS

0.22µF

84.5k

8580 TA07a

0

40

80

120

160

200

240

LOAD CURRENT (mA)

L1, L2: WÜRTH 22µH WE-DD 744877220

D1: DIODES INC. DFLS1100

8580 TA07b

C

: 4.7µF, 50V, 1206, X7R

IN

OUT

: 4.7µF, 25V, 1206, X7R

C1: 1µF, 100V, 0805, X7S

relaTeD parTs

PART NUMBER

DESCRIPTION

COMMENTS

LT1613

550mA (I ), 1.4MHz High Efficiency Step-Up DC/DC Converter V : 0.9V to 10V, V

= 34V, I = 3mA, I < 1µA,

Q SD

SW

IN

OUT(MAX)

ThinSOT Package

LT1618

1.5A (I ), 1.4MHz High Efficiency Step-Up DC/DC Converter

V : 1.6V to 18V, V

= 35V, I = 1.8mA, I < 1µA,

Q SD

SW

IN

OUT(MAX)

MS10, 3mm × 3mm DFN Packages

LT1930/LT1930A 1A (I ), 1.2MHz/2.2MHz High Efficiency Step-Up DC/DC

V : 2.6V to 16V, V

= 34V, I = 4.2mA/5.5mA, I < 1µA,

Q SD

SW

Converter

IN

OUT(MAX)

ThinSOT Package

LT1935

2A (I ), 40V, 1.2MHz High Efficiency Step-Up DC/DC Converter V : 2.3V to 16V, V

= 38V, I = 3mA, I < 1µA,

Q SD

SW

IN

ThinSOT Package

LT1944/LT1944-1 Dual Output 350mA (I ), Constant Off-Time, High Efficiency

V : 1.2V to 15V, V

= 34V, I = 20µA, I < 1µA,

Q SD

SW

IN

Step-Up DC/DC Converter

MS10 Package

LT1946/LT1946A 1.5A (I ), 1.2MHz/2.7MHz High Efficiency Step-Up DC/DC

V : 2.6V to 16V, V

= 34V, I = 3.2mA, I < 1µA,

Q SD

SW

IN

Converter

MS8E Package

LT3467

LT3477

LT3479

LT3580

LT3581

LT3579

LT8582

1.1A (I ), 1.3MHz High Efficiency Step-Up DC/DC Converter

V : 2.4V to 16V, V

= 40V, I = 1.2mA, I < 1µA,

Q SD

SW

IN

ThinSOT, 2mm × 3mm DFN Packages

42V, 3A, 3.5MHz Boost, Buck-Boost, Buck LED Driver

V : 2.5V to 25V, V = 40V, Analog/PWM, I < 1µA,

IN

OUT(MAX)

SD

QFN, TSSOP-20E Packages

3A Full-Featured DC/DC Converter with Soft-Start and Inrush

Current Protection

V : 2.5V to 24V, V

= 40V, I = 5mA, I < 1µA,

Q SD

IN

OUT(MAX)

DFN, TSSOP Packages

2A (I ), 42V, 2.5MHz, High Efficiency Step-Up DC/DC

V : 2.5V to 32V, V

= 42V, I = 1mA, I = <1µA,

Q SD

SW

IN

OUT(MAX)

Converter

3mm × 3mm DFN-8, MSOP-8E

3.3A (I ), 42V, 2.5MHz, High Efficiency Step-Up DC/DC

V : 2.5V to 22V, V = 42V, I = 1.9mA, I = <1µA,

SW

IN

OUT(MAX)

Q

SD

Converter

4mm × 3mm DFN-14, MSOP-16E

6A (I ), 42V, 2.5MHz, High Efficiency, Step-Up DC/DC

V : 2.5V to 16V, V = 42V, I = 1.9mA, I = <1µA,

SW

IN

OUT(MAX)

Q

SD

Converter

4mm × 5mm QFN-20, TSSOP-20

Dual Channel, 3A (I ), 42V, 2.5MHz, High Efficiency Step-Up

V : 2.5V to 22V, V = 42V, I = 2.1mA, I = <1µA,

SW

IN

OUT(MAX)

Q

SD

DC/DC Converter

4mm × 7mm DFN-24

8580fa

LT 0916 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

32

For more information www.linear.com/LT8580

●

 LINEAR TECHNOLOGY CORPORATION 2014

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LT8580


型号：	LT8580EDD#TRPBF
厂家：	Linear
描述：	LT8580 - Boost/SEPIC/Inverting DC/DC Converter with 1A, 65V Switch, Soft-Start and Synchronization; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C
文件：	总32页 (文件大小：436K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT8580EDD#TRPBF [Linear]

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