LT8710 [Linear]
Synchronous SEPIC/ Inverting/Boost Controller with Output Current Control;
| 型号： | LT8710 |
| 厂家： | 
Linear |
| 描述： | Synchronous SEPIC/ Inverting/Boost Controller with Output Current Control |
| 文件： | 总44页 (文件大小：646K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT8710
Synchronous SEPIC/
Inverting/Boost Controller with
Output Current Control
DescripTion
FeaTures
The LT®8710 is a synchronous PWM DC/DC controller
with a rail-to-rail output current monitor and control. The
LT8710isidealformanytypesofpowersupplytopologies
and can be easily configured for boost, SEPIC, inverting,
or flyback configurations.
n
Wide Input Range: 4.5V to 80V
n
Rail-to-Rail Output Current Monitor and Control
n
Input Voltage Regulation for High Impedance Inputs
n
C/10 or Power Good Indication Pin
n
MODE Pin for Forced CCM or Pulse-Skipping
Operation
Switching Frequency Up to 750kHz
TheLT8710’srail-to-railoutputcurrentmonitorandcontrol
allows the part to be configured in current limited applica-
tions such as battery charging. The FLAG pin can be used
as a power good indication or C/10 indication allowing for
accurate bulk and float battery voltages.
n
n
Easily Configurable as a Boost, SEPIC, Inverting or
Flyback Converter with Single Feedback Pin
n
Can Be Synchronized to External Clock
n
High Gain EN/FBIN Pin Accepts Slowly Varying Input
The LT8710’s switching frequency range can be set be-
tween 100kHz and 750kHz using an external resistor or
synchronized to an external clock.
Signals
20-Lead TSSOP Package
n
applicaTions
The LT8710 also features innovative EN/FBIN pin cir-
cuitry that allows for slowly varying input signals and
an adjustable undervoltage lockout function. The pin is
also used for input voltage regulation to avoid collapsing
a high impedance input supply. Additional features such
as frequency foldback and soft-start are integrated. The
LT8710 is available in a 20-lead TSSOP package.
n
High Power Local Power Supply
n
Wide Input Voltage Range SEPIC/Inverting
n
Lead Acid Battery Charger
n
Automotive Engine Control Unit (ECU) Power
n
Solar Panel Power Converter
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, Including 7579816.
Typical applicaTion
300kHz Inverter Generates –5V from a 4.5V to 25V Input
Efficiency and Power Loss
10µF ×2
100
90
80
70
65
50
40
30
20
8
7
6
5
4
3
2
1
0
2.2µH
2.2µH
V
–5V
7A
OUT
V
IN
4.5V TO 25V
330µF
+
499Ω
1.5m
100µF
×2
4m
0.47µF
BG
CSN
CSP TG
V
IN
ISN
+
13.3k
10k
120µF
ISP
LT8710
V
IN
V
IN
= 5V
EN/FBIN
MODE
60.4k
BIAS
INTV
= 12V
CC
2.2µF
0
1
2
3
4
5
6
7
INTV
2.2µF
EE
10µF
×4
LOAD CURRENT (A)
INTV
RT
FBX
8710 TA01b
CC
FLAG
V
C
118k
11.5k
3.3nF
SYNC GND
IMON
SS
100pF
47nF
220nF
8710 TA01a
8710f
1
For more information www.linear.com/LT8710
LT8710
absoluTe MaxiMuM raTings
(Note 1)
V Voltage ................................................ –0.3V to 80V
MODE Voltage............................................ –0.3V to 40V
IN
BIAS Voltage.............................................. –0.3V to 80V
EN/FBIN Voltage......................................... –0.3V to 80V
BG Voltage ............................................................Note 5
TG Voltage ............................................................Note 5
RT Voltage ................................................... –0.3V to 5V
SS Voltage ................................................... –0.3V to 3V
FBX Voltage.................................................................5V
FBX Current............................................................–1mA
INTV Voltage ............................................ –0.3V to 7V
CC
INTV Voltage......................................................Note 5
EE
CSP Voltage ................................................. –0.3V to 2V
CSN Voltage................................................. –0.3V to 2V
ISP Voltage .................................ISN – 0.4V to ISN + 2V
ISN Voltage ................................................ –0.3V to 80V
IMON Voltage............................................ –0.3V to 2.5V
Operating Junction Temperature Range
V Voltage.................................................... –0.3V to 2V
LT8710E............................................. –40°C to 125°C
LT8710I.............................................. –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)...................300°C
C
SYNC Voltage............................................ –0.3V to 5.5V
FLAG Voltage ............................................... –0.3V to 7V
FLAG Current ......................................................... 1mA
pin conFiguraTion
TOP VIEW
FBX
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
GND
V
C
SYNC
RT
SS
FLAG
IMON
ISN
MODE
EN/FBIN
CSP
21
GND
ISP
CSN
BIAS
V
IN
INTV
INTV
CC
EE
TG 10
BG
FE PACKAGE
20-LEAD PLASTIC TSSOP
T
= 125°C, θ = 38°C/W, θ = 10°C/W
JA JC
JMAX
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
LT8710EFE#PBF
LT8710IFE#PBF
TAPE AND REEL
PART MARKING*
LT8710FE
PACKAGE DESCRIPTION
20-Lead Plastic TSSOP
20-Lead Plastic TSSOP
TEMPERATURE RANGE
–40°C to 125°C
LT8710EFE#TRPBF
LT8710IFE#TRPBF
LT8710FE
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
8710f
2
For more information www.linear.com/LT8710
LT8710
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications for each channel are at TA = 25°C. VIN = 12V, VEN/FBIN = 12V, VBIAS = 12V, unless
otherwise noted (Note 2).
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
Minimum Operating Input Voltage
V
IN
V
IN
OR V
4.25
4.5
V
V
BIAS
if V
≥ 4.5V
0
BIAS
Quiescent Current, I
V
BIAS
V
BIAS
= V = 7.5V, Not Switching
4
5.5
5.5
7.5
mA
mA
VIN
ISN
= 6.3V, V
= V = 0V, Not Switching
INTVEE
ISN
Quiescent Current in Shutdown
EN/FBIN Active Mode
V
= 0V
0
1
µA
V
EN/FBIN
l
EN/FBIN Rising
1.64
1.7
1.76
l
l
EN/FBIN Chip Enable
EN/FBIN Rising
EN/FBIN Falling
1.22
1.18
1.3
1.26
1.38
1.34
V
V
EN/FBIN Chip Enable Hysteresis
EN/FBIN Input Voltage Low
EN/FBIN Pin Bias Current
44
mV
V
l
Shutdown Mode
0.3
V
V
V
V
= 3V
44
19.5
17.5
0
60
25
22.5
0.1
µA
µA
µA
µA
EN/FBIN
EN/FBIN
EN/FBIN
EN/FBIN
= 1.7V
= 1.6V
= 0V
14
13
l
l
SS Charge Current
V
= 0V, Current Flows Out of SS Pin
7
10.1
50
13.8
82
µA
SS
SS Low Detection Voltage
SS Hi Detection Voltage
Part Exiting Undervoltage Lockout
18
mV
SS Rising
SS Falling
1.5
1.3
1.8
1.7
2.1
2.05
V
V
SS Hi Detection Hysteresis
100
mV
Low Dropout Regulators, INTV and INTV
CC
EE
l
INTV Voltage
I
= 10mA
INTVCC
6.2
6.3
6.4
V
CC
l
l
INTV Undervoltage Lockout
INTV Rising
3.88
3.5
4
3.73
4.12
3.95
V
V
CC
CC
INTV Falling
CC
INTV Undervoltage Lockout Hysteresis
270
mV
CC
INTV Dropout Voltage
V
V
– INTV , V = 6V, V
= 0V, I = 10mA
INTVCC
BIAS
255
280
mV
mV
CC
IN
CC IN
BIAS
– V
, V = 0V, V
= 6V, I
= 10mA
INTVCC
BIAS
INTVCC IN
INTV Load Regulation
V
V
= 12V, V
= 0V, I
= 0mA to 80mA
= 0mA to 40mA
–0.44
–0.34
–2
–2
%
%
CC
IN
IN
BIAS
INTVCC
= 12V, I
INTVCC
= 0V, V
BIAS
INTV Line Regulation
10V ≤ V ≤ 80V, V
= 0V, I
= 10mA
= 10mA
–0.003
–0.006
–0.03
–0.03
%/V
%/V
CC
IN
BIAS
INTVCC
≤ 80V, V = 0V, I
IN INTVCC
10V ≤ V
BIAS
INTV Maximum External Load Current
5
mA
V
CC
l
INTV Voltage, V
– V
I = 10mA
INTVEE
6.03
6.18
6.33
EE
BIAS
INTVEE
l
l
INTV Undervoltage Lockout,
V
BIAS
V
BIAS
– V
– V
Rising
Falling
3.24
2.94
3.42
3.22
3.6
3.48
V
V
EE
INTVEE
INTVEE
V
– V
BIAS
INTVEE
INTV Undervoltage Lockout
200
mV
EE
Hysteresis, V
– V
INTVEE
BIAS
INTV Dropout Voltage, V
V
= 6V, I = 10mA
INTVEE
0.75
V
EE
INTVEE
BIAS
Control Loops (Refer to Block Diagram to Locate Amplifiers)
l
l
Current Limit Voltage, V
– V
V
V
= 1.1V, Minimum Duty Cycle
= 1.1V, Maximum Duty Cycle
46
23
50
31
54
38
mV
mV
CSP
CSN
FBX
FBX
l
l
V
FBX
V
FBX
= 1.4V, MODE = 0V, Minimum Duty Cycle
= 1.4V, MODE = 0V, Maximum Duty Cycle
–23
–38
–32
–51
–41
–65
mV
mV
l
FBX Positive Output Regulation Voltage,
EA1
1.191
1.213
1.237
V
l
FBX Negative Output Regulation Voltage,
EA2
–2
9.6
21
mV
8710f
3
For more information www.linear.com/LT8710
LT8710
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications for each channel are at TA = 25°C. VIN = 12V, VEN/FBIN = 12V, VBIAS = 12V, unless
otherwise noted (Note 2).
PARAMETER
CONDITIONS
MIN
81.9
81.1
TYP
83.7
83.1
200
MAX
85.6
85.2
UNITS
µA
l
l
Positive FBX Pin Bias Current
Negative FBX Pin Bias Current
V
FBX
V
FBX
= Positive FBX Reg Voltage, Current into Pin
= Negative FBX Reg Voltage, Current Out of Pin
µA
FBX Amp Transconductance,
EA1 or EA2
ΔI = 2μA
µmhos
FBX Amp Voltage Gain, EA1 or EA2
FBX Line Regulation
70
V/V
4.5V ≤ V ≤ 80V, V
= 0V
–0.02
–0.001
0.02
%/V
IN
BIAS
l
l
l
l
Output Current Sense Regulation
V
ISN
V
ISN
V
ISN
V
ISN
= 80V, V = 1V
43
43
40
17
50
50
50
25
57
57
60
34
mV
mV
mV
mV
FBX
Voltage, V – V
= 12V, V = 1V
ISP
ISN
FBX
= 0V, V = 1V
FBX
= 12V, V = 1V, INTV in UVLO and V > 1.8V
FBX
EE
SS
l
l
IMON Regulation Voltage, EA3
V
V
= 1V
1.184
0.885
1.213
0.916
1.24
0.947
V
V
FBX
FBX
= 1V, INTV in UVLO and V > 1.8V
EE
SS
Output Current Sense Amp
Transconductance, A6
ΔI = 10μA
1000
µmhos
Output Current Sense Amp Voltage
Gain, A6
11.9
V/V
Output Current Sense Amp Input
Dynamic Range, A6
Negative Input Range, V – V
–51.8
mV
mV
ISP
ISN
Positive Input Range, V – V
500
ISP
ISN
IMON Amp Transconductance, EA3
IMON Amp Voltage Gain, EA3
ΔI = 2μA, V = 1V
165
65
µmhos
V/V
FBX
V
V
= 1V
= 1V
FBX
FBX
l
EN/FBIN Input Regulation Voltage, EA4
EN/FBIN Amp Transconductance, EA4
EN/FBIN Amp Voltage Gain, EA4
MODE Forced CCM Threshold
1.55
1.607
140
55
1.662
V
ΔI = 2µA, V = 1V
µmhos
V/V
FBX
V
= 1V
FBX
l
l
To Exit Forced CCM Mode, MODE Rising
To Enter Forced CCM Mode, MODE Falling
1.19
1.125
1.224
1.175
1.258
1.23
V
V
MODE Forced CCM Threshold
Hysteresis
49
mV
l
l
l
DCM Comparator Threshold in
Pulse-Skipping Mode, MODE = 2V
V
V
V
= 80V, To Enter DCM Mode, V – V Falling
–4.5
–4.5
–7.5
2.8
2.8
2.8
10
10
13
mV
mV
mV
ISN
ISN
ISN
ISP
ISN
= 12V, To Enter DCM Mode, V – V Falling
ISP ISN
= 0V, To Enter DCM Mode, V – V Falling
ISP
ISN
l
l
l
DCM Comparator Threshold in
Forced CCM, MODE =0V
V
V
V
= 80V, To Enter DCM Mode, V – V Falling
–220
–220
–220
–300
–300
–300
–380
–380
–380
mV
mV
mV
ISN
ISN
ISN
ISP
ISN
= 12V, To Enter DCM Mode, V – V Falling
ISP
ISN
= 0V, To Enter DCM Mode, V – V Falling
ISP
ISN
Oscillator
l
l
Switching Frequency, f
R = 46.4k
T
640
85
750
100
860
115
kHz
kHz
OSC
T
R = 357k
Switching Frequency in Foldback
Switching Frequency Range
SYNC High Level for Sync
Compared to Normal f
1/5
ratio
kHz
V
OSC
l
l
l
Free-Running or Synchronizing
100
1.5
750
SYNC Low Level for Sync
0.4
80
V
SYNC Clock Pulse Duty Cycle
V
= 0V to 3V
20
%
SYNC
Recommended Min SYNC Ratio
SYNC OSC
3/4
f
/f
8710f
4
For more information www.linear.com/LT8710
LT8710
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications for each channel are at TA = 25°C. VIN = 12V, VEN/FBIN = 12V, VBIAS = 12V, unless
otherwise noted (Note 2).
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Gate Drivers, BG and TG
BG Rise Time
C
BG
C
BG
C
TG
C
TG
= 3300pF (Note 3)
= 3300pF (Note 3)
= 3300pF (Note 3)
= 3300pF (Note 3)
24
21
15
16
ns
ns
ns
ns
BG Fall Time
TG Rise Time
TG Fall Time
BG and TG Non-Overlap Time
TG Rising to BG Rising, C = C = 3300pF (Note 3)
80
45
140
90
220
150
ns
ns
BG
TG
BG Falling to TG Falling, C = C = 3300pF (Note 3)
BG
TG
BG Minimum On-Time
C
C
C
C
= C = 3300pF
150
100
0
420
480
150
770
ns
ns
ns
ns
BG
BG
BG
BG
TG
BG Minimum Off-Time
= C = 3300pF
TG
TG Minimum On-Time
= C = 3300pF
TG
TG Minimum Off-Time
= C = 3300pF
290
TG
C/10 and Power Good Indicators, FLAG
FLAG C/10 Indicator Threshold
l
l
V
V
– V Falling, V = 1.215V
1
4
5
10
16
23
mV
mV
ISP
ISP
ISN
FBX
– V Rising, V = 1.215V
ISN
FBX
FLAG C/10 Indicator Hysteresis
5
mV
l
l
FLAG Power Good Threshold for
Positive FBX Voltage
V
V
Rising, V – V = 0V
1.127
1.062
1.153
1.095
1.184
1.126
V
V
FBX
FBX
ISP
ISN
Falling, V – V = 0V
ISP
ISN
l
l
FLAG Power Good Threshold for
Negative FBX Voltage
V
V
Falling, V – V = 0V
46
103
68.5
126
90
152
mV
mV
FBX
FBX
ISP
ISN
Rising, V – V = 0V
ISP
ISN
FLAG Power Good Hysteresis for
Positive or Negative FBX Voltage
58
mV
FLAG Anti-Glitch
Delay from C/10 or Power Good
Threshold Trip to FLAG Toggle
100
9
µs
mV
µA
l
FLAG Output Voltage Low
FLAG Leakage Current
100µA into FLAG Pin
50
1
V
FLAG
= 7V, FLAG Off
0.01
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT8710E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the
–40°C to 125°C operating temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT8710I is guaranteed over the full –40°C to 125°C operating junction
temperature range.
Note 3: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 4: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation over the specified maximum operating junction
temperature may impair device reliability.
Note 5: Do not apply a positive or negative voltage or current source to the
BG, TG, and INTV pins, otherwise permanent damage may occur.
EE
8710f
5
For more information www.linear.com/LT8710
LT8710
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted.
Max Current Limit vs Duty Cycle
(CSP - CSN)
Max Current Limit vs Temperature
at Min DC (CSP - CSN)
Max Current Limit vs SS
(CSP - CSN)
60
50
40
30
20
10
0
60
55
50
45
40
35
30
25
20
–20
–25
–30
–35
–40
–45
–50
–55
–60
56
54
52
50
48
46
44
–26
f
= 300kHz
OSC
–28
–30
–32
–34
–36
–38
0.0 0.2 0.4 0.6 0.8
SS (V)
1
1.2 1.4 1.6
0
10 20 30 40 50 60 70 80 90 100
–50 –25
0
25
50
75 100 125
DUTY CYCLE (%)
TEMPERATURE (°C)
8710 G03
8710 G01
8710 G02
Positive and Negative FBX
Current at Output Voltage
Regulation
Positive and Negative Output
Voltage Regulation (FBX)
Input Voltage Regulation
(EN/FBIN)
86
85
84
83
82
81
80
86
85
84
83
82
81
80
1.63
1.62
1.61
1.60
1.59
1.58
1.57
1.2225
1.2200
1.2175
1.2150
1.2125
1.2100
1.2075
15.0
12.5
10.0
7.5
5.0
2.5
0
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
8710 G05
8710 G06
8710 G04
Output Current Sense Regulation
Voltage vs FBX (ISP-ISN and IMON)
1.30
Input Voltage Regulation vs FBX
(EN/FBIN)
Output Current Sense Regulation
Voltage (ISP-ISN and IMON)
2.0
1.9
1.8
1.7
1.6
1.5
1.4
57.5
55.0
52.5
50.0
47.5
45.0
42.5
1.2175
60
55
50
45
40
35
30
1.2150
1.2125
1.25
IMON
IMON
1.20
AVE ISP-ISN
1.2100
1.2075
1.2050
1.2025
1.15
1.10
1.05
1.00
AVE ISP-ISN
0.6 0.7 0.8 0.9
1
1.1
1.2 1.3
–50 –25
0
25
50
75 100 125
0.6 0.7 0.8 0.9
1
1.1 1.2 1.3
FBX (V)
TEMPERATURE (°C)
FBX (V)
8710 G07
8710 G08
8710 G09
8710f
6
For more information www.linear.com/LT8710
LT8710
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted.
DCM Thresholds (ISP-ISN)
Power Good Thresholds (FBX)
C/10 Thresholds (ISP-ISN)
6
5
4
3
2
1
0
–280
–290
–300
–310
–320
–330
–340
14
12
10
8
1.16
140
130
120
110
100
90
1.15
1.14
1.13
1.12
1.11
1.10
1.09
1.08
RISING
RISING
MODE = 0V, FCM
MODE = 2V, DCM
6
FALLING
4
FALLING
80
70
60
2
0
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
8710 G10
8710 G12
8710 G11
EN/FBIN Chip Enable and Active
Mode Thresholds
MODE Forced CCM Thresholds
EN/FBIN Pin Current
35
30
25
20
15
10
1.24
1.23
1.22
1.21
1.20
1.19
1.18
1.17
1.40
1.38
1.36
1.34
1.32
1.30
1.28
1.26
1.75
1.73
1.71
–40°C
25°C
125°C
RISING ONLY
RISING
RISING, EXIT FCM
1.69
1.67
1.65
1.63
1.61
1.59
FALLING, ENTER FCM
FALLING
1.57
1.55
0
1.14
1.20
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
–50 –25
0
25
50
75
100 125
–50 –25
0
25
50
75
100 125
EN/FBIN VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
8710 G15
8710 G13
8710 G14
Oscillator Frequency During
Soft-Start
Oscillator Frequency vs
Temperature
BG and TG Transition Time
900
800
700
600
500
400
1
80
BG RISING
BG FALLING
TG RISING
TG FALLING
70
60
50
40
30
R
T
= 46.4kΩ
1/2
1/3
200
100
0
R
= 357kΩ
T
INVERTING
NONINVERTING
CONFIGURATIONS
10
0
CONFIGURATIONS
0
–50 –25
0
25
50
75 100 125
0
0.2
0.4
0.6
0.8
1
1.2
0
2
4
6
8
10
TEMPERATURE (°C)
FBX VOLTAGE (V)
CAP LOAD (nF)
8710 G16
8710 G17
8710 G18
8710f
7
For more information www.linear.com/LT8710
LT8710
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted.
Minimum Operating Input Voltage
INTVCC vs Temperature
INTVCC UVLO vs Temperature
4.35
4.33
4.31
4.29
6.40
6.36
4.2
4.1
I
= 10mA
INTVCC
RISING
3.9
3.8
3.7
3.6
3.5
4.25
4.23
4.21
4.19
4.17
4.15
6.28
6.24
6.20
FALLING
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
8710 G19
8710 G20
8710 G21
INTVCC Current Limit vs VIN
or BIAS
INTVCC Dropout from VIN
or BIAS
INTVEE vs Temperature
150
125
100
75
500
450
400
350
300
250
200
6.28
6.24
6.20
6.16
6.12
6.08
I
= 10mA
INTVEE
V
IN
INTV > 3.5V
CC
BIAS
BIAS
V
IN
INTV > 3.5V
CC
50
V
OR BIAS
IN
25
INTV < 3.5V
CC
0
10
20
30
40
50
60
70
80
0
10 20 30 40 50 60 70 80
INTV LOAD CURRENT (mA)
–50 –25
0
25
50
75 100 125
INPUT VOLTAGE (V)
TEMPERATURE (°C)
CC
8710 G22
8710 G23
8710 G24
INTVEE UVLO vs Temperature
INTVEE Current Limit vs BIAS
INTVEE Dropout (BIAS = 6V)
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
3.6
3.5
3.4
3.3
3.2
3.1
3.0
75
60
45
30
15
0
–40°C
25°C
125°C
BIAS - INTV = 5V
EE
RISING
FALLING
0
10
20
30
40
50
–50 –25
0
25
50
75 100 125
10
20
30
40
50
60
70
80
INTV LOAD CURRENT (mA)
TEMPERATURE (°C)
BIAS (V)
EE
8710 G27
8710 G25
8710 G26
8710f
8
For more information www.linear.com/LT8710
LT8710
pin FuncTions
FBX (Pin 1): Positive and Negative Feedback Pin. For a
value is 10nF to 100nF. A 51.8mV offset is added to the
amplifier, so when the average ISP – ISN voltage is 0V,
the IMON voltage is 616mV. When the average voltage
across the ISP and ISN pins is 50mV, the IMON pin will
output 1.213V. Do not resistively load down this pin.
boost, SEPIC, or inverting converter, tie a resistor from
the FBX pin to V
according to the following equations:
OUT
V
–1.213V
83.7µA
OUT
RFBX
=
; Boost or SEPIC Converter
; Inverting Converter
ISN, ISP (Pins 6, 7): Output Current Sense Negative and
Positive Input Pins Respectively. Kelvin connect ISN and
ISP pins to a sense resistor to limit the output current. The
commanded NFET current will limit the voltage difference
across the sense resistor to 50mV.
|V |+9.6mV
OUT
RFBX
=
83.1µA
V (Pin 2): Error Amplifier Output Pin. Tie external com-
C
pensation network to this pin.
BIAS (Pin 8): Alternate Input Supply and PFET Bias Pin.
Mustbelocallybypassed. TheBIASpinsetsthetoprailfor
SS (Pin 3): Soft-Start Pin. Place a soft-start capacitor here
that is greater than 5x the IMON capacitor. Upon start-up,
the SS pin will be charged by a (nominally) 260k resistor
to ~2.7V. During a current overload as seen by ISP - ISN,
overtemperature, or UVLO condition, the SS pin will be
quicklydischargedtoresetthepart.Oncethoseconditions
are clear, the part will attempt to restart.
the TG gate driver. Must connect to the converter’s V
OUT
for a positive output voltage or INTV for a converter’s
CC
negative output voltage.
INTV (Pin 9): 6.18V-Below-BIAS Regulator Pin. Must
EE
be locally bypassed with a minimum capacitance of
2.2µF to BIAS. This pin sets the bottom rail for the TG
gate driver. The TG gate driver can begin switching when
FLAG (Pin 4): Power Good or C/10 Indication Pin. The
FLAG pin functions as an active high power good pin if
C/10 is true. Alternatively, the FLAG pin functions as an
active high C/10 indication pin if power is good. Power
is good when FBX < 68.5mV or FBX > 1.153V and has
58mV of hysteresis. When FBX = 1.153V, it’s 5% below
regulation which corresponds to ~10% below regulation
BIAS – INTV exceeds 3.42V (typical). Connect pin to
EE
ground for an inverting converter.
TG (Pin 10): PFET Gate Drive Pin. Low and high levels are
BIAS – INTV and BIAS respectively.
EE
BG (Pin 11): NFET Gate Drive Pin. Low and high levels
on V
(for V
> 8V). Active high C/10 indication is
OUT
OUT
are GND and INTV respectively.
CC
when the charge current seen by the ISP and ISN pins is
less than 10% of full current (V – V < 5mV) as the
INTV (Pin12):6.3VDualInputLDORegulatorPin. Must
ISP
ISN
CC
chargecurrentdecreases. Forincreasingchargecurrents,
be locally bypassed with a minimum capacitance of 2.2µF
to GND. Logic will choose to run INTV from the V or
the C/10 threshold has to reach 20% of full current (V
ISP
CC
IN
– V > 10mV). The C/10 indication can be used to set
BIAS pins. A maximum 5mA external load can connect
to the INTV pin. The undervoltage lockout on INTV is
ISN
the bulk and float voltage when charging a battery. For
either C/10 or power good indicators, there is a 100µs
anti-glitch delay. A pull-up resistor or some other form
of pull-up network needs to exist on this pin to use these
features. See the Block Diagram and Applications section
for more information.
CC
CC
4V (typical). The BG gate driver can begin switching when
INTV exceeds 4V (typical).
CC
V (Pin 13): Input Supply Pin. Must be locally bypassed.
IN
Can run down to 0V as long as BIAS > 4.5V.
CSN, CSP (Pins 14, 15): NFET Current Sense Negative
andPositiveInputPinsRespectively. Kelvinconnectthese
pins to a sense resistor to limit the NFET switch current.
The maximum sense voltage at low duty cycle is 50mV.
IMON (Pin 5): Output Current Sense Monitor Output Pin.
Outputs a voltage that is proportional to the voltage seen
across the ISP and ISN pins.
V
= 11.9 • (V
+ 51.8mV)
IMON
ISP – ISN
EN/FBIN (Pin 16): Enable and Input Voltage Regulation
Pin. In conjunction with the UVLO (undervoltage lockout)
circuit, this pin is used to enable/disable the chip and
Since the voltage across the ISP and ISN pins is AC, a
filtering capacitor is needed on the IMON pin to average
out the ISP and ISN voltage. Recommended capacitor
restart the soft-start sequence. The EN/FBIN pin is also
8710f
9
For more information www.linear.com/LT8710
LT8710
pin FuncTions
RT (Pin 18): Timing Resistor Pin. Adjusts the LT8710’s
switching frequency. Place a resistor from this pin to
ground to set the frequency to a fixed free-running level.
Do not float this pin.
used to limit the NFET current to avoid collapsing the
input supply. Drive below 0.3V to disable the chip with
very low quiescent current. Drive above 1.7V (typical) to
activate the chip and restart the soft-start sequence. The
commandedNFETcurrentwilladjustwhentheEN/FBINpin
voltage drops between 1.55V and 1.662V. See the Block
Diagram and Applications section for more information.
Do not float this pin.
SYNC (Pin 19): To synchronize the switching frequency
to an outside clock, simply drive this pin with a clock. The
high voltage level of the clock must exceed 1.5V, and the
low level must be less than 0.4V. Drive this pin to less
than 0.4V to revert to the internal free running clock. See
theApplicationsInformationsectionformoreinformation.
MODE(Pin17):ForcedCCMModePin.Drivebelow1.175V
(typical) to operate in forced CCM. Drive above 1.224V
(typical) to operate in DCM and/or pulse-skipping mode
at light loads. If SS < 1.8V (typical) or INTV is in UVLO,
the part will operate in DCM at light load.
GND (Pin 20, Exposed Pad Pin 21): Ground. Must be
soldered directly to local ground plane.
EE
block DiagraM
C1
L1
L2
V
IN
V
OUT
C
OUT
C
IN
MP
MN
D1
R1
C2
R
SENSE2
R
SENSE1
R
FBX
INTV
CC
BIAS
INTV
CC
BIAS
CSP
CSN
BG
TG
V
IN
C
VEE
DRIVER
DRIVER
LEVEL
SHIFT
BIAS
LDO
LDO LOGIC
INTV
BIAS – 6.18V
EE
TG DRIVER
SR1
UVLO
DISABLE
Q
S
–
R
DCM_EN ISP ISN
A5
FLAG
+
LDO
DCM_EN
INTV
CC
+
–
6.3V
IMON
100µs
CHRG
ANTI-GLITCH
666.5mV
1.213V
REFERENCE
A7
C
VCC
UVLO
PG
+
–
IMON
1.38V
+
–
1.153V
R
R
IN1
EN/FBIN
+
–
DIE TEMP
175°C
+
–
EN/FBIN
LOGIC
68.5mV
51.5k
1.213V
IN2
1.3V 1.7V
+
–
MODE
+
–
14.5k
EA1
SLOPE
COMPENSATION
1.224V
1.8V
DCM_EN
FBX
+
–
÷N
ADJUSTABLE
OSCILLATOR
+
–
+
START-UP
AND RESET
LOGIC
50mV
2.7V
SOFT-START
SS
EA2
14.5k
A6
–
SYNC
BLOCK
260k
SS
+
+
–
DRIVER
DISABLE
1.213V
EN/FBIN
1.607V
ISN
ISP
–
+
EA4
–
EA3
C
SS
GND
+–
FBX
FREQUENCY
FOLDBACK
11.9k
51.8mV
DCM_EN
SYNC RT
V
C
IMON
8710 BD
R
C
C
C
R
IMON
T
C
C
F
Figure 1. Block Diagram
8710f
10
For more information www.linear.com/LT8710
LT8710
sTaTe DiagraM
EN/FBIN < 1.3V (TYP)
OR
IN
V
AND BIAS < 4.5V (MAX)
CHIP OFF
• ALL SWITCHES DISABLED
1.3V < EN/FBIN < 1.7V (TYP)
AND
OR BIAS > 4.5V
V
IN
INITIALIZE
RESET
• SS PULLED LOW
• INTV CHARGES UP
CC
EN/FBIN > 1.7V
AND
V
OR BIAS > 4.5V
AND
IN
INTV > 4V (TYP)
CC
ACTIVE MODE
RESET
RESET
• SS SLOWLY CHARGES UP
C
• V PULLED LOW
RESET DETECTED
• SS DISCHARGES QUICKLY
• SWITCHER DISABLED
BEGIN SWITCHING
• NFET BEGINS SWITCHING
• PFET STARTS SWITCHING
SS < 50mV
WHEN INTV REGULATOR
EE
IS OUT OF UVLO
RESET OVER
MODE < 1.175V (TYP)
AND
RESET
• NO RESET CONDITIONS
DETECTED
MODE > 1.224V (TYP)
SS > 1.8V (TYP)
FORCED CCM OPERATION
DCM AT LIGHT LOAD
REGULATION
• BG AND TG SWITCH AT
CONSTANT FREQUENCY
• INDUCTOR CURRENT CAN
REVERSE
• PFET TURNS OFF FOR
REMAINDER OF CYCLE IF
ISP-ISN VOLTAGE FALLS
BELOW 2.8mV (TYP)
• FOR VERY LIGHT LOAD,
PART MAY SKIP PULSES
• V COMMANDS PEAK
C
RESET
INDUCTOR CURRENT TO
MAINTAIN REGULATION
INTV REGULATOR
EE
• IF ISP-ISN VOLTAGE
IN UVLO
GOES BELOW –300mV (TYP),
PFET TURNS OFF SO
INDUCTOR CURRENT
GOES MORE POSITIVE
AND
SS > 1.8V (TYP)
OUTPUT CURRENT FOLDBACK
• OUTPUT CURRENT LIMITED
TO 25mV (TYP) AVERAGE
ACROSS THE ISP-ISN PINS
RESET
8710 SD
REGULATION =
OUTPUT VOLTAGE (FBX)
INPUT VOLTAGE (EN/FBIN)
OUTPUT CURRENT (ISP-ISN AND IMON)
RESET =
UVLO ON V OR BIAS ( < 4.5V (MAX))
IN
UVLO ON INTV ( < 4V (TYP))
CC
EN/FBIN < 1.7V (TYP) AT 1ST POWER-UP
EN/FBIN < 1.26V (TYP) AFTER ACTIVE MODE SET
OVERCURRENT (ISP – ISN > 63.6mV AVERAGE (TYP))
OVERTEMPERATURE (T > 175°C (TYP))
J
Figure 2. State Diagram
8710f
11
For more information www.linear.com/LT8710
LT8710
operaTion
OPERATION – OVERVIEW
ACTIVE MODE
(NORMAL OPERATION)
(MODE LATCHED UNTIL EN/FBIN DROPS BELOW
CHIP ENABLE TRESHOLD)
The LT8710 uses a constant frequency, current mode
control scheme to provide excellent line and load regula-
tion. The part’s undervoltage lockout (UVLO) function,
together with soft-start and frequency foldback, offers a
controlled means of starting up. Output voltage, output
current,andinputvoltagehavecontroloverthecommanded
peak current which allows a wide range of applications to
be built using the LT8710. Synchronous switching makes
high efficiency and high output current applications pos-
sible. When operating at light currents with the MODE pin
> 1.224V (typical), the LT8710 will disable synchronous
operation for part of the cycle to prevent negative switch
currents. Refer to the Block Diagram (Figure 1) and the
State Diagram (Figure 2) for the following description of
the part’s operation.
1.76V
ACTIVE MODE THRESHOLD
(TOLERANCE)
1.64V
NORMAL OPERATION IF ACTIVE MODE SET
1.662V
INPUT VOLTAGE REGULATION
(ONLY IF ACTIVE MODE SET)
1.55V
1.38V
1.18V
SWITCH OFF, INTV AND INTV ENABLED, SS CAP
CC
EE
DISCHARGED IF ACTIVE MODE NOT SET
CHIP ENABLE THRESHOLD
(HYSTERSIS AND TOLERANCE)
LOCKOUT
(SWITCH OFF, SS CAP DISCHARGED, INTV AND
CC
INTV DISABLED)
EE
0.3V
0V
SHUTDOWN
(LOW QUIESCENT CURRENT)
8710 F03
Figure 3. EN/FBIN Modes of Operation
OPERATION – START-UP
Several functions are provided to enable a very clean
start-up of the LT8710.
Undervoltage Lockout (UVLO)
The LT8710 has internal UVLO circuitry that disables the
Precise Turn-On Voltages
chip when the greater of V or BIAS < 4.5V (maximum)
IN
or INTV < 4V (typical). The EN/FBIN pin can also be
CC
The EN/FBIN pin has two voltage levels for activating the
part; one that enables the part and allows internal rails
to operate and a 2nd voltage threshold which activates
a soft-start cycle and switching can begin. To enable the
part, take the EN/FBIN pin above 1.3V (typical). This com-
parator has 44mV of hysteresis to protect against glitches
and slow ramping. To activate a soft-start cycle and allow
switching, take EN/FBIN above 1.7V (typical). When EN/
FBIN exceeds 1.7V (typical), the logic state is latched so
that if EN/FBIN drops between 1.3V to 1.7V (typical), the
SS pin is not pulled low by the EN/FBIN pin. The EN/FBIN
pin is also used for input voltage regulation which is at
1.607V (typical). Input voltage regulation is explained in
more detail in the Operation – Regulation section. Taking
the EN/FBIN pin below 0.3V shuts down the chip, result-
ing in extremely low quiescent current. See Figure 3 that
illustrates the different EN/FBIN voltage thresholds.
used to create a configurable UVLO. See the Applications
section for more information.
Soft-Start of Switch Current
The soft-start circuitry provides for a gradual ramp-up
of the switch current (refer to Max Current Limit vs SS
in Typical Performance Characteristics). When the part
is brought out of shutdown, the external SS capacitor
is first discharged which resets the states of the logic
circuits in the chip. Once INTV comes out of UVLO
CC
(> 4V typical) and the chip is in active mode, an integrated
260k resistor pulls the SS pin to ~2.7V at a ramp rate set
by the external capacitor connected to the pin. Typical
values for the soft-start capacitor range from 100nF to
1µF. The soft-start capacitor should also be at least 5x
greater than the external capacitor connected to the IMON
pin to avoid start-up issues.
8710f
12
For more information www.linear.com/LT8710
LT8710
operaTion
Frequency Foldback
mode of regulation will be described independently so
that only one of the modes of regulation is in command
of the LT8710.
The frequency foldback circuitry reduces the switching
frequency when 175mV < FBX < 1.01V (typical). This
feature lowers the minimum duty cycle that the part can
achieve,thusallowingbettercontroloftheinductorcurrent
at start-up. When the FBX voltage is pulled outside of this
range,theswitchingfrequencyreturnstonormal.Ifthepart
is configured to be in forced continuous conduction mode
(MODE pin is driven below 1.175V), then the frequency
Output Voltage Regulation
A single external resistor is used to set the target output
voltage. See the Pin Functions section for selecting the
feedback resistor for a desired output voltage. The V
C
pin voltage (negative input of A7) is set by EA1 (or EA2),
which is simply an amplified difference between the FBX
pinvoltageandthereferencevoltage(1.213ViftheLT8710
is configured as a noninverting converter or 9.6mV if
configured as an inverting converter). In this manner, the
FBX error amplifier sets the correct peak current level to
maintain output voltage regulation.
foldback circuitry is disabled as long as INTV is not in
UVLO and the SS pin is higher than the SS Hi threshold.
EE
Notethatthepeakinductorcurrentatstart-upisafunction
ofmanyvariablesincludingloadprofile,outputcapacitance,
target V , V , switching frequency, etc.
OUT IN
OPERATION – REGULATION
Input Voltage Regulation
UsetheBlockDiagramwhensteppingthroughthefollowing
description of the LT8710 operating in regulation. Also,
assume the converter’s load current is high enough such
that the part is operating in synchronous switching. The
LT8710 has three modes of regulation:
A single resistor or resistor divider from the EN/FBIN pin
to the converter’s input voltage sets the input voltage
regulation. It is recommended to use a resistor divider for
improved accuracy as described in the Setting the Input
Voltage Regulation or Undervoltage Lockout section.
The EN/FBIN pin voltage connects to the positive input of
1. Output Voltage (via FBX pin)
amplifier EA4. The V pin voltage is set by EA4, which is
C
2. Input Voltage (via EN/FBIN pin)
simply an amplified difference between the EN/FBIN pin
voltage and a 1.607V reference voltage. In this manner,
the EN/FBIN error amplifier sets the correct peak current
level to maintain input voltage regulation.
3. Output Current (via ISP, ISN, and IMON pins)
All three of these regulation loops control the peak com-
manded current through the external NFET, MN. This
operation is the same regardless of the regulation mode,
so that will be described first.
Output Current Regulation
An external sense resistor connected between the ISP and
At the start of each oscillator cycle, the SR latch (SR1)
is set, which first turns off the external PFET, MP, and
then turns on the external NFET, MN. The NFET’s source
current flows through an external current sense resistor
ISNpins(R
)setsthemaximumoutputcurrentofthe
SENSE2
converter when placed in the source of the PFET, MP. A
built-in 51.8mV offset is added to the voltage seen across
R
. That voltage is then amplified and outputs to
SENSE2
(R
) generating a voltage proportional to the NFET
SENSE1
the IMON pin. An external capacitor must be placed from
switch current. This voltage is then amplified by A5 and
added to a stabilizing ramp. The resulting sum is fed into
thepositiveterminalofthePWM comparatorA7.Whenthe
voltage on the positive input of A7 exceeds the voltage on
IMON to ground to filter the amplified chopped voltage
that’s sensed across R
. The voltage at the IMON pin
SENSE2
is fed to the negative input of the IMON error amplifier,
EA3. The V pin voltage is set by EA3, which is simply an
C
the negative input (V pin), the SR latch is reset, turning
amplifieddifferencebetweentheIMONpinvoltageandthe
1.213V reference voltage. In this manner, the IMON error
amplifier sets the correct peak current level to maintain
C
off the NFET and then turning on the PFET. The voltage
on the V pin is controlled by one of the regulation loops,
C
or a combination of regulation loops. For simplicity, each
output current regulation.
8710f
13
For more information www.linear.com/LT8710
LT8710
operaTion
Note that if the INTV LDO is in UVLO and SS > 1.8V
Light Load Current (MODE Pin)
EE
(typical), then the voltage reference at the positive input
of EA3 is 916mV (typical), resulting in limiting the output
current to about half of its set limit.
The MODE pin can be used to tell the LT8710 to operate
in forced CCM regardless of load current, or operate in
DCM at light loads.
• MODE < 1.175V (typical) = Forced CCM or FCM
• MODE > 1.224V (typical) = DCM or Pulse-Skipping
OPERATION – RESET CONDITIONS
The LT8710 has three reset cases. When the part is in
reset, the SS pin is pulled low and both power switches,
MN and MP, are forced off. Once all of the reset conditions
are gone, the part is allowed to begin a soft-start sequence
andswitchingcancommence.Eachofthefollowingevents
can cause the LT8710 to be in reset:
The forced continuous mode (FCM) allows the inductor
current to reverse directions without any switches being
forced off. At very light load currents, the inductor cur-
rent will swing positive and negative as the appropriate
average current is delivered to the output. There are some
exceptions that negate the MODE pin and force the part
to operate in DCM at light loads:
1. UVLO
a. The greater of V and BIAS is < 4.5V (maximum)
IN
1. The INTV LDO is in UVLO (BIAS – INTV < 3.42V
EE
EE
b. INTV < 4V (typical)
typical).
CC
c. EN/FBIN < 1.7V (typical) at first power-up
2. Overcurrent sensed by IMON > 1.38V (typical)
3. Die Temperature > 175°C
2. SS < 1.8V (typical).
3. The part is in a reset condition.
When the LT8710 is in discontinuous mode (DCM), syn-
chronous switch MP is held off whenever MP’s current
falls near 0 current (less than 2.8mV (typical) across
OPERATION – POWER SWITCH CONTROL
R
). This is to prevent current draw from the output
SENSE2
The main power switch is the external NFET (MN in Block
Diagram) and the synchronous power switch is the ex-
ternal PFET (MP in Block Diagram). The two switches
are never on at the same time, and there is a non-overlap
time of ~140ns and ~90ns on the rising and falling edges
respectively (see Electrical Characteristics) to prevent
cross conduction. Figure 4 below shows the BG and TG
(BIAS–TG) signals:
and/or feeding current to the input supply. Under very
light loads, the current comparator A7, may also remain
tripped for several cycles (i.e. skipping pulses). Since MP
is held off during the skipped pulses, the inductor current
will not reverse.
OPERATION – C/10 AND POWER GOOD (FLAG PIN)
The FLAG pin is an open-drain pin that functions as an ac-
tive high C/10 and power good pin. The FLAG pin changes
states 100µs (typical) after the internal comparators tell
the FLAG pin to change states to reject glitches or tran-
sient events.
140ns
90ns
BG
ON
TG
ON
8710 F04
Figure 4. Synchronous Switching
8710f
14
For more information www.linear.com/LT8710
LT8710
operaTion
C/10 Indication
OPERATION – LDO REGULATORS (INTV AND INTV )
CC EE
If power is good, then the FLAG pin will function as an
active high C/10 indication pin. C/10 is when the charging
current(outputcurrent)hasdroppedto1/10itsmaximum
and is useful in battery charging applications. The C/10
comparatormonitorsthevoltageattheIMONpin,andwhen
the average ISP-ISN voltage drops below 5mV (typical),
the FLAG pin pull-down device is turned off, and the FLAG
pin voltage is allowed to pull high. The FLAG pin will pull
lowagainiftheaverageISP-ISNvoltagerisesabove10mV
(typical). The IMON voltage corresponding to 5mV and
10mVonISP–ISNis666.5mVand727.5mVrespectively.
The INTV LDO regulates at 6.3V (typical) and is used
CC
as the top rail for the BG gate driver. The INTV LDO can
CC
run from V or BIAS and will intelligently select to run
IN
from the best for minimizing power loss in the chip, but
at the same time, select the proper input for maintaining
INTV as close to 6.3V as possible. The INTV regulator
CC
CC
also has safety features to limit the power dissipation in
the internal pass device and also to prevent it from dam-
age if the pin is shorted to ground. The UVLO threshold
on INTV is 4V (typical), and the LT8710 will be in reset
CC
until the LDO comes out of UVLO.
Note that if the LT8710 is set to operate in FCM (MODE
pin low), then the C/10 comparator is disabled and the
FLAG pin operates only as a power good pin. See the Ap-
plications section for more information.
The INTV regulator regulates to 6.18V (typical) below
EE
the BIAS pin voltage. The BIAS and INTV voltages are
EE
used for the top and bottom rails of the TG gate driver
respectively. Just like the INTV regulator, the INTV
CC
EE
regulatorhasasafetyfeaturetolimitthepowerdissipation
Power Good Indication
in the internal pass device. The TG pin can begin switch-
ing after the INTV regulator comes out of UVLO (3.42V
EE
IfC/10isdetected(averageISP-ISN<5mVtypical),thenthe
FLAG pin functions as an active high power good (PG) pin.
Power is good when the FBX voltage is greater than 95%
of its regulation target, which corresponds to ~90% of the
typical across the BIAS and INTV pins) and the part is
EE
not in a reset condition.
V
OUT
regulation target (for V
> ~8V). This corresponds
OUT
to FBX > 1.153V (typical) for noninverting converters and
FBX < 68.5mV (typical) for inverting converters. The PG
comparators have 58mV of hysteresis to reject glitches.
8710f
15
For more information www.linear.com/LT8710
LT8710
applicaTions inForMaTion
BOOST CONVERTER COMPONENT SELECTION
Table 1. Boost Design Equations
Parameters/Equations
L1
1.3µH
R
SENSE2
5m
V
12V
6A
V
OUT
IN
MP
Step 1: Inputs
Pick V , V , I , and f to calculate equations
IN OUT OUT
below.
4.5V TO
9V
MN
×2
+
C
OUT2
330µF
R
Step 2: DC
SENSE1
MAX
V
IN(MIN)
1m
DCMAX ≅ 1–
C
IN2
330µF
VOUT
+
C
OUT1
22µF
×4
BG
CSN
CSP TG
ISP
Step 3: V
Step 4: R
See Max Current Limit vs Duty Cycle plot in Typical
CSPN
V
IN
Performance Characteristics to find V
VCSPN
at DC
.
CSPN
MAX
LT8710
R
IN1
13.3k
ISN
SENSE1
RSENSE1 ≤0.58•
•(1– DCMAX)
EN/FBIN
MODE
BIAS
IOUT
R
IN2
10k
R
FBX
130k
INTV
2.2µF
EE
2.2µF
FBX
Step 5: R
SENSE2
0.05
1.6 •IOUT
INTV
RT
CC
RSENSE2
≤
FLAG
C
22µF
×4
IN1
V
C
R
T
Step 6: L
88.7k
R
C
R
SENSE1 •V
IN(MIN) • 1–
12.5m•f
V
VOUT
IN(MIN)
SYNC
GND
18k
LTYP
=
(1)
(2)
C
F
IMON
SS
100pF
C
C
C
VIN(MIN)
VOUT – VIN(MIN)
IMON
47nF
SS
220nF
C
RSENSE1 •V
40m•f
OUT • 1–
3.3nF
LMIN
=
8710 F05
R
SENSE1 •V
V
IN(MIN)
VOUT
IN(MIN) • 1–
(3)
(4)
LMAX1
=
5m•f
SENSE1 •V
Figure 5. Boost Converter – The Component Values Given are
Typical Values for a 400kHz, 4.5V to 9V to 12V/6A Boost.
R
V
IN(MAX)
VOUT
IN(MAX) • 1–
LMAX2
=
5m•f
• Solve equations 1 to 4 for a range of L values.
• The minimum value of the L range is the higher of
and L . The maximum of the L value range is
The LT8710 can be configured as a boost converter as in
Figure5.Thistopologygeneratesapositiveoutputvoltage
where the input voltage is lower than the output voltage.
A single feedback resistor sets the output voltage.
L
TYP
MIN
the lower of L
and L
.
MAX1
MAX2
Step 7: C
OUT
IOUT •DCMAX
COUT
≥
For a desired output current and output voltage over a
given input voltage range, Table 1 is a step-by-step set of
equations to calculate component values for the LT8710
when operating as a boost converter. Refer to more detail
in this section and the Appendix for further information
on the design equations presented in Table 1.
f•0.005•V
OUT
Step 8: C
Step 9: C
IN
DCMAX
8•L•f2 • 0.005
CIN
≥
IMON
100µ•DCMAX
0.005•f
CIMON
≥
Step 10: R
Step 11: R
FBX
T
VOUT –1.213V
83.7µA
RFBX
RT =
=
Variable Definitions:
V
V
V
= Minimum Input Voltage
= Maximum Input Voltage
IN(MIN)
IN(MAX)
35,880
f
–1; f inkHz andRT inkΩ
and C may deviate from the above
= Output Voltage
OUT
NOTE: The final values for C
OUT
IN
I
= Output Current of Converter
OUT
equations in order to obtain desired load transient performance for a
particular application. The C and C equations assume zero ESR, so
f = Switching Frequency
DC
V
OUT
IN
increase the capacitance accordingly based on the combined ESR.
= Power Switch Duty Cycle at V
IN(MIN)
= Current Limit Voltage at DC
MAX
MAX
CSPN
8710f
16
For more information www.linear.com/LT8710
LT8710
applicaTions inForMaTion
SEPIC CONVERTER COMPONENT SELECTION –
Table 2. SEPIC Design Equations
Parameters/Equations
COUPLED OR UNCOUPLED INDUCTORS
C1
10µF ×2
L1
2.9µH
R
Step 1: Inputs
Pick V , V , I , and f to calculate equations
IN OUT OUT
below.
SENSE2
6m
V
5V
5A
OUT
MP
V
IN
3V TO 40V(OPERATING)
4.5V TO 40V(START-UP)
C
10µF
×6
MN
R
IN1
Step 2: DC
MAX
VOUT
VIN(MIN)+VOUT
L2
2.9µH
C
DCMAX
≅
OUT2
330µF
SENSE1
+
1.5m
•
Step 3: V
Step 4: R
See Max Current Limit vs Duty Cycle plot in Typical
CSPN
BG
CSN
CSP
TG
Performance Characteristics to find V
VCSPN
at DC
.
C
CSPN
MAX
OUT1
100µF
×4
V
IN
ISP
ISN
SENSE1
R
IN1
RSENSE1 ≤0.58•
•(1–DCMAX)
4.02k
IOUT
LT8710
EN/FBIN
MODE
BIAS
R
10k
2.2µF
IN2
R
FBX
45.3k
INTV
2.2µF
EE
Step 5: R
SENSE2
0.05
1.6•IOUT
RSENSE2
≤
FBX
INTV
RT
CC
FLAG
Step 6: L
V
C
R
178k
VIN(MIN)
+
T
RSENSE1 •VOUT
12.5m•f
C
IN2
220µF
LTYP
LMIN
LMAX
=
•
(1)
R
C
OUT
VIN(MIN)+V
C
F
100pF
SYNC
GND
8.87k
IMON
SS
2
VIN(MIN)
RSENSE1 •V
OUT • 1–
C
C
C
C
IMON
47nF
SS
220nF
(2)
(3)
=
6.8nF
40m•f
VOUT
8710 F06
VIN(MIN)
VIN(MIN)+VOUT
RSENSE1 •V
5m•f
OUT
=
•
Figure 6. SEPIC Converter – The Component Values Given Are
Typical Values for a 200kHz, 3V to 40V to 5V/5A SEPIC Topology
Using Coupled Inductors.
• Solve equations 1, 2, and 3 for a range of L values.
• The minimum value of the L range is the higher of
L
and L . The maximum of the L value range
MAX
TYP
MIN
The LT8710 can also be configured as a SEPIC as in
Figure 6. This topology generates a positive output volt-
age where the input voltage can be lower, equal, or higher
than the output voltage. Output disconnect is inherently
built into the SEPIC topology, meaning no DC path exists
between the input and output due to capacitor C1.
is L
.
• L = L = L for coupled inductors.
1
2
• L = L || L for uncoupled inductors.
1
2
Step 7: C1
C1≥10µF TYPICAL ;V
> V
IN
RATING
Step 8: C
OUT
IOUT •DCMAX
COUT
≥
f •0.005•V
OUT
For a desired output current and output voltage over a
given input voltage range, Table 2 is a step-by-step set of
equations to calculate component values for the LT8710
when operating as a SEPIC converter. Refer to more detail
in this section and the Appendix for further information
on the design equations presented in Table 2.
Step 9: C
IN
DCMAX
CIN
≥
8•L•f2 • 0.005
Step 10: C
Step 11: R
IMON
100µ•DCMAX
CIMON
≥
0.005•f
FBX
VOUT –1.213V
83.7µA
RFBX
RT =
=
Variable Definitions:
V
V
OUT
= Minimum Input Voltage
Step 12: R
IN(MIN)
T
35,880
f
–1; f inkHz andRT inkΩ
= Output Voltage
OUT
I
= Output Current of Converter
NOTE: The final values for C
and C may deviate from the above
IN
OUT
f = Switching Frequency
equations in order to obtain desired load transient performance for a
particular application. The C and C equations assume zero ESR, so
OUT
IN
DC
= Power Switch Duty Cycle at V
IN(MIN)
= Current Limit Voltage at DC
MAX
MAX
increase the capacitance accordingly based on the combined ESR.
V
CSPN
8710f
17
For more information www.linear.com/LT8710
LT8710
applicaTions inForMaTion
DUAL INDUCTOR INVERTING COMPONENT SELECTION
– COUPLED OR UNCOUPLED INDUCTORS
Table 3. Dual Inductor Inverting Design Equations
Parameters/Equations
Step 1: Inputs
Pick V , V , I , and f to calculate equations
IN OUT OUT
below.
C1
L1
L2
10µF ×2
2.2µH
2.2µH
V
–5V
7A
V
OUT
IN
4.5V TO
25V
Step 2: DC
MAX
|VOUT
VIN(MIN)+|VOUT
|
MP
DCMAX
≅
C
C
10µF
×4
OUT2
330µF
MN
R
IN1
R1
+
|
499Ω
SENSE1
D1
1.5m
Step 3: V
See Max Current Limit vs Duty Cycle plot in Typical
C
R
OUT1
100µF
×2
CSPN
SENSE2
C2
0.47µF
4m
Performance Characteristics to find V
at DC
.
CSPN
MAX
BG
CSN
CSP TG
Step 4: R
Step 5: R
Step 6: L
SENSE1
VCSPN
IOUT
V
ISN
ISP
IN
RSENSE1 ≤0.58•
•(1–DCMAX
R
IN1
13.3k
LT8710
EN/FBIN
MODE
INTV
CC
2.2µF
BIAS
R
FBX
60.4k
SENSE2
0.05
1.6•IOUT
R
IN2
10k
2.2µF
RSENSE2
≤
INTV
EE
FBX
INTV
RT
CC
FLAG
VIN(MIN)
VIN(MIN)+|VOUT
RSENSE1•|VOUT
12.5m•f
|
LTYP
LMIN
LMAX
=
•
(1)
(2)
(3)
V
C
C
R
T
IN2
120µF
|
118k
+
R
C
C
C
SYNC
GND
11.5k
100pF
2
V
IMON
SS
RSENSE1•|VOUT
40m•f
|
IN(MIN)
=
• 1–
C
C
C
C
IMON
47nF
SS
220nF
VOUT
VIN(MIN)
VIN(MIN)+|VOUT
3.3nF
8710 F07
RSENSE1•|V
|
OUT
=
•
|
5m•f
Figure 7. Dual Inductor Inverting Converter – The Component
Values Given Are Typical Values for a 300kHz, 4.5V to 25V to
–5V/7A Inverting Topology Using Coupled Inductors.
• Solve equations 1, 2, and 3 for a range of L values.
• The minimum value of the L range is the higher of
L
and L . The maximum of the L value range
MAX
TYP
MIN
Due to its unique FBX pin, the LT8710 can work in a dual
inductor inverting configuration as in Figure 7. Changing
the connections of L2 and the PFET in the SEPIC topol-
ogy, results in generating negative output voltages. This
solution results in very low output voltage ripple due to
inductor L2 in series with the output. Output disconnect is
inherently built into this topology due to the capacitor C1.
is L
.
• L = L = L for coupled inductors.
1
2
• L = L || L for uncoupled inductors.
1
2
Step 7: C1
C1≥10µF TYPICAL ;V
> V +|V
|
RATING
IN
OUT
Step 8: C
OUT
V
1
IN(MAX)
COUT
≥
•
8•f2•0.005
VIN(MAX)+|VOUT|
For a desired output current and output voltage over a
given input voltage range, Table 3 is a step-by-step set of
equations to calculate component values for the LT8710
whenoperatingasadualinductorinvertingconverter.Refer
to more detail in this section and the Appendix for further
information on the design equations presented in Table 3.
Step 9: C
IN
DCMAX
CIN
≥
8•L•f2 • 0.005
Step 10: C
Step 11: R
IMON
100µ•DCMAX
0.005•f
CIMON
≥
FBX
|VOUT |+9. 6mV
83.1µA
RFBX
RT =
=
Variable Definitions:
Step 12: R
T
35,880
V
V
V
I
= Minimum Input Voltage
= Maximum Input Voltage
–1; f inkHz andRT inkΩ
IN(MIN)
IN(MAX)
f
NOTE: The final values for C
and C may deviate from the above
OUT
IN
= Output Voltage
OUT
equations in order to obtain desired load transient performance for a
= Output Current of Converter
f = Switching Frequency
particular application. The C
and C equations assume zero ESR, so
IN
OUT
OUT
increase the capacitance accordingly based on the combined ESR.
DC
= Power Switch Duty Cycle at V
IN(MIN)
= Current Limit Voltage at DC
MAX
MAX
V
CSPN
8710f
18
For more information www.linear.com/LT8710
LT8710
applicaTions inForMaTion
SETTING THE OUTPUT VOLTAGE REGULATION
TheLT8710outputvoltageissetbyconnectinganexternal
V
IN
1.7V
1.3V
ACTIVE MODE
CHIP ENABLE
V
IN
EN/FBN
LOGIC
R
R
IN1
EN/FBIN
resistor (R ) from the converter’s output, V , to the
FBX
OUT
17.6µA
FBX pin. The equations below determines R
:
FBX
AT 1.607V
+
V
C
EA4
IN2
VOUT –1.213V
–
1.607V
(OPTIONAL)
51.5k
RFBX
=
=
; Boost or SEPICConverter
; InvertingConverter
83.7µA
|VOUT |–9.6mV
83.1µA
GND
8710 F08
RFBX
Figure 8. Configurable UVLO
SeetheElectricalCharacteristicsfortolerancesontheFBX
regulation voltage and current.
Thissametechniquecanbeusedtocreateanundervoltage
lockout if the LT8710 is NOT in forced continuous mode.
When in discontinuous mode, forcing V low will stop all
switching activity. Note that this does not reset the soft
start function, therefore resumption of switching activity
will not be accompanied by a soft-start.
SETTING THE INPUT VOLTAGE REGULATION OR
UNDERVOLTAGE LOCKOUT
C
By connecting a resistor divider between V , EN/FBIN,
IN
and GND, the EN/FBIN pin provides a mean to regulate
the input voltage or to create an undervoltage lockout
function. Referring to error amplifier EA4 in the block
diagram, when EN/FBIN is lower than the 1.607V refer-
Note that for very low input impedance supplies, a capaci-
tor from EN/FBIN to ground may be needed to prevent
oscillationsfromtheinputvoltageregulationcontrolloop.
ence, V is pulled low. For example, if V is provided by
C
IN
Atstart-up,theminimumvoltageonEN/FBINmustexceed
1.7V (typical) to begin a soft-start cycle. Afterwards, the
EN/FBIN voltage can drop below 1.7V and the input can
be regulated such that the EN/FBIN voltage is at ~1.607V.
So the equation below gives the start-up V for a desired
input regulation voltage:
a relatively high impedance source (e.g. a solar panel) and
the current draw pulls V below a preset limit, V will be
IN
C
reduced,thusreducingcurrentdrawfromtheinputsupply
and limiting the input voltage drop. Note that using this
function in forced continuous mode (MODE pin low) can
result in current being drawn from the output and forced
into the input. If this behavior is not desired then set the
MODE pin high to prevent reverse current flow.
IN
1.7V
1.607V
VIN(START-UP)
=
•V
+0.78µA •RIN1
IN(MIN–REG)
To set the minimum or regulated input voltage use:
OUTPUT CURRENT MONITORING AND LIMITING
(R AND ISP-ISN AND IMON PINS)
R
RIN2
IN1
VIN(MIN–REG) = 1.607V • 1+
+17.6µA •RIN1
SENSE2
The LT8710 has an output current monitor circuit that
can be used to monitor and/or limit the output current.
The current monitor circuit works as shown in Figure 9.
If it is not desirable to monitor and limit the output cur-
rent, simply connect the IMON pin to ground. Note that
the current sense resistor connected to the ISP and ISN
pins must still be used, and the value should follow the
guidelines in the next couple sections.
VIN(MIN–REG)–1.607V
RIN1
=
1.607V
+17.6µA
R
IN2
where R and R are shown in Figure 8. For increased
IN1
IN2
accuracy, set R ≤ 10k. The resistor R is optional, but
IN2
IN2
it is recommended to be used to increase the accuracy of
the input voltage regulation by making the R current
IN1
much higher than the EN/FBIN pin current.
8710f
19
For more information www.linear.com/LT8710
LT8710
applicaTions inForMaTion
R
SENSE2
voltage. Assume the current through R
state and that its time average current is approximately
equal to the converter’s load current:
is steady
MP
SENSE2
TO SYSTEM
V
OUT
ISN
TG
ISP
VIMON =11.9• I
•R
+51.8mV
SENSE2
(
)
RSENSE2(AVE)
–
51.8mV
+
V
IMON
–51.8mV
11.9
R
I
≈I
=
OUT RSENSE2(AVE)
1mA/V
A7
SENSE2
–
+
1.38V
1.213V
OVER
CURRENT
EA3
+
Output Current Limiting
–
+
–
As shown in Figure 9, IMON voltages exceeding 1.213V
CHRG
(typical) causes the V voltage to reduce, thus limiting
666.5mV
C
11.9K
GND
the inductor current. This voltage on IMON corresponds
IMON
V
C
to an average voltage of 50mV across R
. Below is
SENSE2
resistor for limiting
the equation for selecting the R
SENSE2
C
IMON
the output current at steady state:
50mV
8710 F09
RSENSE2
=
Figure 9. Output Current Monitor and Control
I
OUT(LIMIT)
ThecurrentthroughR
MP which is turning on and off every clock cycle. Since
the current through R is chopped, a filter capacitor
connected from the IMON pin to ground is needed to filter
thevoltageattheIMONpinbeforeheadingtoEA3. Belowis
the equation to calculate the required IMON pin capacitor:
issensingthecurrentthrough
SENSE2
If it is not desirable to limit the output current, size
by setting I at least 60% higher than
themaximumoutputcurrentoftheconverter.Thiscurrent
sense resistor is needed if using the synchronous PFET
in the converter. If the PFET is replaced with a Schottky,
R
SENSE2
OUT(LIMIT)
SENSE2
then R
is not needed if output current limiting or
SENSE2
monitoring isn’t required.
100µA •DC
5mV •f
MAX
CIMON
≥
Note that if the INTV LDO is in UVLO and SS > 1.8V (typi-
EE
cal), then the reference voltage at EA3 reduces to 916mV,
and the output current is limited to about half its set point.
whereDC
isthemaximumdutycycleoftheconverter’s
IN
MAX
application (V at the lowest of its input range) and f is
the switching frequency.
Output Overcurrent
To prevent start-up issues, the IMON capacitor should
charge up faster than the SS capacitor. It is recommended
to size the SS capacitor at least 5x greater than the IMON
capacitor.
As shown in Figure 9, a comparator monitors the voltage
at the IMON pin and triggers a reset condition if the IMON
pin voltage exceeds 1.38V (typical). This corresponds to
an average voltage of 63.6mV (typical) across the ISP
and ISN pins:
Output Current Monitoring
63.6mV
I
I
=
The voltage at the IMON pin is a gained up version of the
voltage seen across the ISP and ISN pins. Below are the
OUT(OVERCURRENT)
R
SENSE2
=1.27•I
OUT(OVERCURRENT)
OUT(LIMIT)
equations relating the R
current to the IMON pin
SENSE2
8710f
20
For more information www.linear.com/LT8710
LT8710
applicaTions inForMaTion
Battery Charging and C/10
Capacitor Charging
A useful application for limiting the output current is to
charge a battery. When charging a battery such as a 12V
lead acid battery, it may be useful to charge to a bulk and
float voltage, in which case, the C/10 function of the FLAG
pin can be used. For decreasing charge currents, C/10
is detected when the IMON voltage falls below 666.5mV
(typical) and corresponds to an average ISP – ISN voltage
of 5mV (typical). For increasing charge currents, C/10 is
cleared when IMON gets above 727.5mV (typical) which
corresponds to an average ISP – ISN voltage of 10mV
(typical).
When the application is to charge a bank of capacitors
suchasSuperCaps, thechargingcurrentissetbyR
SENSE2
and the FLAG pin isn’t necessarily needed as in the case
of charging a battery.
Temperature Dependent Output Voltage Using NTC
Resistor
Itmaybedesirabletoregulatetheconverter’soutputbased
on the ambient temperature. The INTV LDO regulated
CC
voltageis6.3V 1.6ꢀ(seeElectricalCharacteristics), and
a negative temperature coefficient (NTC) resistor can be
used to sum into the FBX pin to create an output voltage
that decreases with temperature. See Figure 11 for the
necessary connections.
To set a bulk and float battery voltage, simply connect
a resistor from the FLAG pin to the FBX pin. When the
battery charging current is high (C/10 not detected), the
target output voltage is the bulk battery voltage as set by
the resistor connected between the FLAG and FBX pins.
OncethechargingcurrentdropssuchthatC/10isdetected,
the target output voltage drops to the float battery voltage
as set by the external FBX resistor. See Figure 10 below
on the FLAG pin connections and equations for setting the
bulk and float battery voltages. Note that in order to use
the C/10 feature, the MODE pin must be high to operate
in DCM at light loads.
The FBX voltages regulates to 1.213V (typical) for posi-
tive output voltages. For an accurate room temperature
output voltage, size the resistor divider off the INTV
CC
pin to give 1.213V such that the current through R2 is
~0 at room temperature. Choose R ≤ 10kΩ and
NTC(25)
use the equations below to calculate R , R , and V
1
FBX
OUT
change
at room temperature and R for a desired V
2
OUT
over temperature.
6.3–1.213V
FROM
R =R
1
NTC(25)
CONTROLLER
V
OUT
1.213V
≅1.213V+83.7µA •R
V
OUT
+
C
LEAD ACID
BATTERY
OUT
R
R
FBX
R
FBX
V
+
•
OUT(25)
FBX
R
FLAG
2
R
1
FLAG
FBX
1.213V –6.3V •
R +R
PG
100µs
ANTI-GLITCH
1.213V
1
NTC(25)
83.7µA
–
1
1
T
666.5mV
CHRG
–
R
=R
•e β•
NTC(25)
(
)
+
T
25
NTC
DCM_EN
IMON
GND
8710 F10
R
FBX
∆V
= –6.3V •
•R •
OUT
1
R
2
1
1
V
–1.213V
83.7µA
–
OUT(FLOAT)
R
R
=
R +R
R +R
FBX
1
1
NTC(T(MAX))
NTC(T(MIN))
1.213V
– V
–6.3V
=R
•
FLAG
FBX
R =
•R •R •
FBX 1
2
V
OUT(BULK)
OUT(FLOAT)
∆V
OUT
1
1
–
Figure 10. FLAG Pin Connections and Equations
for Battery Charging
R +R
R +R
1
NTC(T(MIN))
1
NTC(T(MAX))
8710f
21
For more information www.linear.com/LT8710
LT8710
applicaTions inForMaTion
where:
To provideadesiredloadcurrentforanygivenapplication,
must be sized appropriately. The switch current
R
SENSE1
R
= Resistance of the NTC resistor at 25°C
NTC(25)
will be at its highest when the input voltage is at the lowest
b
= Material-specific constant of NTC resistor.
of its range. The equation below calculates R
desired output current:
for a
SENSE1
Specified at two temperatures such as b
.
25/85
If more than two bs are specified, use the most
appropriate for the application.
V
I
i
CSPN
OUT
RIPPLE
R
≤0.74•η •
• 1–DC
(
• 1–
)
SENSE1
MAX
2
T
= Absolute temperature in Kelvin
where
T
25
= Room temperature in Kelvin (298.15k)
η
= Converter efficiency (assume ~90ꢀ)
1.213V
V
= Max current limit voltage (see Max Current
Limit vs Duty Cycle (CSP-CSN) plot in the
Typical Performance Characteristics)
CSPN
FROM SYSTEM
V
+
–
OUT
EA1
EA2
14.5k
R
FBX
I
= Converter load current
OUT
FBX
DC
= Switching duty cycle at minimum V (see
MAX
IN
R2
+
–
Power Switch Duty Cycle in Appendix)
INTV
6.3V
CC
14.5k
GND
R
NTC
i
= Peak-to-peakinductorripplecurrentpercent-
RIPPLE
age at minimum V (recommended to use
IN
V
25ꢀ)
C
R1
REVERSE CURRENT APPLICATIONS (MODE PIN LOW)
When the forced continuous mode is selected (MODE pin
low), inductor current is allowed to reverse directions and
8710 F11
Figure 11. Temperature Dependent Output Using an NTC
Resistor Divider
flow from the V
side to the V side. This can lead to
OUT
IN
current sinking from the output and being forced into the
input. The reverse current is at a maximum magnitude
SWITCH CURRENT LIMIT (R
PINS)
AND CSP-CSN
SENSE1
when V is lowest. The graph of Max Current Limit vs Duty
C
Cycle (CSP – CSN) in the Typical Performance Character-
istics section can help to determine the maximum reverse
current capability.
The external current sense resistor (R
) sets the
SENSE1
maximum peak current though the external NFET switch
(MN). The maximum voltage across R is 50mV
SENSE1
The IMON pin voltage will indicate negative inductor cur-
rents. Refer to the equation for IMON in the Pin Functions.
Note that the IMON voltage is only accurate if the dynamic
(typical) at very low switch duty cycles, and then slope
compensationdecreasesthecurrentlimitasthedutycycle
increases (see the Max Current Limit vs Duty Cycle (CSP-
CSN)plotintheTypicalPerformanceCharacteristics).The
equation below gives the switch current limit for a given
voltage across R
stays within –51.8mV to 500mV.
SENSE2
If the valley inductor current goes more negative than
–300mV as sensed by R
off, andtheinductorcurrentwillstartgoingmorepositive.
, the external PFET will turn
SENSE2
duty cycle and current sense resistor (find V
operating duty cycle in the plot mentioned).
at the
CSPN
V
CSPN
I
=
SW(LIMIT)
R
SENSE1
8710f
22
For more information www.linear.com/LT8710
LT8710
applicaTions inForMaTion
Backup Power
approach, asV approachestheOVPpoint, theMODEpin
IN
approachestheMODEFCMthreshold(1.224Vtypical)and
the LT8710 won't allow reverse current flow, preventing
IN
With the use of reverse current control and input voltage
regulation, the LT8710 can be used as a backup power
converterasshowninFigure12below.WiththeMODEpin
low to operate in FCM, when the input source is removed,
the output can supply current into the input and keep the
input regulated for some amount of time. The amount
of time depends on the output capacitance and the load
current at the input.
V to go above the OVP point.
CURRENT SENSE FILTERING
Certain applications may require filtering of the inductor
currentsensesignalsduetoexcessiveswitchingnoisethat
canappearacrossR
and/orR
. Higheroperat-
SENSE1
SENSE2
, andmorecapacitive
V
SYSTEM
IF V
ingvoltages, highervaluesofR
V
IS PRESENT
IS REMOVED
SENSE
PWR
PWR
PWR
IDEAL
DIODE
10.5V IF V
MOSFETswillallcontributeadditionalnoiseacrossR
C1
SENSE
L1
R
MP
SENSE2
V
PWR
V
OUT
12V 5ꢀ
when MOSFETs transition. The CSP/CSN and/or the ISP/
ISN sense signals can be filtered by adding one of the RC
networks shown in Figure 14. The filter shown in Figure
14afiltersoutdifferentialnoise,whereasthefilterinFigure
14b filters out the differential and common mode noise at
the expense of an additional capacitor and approximately
twice the capacitance value. It is recommended to Kelvin
thegroundconnectiondirectlytothepaddleoftheLT8710
if using the filter in Figure 14b. The filter network should
be placed as close as possible to the LT8710. Resistors
greater than 10Ω should be avoided as this can increase
the offset voltages at the CSP/CSN and ISP/ISN pins.
C
MN
IN1
INPUT POWER
SOURCE CAN BE
REMOVED
L2
R
SENSE1
+
CAP
•
BANK
BG
CSN
CSP
TG
ISP
V
IN
R
IN1
ISN
49.9k
LT8710
EN/FBIN
MODE
BIAS
R
IN2
10k
INTV
EE
R
FBX
C
IN2
+
FBX
GND
8710 F12
Figure 12. Backup Power Converter
Once V
drops low enough to put the INTV LDO in
EE
OUT
UVLO (V
5.1Ω
at ~4.25V), the PFET will stop switching and
OUT
CSP OR ISP
thecurrentwillstopflowingfromV
typeofapplication, itisrecommendedtouseaPFETthatis
in the linear mode of operation with only 4V of gate drive.
toV
.Forthis
OUT
SYSTEM
R
, R
LT8710
2.2nF
SENSE1 SENSE2
CSN OR ISN
5.1Ω
8710 F014a
Input Overvoltage Protection
Figure 14a. Differential RC Filter on CSP/CSN and/or ISP/ISN Pins
Whenever the MODE pin is low to allow current to flow
from output to input, it is strongly recommended to add
a couple external components to protect the input from
overvoltage as shown in Figure 13 below. With either
5.1Ω
CSP OR ISP
V
V
IN
IN
4.7nF
R
OVP2
LT8710
R
, R
SENSE1 SENSE2
4.7nF
MODE
OR
MODE
1k
R
OVP1
CSN OR ISN
5.1Ω
8710 F014b
R
R
OVP2
OVP1
V
= V + 1.224V
Z
V
= 1.224V • 1 +
IN_OVP
IN_OVP
(
)
8710 F13
Figure 14b. Differential and Common Mode RC Filter on CSP/
CSN and/or ISP/ISN Pins
Figure 13. Input Overvoltage Protection
8710f
23
For more information www.linear.com/LT8710
LT8710
applicaTions inForMaTion
The RC product should be kept less than 30ns, which is
simply the total series R (5.1Ω+5.1Ω in this case) times
the equivalent capacitance seen across the sense pins
(2.2nF for Figure 14a and 2.35nF for Figure 14b).
Driving SYNC high for an extended period of time effec-
tively stops the operating clock and prevents latch SR1
from becoming set (see Block Diagram). As a result, the
switching operation of the LT8710 will stop.
The duty cycle of the SYNC signal must be between 20ꢀ
and 80ꢀ for proper operation. Also, the frequency of the
SYNC signal must meet the following two criteria:
SWITCHING FREQUENCY
TheLT8710usesaconstantfrequencyarchitecturebetween
100kHz and 750kHz. The frequency can be set using the
internal oscillator or can be synchronized to an external
clock source. Selection of the switching frequency is a
trade-off between efficiency and component size. Low
frequency operation increases efficiency by reducing
MOSFET switching losses, but requires larger inductance
and/or capacitance to maintain low output ripple voltage.
For high power applications, consider operating at lower
frequencies to minimize MOSFET heating from switching
losses. The switching frequency can be set by placing an
appropriate resistor from the RT pin to ground and tying
theSYNCpinlow. Thefrequencycanalsobesynchronized
to an external clock source driven into the SYNC pin. The
following sections provide more details.
1. SYNC may not toggle outside the frequency range of
100kHz to 750kHz unless it is stopped below 0.4V
to enable the free-running oscillator.
2. The SYNC frequency can always be higher than the
free-running oscillator frequency (as set by the R
T
resistor), f , but should not be less than 25ꢀ
OSC
below f
.
OSC
AfterSYNCbeginstoggling,itisrecommendedthatswitch-
ing activity is stopped before the SYNC pin stops toggling.
Excess negative inductor current can result when SYNC
stops toggling as the LT8710 transitions from the external
SYNC clock source to the internal free-running oscillator
clock. Switching activity can be stopped by driving the
EN/FBIN pin low.
Oscillator Timing Resistor (R )
T
The operating frequency of the LT8710 can be set by the
internal free-running oscillator. When the SYNC pin is
driven low (< 0.4V), the frequency of operation is set by a
resistorfromtheRT pintoground.Theoscillatorfrequency
is calculated using the following formula:
LDO REGULATORS
The LT8710 has two linear regulators to run the BG and
TG gate drivers. The INTV LDO regulates 6.3V (typical)
CC
above ground, and the INTV regulator regulates 6.18V
EE
(typical) below the BIAS pin.
35,880
f=
R +1
T
INTV LDO Regulator
CC
The INTV LDO is used as the top rail for the BG gate
where f is in kHz and R is in k. Conversely, R (in k) can
CC
T
T
driverforpositiveoutputconverters. Inthecaseofanega-
be calculated from the desired frequency (in kHz) using:
tive output converter, the INTV LDO is used as the top
CC
35,880
rail for both the BG and TG gate drivers (BIAS and INTV
EE
R =
–1
T
must tie to INTV and GND respectively). An external
f
CC
capacitor greater than 2.2µF must be placed from the
INTV pin to ground. The UVLO threshold on INTV is
Clock Synchronization
CC
CC
4V (typical), and the LT8710 will be in reset until the LDO
comes out of UVLO.
An external source can set the operating frequency of the
LT8710 by providing a digital clock signal into the SYNC
The INTV LDO can run off V or BIAS and will intel-
pin (R resistor still required). The LT8710 will operate at
CC
IN
T
ligently select to run off the best for minimizing chip
the SYNC clock frequency. The LT8710 will revert to its
internal free-running oscillator clock when the SYNC pin
is driven below 0.4V for a few free-running clock periods.
power loss, but at the same time, select the proper input
for maintaining INTV as close to 6.3V as possible. For
CC
8710f
24
For more information www.linear.com/LT8710
LT8710
applicaTions inForMaTion
INTV LDO Regulator
EE
V
IN
24V
The BIAS and INTV voltages are used for the top and
EE
bottom rails of the TG gate driver respectively. An exter-
nal capacitor greater than 2.2µF must be placed between
BIAS
BIAS
12V
11.2V
the BIAS and INTV pins. The UVLO threshold on the
EE
8.5V
8V
regulator (BIAS-INTV ) is 3.42V (typical) as long as the
EE
BIAS voltage is greater than ~3.36V. The TG pin can begin
TIME
V
IN
BIAS
V
IN
switching after the INTV regulator comes out of UVLO.
EE
SELECTED INPUT
8710 F15
For positive output converters, BIAS must be tied to the
converter’soutputvoltage.Fornegativeoutputconverters,
Figure 15. INTVCC Input Voltage Selection
BIAS must connect to the INTV pin and the INTV pin
CC
EE
example, Figure 15 is a plot that shows an application
where V /BIAS is regulated to 12V and V starts at
ties to ground. In this manner, the voltage of the INTV
EE
regulatorisdriventotheINTV voltageof6.3Vandhence
OUT
IN
CC
24V and ramps down to 5V and indicates that INTV is
the TG gate driver will have levels of 0V and 6.3V.
CC
regulating from V or BIAS.
IN
Overcurrent protection circuitry typically limits the maxi-
mum current draw from the regulator to ~70mA. If the
BIAS voltage is greater than 20V (typical), then the current
limit of the regulator reduces linearly with input voltage
Overcurrent protection circuitry typically limits the maxi-
mum current draw from the LDO to ~125mA and ~65mA
whenrunningfromV andBIASrespectively.WhenINTV
IN
CC
is below ~3.5V during start-up or an overload condition,
to limit the maximum power in the INTV pass device.
EE
thetypicalcurrentlimitisreducedto~25mAwhenrunning
See the INTV Current Limit vs BIAS plot in the Typical
EE
from either V or BIAS. If the selected input voltage is
Performance Characteristics.
IN
greaterthan20V(typical),thenthecurrentlimitoftheLDO
ThesamethermalguidelinesfromtheINTV LDORegula-
CC
reduces linearly with input voltage to limit the maximum
tor section apply to the INTV regulator as well.
EE
power in the INTV pass device. See the INTV Current
CC
CC
Limit vs V or BIAS plot in the Typical Performance Char-
IN
NON-SYNCHRONOUS CONVERTER
acteristics. Ifthedietemperature exceeds 175°C(typical),
the current limit of the LDO drops to 0.
It may be desirable in some applications to replace the
external PFET with a Schottky diode to make a non-
synchronous converter. One example would be a high
output voltage application because the voltage drop
across the rectifier has a small affect on the efficiency of
the converter. In fact, for high output voltage applications,
replacing the PFET with a Schottky may result in higher
efficiencybecausetheLT8710doesn’thavetosupplygate
drive to the PFET. Figure 16 shows the recommended
connections for using the LT8710 as a non-synchronous
boost converter, however the same concept can be used
for any other converter.
PowerdissipatedintheINTV LDOshouldbeminimizedto
CC
improveefficiencyandpreventoverheatingoftheLT8710.
The current limit reduction with input voltage circuit helps
prevent the part from overheating, but these guidelines
should be followed. The maximum current drawn through
the INTV LDO occurs under the following conditions:
CC
1. Large (capacitive) MOSFETs being driven at high
frequencies.
2. The converter’s switch voltage (V
for boost or
OUT
V + |V | for dual inductor converters) is high,
IN
OUT
thus requiring more charge to turn the MOSFET
Note that the MODE pin must be tied high if using the
LT8710 as a non-synchronous converter or else the out-
put might not be regulated at light load. Also, the TG pin
gates on and off.
In general, use appropriately sized MOSFETs and lower
the switching frequency for higher voltage applications to
keep the INTV current at a minimum.
CC
8710f
25
For more information www.linear.com/LT8710
LT8710
applicaTions inForMaTion
must be left floating or permanent damage could occur to
the TG gate driver. The schematic of Figure 16 could be
modified if needed. If it is not desirable to monitor and/
• Place bypass capacitors for the V and BIAS pins (1µF
IN
or greater) as close as possible to the LT8710.
• Place bypass capacitors for the INTV and INTV
CC
EE
or control the output current, R
is not needed and
SENSE2
(between BIAS and INTV ) pins (2.2µF or greater) as
EE
simply tie the ISP and ISN pins to INTV . The IMON pin
CC
close as possible to the LT8710.
canbeleftfloatingorcanconnecttoground. TheBIASand
INTV pins can tie to ground if the dual input feature of
• The load should connect directly to the positive and
negative terminals of the output capacitor for best load
regulation.
EE
the INTV LDO is not needed and V stays above 4.5V.
CC
IN
L1
R
SENSE2
V
OUT
V
IN
Boost Topology Specific Layout Guidelines
MN
C
OUT1
C
OUT2
C
IN1
R
SENSE1
• Keeplengthofloop(highspeedswitchingpath)govern-
ingR ,MN,MP,R ,C ,andgroundreturn
SENSE1 SENSE2 OUT
as short as possible to minimize parasitic inductive
spikes at the switch node during switching.
BG
CSN
CSP
TG
ISP
V
IN
R
R
IN1
ISN
LT8710
EN/FBIN
BIAS
V
V
OUT
IN
IN2
R
FBX
INTV
L1
EE
MODE
FBX
C
INTV
CC
+
IN2
GND
IMON
MP
8710 F16
MN
Figure 16. Simplified Schematic of a Non-Synchronous
Boost Converter
R
SENSE2
C
C
IN
OUT
LAYOUT GUIDELINES FOR BOOST, SEPIC, AND DUAL
INDUCTOR INVERTING TOPOLOGIES
R
SENSE1
General Layout Guidelines
LT8710
CKT
GND
• To optimize thermal performance, solder the exposed
pad of the LT8710 to the ground plane with multiple
vias around the pad connecting to additional ground
planes.
8705 F17
Figure 17. Suggested Component Placement for Boost Topology
• Highspeedswitchingpath(seespecifictopologybelow
formoreinformation)mustbekeptasshortaspossible.
SEPIC Topology Specific Layout Guidelines
• The FBX, V , IMON, and RT components should be
• Keeplengthofloop(highspeedswitchingpath)govern-
C
placed as close to the LT8710 as possible, while being
far away as practically possible from switching nodes.
The ground for these components should be separated
from the switch current path.
ing R
, MN, C1, MP, R
, C , and ground
SENSE1
SENSE2 OUT
return as short as possible to minimize parasitic induc-
tive spikes at the switch node during switching.
8710f
26
For more information www.linear.com/LT8710
LT8710
applicaTions inForMaTion
V
V
OUT
IN
V
V
OUT
L1 L2
IN
C1
L1 L2
C1
MP
MN
MP
R1
MN
C
C
IN
OUT
C2
R
SENSE2
C
C
OUT
IN
D1
R
R
SENSE2
SENSE1
R
SENSE1
LT8710
CKT
GND
8705 F19
LT8710
CKT
GND
Figure 19. Suggested Component Placement for Dual Inductor
Inverting Topology
8705 F18
Figure 18. Suggested Component Placement for SEPIC Topology
R
Dual Inductor Inverting Topology Specific Layout
Guidelines
SENSE1, 2
TO
CURRENT
SENSE
• Keep ground return path from the low side of R
SENSE1
8705 F20
PINS
and R
(to chip) separated from C ’s and C ’s
SENSE2
IN OUT
groundreturnpath(tochip)inordertominimizeswitch-
ing noise coupling into the input and output. Notice the
Figure 20. Suggested Routing and Connections of CSP/CSN
and ISP/ISN Lines
cuts in the ground return for the low side of R
SENSE1
and R
.
SENSE2
THERMAL CONSIDERATIONS
Overview
• Keeplengthofloop(highspeedswitchingpath)govern-
ing R , MN, C1, MP, R , and ground return
SENSE1
SENSE2
as short as possible to minimize parasitic inductive
spikes at the switch node during switching.
The primary components on the board that consume the
most power and produce the most heat are the power
switches,MNandMP,thepowerinductor,andtheLT8710
IC. It is imperative that a good thermal path be provided
for these components to dissipate the heat generated
within the packages. This can be accomplished by taking
advantage of the thermal pads on the underside of the
packages. It is recommended that multiple vias in the
printed circuit board be used to conduct heat away from
each of these components and into a copper plane with as
muchareaaspossible. Forthecaseofthepowerswitches,
the copper area of the drain connections shouldn’t be too
big as to create a large EMI surface that can radiate noise
around the board.
Current Sense Resistor Layout Guidelines
• Route the CSP/CSN and ISP/ISN lines differentially
(close together) from the chip to the current sense
resistor as shown in Figure 20.
• Place the vias that connect the CSP/CSN and ISP/ISN
lines directly at the terminals of the current sense resis-
tor as shown in Figure 20.
8710f
27
For more information www.linear.com/LT8710
LT8710
applicaTions inForMaTion
Power MOSFET Loss and Thermal Calculations
2
=
P
P
P
P
+
MOSFET
I R SWITCHING
2
=I •R
+V •I •f•t
P
+
The LT8710 requires two external power MOSFETs, an
NFET switch for the BG gate driver and a PFET switch for
the TG gate driver. Important parameters for estimating
the power dissipation in the MOSFETs are:
MN
MP
N
DSON DS
N
RF RR –N
I
1.6
VY
2
=I •R
P
P
I
+V • I +
DSON BD PK
•f•140ns+P
RR –P
I
i
i
RIPPLE
OUT
RIPPLE
=
; I =I
+
; I =I
–
1. On-resistance (R
)
PK SW
VY SW
SW
DSON
(1–DC)
2
2
2. Gate-to-drain charge (Q )
GD
2
i
RIPPLE
12
2
+
I = DC• I
N
SW
3. PFET body diode forward voltage (V )
BD
4. V of the FETs during their Off-Time
DS
2
i
RIPPLE
12
2
+
I = 1–DC • I
(
)
P
SW
5. Switch current (I
)
SW
6. Switching frequency (f)
V
•I •t •f
DS RR RR
P
P
≈
≈
RR –N
RR –P
The power loss in each power switch has a DC and AC
term. The DC term is when the power switch is fully on,
and the AC term is when the power switch is transitioning
from on-off or off-on.
2
V
•I •t •f
DS RR RR
2
The following applies for both the NFET and PFET power
switches. For a boost application, the average current
where:
f
= Switching Frequency
= NFET RMS Current
= PFET RMS Current
through the MOSFET (I ) during its on-time, is the same
SW
I
N
as the average input current. The magnitude of the drain-
to-sourcevoltage,V ,duringitsoff-timeisapproximately
DS
I
t
P
V
OUT
. For a SEPIC or dual inductor inverting application,
= Average of the rise and fall times of the NFET’s
drain voltage
RF
the average current through each MOSFET (I ) during
SW
its on-time, is the sum of the average input current and
the output current. The |V | voltage during the off-time
I
I
I
= Average switch current during its on-time
= Peak inductor current
DS
OUT
SW
isapproximatelyV +|V |. Duringthenon-overlaptime
IN
PK
of the gate drivers, the peak and valley inductor current
is flowing through the body diode of the PFET. Below are
the equations for the power loss in MN and MP.
= Valley inductor current
VY
i
= Inductor ripple current
RIPPLE
DC = Switch duty cycle (see Power Switch Duty
Cycle section in Appendix)
V
V
= PFET body diode forward voltage at I
SW
BD
DS
= Voltage across the FET when it’s off. V
for
OUT
a boost, V + |V | for a dual inductor
IN
OUT
inverting or SEPIC converter
P
P
= PFET body diode reverse recovery power loss
in the NFET
RR-N
= PFET body diode reverse recovery power loss
in the PFET
RR-P
8710f
28
For more information www.linear.com/LT8710
LT8710
applicaTions inForMaTion
I
= CurrentneededtoremovethePFETbodydiode
charge
V
V
= INTV LDO selected input voltage, V or
RR
SELECT
CC
IN
BIAS (see LDO REGULATORS section)
t
RR
= Reverse recovery time of PFET body diode
= Higher of V and BIAS.
MAX
IN
Typical values for t are 10ns to 40ns depending on the
Inverting Converter: Due to BIAS connecting to INTV
RF
CC
MOSFET capacitance and drain voltage. In general, the
and INTV connecting to ground (see Typical Applica-
EE
lower the Q of the MOSFET, the faster the rise and fall
tions), all the chip power comes from the V pin. The
GD
IN
times of its drain voltage. For best calculations, measure
INTV LDO primarily supplies voltage for both the BG
CC
the rise and fall times in the application.
and TG gate drivers. The chip Q current comes from
V . For consistency, the power that’s needed to run
IN
PFET body diode reverse recovery power loss is depen-
dent on many factors and can be difficult to quantify in
an application. In general, this power loss increases with
the TG gate driver is still labeled as P even though
VEE
the power is coming from INTV . Below are the chip
CC
power equations for an inverting converter:
higher V and/or higher switching frequency.
DS
P
P
P
= 1.04 • Q • f • V
MN IN
VCC
Chip Power and Thermal Calculations
= Q • f • V
VEE1
VEE2
P = 5.5mA • V
MP
IN
Power dissipation in the LT8710 chip comes from three
= 3.15mA • (1 – DC) • V
IN
primary sources: INTV and INTV LDOs providing gate
CC
EE
Q
IN
drive to the BG and TG pins and additional input quiescent
current. The average current through each LDO is deter-
mined by the gate charge of the power switches, MN and
MP, and the switching frequency. Below are the equations
for calculating the chip power loss followed by examples.
where:
f
= Switching frequency
DC = Switch duty cycle (see Power Switch Duty Cycle
section in Appendix)
Noninverting Converter: The INTV LDO primarily sup-
CC
Q
MN
= Total gate charge of NFET power switch (MN)
plies voltage for the BG gate driver. The BIAS and INTV
EE
at 6.3V
GS
voltages supply the top and bottom rails of the TG gate
driver respectively. The chip Q current comes from the
Q
MP
= Total gate charge of PFET power switch (MP)
higher of V and BIAS. Below are the chip power equa-
at 6.3V
IN
SG
tions for a noninverting converter:
Chip Power Calculations Example
P
P
P
= 1.04 • Q • f • V
MN SELECT
VCC
Table 4 calculates the power dissipation of the LT8710 for
= Q • f • V
VEE1
VEE2
P = 4mA • V
MP
BIAS
a 200kHz, 3V – 40V to 5V SEPIC application when V is
= 3.1mA • (1 – DC) • V
IN
BIAS
12V. From P
in Table 4, the die junction temperature
CHIP
Q
MAX
canbecalculatedusingtheappropriatethermalresistance
where:
and worst-case ambient temperature:
f
= Switching frequency
T = T + Q • P
J CHIP
A
JA
DC
= Switch duty cycle (see Power Switch Duty
Cycle section in Appendix)
where T = die junction temperature, T = ambient tem-
J
A
perature and θ is the thermal resistance from the silicon
JA
Q
MN
= TotalgatechargeofNFETpowerswitch(MN)
junction to the ambient air.
at 6.3V
GS
Thepublishedθ valueis38°C/WfortheTSSOPexposed
JA
Q
= TotalgatechargeofPFETpowerswitch(MP)
pad package. In practice, lower θ values are realizable
MP
JA
at 6.18V
if board layout is performed with appropriate grounding
SG
8710f
29
For more information www.linear.com/LT8710
LT8710
applicaTions inForMaTion
(accounting for heat sinking properties of the board) and
Thermal Lockout
other considerations listed in the Layout Guidelines sec-
If the die temperature reaches ~175°C, the part will go into
reset, so the power switches turn off and the soft-start
capacitor will be discharged. The LT8710 will come out of
reset when the die temperature drops by ~5°C (typical).
tion.Forinstance,aθ valueof~22°C/Wwasconsistently
JA
achieved when board layout was optimized as per the
suggestions in the Layout Guidelines section.
Table 4. Power Calculations Example for a 200kHz, 3V to 40V to 5V/5A SEPIC (VIN = 12V, MN = FDMS86500L and MP = SUD50P06-15)
DEFINITION OF VARIABLES
EQUATION
DESIGN EXAMPLE
VALUE
DC = Switch Duty Cycle
V
5V
DC ≅
DC ≅ 29.4ꢀ
OUT
DC ≅
12V+5V
V
+ V
IN OUT
P
= INTV LDO Power Driving
P
VCC
= 1.04 • Q • f • V
P
VCC
= 1.04 • 73nC • 200kHz • 12V
P
VCC
= 182.2mW
VCC
CC
MN
SELECT
the BG Gate Driver
Q
= NFET Total Gate Charge at
= 6.3V
MN
GS
V
f = Switching Frequency
V
= LDO Chooses V
IN
SELECT
P
= INTV LDO Power
P
VEE1
= Q • f • V
P
VEE1
= 55nC • 200kHz • 5V
P
VEE1
= 55mW
VEE1
EE
MP
BIAS
Driving the TG Gate Driver
Q
= PFET Total Gate Charge at
= 4.25V
MP
SG
V
P
= Additional TG Gate Driver
P
VEE2
= 3.1mA • (1 – DC) • V
P
VEE2
= 3.1mA • (1– 0.294) • 5V
P
VEE2
= 10.9mW
VEE2
BIAS
Power Loss
P = Chip Bias Loss
MAX
BIAS
P = 4mA • V
P = 4mA • 12V
Q
P = 48mW
Q
Q
Q
MAX
V
= Higher Voltage of V and
IN
P
CHIP
= 296.1mW
8710f
30
For more information www.linear.com/LT8710
LT8710
appenDix
POWER SWITCH DUTY CYCLE
The LT8710 can be used in configurations where the duty
cycle is higher than DC
, but it must be operated in the
MAX
In order to maintain loop stability and deliver adequate
current to the load, the external power NFET (MN in the
Block Diagram) cannot remain on for 100ꢀ of each clock
cycle. The maximum allowable duty cycle is given by:
discontinuousconductionmode(MODEpinmustbehigh)
so that the effective duty cycle is reduced.
INDUCTOR SELECTION
T –MinOffTime
(
)
•100ꢀ
P
DCMAX
=
For high efficiency, choose inductors with high frequency
core material, such as ferrite, to reduce core losses. Also
toimproveefficiency, chooseinductorswithmorevolume
for a given inductance. The inductor should have low DCR
T
P
where T is the clock period and MinOffTime (found in the
P
Electrical Characteristics) is a maximum of 480ns.
2
(copper-wireresistance)toreduceI Rlosses,andmustbe
Conversely, the external power NFET (MN in the Block
Diagram) cannot remain off for 100ꢀ of each clock cycle,
andwillturnonforaminimumontime(MinOnTime)when
in regulation. This MinOnTime governs the minimum al-
lowable duty cycle given by:
able to handle the peak inductor current without saturat-
ing. Note that in some applications, the current handling
requirements of the inductor can be lower, such as in the
SEPIC topology where each inductor carries a fraction of
the total switch current. Molded chokes or chip inductors
do not have enough core area to support peak inductor
currents in the 5A to 15A range. To minimize radiated
noise, use a toroidal or shielded inductor. See Table 5 for
a list of inductor manufacturers.
(MinOnTime)
DCMIN
=
•100ꢀ
T
P
where T is the clock period and MinOnTime (found in the
P
Electrical Characteristics) is a maximum of 420ns.
Table 5. Inductor Manufacturers
Coilcraft
MSS1278, XAL1010, and
MSD1278 Series
www.coilcraft.com
Theapplicationshouldbedesignedsuchthattheoperating
duty cycle is between DC
and DC
.
MIN
MAX
Cooper
DRQ127, DR127, and
www.cooperbussmann.com
Bussmann HCM1104 Series
Duty cycle equations for several common topologies are
given below where V is the voltage drop across the
Vishay
Würth
IHLP Series
www.vishay.com
ON_MP
WE-DCT Series
WE-CFWI Series
www.we-online.com
external power PFET (MP) when it is on, and V
is
ON_MN
the voltage drop across the external power NFET (MN)
when it is on.
Minimum Inductance
For the boost topology (see Figure 5):
Although there can be a trade-off with efficiency, it is often
desirable to minimize board space by choosing smaller
inductors. When choosing an inductor, there are three
conditionsthatlimittheminimuminductance;(1)providing
adequate load current, and (2) avoidance of subharmonic
oscillation, and (3) supplying a minimum ripple current to
avoid false tripping of the current comparator.
V
– V +V
ON_MP
+V
OUT
IN
– V
ON_MP ON_MN
DCBOOST
≅
V
OUT
For the SEPIC or dual inductor inverting topology (see
Figures 6 and 7):
V
V
ON_MP
|
|+
OUT
DCSEPIC_&_INVERT
≅
V + V
|
|+V
– V
IN
OUT
ON_MP ON_MN
8710f
31
For more information www.linear.com/LT8710
LT8710
appenDix
Adequate Load Current
Avoiding Subharmonic Oscillations
Small value inductors result in increased ripple currents
and thus, due to the limited peak switch current, decrease
the average current that can be provided to the load. In
ordertoprovideadequateloadcurrent,Lshouldbeatleast:
The LT8710’s internal slope compensation circuit will
prevent subharmonic oscillations that can occur when
the duty cycle is greater than 50ꢀ, provided that the in-
ductance exceeds a minimum value. In applications that
operate with duty cycles greater than 50ꢀ, the inductance
must be at least:
V
•DC
Boost
Topology
IN
LBOOST
≥
V
V
•I
CSPN
OUT OUT
2•f•
–
V
IN
•R
•(2•DC–1)
SENSE1
R
V •η
LMIN
≥
SENSE1
IN
40m•DC•f•(1–DC)
where
or
SEPIC
or
L
L
= L for boost topologies (see Figure 5)
MIN
MIN
1
V
•DC
IN
LDUAL
≥
Inverting
V
R
|V |•I
= L = L for coupled dual inductor topologies
CSPN
OUT OUT
1
2
2•f•
–
–I
OUT
Topologies
(see Figures 6 and 7)
V •η
IN
SENSE1
L
= L || L for uncoupled dual inductor topologies
1 2
MIN
where:
(see Figures 6 and 7)
L
L
= L for boost topologies (see Figure 5)
1
BOOST
DUAL
Maximum Inductance
= L = L for coupled dual inductor topologies
1
2
Excessive inductance can reduce ripple current to levels
thataredifficultforthecurrentcomparator(A5intheBlock
Diagram) to cleanly discriminate, thus causing duty cycle
jitter and/or poor regulation. The maximum inductance
can be calculated by:
(see Figures 6 and 7)
L
= L || L for uncoupled dual inductor topolo-
1 2
gies (see Figures 6 and 7)
DUAL
DC
= Switch duty cycle (see previous section)
V
= Current limit voltage at the operating switch
duty cycle (see Max Current Limit vs Duty
Cycle (CSP – CSN) plot in the Typical Per-
formance Characteristics)
CSPN
V
•R
5m•f
•DC
IN SENSE1
LMAX
where:
≤
R
= Current sense resistor connected across
the CSP-CSN pins (see Block Diagram)
SENSE1
L
L
= L for boost topologies (see Figure 5)
1
MAX
MAX
= L = L for coupled dual inductor topologies
1
2
η
= Powerconversionefficiency(assume90ꢀ)
= Switching frequency
(see Figures 6 and 7)
f
L
MAX
= L || L for uncoupled dual inductor topologies
1
2
(see Figures 6 and 7)
I
= Maximum output current
OUT
Negative values of L
or L
indicate that the out-
BOOST
DUAL
Inductor Current Rating
put load current, I , exceeds the switch current limit
OUT
The inductor(s) must have a rating greater than its (their)
peak operating current to prevent inductor saturation,
which would result in efficiency losses. The maximum
capability of the converter. Decrease R
the switch current limit.
to increase
SENSE1
8710f
32
For more information www.linear.com/LT8710
LT8710
appenDix
inductor current (considering start-up and steady-state
conditions) is given by:
4. Total gate charge (Q )
G
5. Turn-off delay time (t
)
D(OFF)
2
54mV –16mV •DC V •T
IN MIN_PROP
6. Package has exposed paddle
I
=
+
L_PEAK
R
L
SENSE1
The drain-to-source breakdown voltage of the NFET and
PFET power MOSFETs must exceed:
where
• BV
• BV
> V
for boost converter
OUT
DSS
I
= Peak inductor current in L for a boost
L_PEAK
1
topology, orthesumofthepeakinductor
> V +|V | for SEPIC or dual inductor
inverting converter
DSS
IN
OUT
currents for dual inductor topologies.
T
= 100ns (propagation delay through the
current feedback loop).
IfoperatingclosetotheBV ratingoftheMOSFET,check
MIN_PROP
DSS
theleakagespecificationsontheMOSFETbecauseleakage
can decrease the efficiency of the converter.
Forwideinputvoltagerangeapplications,astheinputvolt-
ageincreases,themaxpeakinductorcurrentalsoincreases
due to the duty cycle decreasing. It is recommended to
utilize the output current limiting feature to reduce the
maxpeakinductorcurrentgivenbythefollowingequation:
The NFET and PFET gate-to-source drive is approximately
6.3V and 6.18V respectively, so logic level MOSFETs are
required. The BG gate driver can begin switching when
the INTV voltage exceeds ~4V, so ensure the selected
CC
NFET is in the linear mode of operation with 4V of gate-
V
V •DC
IN
•(1–DC) 2•f•L
ISPN
to-source drive to prevent possible damage to the NFET.
I
=
+
L_PEAK
R
SENSE2
The TG gate driver can begin switching when the BIAS-
INTV voltage exceeds ~3.42V, so it is optimal that the
where….
EE
PFET be in the linear mode of operation with 3.42V of
gate-to-source drive. However, the PFET is less likely to
get damaged if it’s not operating in the linear region since
the drain-to-source voltage is clamped by its body diode
during the NFET’s off-time. Having said that, try to choose
a PFET with a low body diode reverse recovery time to
minimize stored charge in the PFET. The stored charge in
the PFET body diode gets removed when the NFET switch
turns on and can lead to efficiency hits especially in ap-
V
= 57mV max for noninverting converters and
ISPN
60mV max for inverting converters.
Note that these equations offer conservative results for
the required inductor current ratings. The current ratings
could be lower for applications with light loads, and if
the SS capacitor is sized appropriately to limit inductor
currents at start-up.
plications where the V of the PFET (during off-time) is
DS
high. For these applications, it may be beneficial to put a
Schottky diode across the PFET to reduce the amount of
charge in the PFET body diode. In applications where the
output voltage is high in magnitude, it may be better to
replacethePFETwithaSchottkydiodesincetheconverter
may be more efficient with a Schottky.
POWER MOSFET SELECTION
The LT8710 requires two external power MOSFETs, an
NFET switch for the BG gate driver and a PFET switch for
the TG gate driver. It is important to select MOSFETs for
optimizing efficiency. For choosing an NFET and PFET,
the important device parameters are:
Power MOSFET on-resistance and total gate charge go
hand-in-hand and are typically inversely proportional to
each other; the lower the on-resistance, the higher total
gate charge. Choose MOSFETs with an on-resistance to
give a voltage drop to be less than 300mV at the peak
1. Breakdown voltage (BV
)
DSS
2. Gate threshold voltage (V
)
GSTH
3. On-resistance (r
)
DSON
8710f
33
For more information www.linear.com/LT8710
LT8710
appenDix
current. At the same time, choose MOSFETs with a lower
total gate charge to reduce LT8710 power dissipation and
MOSFET switching losses.
Ceramic capacitors should be placed near the regulator
input and output to suppress high frequency switching
noise. A minimum 1µF ceramic capacitor should also be
placed from V to GND and from BIAS to GND as close
IN
The turn-off delay time (t
) of available NFETs is
D(OFF)
to the LT8710 pins as possible. Due to their excellent low
ESR characteristics, ceramic capacitors can significantly
reduce ripple voltage and help reduce power loss in the
higher ESR bulk capacitors. X5R or X7R dielectrics are
preferred, as these materials retain their capacitance over
wide voltage and temperature ranges. Many ceramic ca-
pacitors,particularly0805or0603casesizes,havegreatly
reduced capacitance at the desired operating voltage.
generally smaller than the LT8710’s non-overlap time.
However, the turn-off time of the available PFETs should
be looked at before deciding on a PFET for a given applica-
tion. The turn-off time must be less than the non-overlap
time of the LT8710 or else the NFET and PFET could be
on at the same time and damage to external components
may occur. If the PFET turn-off delay time as specified in
the data sheet is less than the LT8710 non-overlap time,
then the PFET is good to use. If the turn-off delay time is
longer than the non-overlap time, it doesn’t necessarily
mean it can’t be used. It may be unclear how the PFET
manufacturer measures the turn-off delay time, so it is
best to measure the PFET turn-off delay time with respect
to the PFET gate voltage.
Input Capacitor, C
IN
Theinputcapacitor,C ,seestheripplecurrentoftheinput
IN
inductor, L , which eases the capacitancerequirements of
1
C . Below is the equation for calculating the capacitance
IN
of C for 0.5ꢀ input voltage ripple:
IN
Finally, both the NFET and PFET power MOSFETs should
be in a package with an exposed paddle for the drain
connection to be able to dissipate heat. The on-resistance
of MOSFETs is proportional to temperature, so it’s more
efficient if the MOSFETs are running cool with the help
of the exposed paddle. See Table 6 for a list of power
MOSFET manufacturers.
DC
C >
IN
2
8•L•f •0.005
where:
DC = Switch duty cycle (see Power Switch Duty Cycle
section)
L = L
or L
(see Inductor Selection section)
DUAL
BOOST
Table 6. Power MOSFET (NFET and PFET) Manufacturers
f
= Switching frequency
Fairchild Semiconductor
On-Semiconductor
Vishay
www.fairchildsemi.com
www.onsemi.com
www.vishay.com
Theworst-casefortheinputcapacitor(largestcapacitance
needed) is when the input voltage is at its lowest because
the duty cycle is the highest. Keep in mind that the volt-
age rating of the input capacitor needs to be greater than
the maximum input voltage. This equation calculates the
capacitance value during steady-state operation and may
need to be adjusted for desired transient response. Also,
this assumes no ESR, so the input capacitance may need
to be larger depending on the equivalent ESR of the input
capacitor(s).
Diodes Inc.
www.diodes.com
INPUT AND OUTPUT CAPACITOR SELECTION
Input and output capacitance is necessary to suppress
voltage ripple caused by discontinuous current moving
in and out of the regulator. A parallel combination of ca-
pacitors is typically used to achieve high capacitance and
low ESR (equivalent series resistance). Tantalum, special
polymer,aluminumelectrolyticandceramiccapacitorsare
all available in surface mount packages. Capacitors with
low ESR and high ripple current ratings, such as OS-CON
and POSCAP are also available.
Output Capacitor, C
OUT
The output capacitor, C , in a boost or SEPIC topology
OUT
haschoppedcurrentflowingthroughit,whereastheoutput
capacitor in a dual inductor inverting topology sees the
8710f
34
For more information www.linear.com/LT8710
LT8710
appenDix
inductorripplecurrent.Belowistheequationforcalculating
the optimum value for R can be found. The series capaci-
C
the capacitance of C
for 0.5ꢀ output voltage ripple:
tor can be reduced or increased from 4.7nF to speed up
the converter or slow down the converter, respectively.
For the circuit in Figure 7, a 3.3nF series cap was used.
Figures 21a to 21c illustrate this process for the circuit
of Figure 7 with a load current stepped between 2A and
5.5A with an input voltage of 9V. Figure 21a shows the
OUT
Boost or
SEPIC
Topologies
I
•DC
OUT
C
C
>
OUT
f•0.005•V
OUT
or
Dual Inductor
Inverting
Topology
1–DC
transient response with R equal to 1k. The phase mar-
C
>
OUT
2
gin is poor as evidenced by the excessive ringing in the
output voltage and inductor current. In Figure 21b, the
8•L•f •0.005
where:
value of R is increased to 4k, which results in a more
C
dampedresponse.Figure21cshowstheresultswhenR is
I
= Maximum output current of converter
C
OUT
increasedfurtherto11.5k.Thetransientresponseisnicely
damped and the compensation procedure is complete.
DC = Switch duty cycle (see Power Switch Duty Cycle
section)
L
f
= L
orL
(seeInductorSelectionsection)
BOOST
DUAL
V
OUT
200mV/DIV
= Switching frequency
AC-COUPLED
LOAD STEP
5A/DIV
Theworst-casefortheoutputcapacitor(largestcapacitance
needed) is when the output regulation voltage is relatively
low. This equation calculates the capacitance value during
steady-state operation and may need to be adjusted for
desiredtransientresponse. Also, thisassumesnoESR, so
theoutputcapacitancemayneedtobelargerdependingon
the equivalent ESR of the output capacitor(s). See Table 7
for a list of ceramic capacitor manufacturers.
I
+ I
L1 L2
5A/DIV
8705 F21a
200µs/DIV
R
= 1k
C
Figure 21a. Transient Response Shows Excessive Ringing
Table 7. Ceramic Capacitor Manufacturers
V
OUT
200mV/DIV
TDK
www.tdk.com
AC-COUPLED
Murata
www.murata.com
www.t-yuden.com
LOAD STEP
5A/DIV
Taiyo Yuden
I
+ I
L1 L2
5A/DIV
COMPENSATION – ADJUSTMENT
8705 F21b
200µs/DIV
To compensate the feedback loop of the LT8710, a series
resistor capacitor network in parallel with an optional
R
= 4k
C
Figure 21b. Transient Response is Better
single capacitor should be connected from the V pin to
C
GND. For most applications, choose a series capacitor in
the range of 1nF to 10nF with 4.7nF being a good starting
value.Theoptionalparallelcapacitorshouldrangeinvalue
from 47pF to 220pF with 100pF being a good starting
V
OUT
200mV/DIV
AC-COUPLED
LOAD STEP
5A/DIV
value. The compensation resistor, R , is usually in the
C
range of 5k to 50k. A good technique to compensate a
new application is to use a 100k potentiometer in place
I
+ I
L1 L2
5A/DIV
of the series resistor R . With the series and parallel
C
8705 F21c
200µs/DIV
R
= 11.5k
capacitors at 4.7nF and 100pF respectively, adjust the
potentiometer while observing the transient response and
C
Figure 21c. Transient Response is Well Damped
8710f
35
For more information www.linear.com/LT8710
LT8710
appenDix
COMPENSATION – THEORY
Note that the maximum output currents of g and g
mp ma
are finite. The external current sense resistor, R
sets the value of:
,
SENSE1
Like all other current mode switching regulators, the
LT8710 needs to be compensated for stable and efficient
operation. Two feedback loops are used in the LT8710: a
fast current loop which does not require compensation,
and a slower voltage loop which does. Standard bode plot
analysis can be used to understand and adjust the voltage
feedback loop.
1
g
≈
mp
6•R
SENSE1
The error amplifier, g , is nominally about 200µmhos
ma
with a source and sink current of about 12µA and 19µA
respectively.
As with any feedback loop, identifying the gain and phase
contribution of the various elements in the loop is critical.
Figure 22 shows the key equivalent elements of a boost
converter. Because of the fast current control loop, the
power stage of the IC, inductor and PFET have been re-
placedbyacombinationoftheequivalenttransconductance
From Figure 22, the DC gain, poles and zeros can be
calculated as follows:
DC GAIN:
V
R
0.5•R
2
IN
L
A
=g •R •g •η •
•
•
DC ma
O
mp
amplifier g and the current controlled current source
mp
V
2 R +0.5•R
OUT
FBX 2
ηV
IN
2
I
(which converts I to
). G acts as a current
mp
VIN
VIN
V
Output Pole:P1=
OUT
2•π •R •C
source where the peak input current, I , is proportional
L
OUT
VIN
1
to the V voltage and current sense resistor, R
.
C
SENSE1
Error AmpPole:P2=
Error Amp Zero: Z1=
2•π •(R +R )•C
C
O
C
1
–
V
2•π •R •C
OUT
C
C
g
mp
I
VIN
+
R
L
R
R
L
1
ESR
η • V
IN
• I
VIN
ESR Zero: Z2=
V
V
OUT
C
OUT
2•π •R •C
ESR OUT
2
•R
C
PL
1.213V
REFERENCE
IN
L
2
RHP Zero: Z3=
2•π •V
•L
OUT
R
+
–
FBX
V
C
g
ma
R2
R2
f
3
S
FBX
HighFrequency Pole:P3>
R
R
O
C
C
F
8710 F22
C
C
1
PhaseLead Zero: Z4=
2•π •R •C
FBX PL
C : COMPENSATION CAPACITOR
C
OUT
PL
C
C
: OUTPUT CAPACITOR
1
: PHASE LEAD CAPACITOR
PhaseLeadPole:P4=
C : HIGH FREQUENCY FILTER CAPACITOR
F
R
R
•0.5•R
+0.5•R
1
g
g
: TRANSCONDUCTANCE AMPLIFIER INSIDE IC
: POWER STAGE TRANSCONDUCTANCE AMPLIFIER
FBX
2
ma
mp
2•π •
•C
PL
R : COMPENSATION RESISTOR
C
FBX
2
R : OUTPUT RESISTANCE DEFINED AS V /I
OUT LOADMAX
L
R : OUTPUT RESISTANCE OF g
O
ma
C
C
R2, R : FEEDBACK RESISTOR DIVIDER NETWORK
FBX
Error AmpFilter Pole:P5=
,C <
F
R
: OUTPUT CAPACITOR ESR
ESR
R •R
10
C
O
η: CONVERTER EFFICIENCY (~90% AT HIGHER CURRENTS)
2•π •
•C
F
R +R
C
O
Figure 22. Boost Converter Equivalent Model
The current mode zero (Z3) is a right half plane zero
which can be an issue in feedback control design, but is
manageable with proper external component selection.
8710f
36
For more information www.linear.com/LT8710
LT8710
appenDix
Using the circuit in Figure 24 with a 4A load as an example,
Table 9 shows the parameters used to generate the bode
plot shown in Figure 23.
From Figure 23, the phase is –135° when the gain reaches
0dB giving a phase margin of 45°. The crossover fre-
quency is 20kHz, which is about three times lower than
the frequency of the RHP zero Z3 to achieve adequate
phase margin.
Table 9: Bode Plot Parameters
PARAMETER
VALUE
3
UNITS
Ω
COMMENT
Application Specific
Application Specific
Application Specific
Not Adjustable
R
L
140
120
100
80
0
C
88
µF
OUT
–45
R
ESR
2
mΩ
kΩ
pF
–90
R
350
3300
100
0
O
C
PHASE
–135
–180
–225
–270
–315
–360
C
Adjustable
45° AT
20kHz
C
pF
Optional/Adjustable
Optional/Adjustable
Adjustable
60
F
GAIN
C
pF
PL
40
R
18
kΩ
kΩ
kΩ
V
C
20
R
130
14.5
12
Adjustable
FBX
0
R2
Not Adjustable
–20
V
OUT
Application Specific
Application Specific
Not Adjustable
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
V
IN
5
V
8710 F23
g
g
200
167
1.3
400
µmho
mho
µH
ma
Figure 23. Bode Plot for Example Boost Converter
Application Specific
Application Specific
Adjustable
mp
L
f
kHz
OSC
L1
1.3µH
R
SENSE2
5m
V
12V
6A
OUT
MP
V
IN
5V
MN
×2
R
C
OUT
22µF
×4
SENSE1
1m
BG
CSN
CSP
TG
ISP
V
IN
+
R
C
IN1
IN2
ISN
13.3k
330µF
LT8710
EN/FBIN
MODE
BIAS
2.2µF
R
IN2
R
FBX
INTV
EE
10k
2.2µF
130k
C
22µF
×4
IN1
FBX
INTV
RT
CC
FLAG
V
C
R
T
88.7k
R
C
18k
SYNC
GND
C
F
IMON
SS
100pF
C
C
SS
220nF
C
IMON
C
47nF
3.3nF
8710 F24
Figure 24. 5V to 12V Boost Converter
8710f
37
For more information www.linear.com/LT8710
LT8710
Typical applicaTion
300kHz, 4.5V to 25V Input to –5V Output Delivers Up to 7A Output Current
C1
10µF ×2
L1
2.2µH
L2
2.2µH
V
–5V
7A
OUT
V
IN
4.5V TO 25V
C
10µF
×4
IN1
MP
MN
499Ω
D1
C
OUT2
R
+
SENSE1
330µF
1.5m
R
SENSE2
4m
0.47µF
C
OUT1
BG
CSN
CSP TG
100µF
×2
V
IN
ISN
13.3k
10k
ISP
EN/FBIN
MODE
+
BIAS
INTV
60.4k
CC
C
IN2
2.2µF
LT8710
120µF
INTV
2.2µF
EE
INTV
RT
FBX
CC
FLAG
118k
V
C
SYNC
GND
11.5k
IMON
SS
100pF
47nF
220nF
3.3nF
8710 TA02a
L1, L2: WÜRTH 2.2µH WE-CFWI 74485540220
MN: FAIRCHILD FDMS8333L
C
: 10µF, 50V, 1210, X7S
IN1
C
C
C
: OSCON 120µF, 35V, 35SVPF120M
IN2
MP: FAIRCHILD FDD4141
: 100µF, 6.3V, 1812, X5R
OUT1
OUT2
R
R
: 1.5mΩ 2010
SENSE1
: 4mΩ 2512
SENSE2
: OSCON 330µF, 16V, 16SEQP330M
C1: 10µF, 50V, 1210, X7S
D1: NXP PMEG2010EA
Transient Response with 2A to 5.5A to 2A
Output Load Step (VIN = 12)
Efficiency and Power Loss
100
90
80
70
65
50
40
30
20
8
7
6
5
4
3
2
1
0
V
OUT
200mV/DIV
AC-COUPLED
LOAD STEP
5A/DIV
I
+ I
L1 L2
5A/DIV
8710 TA02c
200µs/DIV
V
V
= 5V
IN
IN
= 12V
0
1
2
3
4
5
6
7
LOAD CURRENT (A)
8710 TA02b
8710f
38
For more information www.linear.com/LT8710
LT8710
Typical applicaTion
300kHz, SuperCap Backup Power
V
WHEN V IS PRESENT
IN
IN
V
=
SYSTEM
10.5V WHEN V IS REMOVED
IN
R
SENSE2
50m
D
IN
C1, 10µF
L1, 10µH
MP
V
IN
V
OUT
12V 5ꢀ
15V
C
22µF
×2
C
22µF
×2
IN1
OUT
MN
+
+
+
+
+
+
L2
INPUT POWER
SOURCE CAN BE
REMOVED
C
S1
1.2k
1.2k
1.2k
1.2k
1.2k
1.2k
10µH
60F
R
SENSE1
5.1Ω 5.1Ω
4.7nF 4.7nF
•
5m
C
S2
60F
TG
ISP
BG
IN
CSN
CSP
C
S3
V
60F
49.9k
ISN
LT8710
C
S4
EN/FBIN
60F
BIAS
165k
2.2µF
10k
2.2µF
C
S5
INTV
CC
D1
60F
INTV
EE
15V
C
MODE
RT
FBX
IN2
C
S6
120µF
+
60F
FLAG
R
118k
T
1k
V
C
SYNC
GND
14.3k
2.2nF
IMON
SS
100pF
47nF
220nF
8710 TA03a
L1, L2: COILCRAFT 10µH MSD1278-103ML
MN: FAIRCHILD FDMC8327L
C
C
: 22µF, 25V, 1812, X7R
IN1
: 22µF, 25V, 1812, X7R
OUT
MP: VISHAY Si7611DN
C1: 10µF, 25V, 1210, X7R
R
R
D
: 5mΩ 2010
C
: POWERSTOR HB1840-2R5606-R
SENSE1
SENSE2
IN
S1-6
: 50mΩ 2512
D1: CENTRAL SEMI CMDZ5245B-LTZ
: APPROPRIATE SCHOTTKY DIODE OR IDEAL
DIODE SUCH AS LTC4358, LTC4352, LTC4412, ETC.
SuperCaps Charging When VIN Is Applied
V
IN
10V/DIV
V
System Hold-Up Time vs
System Load Current
OUT
10V/DIV
V
IMON
1V/DIV
200
V
= 10.5V
SYSTEM
DURING HOLD-UP
I
+ I
L1 L2
175
150
125
100
75
5A/DIV
8710 TA03c
30s/DIV
SuperCaps Hold-Up System at 10.5V for ~83s
When VIN Is Removed (ISYSTEM = 1A)
V
IN
10V/DIV
50
V
OUT
10V/DIV
25
0
0
0.5
1
1.5
2
2.5
3
V
IMON
1V/DIV
LOAD CURRENT (A)
8710 TA03b
I
+ I
L1 L2
5A/DIV
8710 TA03d
30s/DIV
8710f
39
For more information www.linear.com/LT8710
LT8710
Typical applicaTion
400kHz, 12V Boost Converter Delivers Up to 6A from a 4.5V to 9V Input
R
L1
SENSE2
5m
V
12V
6A
1.3µH
OUT
MP
V
IN
4.5 TO 9V
C
MN
×2
R
IN1
22µF
×4
C
22µF
×4
+
C
OUT2
330µF
OUT1
SENSE1
1m
TG
ISP
BG
IN
CSN
CSP
V
13.3k
10k
ISN
LT8710
C
OUT2
EN/FBIN
BIAS
330µF
+
2.2µF
130k
MODE
INTV
EE
2.2µF
INTV
CC
FBX
RT
FLAG
88.7k
V
C
SYNC
GND
100pF
18k
3.3nF
IMON
SS
47nF
220nF
8710 TA04a
L1: WÜRTH 1.3µH WE-HCI 7443551130
MN: VISHAY SiR802DP
C
C
C
C
: 22µF, 16V, 1206, X5R
IN1
: OSCON 330µF, 16V, 16SEQP330M
IN2
OUT1
OUT2
MP: VISHAY Si7635DP
: 22µF, 25V, 1812, X7R
R
R
: 1mΩ 2512
SENSE1
: 5mΩ 2512
SENSE2
: OSCON 330µF, 16V, 16SEQP330M
Transient Response with 2A to 5A to 2A
Output Load Step (VIN = 5V)
Efficiency and Power Loss
100
90
80
70
60
50
40
30
20
8
7
6
5
4
3
2
1
0
V
OUT
200mV/DIV
AC-COUPLED
LOAD STEP
2A/DIV
I
+ I
L1 L2
5A/DIV
8710 TA04c
200µs/DIV
V
V
= 5V
= 8V
IN
IN
0
1
2
3
4
5
6
LOAD CURRENT (A)
8710 TA04b
8710f
40
For more information www.linear.com/LT8710
LT8710
Typical applicaTion
300kHz, –5V to 5V Output Cleanly Transitions Through 0V with 3A Source and Sink Capability*
R
SENSE2
10m
MP
TG
ISN
ISP
C1
10µF ×2
L1
4.4µH
L2
4.4µH
V
V
OUT
IN
–5V TO 5V
3A
11V TO
13V
C
22µF
×4
IN1
MN
R
TG
TG
SENSE1
ISP ISN
C
OUT
3m
100µF
×3
V
– V
OUT
IN
DC =
BG
CSN
CSP
2V – V
IN
OUT
V
IN
ISP
FET BV
> 2V – V
IN OUT
> V – V
IN OUT
DSS
CI
VRATING
+
ISN
LT8710
60.4k
6.04k
C
IN2
EN/FBIN
MODE
330µF
V
BIAS
IN
INTV
2.2µF
2.2µF
EE
0V FOR V
–0.5V FOR V
–1V FOR V
= –5V
OUT
INTV
CC
FBX
=
CNTL
V
= 0V
OUT
= 5V
D1
OUT
10nF
RT
FLAG
118k
V
C
SYNC
GND
39.2k
IMON
SS
100pF
Schematic and Equations for Calculating VOUT
47nF
220nF
2.2nF
V
OUT
8710 TA05a
L1, L2: WÜRTH 4.4µH WE-CFWI 74485540440
MN: FAIRCHILD FDMS8333L
C
C
C
: 22µF, 25V, 1812, X7R
R
IN1
IN2
OUT
FBX
LT8710
FBX
: OSCON 330µF, 16V, 16SEQP330M
R
CNTL
~9.6mV
~83.1µA
MP: FAIRCHILD FDD4141
: 100µF, 6.3V, 1812, X5R
C1: 10µF, 25V, 1210, X7R
V
CNTL
R
R
: 3mΩ 2010
SENSE1
SENSE2
: 10mΩ 2512
D1: CENTRAL SEMI CMPD1001
8710 TA05b
* PATENT PENDING
R
FBX
V
= 9.6mV –83.1µA • R
–
(V – 9.6mV)
CNTL
OUT
FBX
R
CNTL
VOUT Cleanly Transitions Through 0V with a 1V,
100Hz Sine Wave CNTL Signal (RLOAD = 2Ω)
Transient Response with Stepping VCNTL from 0V to
–1V to 0V with 2Ω Output Load
V
V
CNTL
CNTL
1V/DIV
1V/DIV
V
OUT
5V/DIV
V
OUT
5V/DIV
+ I
I
L1 L2
I
+ I
L1 L2
10A/DIV
10A/DIV
8710 TA05c
8710 TA05d
5ms/DIV
500µs/DIV
8710f
41
For more information www.linear.com/LT8710
LT8710
Typical applicaTion
300kHz, 3A Sealed Lead Acid Battery Charger with an Optional Negative Temp-Co Bulk and Float Battery Voltage
C1
10µF ×2
L1
3.5µH
R
SENSE2
16m
V
OUT
V
MP1
IN
14.7V BULK
13.77V FLOAT
3A CHARGE
5V TO
30V
C
10µF
×4
C
22µF
×4
IN1
OUT
MN
L2
3.5µH
R
+
SENSE1
5.1Ω 5.1Ω
•
SEALED
LEAD ACID
BATTERY
1.5m
4.7nF 4.7nF
BG
CSN
CSP
TG
ISP
*OPTIONAL
MP2
V
IN
**OPTIONAL
13.3k
10k
ISN
LT8710
C
IN2
INTV
CC
EN/FBIN
MODE
100µF
+
BIAS
2.2µF
196k
INTV
2.2µF
EE
150k
R
NTC
10k
INTV
RT
FBX
CC
220nF
316k
FLAG
118k
100nF
2.37k
V
C
SYNC
6.19k
6.8nF
GND
IMON
SS
100pF
47nF
220nF
L1, L2: WÜRTH 3.5µH WE-CFWI 74485540350
MN: FAIRCHILD FDMS86500L
MP1: VISHAY SUD50P06-15
SEE THE BATTERY CHARGING AND C/10 SECTION
IN APPLICATIONS INFORMATION FOR MORE
INFORMATION ON BATTERY CHARGING
* MP2 DISCONNECTS FBX PIN CURRENT
DRAW FROM BATTERY WHEN LT8710 IS IN
SHUTDOWN
R
R
: 1.5mΩ 2010
: 16mΩ 2512
SENSE1
SENSE2
**PLACE 316kΩ AND 100nF AS CLOSE
TO THE FBX PIN AS POSSIBLE. ALSO,
CONNECT ALL GROUNDS OF THESE
COMPONENTS TO THE LT8710 GROUND
C
C
: 10µF, 50V, 1210, X7S
IN1
OUT
: 22µF, 25V, 1812, X7R
C1: 10µF, 50V, 1210, X7S
MP2: VISHAY Si2343CDS
R
: MURATA NCP18XH103F03RB
8710 TA06a
NTC
Bulk and Float Output Voltage
with **Optional Components
Efficiency vs Input Voltage
95
90
85
80
75
16.0
15.5
15.0
14.5
14.0
13.5
13.0
12.5
12.0
V
= 12V
= 3A
OUT
OUT
I
BULK
FLOAT
5
10
15
20
25
30
–40
–20
0
20
40
60
80
INPUT VOLTAGE (V)
8710 TA06c
TEMPERATURE (°C)
8710 TA06b
8710f
42
For more information www.linear.com/LT8710
LT8710
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev J)
Exposed Pad Variation CB
6.40 – 6.60*
3.86
(.152)
(.252 – .260)
3.86
(.152)
20 1918 17 16 15 14 1312 11
6.60 0.10
2.74
(.108)
4.50 0.10
6.40
(.252)
BSC
2.74
(.108)
SEE NOTE 4
0.45 0.05
1.05 0.10
0.65 BSC
5
7
8
1
2
3
4
6
9 10
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE20 (CB) TSSOP REV J 1012
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
8710f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
43
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT8710
Typical applicaTion
200kHz, Wide Input Range SEPIC Converter Generates a 5V Output with Up to 5A Output Current
C1
10µF ×2
R
L1
2.9µH
SENSE2
6m
V
5V
5A
MP
OUT
V
IN
3V TO 40V (OPERATING)
4.5V TO 40V (START-UP)
+
MN
C
10µF
×6
IN1
C
L2
OUT2
330µF
2.9µH
R
SENSE1
•
1.5m
C
OUT1
TG
ISP
BG
IN
CSN
CSP
100µF
×4
V
4.02k
ISN
LT8710
C
IN2
220µF
EN/FBIN
BIAS
+
10k
2.2µF
2.2µF
45.3k
8.87k
Efficiency and Power Loss
MODE
INTV
EE
INTV
CC
FBX
100
6.00
5.25
4.50
3.75
3.00
2.25
1.50
0.75
0
RT
FLAG
90
80
70
60
50
40
30
20
178k
V
C
SYNC
GND
100pF
IMON
SS
47nF
220nF
6.8nF
8710 TA07a
L1, L2: WÜRTH 2.9µH WE-CFWI 74485540290
MN: FAIRCHILD FDMS86500L
MP: VISHAY SUD50P06-15
R
R
: 1.5mΩ 2010
: 6mΩ 2512
V
V
= 5V
= 12V
SENSE1
SENSE2
IN
IN
C
C
C
: 10µF, 50V, 1210, X7S
IN1
OUT1
OUT2
: 100µF, 6.3V, 1812, X5R
0
1
2
3
4
5
: OSCON 330µF, 16V, 16SEQP330M
LOAD CURRENT (A)
C1: 10µF, 50V, 1210, X7S
8710 TA07b
relaTeD parTs
PART NUMBER
DESCRIPTION
COMMENTS
LT3757A
Boost, Flyback, SEPIC and Inverting Controller
Boost, Flyback, SEPIC and Inverting Controller
Boost, SEPIC and Inverting Controller
2.9V ≤ V ≤ 40V, 100kHz to 1MHz Programmable Operating Frequency,
IN
3mm × 3mm DFN-10 and MSOP-10E Packages
LT3758A
LT3759
LT3957A
LT3958
LT3959
LTC3786
5.5V ≤ V ≤ 100V, 100kHz to 1MHz Programmable Operating Frequency,
IN
3mm × 3mm DFN-10 and MSOP-10E Packages
1.6V ≤ V ≤ 42V, 100kHz to 1MHz Programmable Operating Frequency,
IN
MSOP-12E Package
Boost, Flyback, SEPIC and Inverting Converter
with 5A, 40V Switch
3V ≤ V ≤ 40V, 100kHz to 1MHz Programmable Operating Frequency,
IN
5mm × 6mm QFN Package
Boost, Flyback, SEPIC and Inverting Converter
with 3.3A, 84V Switch
5V ≤ V ≤ 80V, 100kHz to 1MHz Programmable Operating Frequency,
IN
5mm × 6mm QFN Package
Boost, SEPIC and Inverting Converter with 6A,
40V Switch
1.6V ≤ V ≤ 40V, 100kHz to 1MHz Programmable Operating Frequency,
IN
5mm × 6mm QFN Package
Low I Synchronous Step-Up Controller
4.5V (Down to 2.5V After Start-Up) ≤ V ≤ 38V, V
Up to 60V, 55µA
Q
IN
OUT
Quiescent Current, 3mm × 3mm QFN-16, MSOP-16E
8710f
LT 0114 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
44
(408)432-1900 FAX: (408) 434-0507 www.linear.com/8710
●
●
LINEAR TECHNOLOGY CORPORATION 2014
相关型号：
LT8711EFE#PBF
LT8711 - Micropower Synchronous Multitopology Controller with 42V Input Capability; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 85°C
Linear
LT8711EUDC#PBF
LT8711 - Micropower Synchronous Multitopology Controller with 42V Input Capability; Package: QFN; Pins: 20; Temperature Range: -40°C to 85°C
Linear
LT8711IFE#PBF
LT8711 - Micropower Synchronous Multitopology Controller with 42V Input Capability; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 85°C
Linear
LT8711IUDC#PBF
LT8711 - Micropower Synchronous Multitopology Controller with 42V Input Capability; Package: QFN; Pins: 20; Temperature Range: -40°C to 85°C
Linear
LT9001/4S823JT26
RESISTOR, TEMPERATURE DEPENDENT, PTC, 82000ohm, THROUGH HOLE MOUNT, AXIAL LEADED
KOA
LT9001/6S433JT26
RESISTOR, TEMPERATURE DEPENDENT, PTC, 43000ohm, THROUGH HOLE MOUNT, AXIAL LEADED
KOA
©2020 ICPDF网 联系我们和版权申明