LTC1046MJ8 [Linear]
“Inductorless” 5V to + 5V Converter; “电感” 5V至+ 5V转换器
| 型号： | LTC1046MJ8 |
| 厂家： | 
Linear |
| 描述： | “Inductorless” 5V to + 5V Converter |
| 文件： | 总12页 (文件大小：175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1046
“Inductorless”
5V to –5V Converter
U
FEATURES
DESCRIPTIO
The LTC®1046 is a 50mA monolithic CMOS switched
capacitor voltage converter. It plugs in for ICL7660/
LTC1044 in 5V applications where more output current is
needed. The device is optimized to provide high current
capability for input voltages of 6V or less. It trades off
operating voltage to get higher output current. The
LTC1046 provides several voltage conversion functions:
the input voltage can be inverted (VOUT = –VIN), divided
(VOUT =VIN/2) or multiplied (VOUT = ±nVIN).
■
50mA Output Current
■
Plug-In Compatible with ICL7660/LTC1044
■
ROUT = 35ΩMaximum
■
300µA Maximum No Load Supply Current at 5V
■
Boost Pin (Pin 1) for Higher Switching Frequency
■
97% Minimum Open-Circuit Voltage Conversion
Efficiency
■
95% Minimum Power Conversion Efficiency
■
Wide Operating Supply Voltage Range: 1.5V to 6V
■
Easy to Use
Low Cost
Designed to be pin-for-pin and functionally compatible
with the ICL7660 and LTC1044, the LTC1046 provides 2.5
times the output drive capability.
■
U
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
■
Conversion of 5V to ±5V Supplies
■
Precise Voltage Division, VOUT = VIN/2
■
Supply Splitter, VOUT = ±VS/2
U
TYPICAL APPLICATIO
Output Voltage vs Load Current for V+ = 5V
–5
T
= 25°C
A
Generating –5V from 5V
–4
–3
–2
–1
0
LTC1046
ICL7660/LTC1044,
= 55Ω
1
2
3
4
8
7
6
5
R
+
OUT
5V INPUT
BOOST
V
+
CAP
OSC
LV
LTC1046,
= 27Ω
+
R
OUT
GND
10µF
–
CAP
V
OUT
–5V INPUT
10µF
+
1046 TA01
0
10
20
30
40
50
LOAD CURRENT, I (mA)
L
1046 TA02
1
LTC1046
W
U
W W W
U
/O
ABSOLUTE AXI U RATI GS
PACKAGE RDER I FOR ATIO
(Note 1)
Supply Voltage ....................................................... 6.5V
Input Voltage on Pins 1, 6 and 7
ORDER PART
TOP VIEW
NUMBER
(Note 2) ............................ –0.3 < VIN < (V+) +0.3V
Current into Pin 6 .................................................. 20µA
Output Short Circuit Duration
+
BOOST
1
2
3
4
8
7
6
5
V
LTC1046CN8
LTC1046CS8
LTC1046IN8
LTC1046IS8
LTC1046MJ8
+
CAP
OSC
LV
GND
(V+ ≤ 6V) ...............................................Continuous
Operating Temperature Range
LTC1046C .................................... 0°C ≤ TA ≤ 70°C
LTC1046I ................................. –40°C ≤ TA ≤ 85°C
LTC1046M .................................... –55°C to 125°C
Storage Temperature Range ............... –65°C to +150°C
Lead Temperature (Soldering, 10 sec.)................. 300°C
–
CAP
V
OUT
J8 PACKAGE
N8 PACKAGE
8-LEAD CERDIP 8-LEAD PDIP
S8 PACKAGE
8-LEAD PLASTIC SO
S8 PART MARKING
TJMAX = 160°C, θJA = 100°C (J8)
TJMAX = 110°C, θJA = 130°C (N8)
JMAX = 150°C, θJA = 150°C (S8)
1046
1046I
T
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, COSC = 0pF, unless otherwise noted.
LTC1046C
TYP
LTC1046I/M
TYP
SYMBOL PARAMETER
CONDITIONS
R = ∞, Pins 1 and 7 No Connection
MIN
MAX
MIN
MAX
UNITS
I
Supply Current
165
35
300
165
35
300
µA
µA
S
L
R = ∞, Pins 1 and 7 No Connection,
L
+
V = 3V
+
+
V
V
Minimum Supply Voltage
R = 5kΩ
●
●
1.5
1.5
V
V
L
L
Maximum Supply Voltage R = 5kΩ
6
6
H
L
+
R
OUT
Output Resistance
V = 5V, I = 50mA (Note 3)
27
27
60
35
45
85
27
27
60
35
50
90
Ω
Ω
Ω
L
●
●
+
V = 2V, I = 10mA
L
+
f
Oscillator Frequency
Power Efficiency
V = 5V (Note 4)
20
4
30
5.5
20
4
30
5.5
kHz
kHz
OSC
+
V = 2V
P
V
R = 2.4kΩ
L
95
97
97
95
97
97
%
%
EFF
Voltage Conversion
Efficiency
R = ∞
L
99.9
99.9
OUTEFF
+
I
Oscillator Sink or Source
Current
V
= 0V or V
OSC
OSC
Pin 1 = 0V
Pin 1 = V
●
●
4.2
15
35
45
4.2
15
40
50
µA
µA
+
Note 1: Absolute Maximum Ratings are those values beyond which
Note 3: R
is measured at T = 25°C immediately after power-on.
J
OUT
the life of the device may be impaired.
Note 2: Connecting any input terminal to voltages greater than V or
Note 4: f
is tested with C
= 100pF to minimize the effects of test
OSC
OSC
+
fixture capacitance loading. The 0pF frequency is correlated to this 100pF
test point, and is intended to simulate the capacitance at pin 7 when the
device is plugged into a test socket and no external capacitor is used.
less than ground may cause destructive latch-up. It is recommended
that no inputs from sources operating from external supplies be
applied prior to power-up of the LTC1046.
2
LTC1046
U W
TYPICAL PERFOR A CE CHARACTERISTICS
(Using Test Circuit in Figure 1)
Output Resistance vs
Oscillator Frequency
Output Resistance vs
Supply Voltage
Output Resistance vs
Temperature
500
400
300
200
100
0
1000
100
10
80
70
60
50
40
30
20
10
C1 = C2 = 10µF
T
= 25°C
= 5V
T
L
= 25°C
= 3mA
A
A
+
V
I
I
L
= 10mA
+
V
= 2V, C
= 0pF
OSC
C1 = C2
= 1µF
C
= 100pF
OSC
C1 = C2
= 10µF
C1 = C2
= 100µF
+
V
= 5V, C
= 0pF
OSC
C
1
= 0pF
OSC
100
1k
10k
100k
0
2
3
4
5
6
7
–55 –25
0
25
50
75 100 125
+
OSCILLATOR FREQUENCY, f
(Hz)
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE, V (V)
OSC
1046 G01
1046 G02
1046 G03
Power Conversion Efficiency vs
Load Current for V+ = 2V
Power Conversion Efficiency vs
Load Current for V+ = 5V
Power Conversion Efficiency vs
Oscillator Frequency
100
98
96
94
92
90
88
86
84
82
80
100
90
80
70
60
50
40
30
20
10
0
100
90
100
90
10
A = 100µF, 1mA
B = 100µF, 15mA
C = 10µF, 1mA
9
8
7
6
5
4
3
2
1
0
P
EFF
A
P
EFF
80
70
60
50
40
30
20
10
0
80
D = 10µF, 15mA
E = 1µF, 1mA
70
F = 1µF, 15mA
C
I
S
+
60
50
40
30
20
10
0
V
= 5V
= 25°C
B
T
A
C1 = C2
I
E
S
T
= 25°C
D
T
= 25°C
A
A
+
+
V
= 5V
V
= 2V
F
C1 = C2 = 10µF
C1 = C2 = 10µF
f
= 30kHz
f
= 8kHz
OSC
OSC
100
1k
10k
100k
(Hz)
1M
0
10
20
30
40
50
60
70
0
1
2
3
4
5
6
7
8
9
10
OSCILLATOR FREQUENCY, f
LOAD CURRENT, I (mA)
OSC
LOAD CURRENT, I (mA)
L
L
1046 G06
1046 G05
1046 G04
Output Voltage vs Load Current
for V+ = 2V
Output Voltage vs Load Current
for V+ = 5V
Oscillator Frequency as a
Function of COSC
100
10
1
2.5
2.0
5
4
+
T
V
f
= 25°C
= 5V
T
V
f
= 25°C
V
T
= 5V
= 25°C
A
A
+
+
= 2V
A
= 30kHz
= 8kHz
OSC
OSC
1.5
1.0
0.5
0.0
3
2
1
0
C1 = C2 = 10µF
C1 = C2 = 10µF
+
PIN 1 = V
PIN 1 = OPEN
–0.5
–1.0
–1
–2
–1.5
–2.0
–2.5
–3
–4
–5
SLOPE = 52Ω
SLOPE = 27Ω
50 60 70 80 90 100
0.1
1
10
100
1000
10000
(pF)
0
2
6
10 12 14 16 18 20
4
8
0
10 20 30 40
EXTERNAL CAPACITOR (PIN 7 TO GND), C
LOAD CURRENT, I (mA)
LOAD CURRENT, I (mA)
OSC
L
L
1046 G09
1046 G07
1046 G08
3
LTC1046
U W
TYPICAL PERFOR A CE CHARACTERISTICS
(Using Test Circuit in Figure 1)
Oscillator Frequency as a
Function of Supply Voltage
100
Oscillator Frequency vs
Temperature
40
+
T
= 25°C
V
C
= 5V
= 0pF
A
C
= 0pF
OSC
OSC
38
36
34
32
30
28
26
10
1
0
1
2
3
4
5
6
7
–55 –25
0
25
50
75 100 125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
1046 G10
1046 G11
TEST CIRCUIT
+
V
(5V)
LTC1046
I
S
1
2
3
4
8
7
6
5
+
BOOST
V
EXTERNAL
OSCILLATOR
+
CAP
OSC
LV
I
L
+
R
L
C1
10µF
GND
–
CAP
V
OUT
V
OUT
C
C2
10µF
OSC
+
1046 F01
Figure 1
O U
W
U
PPLICATI
A
S I FOR ATIO
Theory of Operation
If the switch is cycled “f” times per second, the charge
transfer per unit time (i.e., current) is:
To understand the theory of operation of the LTC1046, a
review of a basic switched capacitor building block is
helpful.
I = f • ∆q = f • C1(V1 – V2).
V1
V2
InFigure2,whentheswitchisintheleftposition,capacitor
C1 will charge to voltage V1. The total charge on C1 will be
q1 = C1V1. The switch then moves to the right, discharg-
ing C1 to voltage V2. After this discharge time, the charge
on C1 is q2 = C1V2. Note that charge has been transferred
from the source, V1, to the output, V2. The amount of
charge transferred is:
f
R
L
C1
C2
1046 F02
Figure 2. Switched Capacitor Building Block
∆ q = q1 – q2 = C1(V1 – V2).
4
LTC1046
O U
W
U
PPLICATI
A
S I FOR ATIO
Rewriting in terms of voltage and impedance equivalence,
As frequency is decreased, the output impedance will
eventually be dominated by the 1/fC1 term and power
efficiency will drop. The typical curves for power effi-
ciency versus frequency show this effect for various capaci-
tor values.
–
V1– V2
REQUIV
V1 V2
I =
=
.
1/ fC1
(
)
A new variable, REQUIV, has been defined such that
REQUIV =1/fC1.Thus,theequivalentcircuitfortheswitched
capacitor network is as shown in Figure 3.
Note also that power efficiency decreases as frequency
goes up. This is caused by internal switching losses which
occur due to some finite charge being lost on each
switching cycle. This charge loss per unit cycle, when
multiplied by the switching frequency, becomes a current
loss. At high frequency this loss becomes significant and
the power efficiency starts to decrease.
R
EQUIV
V1
V2
C2
R
L
1
fC1
R
=
EQUIV
1046 F03
LV (Pin 6)
The internal logic of the LTC1046 runs between V+ and LV
(Pin 6). For V+ greater than or equal to 3V, an internal
switch shorts LV to GND (Pin 3). For V+ less than 3V, the
LV pin should be tied to ground. For V+ greater than or
equalto3V,theLVpincanbetiedtogroundorleftfloating.
Figure 3. Switched Capacitor Equivalent Circuit
Examination of Figure 4 shows that the LTC1046 has the
same switching action as the basic switched capacitor
building block. With the addition of finite switch ON
resistance and output voltage ripple, the simple theory,
although not exact, provides an intuitive feel for how the
device works.
OSC (Pin 7) and BOOST (Pin 1)
The switching frequency can be raised, lowered or driven
from an external source. Figure 5 shows a functional
diagram of the oscillator circuit.
+
V
(8)
SW1
SW2
+
–
CAP
(2)
BOOST
+
φ
φ
3x
(1)
V
+
C1
OSC
+2
OSC
(7)
CAP
(4)
V
OUT
(5)
2I
I
BOOST
(1)
C2
+
1046 F04
LV
(6)
GND
(3)
CLOSED WHEN
+
V
> 3.0V
OSC
(7)
SCHMITT
TRIGGER
Figure 4. LTC1046 Switched Capacitor
Voltage Converter Block Diagram
14pF
2I
I
For example, if you examine power conversion efficiency
as a function of frequency (see typical curve), this simple
theory will explain how the LTC1046 behaves. The loss,
and hence the efficiency, is set by the output impedance.
LV
(6)
1046 F05
Figure 5. Oscillator
5
LTC1046
PPLICATI
O U
W
U
A
S I FOR ATIO
By connecting the BOOST (Pin 1) to V+, the charge and
discharge current is increased and, hence, the frequency
is increased by approximately three times. Increasing the
frequency will decrease output impedance and ripple for
higher load currents.
are necessary to minimize voltage losses at high currents.
For CIN the effect of the ESR of the capacitor will be
multiplied by four, due to the fact that switch currents are
approximately two times higher than output current, and
losses will occur on both the charge and discharge cycle.
This means that using a capacitor with 1Ω of ESR for CIN
will have the same effect as increasing the output imped-
ance of the LTC1046 by 4Ω. This represents a significant
increase in the voltage losses. For COUT the effect of ESR
is less dramatic. COUT is alternately charged and dis-
charged at a current approximately equal to the output
current, and the ESR of the capacitor will cause a step
function to occur, in the output ripple, at the switch
transitions. This step function will degrade the output
regulation for changes in output load current, and should
be avoided. Realizing that large value tantalum capacitors
can be expensive, a technique that can be used is to
parallel a smaller tantalum capacitor with a large alumi-
num electrolytic capacitor to gain both low ESR and
reasonable cost. Where physical size is a concern some
of the newer chip type surface mount tantalum capacitors
can be used. These capacitors are normally rated at
working voltages in the 10V to 20V range and exhibit very
low ESR (in the range of 0.1Ω).
Loading Pin 7 with more capacitance will lower the fre-
quency. Using the BOOST pin in conjunction with external
capacitance on Pin 7 allows user selection of the fre-
quency over a wide range.
Driving the LTC1046 from an external frequency source
can be easily achieved by driving Pin 7 and leaving the
BOOST pin open, as shown in Figure 6. The output current
from Pin 7 is small, typically 15µA, so a logic gate is
capableofdrivingthiscurrent.ThechoiceofusingaCMOS
logicgateisbestbecauseitcanoperateoverawidesupply
voltage range (3V to 15V) and has enough voltage swing
to drive the internal Schmitt trigger shown in Figure 5. For
5V applications, a TTL logic gate can be used by simply
adding an external pull-up resistor (see Figure 6).
Capacitor Selection
While the exact values of CIN and COUT are noncritical,
good quality, low ESR capacitors such as solid tantalum
+
REQUIRED FOR TTL LOGIC
LTC1046
V
1
2
3
4
8
7
6
5
+
NC
BOOST
V
100k
+
OSC INPUT
CAP
OSC
LV
+
GND
C1
+
–
–(V )
CAP
V
OUT
C2
+
1046 F06
Figure 6. External Clocking
6
LTC1046
U
O
TYPICAL APPLICATI S
Negative Voltage Converter
the typical curves of output impedance and power effi-
ciency versus frequency. For C1 = C2 = 10µF, the output
impedance goes from 27Ω at fOSC = 30kHz to 225Ω at
fOSC = 1kHz. As the 1/fC term becomes large compared to
switch ON resistance term, the output resistance is deter-
mined by 1/fC only.
Figure 7 shows a typical connection which will provide a
negative supply from an available positive supply. This
circuit operates over full temperature and power supply
ranges without the need of any external diodes. The LV pin
(Pin 6) is shown grounded, but for V+ ≥ 3V, it may be
floated, since LV is internally switched to GND (Pin 3) for
V+ ≥ 3V.
Voltage Doubling
Figure 8 shows a two diode, capacitive voltage doubler.
With a 5V input, the output is 9.1V with no load and 8.2V
with a 10mA load.
The output voltage (Pin 5) characteristics of the circuit are
thoseofanearlyidealvoltagesourceinserieswithan27Ω
resistor. The 27Ω output impedance is composed of two
terms: 1) the equivalent switched capacitor resistance
(see Theory of Operation), and 2) a term related to the ON
resistance of the MOS switches.
LTC1046
+
1
2
3
4
8
7
6
5
V
+
BOOST
V
1.5V TO 6V
+
+
V
CAP
OSC
LV
D
V
D
+
V
= 2
OUT
REQUIRED
FOR
GND
Atanoscillatorfrequencyof30kHzandC1=10µF, thefirst
term is:
(V – 1)
IN
–
+
CAP
V
OUT
V
< 3V
+
+
10µF
10µF
1046 F08
1
REQUIV
=
=
fOSC /2 • C1
(
)
Figure 8. Voltage Doubler
1
= 6.7Ω.
15 • 103 10 • 10–6
•
Ultraprecision Voltage Divider
An ultraprecision voltage divider is shown in Figure 9. To
achieve the 0.0002% accuracy indicated, the load current
should be kept below 100nA. However, with a slight loss
in accuracy, the load current can be increased.
Notice that the equation for REQUIV is not a capacitive
reactance equation (XC = 1/ωC) and does not contain a 2π
term.
The exact expression for output impedance is complex,
butthedominanteffectofthecapacitorisclearlyshownon
LTC1046
+
1
2
3
4
8
7
6
5
V
+
LTC1046
BOOST
V
3V TO 12V
+
1
2
3
4
8
7
6
5
V
+
+
CAP
OSC
LV
BOOST
V
1.5V TO 6V
+
C1
+
GND
CAP
OSC
LV
10µF
+
+
–
REQUIRED FOR V < 3V
CAP
V
OUT
GND
10µF
–
+
+
CAP
V
OUT
V
= –V
V
OUT
1046 F09
±0.002%
2
+
10µF
+
+
C2
10µF
REQUIRED FOR V < 6V
T
I
≤ T ≤ T
A MAX
MIN
≤ 100nA
T
≤ T ≤ T
1046 F07
L
MIN
A
MAX
Figure 9. Ultraprecision Voltage Divider
Figure 7. Negative Voltage Converter
7
LTC1046
U
O
TYPICAL APPLICATI S
Battery Splitter
equal to one half the input voltage. The output voltages are
both referenced to Pin 3 (output common). If the input
voltage between Pin 8 and Pin 5 is less than 6V, Pin 6
should also be connected to Pin 3, as shown by the
dashed line.
A common need in many systems is to obtain positive and
negative supplies from a single battery or single power
supplysystem. Wherecurrentrequirementsaresmall, the
circuit shown in Figure 10 is a simple solution. It provides
symmetrical positive or negative output voltages, both
Paralleling for Lower Output Resistance
AdditionalflexibilityoftheLTC1046isshowninFigures11
and 12. Figure 11 shows two LTC1046s connected in
parallel to provide a lower effective output resistance. If,
however, the output resistance is dominated by 1/fC1,
increasing the capacitor size (C1) or increasing the fre-
quency will be of more benefit than the paralleling
circuit shown.
LTC1046
1
2
3
4
8
7
6
5
+V /2
B
+
BOOST
V
4.5V
V
B
+
9V
CAP
OSC
LV
+
REQUIRED FOR V < 6V
B
C1
10µF
GND
–V /2
B
–4.5V
–
CAP
V
OUT
C2
Figure 12 makes use of “stacking” two LTC1046s to
provide even higher voltages. In Figure 12, a negative
voltage doubler or tripler can be achieved depending upon
how Pin 8 of the second LTC1046 is connected, as shown
schematically by the switch.
+
10µF
OUTPUT COMM0N
1046 F10
3V ≤ V ≤ 12V
B
Figure 10. Battery Splitter
+
V
LTC1046
LTC1046
1
2
3
4
1
2
3
4
8
7
6
5
8
7
6
5
+
+
BOOST
V
BOOST
V
+
+
CAP
OSC
LV
CAP
OSC
LV
+
+
C1
10µF
C1
10µF
GND
GND
–
–
+
CAP
V
CAP
V
OUT
V
= –(V )
OUT
OUT
C2
20µF
1/4 CD4077
+
OPTIONAL SYNCHRONIZATION
CIRCUIT TO MINIMIZE RIPPLE
1046 F11
Figure 11. Paralleling for 100mA Load Current
+
+
FOR V
= –3V
FOR V
= –2V
OUT
OUT
+
V
+
LTC1046
LTC1046
C1
10µF
1
2
3
4
1
8
7
6
5
8
7
6
5
+
BOOST
V
BOOST
V
2
3
4
+
+
CAP
OSC
LV
CAP
OSC
LV
+
10µF
GND
GND
–
+
–
CAP
V
–(V )
CAP
V
OUT
V
OUT
OUT
10µF
10µF
+
+
1046 F12
Figure 12. Stacking for Higher Voltage
8
LTC1046
U
PACKAGE DESCRIPTIO Dimensions in inches (milimeters) unless otherwise noted.
J8 Package
8-Lead CERDIP (Narrow 0.300, Hermetic)
(LTC DWG # 05-08-1110)
0.405
(10.287)
MAX
CORNER LEADS OPTION
(4 PLCS)
0.005
(0.127)
MIN
6
5
4
8
7
2
0.023 – 0.045
(0.584 – 1.143)
HALF LEAD
OPTION
0.025
(0.635)
RAD TYP
0.220 – 0.310
(5.588 – 7.874)
0.045 – 0.068
(1.143 – 1.727)
FULL LEAD
OPTION
1
3
0.200
0.300 BSC
(5.080)
MAX
(0.762 BSC)
0.015 – 0.060
(0.381 – 1.524)
0.008 – 0.018
(0.203 – 0.457)
0° – 15°
0.045 – 0.065
(1.143 – 1.651)
0.125
3.175
MIN
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
0.014 – 0.026
(0.360 – 0.660)
0.100
(2.54)
BSC
J8 1298
9
LTC1046
U
Dimensions in inches (milimeters) unless otherwise noted.
PACKAGE DESCRIPTIO
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.400*
(10.160)
MAX
8
7
6
5
4
0.255 ± 0.015*
(6.477 ± 0.381)
1
2
3
0.130 ± 0.005
0.300 – 0.325
0.045 – 0.065
(3.302 ± 0.127)
(1.143 – 1.651)
(7.620 – 8.255)
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
0.125
0.020
(0.508)
MIN
(3.175)
MIN
+0.035
0.325
–0.015
0.018 ± 0.003
(0.457 ± 0.076)
0.100
(2.54)
BSC
+0.889
8.255
(
)
N8 1098
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
10
LTC1046
U
Dimensions in inches (milimeters) unless otherwise noted.
PACKAGE DESCRIPTIO
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
7
5
8
6
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
3
4
2
0.010 – 0.020
(0.254 – 0.508)
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.050
(1.270)
BSC
0.014 – 0.019
(0.355 – 0.483)
TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
SO8 1298
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
11
LTC1046
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Doubler or Inverter, 100mA I , SO-8 Package
OUT
LTC1550
<1mV Output Ripple, 900kHz Operation, SO-8 Package
P-P
LT1611
5V to –5V at 150mA, Low Output Noise, SOT-23 Package
5V to –5V at 20µA Supply Current, SOT-23 Package
5V/50mA, 13µA Supply Current, 2.7V to 5.5V Input Range
LT1617
Micropower Inverting Switching Regulator
Micropower Regulated 5V Charge Pump in SOT-23
LTC1754-5
1046fa LT/TP 1099 2K REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
12
●
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LINEAR TECHNOLOGY CORPORATION 1991
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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